A two-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks and its dynamic excitation mutual selection MPUF generation method

Abstract

The present invention discloses a dual-layer dynamic excitation mutual selection MPUF circuit and a dynamic excitation mutual selection MPUF generation method for resisting machine learning attacks. When either a first selection excitation module or a second selection excitation module is used as the excitation module, the other serves as the response module. The excitation module inputs an excitation signal to the corresponding spin-transfer torque-magnetic random access memory array. The discharge path port of the corresponding pre-charge sense amplifier circuit selects two discharge paths from the corresponding spin-transfer torque-magnetic random access memory array for comparison, generates a response signal, and inputs it into an obfuscated decoder circuit. This generates an excitation signal for the response module. The discharge path port of the pre-charge sense amplifier circuit corresponding to the response module selects two discharge paths from the corresponding spin-transfer torque-magnetic random access memory array based on the excitation signal generated by the response module for comparison, and outputs the comparison result. The present invention improves resistance to machine learning attacks, thereby enhancing safety during use.

Description

Technical Field

[0001] The present invention relates to the technical field of physical unclonable function generation, and in particular to a double-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks and a dynamic excitation mutual selection MPUF generation method thereof. Background Art

[0002] The rapid development of the Internet of Things (IoT) has led to increased demands for secure mobile device chips. As a key component in improving security, physical unclonable functions (PUFs) hold significant research significance. Currently, PUFs based on CMOS processes are widely used in the commercial sector. However, these traditional CMOS PUFs are limited by random entropy and are vulnerable to side-channel attacks, fault injection attacks, and modeling attacks based on machine learning techniques. Furthermore, various memory PUF solutions have been proposed, with DRAM and SRAM PUFs being the most representative. However, as the size of memory PUFs decreases, the semiconductor material used in DRAM generates leakage current, leading to increased power consumption. Furthermore, SRAM has a significant area overhead. Therefore, developing a low-power, high-speed, and low-area PUF that is resistant to machine learning attacks is an urgent task. MRAM PUFs offer a suitable solution.

[0003] The Chinese patent application, Publication No. CN117951756A, entitled "A Physical Unclonable Function Based on MRAM and Its Generation Method," states: A magnetic tunnel junction (MTJ) group consisting of two units is selected, and the resistance values ​​of two target MTJs in the same group are compared. Based on the resistance comparison result, the corresponding response value is determined, and the execution MTJ in the two target MTJs in the same group is penetrated. This process is repeated until the PUF generation area is covered by the processed MTJ group to be compared. The MRAM-based physical unclonable function is determined based on the corresponding response values ​​of all MTJ groups to be compared. This scheme requires penetrating the target MTJ after the comparison test, which is a relatively complex operation. Although it improves the repeatability of the PUF, it makes the designed circuit less reconfigurable to a certain extent and reduces the number of stimulus response pairs (CRPs). At the same time, because the final MTJ state of this scheme is fixed and cannot be changed, it is vulnerable to side-channel attacks and machine learning attacks during use, ultimately resulting in low security of the PUF. Once an attacker obtains a certain CRP, they can crack other CRPs, rendering it ineffective. A Chinese patent application with publication number CN109472169A, titled "A Method and Apparatus for Generating a Physical Unclonable Function for an MRAM Chip," states that: A magnetic tunnel junction (MTJ) bit is arbitrarily selected from the MRAM chip as a reference bit, the resistance of a preset number of other MTJ bits in the MRAM chip is sequentially compared with the resistance of the reference bit, the comparison results are recorded, a logic state diagram is generated, and the physical unclonable function (PUF) of the MRAM chip is generated using the logic state diagram. However, the decoding process when comparing an MTJ with the reference MTJ is relatively complex and may cause unnecessary power consumption. In addition, the comparison scheme has a strong regularity and is susceptible to side-channel attacks and machine learning attacks, resulting in low security and poor practicality of the PUF. Summary of the Invention

[0004] In response to the problems existing in the prior art, the present invention provides a two-layer dynamic excitation mutual selection MPUF circuit that is resistant to machine learning attacks and a dynamic excitation mutual selection MPUF generation method thereof, which improves the ability to resist machine learning attacks, thereby enhancing security during use, and has the characteristics of high speed, small area, low power consumption and high robustness.

[0005] To achieve the above technical objectives, the present invention adopts the following technical solutions: a dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks, comprising: a first selection excitation module, a first precharge sense amplifier circuit, a first spin-transfer torque-magnetic random access memory array, an obfuscation decoding circuit, a second selection excitation module, a second precharge sense amplifier circuit, and a second spin-transfer torque-magnetic random access memory array;

[0006] When the first selection excitation module serves as the excitation module and the second selection excitation module serves as the response module, the first selection excitation module is used to input an excitation signal to the first spin-transfer torque-magnetic random access memory array, and the discharge path port of the first pre-charge sense amplifier circuit selects two discharge paths from the first spin-transfer torque-magnetic random access memory array according to the excitation signal for comparison, generates a response signal, inputs the response signal to the aliasing decoder circuit, and controls the second selection excitation module to generate an excitation signal through the aliasing decoder circuit. The discharge path port of the second pre-charge sense amplifier circuit selects two discharge paths from the second spin-transfer torque-magnetic random access memory array according to the excitation signal generated by the second selection excitation module for comparison, and outputs a comparison result;

[0007] When the second selection excitation module serves as the excitation module, the first selection excitation module serves as the response module. At this time, the second selection excitation module is used to input an excitation signal to the second spin-transfer torque-magnetic random access memory array. The discharge path port of the second pre-charge sense amplifier circuit selects two discharge paths from the second spin-transfer torque-magnetic random access memory array according to the excitation signal for comparison, generates a response signal, inputs the response signal into the confusion decoder circuit, and controls the first selection excitation module to generate an excitation signal through the confusion decoder circuit. The discharge path port of the first pre-charge sense amplifier circuit selects two discharge paths from the first spin-transfer torque-magnetic random access memory array for comparison according to the excitation signal generated by the first selection excitation module, and outputs the comparison result.

[0008] Furthermore, the first selection excitation module and the second selection excitation module are both composed of a column selection excitation module group and a row selection excitation module, the column selection excitation module group is divided into a first column selection excitation module and a second column selection excitation module, the first column selection excitation module and the second column selection excitation module are both composed of n column NMOS transistors in parallel, and the row selection excitation module is composed of n row NMOS transistor groups, and each row NMOS transistor group is provided with 2n parallel row NMOS transistors.

[0009] Furthermore, the drain of each column NMOS transistor in the first column selection excitation module of the first selection excitation module is connected to the first discharge path port of the first pre-charge sense amplifier circuit, and the drain of each column NMOS transistor in the second column selection excitation module of the first selection excitation module is connected to the second discharge path port of the first pre-charge sense amplifier circuit; the gate of each column NMOS transistor in the first column selection excitation module and the second column selection excitation module of the first selection excitation module is connected to the confusion decoding circuit, the source of each column NMOS transistor in the first column selection excitation module of the first selection excitation module is correspondingly connected to the drain of the first n row NMOS transistors in each row in the row selection excitation module of the first selection excitation module, and the source of each column NMOS transistor in the second column selection excitation module of the first selection excitation module is correspondingly connected to the drain of the last n row NMOS transistors in each row in the row selection excitation module of the first selection excitation module; the gate of each row NMOS transistor in the row selection excitation module of the first selection excitation module is connected to the confusion decoding circuit, and the source of each row NMOS transistor in the row selection excitation module of the first selection excitation module is connected to the first spin transfer torque-magnetic random access memory array.

[0010] Furthermore, the first spin-transfer torque-magnetic random access memory array is composed of n×2n first spin-transfer torque-magnetic random access memories, each of which contains a magnetic tunnel junction, the free end of each magnetic tunnel junction is respectively connected to the source of a row NMOS transistor of the row selection excitation module in the first selection excitation module, and the fixed end of each magnetic tunnel junction is grounded.

[0011] Furthermore, the drain of each column NMOS transistor in the first column selection excitation module of the second selection excitation module is connected to the first discharge path port of the second pre-charge sense amplifier circuit, and the drain of each column NMOS transistor in the second column selection excitation module of the second selection excitation module is connected to the second discharge path port of the second pre-charge sense amplifier circuit; the gate of each column NMOS transistor in the first column selection excitation module and the second column selection excitation module of the second selection excitation module is connected to the confusion decoding circuit, the source of each column NMOS transistor in the first column selection excitation module of the second selection excitation module is correspondingly connected to the drain of the first n row NMOS transistors in each row in the row selection excitation module of the second selection excitation module, and the source of each column NMOS transistor in the second column selection excitation module of the second selection excitation module is correspondingly connected to the drain of the last n row NMOS transistors in each row in the row selection excitation module of the second selection excitation module; the gate of each row NMOS transistor in the row selection excitation module of the second selection excitation module is connected to the confusion decoding circuit, and the source of each row NMOS transistor in the row selection excitation module of the second selection excitation module is connected to the second spin transfer torque-magnetic random access memory array.

[0012] Furthermore, the second spin-transfer torque-magnetic random access memory array is composed of n×2n second spin-transfer torque-magnetic random access memories, each of which contains a magnetic tunnel junction, the free end of each magnetic tunnel junction is respectively connected to the source of a row NMOS transistor of the row selection excitation module in the second selection excitation module, and the fixed end of each magnetic tunnel junction is grounded.

[0013] Furthermore, the confusion decoder circuit includes: an exclusive OR gate, a first column decoder group, a second column decoder group, a first row decoder group and a second row decoder group, the output end Qm of the first pre-charge sense amplifier circuit is respectively connected to the first input end of the exclusive OR gate and the input end of the second column decoder group, the output end of the second column decoder group is connected to the gates of all column NMOS tubes in the second selection excitation module, the output end of the exclusive OR gate is used to control the input signals of the first row decoder group and the second row decoder group, the output end of the second row decoder group is connected to the gates of all row NMOS transistors in the second selection excitation module; the output end Qm of the second pre-charge sense amplifier circuit is respectively connected to the second input end of the exclusive OR gate and the input end of the first column decoder group, the output end of the first column decoder group is connected to the gates of all column NMOS tubes in the first selection excitation module, and the output end of the first row decoder group is connected to the gates of all row NMOS transistors in the first selection excitation module.

[0014] Furthermore, the present invention also provides a dynamic excitation mutual selection MPUF generation method for the dual-layer dynamic excitation mutual selection MPUF circuit that is resistant to machine learning attacks, with the first selection excitation module as the excitation module and the second selection excitation module as the response module, comprising the following steps:

[0015] Step 1: Initializing all magnetic tunnel junction bits in the first spin-transfer torque-magnetic random access memory array and the second spin-transfer torque-magnetic random access memory array to the same state;

[0016] Step 2: selecting two discharge paths from the first spin-transfer torque-magnetic random access memory array through a first pre-charge sense amplifier circuit according to an excitation signal input by the excitation module, comparing the magnetic tunnel junction resistances in the two discharge paths, and generating a response signal;

[0017] Step 3: Continue to input the excitation signal to the excitation module and repeat step 2 until the generated response signal can drive the response module to perform decoding. The response signal is input into the obfuscation decoding circuit to generate an excitation signal for the response module. Two discharge paths are selected from the second spin-transfer torque-magnetic random access memory array through the second pre-charge sense amplifier circuit. The magnetic tunnel junction resistances in the two discharge paths are compared and the comparison result is output.

[0018] Furthermore, the present invention also provides a dynamic excitation mutual selection MPUF generation method for the dual-layer dynamic excitation mutual selection MPUF circuit that is resistant to machine learning attacks, using the second selection excitation module as the excitation module and the first selection excitation module as the response module, comprising the following steps:

[0019] Step 1: Initializing all magnetic tunnel junction bits in the first spin-transfer torque-magnetic random access memory array and the second spin-transfer torque-magnetic random access memory array to the same state;

[0020] Step 2: selecting two discharge paths from the second spin-transfer torque-magnetic random access memory array through a second pre-charge sense amplifier circuit according to an excitation signal input by the excitation module, comparing the magnetic tunnel junction resistances in the two discharge paths, and generating a response signal;

[0021] Step 3: Continue to input the excitation signal to the excitation module and repeat step 2 until the generated response signal can drive the response module to perform decoding. The response signal is input into the obfuscation decoding circuit to generate an excitation signal for the response module. Two discharge paths are selected from the first spin-transfer torque-magnetic random access memory array through the first pre-charge sense amplifier circuit. The magnetic tunnel junction resistances in the two discharge paths are compared and the comparison result is output.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] (1) The dual-layer dynamic excitation mutual selection MPUF circuit and the dynamic excitation mutual selection MPUF generation method of the present invention are resistant to machine learning attacks. According to the excitation module and response module selected by the user, and the discharge path is selected according to the excitation signal input by the user, compared with the prior art, due to the state of the magnetic tunnel junction of the present invention, under the same write current, the flipping of different units presents a probability distribution, so that the CRP space increases exponentially with the change of n in the excitation module, which improves the security to a certain extent and can be used as a strong PUF; and, when the response module of the present invention selects two discharge paths for comparison, it does not need to traverse all discharge paths to compare with the selected discharge path, which greatly improves the speed of response generation and reduces power consumption;

[0024] (2) The dual-layer dynamic excitation mutual selection MPUF circuit and its dynamic excitation mutual selection MPUF generation method for resisting machine learning attacks of the present invention greatly improve the nonlinearity between the excitation and the response by setting an obfuscated decoding circuit, and have high robustness against machine learning attacks such as logistic regression, support vector machine, multilayer perceptron and random forest;

[0025] (3) The magnetic tunnel junction in the double-layer dynamic excitation mutual selection MPUF circuit and the dynamic excitation mutual selection MPUF generation method of the present invention that are resistant to machine learning attacks can achieve a reconfigurable PUF effect after writing current. Compared with the previous solution of directly breaking down the MTJ to completely fix the resistance value of the MTJ, it will have a wider range of applications and higher security. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the dual-layer dynamic excitation mutual selection MPUF circuit for resisting machine learning attacks of the present invention;

[0027] Figure 2 This is a flow chart of the dynamic excitation mutual selection MPUF generation method of the double-layer dynamic excitation mutual selection MPUF circuit that is resistant to machine learning attacks of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention will be further explained below with reference to the accompanying drawings.

[0029] like Figure 1 The present invention provides a schematic diagram of a double-layer dynamic excitation mutual selection MPUF circuit that is resistant to machine learning attacks. The double-layer dynamic excitation mutual selection MPUF circuit includes: a first selection excitation module, a first pre-charge sense amplifier circuit, a first spin-transfer torque-magnetic random access memory array, an obfuscation decoding circuit, a second selection excitation module, a second pre-charge sense amplifier circuit, and a second spin-transfer torque-magnetic random access memory array;

[0030] When the first selection excitation module serves as the excitation module and the second selection excitation module serves as the response module, the first selection excitation module is used to input an excitation signal to the first spin-transfer torque-magnetic random access memory array, and the discharge path port of the first pre-charge sense amplifier circuit is used to control the switch of the first selection excitation module to select two discharge paths from the first spin-transfer torque-magnetic random access memory array for comparison, generate a response signal, input the response signal to the aliasing decoder circuit, and control the second selection excitation module to generate an excitation signal through the aliasing decoder circuit. The discharge path port of the second pre-charge sense amplifier circuit is used to control the switch of the second selection excitation module to select two discharge paths from the second spin-transfer torque-magnetic random access memory array for comparison, and output a comparison result.

[0031] When the second selection excitation module serves as the excitation module, the first selection excitation module serves as the response module. At this time, the second selection excitation module is used to input an excitation signal to the second spin-transfer torque-magnetic random access memory array, and the discharge path port of the second pre-charge sensing amplifier circuit is used to control the switch of the second selection excitation module to select two discharge paths from the second spin-transfer torque-magnetic random access memory array for comparison, generate a response signal, input the confusion decoder circuit, and control the first selection excitation module to generate an excitation signal through the confusion decoder circuit. The discharge path port of the first pre-charge sensing amplifier circuit is used to control the switch of the first selection excitation module to select two discharge paths from the first spin-transfer torque-magnetic random access memory array for comparison, and output the comparison result.

[0032] The present invention adopts a dual-layer structure of optional excitation modules and response modules, which increases the potential for confusion between the excitation modules and the response modules. Furthermore, the discharge path is selected based on the user's customized excitation module and response module, and based on the excitation signal input by the user. Compared with the prior art, due to the inherent state of the magnetic tunnel junction of the present invention, the flipping of different units presents a probability distribution under the same write current, so that the CRP space increases exponentially with the change of n in the excitation module, which improves security to a certain extent and can be used as a strong PUF. In addition, when selecting two discharge paths for comparison, the response module of the present invention does not need to traverse all discharge paths to compare with the selected discharge path, which greatly improves the speed of response generation and reduces power consumption.

[0033] In the present invention, the first selection excitation module and the second selection excitation module are both composed of a column selection excitation module group and a row selection excitation module. The column selection excitation module group is divided into a first column selection excitation module and a second column selection excitation module. The first column selection excitation module and the second column selection excitation module are both composed of n column NMOS transistors connected in parallel. Among them, the column NMOS transistors of the first column selection excitation module and the second column selection excitation module in the first selection excitation module are expressed as: X00, X01, ..., X0(n-1), Y00, Y01, ..., Y0(n-1), and the first column selection excitation module in the second selection excitation module are expressed as: The column NMOS transistors of the column selection excitation module and the second column selection excitation module are represented as: X10, X11, ..., X1(n-1), Y10, Y11, ..., Y1(n-1); the row selection excitation module is composed of n row NMOS transistor groups, among which the row NMOS transistor group in the first selection excitation module is represented as: C00, C01, ..., C0(n-1), and the row NMOS transistor group in the second selection excitation module is represented as: C10, C11, ..., C1(n-1), and each row NMOS transistor group is provided with 2n parallel row NMOS transistors.

[0034] The drain of each column NMOS transistor in the first column selection excitation module of the first selection excitation module is connected to the first discharge path port of the first pre-charge sensing amplifier circuit, and the drain of each column NMOS transistor in the second column selection excitation module of the first selection excitation module is connected to the second discharge path port of the first pre-charge sensing amplifier circuit; the gate of each column NMOS transistor in the first column selection excitation module and the second column selection excitation module of the first selection excitation module is connected to the confusion decoding circuit, the source of each column NMOS transistor in the first column selection excitation module of the first selection excitation module is correspondingly connected to the drain of the first n row NMOS transistors in each row in the row selection excitation module of the first selection excitation module, and the source of each column NMOS transistor in the second column selection excitation module of the first selection excitation module is correspondingly connected to the drain of the last n row NMOS transistors in each row in the row selection excitation module of the first selection excitation module; the gate of each row NMOS transistor in the row selection excitation module of the first selection excitation module is connected to the confusion decoding circuit, and the source of each row NMOS transistor in the row selection excitation module of the first selection excitation module is connected to the first spin transfer torque-magnetic random access memory array.

[0035] The first spin-transfer torque-magnetic random access memory array is composed of n×2n first spin-transfer torque-magnetic random access memories, each of which contains a magnetic tunnel junction. The magnetic tunnel junction is a "sandwich" structure consisting of two ferromagnetic layers and a metal oxide layer. One of the ferromagnetic layers, whose magnetization direction can be changed, is called a "free layer", while the other ferromagnetic layer, whose magnetization direction cannot be changed, is called a "pinned layer". By changing the magnetization direction of the free layer and comparing it with the pinned layer, two different resistance states can be obtained. When the magnetization direction of the free layer is opposite to that of the pinned layer, it is considered "parallel" and the magnetic tunnel junction exhibits a high-resistance state. When the magnetization direction of the free layer is the same as that of the pinned layer, it is considered "antiparallel" and the magnetic tunnel junction exhibits a low-resistance state. The free end of each magnetic tunnel junction is respectively connected to the source of a row NMOS transistor in the row selection excitation module in the first selection excitation module, and the fixed end of each magnetic tunnel junction is grounded. Due to the state of the magnetic tunnel junction of the present invention, under the same write current, the flipping conditions of different units present a probability distribution, so that the CRP space increases exponentially with the change of n in the excitation module, which improves security to a certain extent and can be used as a strong PUF.

[0036] Similarly, the drain of each column NMOS transistor in the first column selection excitation module of the second selection excitation module is connected to the first discharge path port of the second pre-charge sensing amplifier circuit, and the drain of each column NMOS transistor in the second column selection excitation module of the second selection excitation module is connected to the second discharge path port of the second pre-charge sensing amplifier circuit; the gate of each column NMOS transistor in the first column selection excitation module and the second column selection excitation module of the second selection excitation module is connected to the confusion decoding circuit, and the source of each column NMOS transistor in the first column selection excitation module of the second selection excitation module is correspondingly connected to the drain of the first n row NMOS transistors in each row in the row selection excitation module of the second selection excitation module, and the source of each column NMOS transistor in the second column selection excitation module of the second selection excitation module is correspondingly connected to the drain of the last n row NMOS transistors in each row in the row selection excitation module of the second selection excitation module; the gate of each row NMOS transistor in the row selection excitation module of the second selection excitation module is connected to the confusion decoding circuit, and the source of each row NMOS transistor in the row selection excitation module of the second selection excitation module is connected to the second spin transfer torque-magnetic random access memory array.

[0037] The second spin-transfer torque-magnetic random access memory array is composed of n×2n second spin-transfer torque-magnetic random access memories, each of which contains a magnetic tunnel junction, the free end of each magnetic tunnel junction is respectively connected to the source of a row NMOS transistor of the row selection excitation module in the second selection excitation module, and the fixed end of each magnetic tunnel junction is grounded.

[0038] The first selection excitation module and the second selection excitation module both have enable signals. Users can customize the selected excitation module and response module. Users only need to give one binary bit to enable the excitation module, thereby enabling the response module.

[0039] The confusion decoder circuit includes: an exclusive OR gate, a first column decoder group, a second column decoder group, a first row decoder group and a second row decoder group. The output end Qm of the first pre-charge sense amplifier circuit is respectively connected to the first input end of the exclusive OR gate and the input end of the second column decoder group, the output end of the second column decoder group is connected to the gates of all column NMOS tubes in the second selection excitation module, the output end of the exclusive OR gate is used to control the input signals of the first row decoder group and the second row decoder group, the output end of the second row decoder group is connected to the gates of all row NMOS transistors in the second selection excitation module; the output end Qm of the second pre-charge sense amplifier circuit is respectively connected to the second input end of the exclusive OR gate and the input end of the first column decoder group, the output end of the first column decoder group is connected to the gates of all column NMOS tubes in the first selection excitation module, and the output end of the first row decoder group is connected to the gates of all row NMOS transistors in the first selection excitation module. Because the obfuscated decoding circuit contains XOR gates, the excitation conditions of the response modules are different, which greatly improves the nonlinearity between the excitation and the response, and has high robustness against machine learning attacks such as logistic regression, support vector machines, multi-layer perceptrons and random forests.

[0040] like Figure 2 The present invention also provides a method for generating a dynamic excitation mutual selection MPUF of a double-layer dynamic excitation mutual selection MPUF circuit that is resistant to machine learning attacks, comprising the following steps:

[0041] If the first selection excitation module is used as the excitation module and the second selection excitation module is used as the response module,

[0042] Step 1: Initializing all magnetic tunnel junction bits in the first spin-transfer torque-magnetic random access memory array and the second spin-transfer torque-magnetic random access memory array to the same state;

[0043] Step 2: selecting two discharge paths from the first spin-transfer torque-magnetic random access memory array through a first pre-charge sense amplifier circuit according to an excitation signal input by the excitation module, comparing the magnetic tunnel junction resistances in the two discharge paths, and generating a response signal;

[0044] Step 3: Continue to input the excitation signal to the excitation module and repeat step 2 until the generated response signal can drive the response module to perform decoding. The response signal is input into the obfuscation decoding circuit to generate an excitation signal for the response module. Two discharge paths are selected from the second spin-transfer torque-magnetic random access memory array through the second pre-charge sense amplifier circuit. The magnetic tunnel junction resistances in the two discharge paths are compared and the comparison result is output.

[0045] If the second selection incentive module is used as the incentive module and the first selection incentive module is used as the response module, the following steps are included:

[0046] Step 1: Initializing all magnetic tunnel junction bits in the first spin-transfer torque-magnetic random access memory array and the second spin-transfer torque-magnetic random access memory array to the same state;

[0047] Step 2: selecting two discharge paths from the second spin-transfer torque-magnetic random access memory array through a second pre-charge sense amplifier circuit according to an excitation signal input by the excitation module, comparing the magnetic tunnel junction resistances in the two discharge paths, and generating a response signal;

[0048] Step 3: Continue to input the excitation signal to the excitation module and repeat step 2 until the generated response signal can drive the response module to perform decoding. The response signal is input into the obfuscation decoding circuit to generate an excitation signal for the response module. Two discharge paths are selected from the first spin-transfer torque-magnetic random access memory array through the first pre-charge sense amplifier circuit. The magnetic tunnel junction resistances in the two discharge paths are compared and the comparison result is output.

[0049] The magnetic tunnel junction in the dynamic excitation mutual selection MPUF generation method of the double-layer dynamic excitation mutual selection MPUF circuit of the present invention that is resistant to machine learning attacks can achieve a reconfigurable PUF effect after writing current. Compared with the previous solution of directly breaking down the MTJ to completely fix the resistance value of the MTJ, it will have a wider range of applications and higher security.

[0050] In one technical solution of the present invention, other non-volatile memories such as resistive random access memory (RRAM), phase change memory (PRAM), or SOT-MRAM may be used to replace STT-MRAM.

[0051] In one technical solution of the present invention, the obfuscation operation in the obfuscation decoding circuit can be performed using an encryption algorithm or a mask, so that the nonlinearity between the stimulus and the response is increased.

[0052] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks, characterized in that: include: A first selection excitation module, a first precharge sense amplifier circuit, a first spin-transfer torque-magnetic random access memory array, a scrambling decoding circuit, a second selection excitation module, a second precharge sense amplifier circuit, and a second spin-transfer torque-magnetic random access memory array; When the first selection excitation module serves as the excitation module and the second selection excitation module serves as the response module, the first selection excitation module is used to input an excitation signal to the first spin-transfer torque-magnetic random access memory array, and the discharge path port of the first pre-charge sense amplifier circuit selects two discharge paths from the first spin-transfer torque-magnetic random access memory array according to the excitation signal for comparison, generates a response signal, inputs the response signal to the aliasing decoder circuit, and controls the second selection excitation module to generate an excitation signal through the aliasing decoder circuit. The discharge path port of the second pre-charge sense amplifier circuit selects two discharge paths from the second spin-transfer torque-magnetic random access memory array according to the excitation signal generated by the second selection excitation module for comparison, and outputs a comparison result; When the second selection excitation module serves as the excitation module, the first selection excitation module serves as the response module. At this time, the second selection excitation module is used to input an excitation signal to the second spin-transfer torque-magnetic random access memory array. The discharge path port of the second pre-charge sense amplifier circuit selects two discharge paths from the second spin-transfer torque-magnetic random access memory array according to the excitation signal for comparison, generates a response signal, inputs the response signal into the confusion decoder circuit, and controls the first selection excitation module to generate an excitation signal through the confusion decoder circuit. The discharge path port of the first pre-charge sense amplifier circuit selects two discharge paths from the first spin-transfer torque-magnetic random access memory array for comparison according to the excitation signal generated by the first selection excitation module, and outputs the comparison result.

2. The dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks according to claim 1 is characterized in that: The first selection excitation module and the second selection excitation module are both composed of a column selection excitation module group and a row selection excitation module. The column selection excitation module group is divided into a first column selection excitation module and a second column selection excitation module. The first column selection excitation module and the second column selection excitation module are both composed of n column NMOS transistors in parallel. The row selection excitation module is composed of n row NMOS transistor groups, and each row NMOS transistor group is provided with 2n parallel row NMOS transistors.

3. The dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks according to claim 2 is characterized in that: The drain of each column NMOS transistor in the first column selection excitation module of the first selection excitation module is connected to the first discharge path port of the first pre-charge sensing amplifier circuit, and the drain of each column NMOS transistor in the second column selection excitation module of the first selection excitation module is connected to the second discharge path port of the first pre-charge sensing amplifier circuit; the gate of each column NMOS transistor in the first column selection excitation module and the second column selection excitation module of the first selection excitation module is connected to the confusion decoding circuit, the source of each column NMOS transistor in the first column selection excitation module of the first selection excitation module is correspondingly connected to the drain of the first n row NMOS transistors in each row in the row selection excitation module of the first selection excitation module, and the source of each column NMOS transistor in the second column selection excitation module of the first selection excitation module is correspondingly connected to the drain of the last n row NMOS transistors in each row in the row selection excitation module of the first selection excitation module; the gate of each row NMOS transistor in the row selection excitation module of the first selection excitation module is connected to the confusion decoding circuit, and the source of each row NMOS transistor in the row selection excitation module of the first selection excitation module is connected to the first spin transfer torque-magnetic random access memory array.

4. The dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks according to claim 3 is characterized in that: The first spin-transfer torque-magnetic random access memory array is composed of n×2n first spin-transfer torque-magnetic random access memories, each of which contains a magnetic tunnel junction, the free end of each magnetic tunnel junction is respectively connected to the source of a row NMOS transistor of the row selection excitation module in the first selection excitation module, and the fixed end of each magnetic tunnel junction is grounded.

5. The dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks according to claim 4 is characterized in that: The drain of each column NMOS transistor in the first column selection excitation module of the second selection excitation module is connected to the first discharge path port of the second pre-charge sensing amplifier circuit, and the drain of each column NMOS transistor in the second column selection excitation module of the second selection excitation module is connected to the second discharge path port of the second pre-charge sensing amplifier circuit; the gate of each column NMOS transistor in the first column selection excitation module and the second column selection excitation module of the second selection excitation module is connected to the confusion decoding circuit, the source of each column NMOS transistor in the first column selection excitation module of the second selection excitation module is correspondingly connected to the drain of the first n row NMOS transistors in each row in the row selection excitation module of the second selection excitation module, and the source of each column NMOS transistor in the second column selection excitation module of the second selection excitation module is correspondingly connected to the drain of the last n row NMOS transistors in each row in the row selection excitation module of the second selection excitation module; the gate of each row NMOS transistor in the row selection excitation module of the second selection excitation module is connected to the confusion decoding circuit, and the source of each row NMOS transistor in the row selection excitation module of the second selection excitation module is connected to the second spin transfer torque-magnetic random access memory array.

6. The dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks according to claim 5 is characterized in that: The second spin-transfer torque-magnetic random access memory array is composed of n×2n second spin-transfer torque-magnetic random access memories, each of which contains a magnetic tunnel junction, the free end of each magnetic tunnel junction is respectively connected to the source of a row NMOS transistor of the row selection excitation module in the second selection excitation module, and the fixed end of each magnetic tunnel junction is grounded.

7. The dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks according to claim 6 is characterized in that: The confusion decoder circuit includes: an exclusive OR gate, a first column decoder group, a second column decoder group, a first row decoder group and a second row decoder group. The output end Qm of the first pre-charge sense amplifier circuit is respectively connected to the first input end of the exclusive OR gate and the input end of the second column decoder group, and the output end of the second column decoder group is connected to the gates of all column NMOS tubes in the second selection excitation module. The output end of the exclusive OR gate is used to control the input signals of the first row decoder group and the second row decoder group, and the output end of the second row decoder group is connected to the gates of all row NMOS transistors in the second selection excitation module; the output end Qm of the second pre-charge sense amplifier circuit is respectively connected to the second input end of the exclusive OR gate and the input end of the first column decoder group, the output end of the first column decoder group is connected to the gates of all column NMOS tubes in the first selection excitation module, and the output end of the first row decoder group is connected to the gates of all row NMOS transistors in the first selection excitation module.

8. A method for generating a dynamic excitation mutual selection MPUF of a double-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks according to any one of claims 1 to 7, characterized in that: The first selection incentive module is used as the incentive module, and the second selection incentive module is used as the response module, including the following steps: Step 1: Initializing all magnetic tunnel junction bits in the first spin-transfer torque-magnetic random access memory array and the second spin-transfer torque-magnetic random access memory array to the same state; Step 2: Selecting two discharge paths from the first spin-transfer torque-magnetic random access memory array through a first pre-charge sense amplifier circuit according to an excitation signal input by the excitation module, comparing the magnetic tunnel junction resistances in the two discharge paths, and generating a response signal; Step 3: Continue to input the excitation signal to the excitation module and repeat step 2 until the generated response signal can drive the response module to perform decoding. The response signal is input into the obfuscation decoding circuit to generate an excitation signal for the response module. Two discharge paths are selected from the second spin-transfer torque-magnetic random access memory array through the second pre-charge sense amplifier circuit. The magnetic tunnel junction resistances in the two discharge paths are compared and the comparison result is output.

9. A method for generating a dynamic excitation mutual selection MPUF for a dual-layer dynamic excitation mutual selection MPUF circuit resistant to machine learning attacks according to any one of claims 1 to 7, characterized in that: The second selection incentive module is used as the incentive module and the first selection incentive module is used as the response module, including the following steps: Step 1: Initializing all magnetic tunnel junction bits in the first spin-transfer torque-magnetic random access memory array and the second spin-transfer torque-magnetic random access memory array to the same state; Step 2: selecting two discharge paths from the second spin-transfer torque-magnetic random access memory array through a second pre-charge sense amplifier circuit according to an excitation signal input by the excitation module, comparing the magnetic tunnel junction resistances in the two discharge paths, and generating a response signal; Step 3: Continue to input the excitation signal to the excitation module and repeat step 2 until the generated response signal can drive the response module to perform decoding. The response signal is input into the obfuscation decoding circuit to generate an excitation signal for the response module. Two discharge paths are selected from the first spin-transfer torque-magnetic random access memory array through the first pre-charge sense amplifier circuit. The magnetic tunnel junction resistances in the two discharge paths are compared and the comparison result is output.

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