A time-driven segmentation cost calculation method

Abstract

The present invention relates to a timing-driven segmentation cost calculation method, which belongs to the field of electronic design automation, and comprises the following steps: establishing a graph structure; respectively calculating the maximum time delay and the minimum time delay between adjacent triggers; constructing a timing analysis model between adjacent triggers, solving the timing analysis model based on linear programming constraints, and obtaining the expected arrival time of the clock signal of each node; gradually merging nodes in the order of the expected arrival time of the clock signal from small to large; the clock signal starts from the clock source, and the clock signal is routed in the reverse order of the node merging order, and the weights of all edges passed by the clock routing route and the actual arrival time of each node clock are obtained, and the cutting cost is calculated to judge the quality of the timing segmentation. The method can obtain more accurate timing analysis and more accurate segmentation cost evaluation.

Description

Technical Field

[0001] The invention belongs to the field of electronic design automation (EDA), and in particular relates to a timing-driven segmentation cost calculation method. Background Art

[0002] Whether in logic synthesis or in the later layout and routing stage, timing is always the most critical consideration for digital circuits. In timing analysis, the setup time requires that the transmission time of the data signal should be less than the sampling time plus the cycle, that is, the transmission time of the data signal cannot be too long; the hold time requires that the transmission time of the data signal should be greater than the arrival time of the sampling signal, that is, the transmission time of the data signal cannot be too short. There are setup time and hold time constraints between adjacent timing devices such as triggers. Adjacent here means that there is a combinational logic connection between triggers, and the clocks of adjacent triggers do not arrive at the same time, which is related to the routing of the clock signal.

[0003] Nowadays, large-scale designs usually need to form different sub-modules through segmentation, and each sub-module is segmented and laid out to specific locations in the chip. There is a certain distance between different locations, and the signal routing between different locations is also restricted. Signal transmission is affected by parasitic resistance and capacitance, which will cause a certain delay. The size of the segmentation cost determines the quality of the segmentation. The smaller the segmentation cost, the better the segmentation quality.

[0004] The existing partitioning cost calculation process that considers physical layout only considers the total transmission delay of the data signal or the maximum delay, and does not consider the routing delay length from the clock source to each trigger and the time difference when reaching each trigger. It ignores the impact of the important factor of clock on timing, resulting in inaccurate timing analysis, and also ignores the cost of clock delay.

[0005] In addition, the existing clock routing method is based on the layout of a planar rectangular grid structure, and there is no routing method for an arbitrary graph structure. An arbitrary graph structure means that given an arbitrary graph, the nodes in the graph represent the locations of physical devices, the edges between the nodes represent the routes that the signals can pass through, and the weights of the edges represent the delay when the signals pass through. Triggers can be distributed on any nodes in the graph, and the connection method between the nodes is not restricted. Summary of the invention

[0006] The present invention provides a timing-driven segmentation cost calculation method to solve the problems that the existing segmentation cost calculation method ignores the influence of the important factor of clock on the timing and the timing analysis is inaccurate.

[0007] In order to solve the above technical problems, the technical solution provided by the present invention is:

[0008] The present invention relates to a time-series driven segmentation cost calculation method, which comprises the following steps:

[0009] S1. Input the netlist after timing segmentation, abstract the sub-designs in the top layer into nodes, abstract the signal transmission relationship between the sub-designs into edges, and establish a graph structure. Each of the sub-designs contains at least one trigger, and adjacent triggers are connected by combinational logic and routing routes;

[0010] S2. Based on the delay size on the combinational logic and routing route, the maximum time delay and minimum time delay between adjacent triggers are calculated respectively;

[0011] S3. construct a timing analysis model between adjacent triggers, establish linear programming constraints of the timing analysis model based on the maximum time delay and the minimum time delay, solve the timing analysis model based on the linear programming constraints, and obtain the expected arrival time of the clock signal of each node;

[0012] S4. Extract two nodes whose expected arrival time of two clock signals is the shortest from the nodes, and calculate a virtual circle with the two nodes as the center based on the expected arrival time of the clock signals of the two nodes and the path delay of the shortest path of signal transmission, merge the two nodes to form a new node, and use the position of the original node closest to the tangent point of the two virtual circles as the position of the new node;

[0013] S5. Determine whether the number of remaining nodes is 1. If not, return to S4. If it is 1, proceed to S6.

[0014] S6. The clock signal starts from the clock source and is routed in the reverse order of the node merging order. The weights of all edges passed by the clock routing route and the actual arrival time of each node clock are obtained, and the cutting cost is calculated. The calculated cutting cost is used to judge the quality of timing segmentation.

[0015] Preferably, the specific steps of S2 calculating the maximum time delay and the minimum time delay between adjacent triggers are:

[0016] S2.1. Traverse all signal transmission paths between adjacent triggers;

[0017] S2.2. Add the delay size of the combinatorial logic contained in each signal transmission path and the delay size on the routing route to form the delay size of each signal transmission path;

[0018] S2.3. Take the maximum and minimum values ​​of the signal transmission path delay as the maximum time delay and minimum time delay between adjacent triggers respectively.

[0019] Preferably, the specific steps of constructing a timing analysis model between each pair of triggers in S3 are:

[0020] S3.1. Set the clock source and clock period P. The two ends of the clock source are connected to two adjacent triggers respectively. The clock delay from the clock source to the previous trigger is T3, and the clock delay from the clock source to the next trigger is T4.

[0021] Preferably, the specific steps of S3 for establishing the linear programming constraint conditions of the timing analysis model based on the maximum time delay and the minimum time delay are:

[0022] S3.2. Establish the linear programming constraints of the timing analysis model. The constraint formula is:

[0023] (1),

[0024] Among them, Max time represents the maximum time delay between adjacent triggers, Min time represents the minimum time delay between adjacent triggers, TCQ represents the time for data to be transferred from the input to the output of each trigger after being triggered by the sampling clock, Tsetup represents the time for each trigger to be established, and Thold represents the hold time of each trigger.

[0025] Preferably, in S3, the timing analysis model is solved with the goal of maximizing the clock period to obtain the expected arrival time of the clock signal of each sub-design, and the specific steps are:

[0026] S3.3. Obtain the result of linear programming by using a linear programming solver to obtain the clock delay of adjacent flip-flops;

[0027] S3.4. Take the average value of the clock delays of all triggers in the node as the expected arrival time of the clock signal of the node.

[0028] Preferably, the specific steps of S4 are:

[0029] S4.1. Mark all nodes as nodes that have not completed clock routing;

[0030] S4.2. Extract the two nodes with the shortest expected arrival time of the clock signal from all the nodes that have not completed the clock routing, and find the shortest routing path between the two nodes, where the short routing path refers to the routing path with the shortest delay;

[0031] S4.3. Calculate the expected arrival time of the clock signal of the new node after the two nodes are merged. The calculation formula is:

[0032] Tex ij = ( Texi + Tex j + Tex i→j ) / twenty two);

[0033] in, Tex i and Tex j Respectively represent the extracted numbers i and j The expected arrival time of the clock signals of the two nodes is Tex i→j Indicates the number i and j The delay of the shortest routing path between two nodes, Tex ij Indicates the number i and j The expected arrival time of the clock signal of the node after the two nodes are merged;

[0034] S4.4. Calculate the radius of the two virtual circles, and draw a virtual circle with the two nodes as the center, and find the position of the node closest to the tangent point of the two virtual circles as the position of the new node. The calculation formula of the radius of the virtual circle is:

[0035] r i = Tex ij - Tex i (3);

[0036] r j = Tex ij - Tex j (4);

[0037] in, r i and r j Respectively represent the extracted numbers i and j The radius of the virtual circle with the two nodes as the center;

[0038] S4.5. Mark the two nodes before merging as nodes that have completed clock routing, and mark the new node formed by the merger as a node that has not completed clock routing.

[0039] Preferably, the calculation formula of the S6 cutting cost is:

[0040] Cost = α*Tclk + β*Slack_setup+ γ*Slack_hold (5),

[0041] Among them, Cost represents the cutting cost, Tclk represents the weight of all edges through which the clock signal is routed, the weight of the edge is the delay of signal transmission between sub-designs, Slack_setup represents the timing margin of the setup time recalculated according to the actual clock arrival time of each trigger, Slack_hold represents the timing margin of the hold time recalculated according to the actual clock arrival time of each trigger, α, β and γ all represent weight coefficients, and satisfy: α+ β+ γ= 1, α≥0, β≥0, γ≥0.

[0042] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0043] 1. The timing-driven segmentation cost calculation method of the present invention constructs a timing analysis model between adjacent triggers, establishes linear programming constraints of the timing analysis model based on maximum time delay and minimum time delay, solves the timing analysis model based on the linear programming constraints, obtains the expected arrival time of the clock signal of each node, and uses the linear programming method to maximize the clock frequency. The optimal clock arrival time of each trigger in the same clock domain is determined; by repeatedly extracting and merging the two nodes with the smallest expected arrival time of the clock signal, and routing the clock signal in the reverse order of the merging order, the routing route of the clock signal is planned to maximize the clock arrival time of each trigger and minimize the total clock delay. The total clock routing delay of the layout result under the physical position constraint is obtained, the timing margin between the triggers is updated, and the timing margin between adjacent triggers and the total clock routing delay are comprehensively considered as the new segmentation cost, so as to obtain more accurate timing analysis and more accurate segmentation cost evaluation.

[0044] 2. The timing-driven segmentation cost calculation method involved in the present invention is based on the netlist after timing segmentation. The sub-designs in the top layer are abstracted as nodes, and the signal transmission relationship between the sub-designs is abstracted as edges. A graph structure is established, and subsequent segmentation cost calculations are performed on this basis. It is suitable for routing methods with arbitrary graph structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a flow chart of the timing-driven segmentation cost calculation method;

[0046] Figure 2 It is a schematic diagram of the established graph structure;

[0047] Figure 3 It is a schematic diagram of the connection relationship between adjacent triggers;

[0048] Figure 4 It is a structural diagram of the timing analysis model;

[0049] Figure 5 It is a partition layout diagram with the expected arrival time of the clocks marked;

[0050] Figure 6 yes Figure 5 A schematic diagram of the first node merging of the segmented layout graph shown;

[0051] Figure 7 yes Figure 5 A schematic diagram of the second node merging of the segmented layout graph shown;

[0052] Figure 8 yes Figure 5 A schematic diagram of the third node merging of the segmentation layout graph shown;

[0053] Fig. 9 yes Figure 5 A schematic diagram of the fourth node merging of the segmentation layout graph shown;

[0054] Fig.10 This is the clock routing effect diagram. DETAILED DESCRIPTION

[0055] In order to further understand the content of the present invention, the present invention is described in detail in conjunction with examples. The following examples are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0056] The present invention relates to a time-series driven segmentation cost calculation method, which comprises the following steps:

[0057] S1. Input the netlist after timing segmentation, abstract the sub-designs in the top layer as nodes, abstract the signal transmission relationship between the sub-designs as edges, and establish a graph structure. This embodiment is constructed as follows Figure 2 The content of the present invention is described in detail using the graph structure shown in the figure as an example. The numbers on the edges represent the delay of signal transmission between sub-designs. Each of the sub-designs includes at least one trigger. Adjacent triggers are connected by combinational logic and routing routes. The so-called adjacent triggers can come from the same node or from two nodes with a signal transmission relationship. The connection relationship between adjacent triggers is as follows: Figure 3 described.

[0058] S2. Based on the delay size of the combinational logic and the routing path, the maximum time delay and the minimum time delay between adjacent triggers are calculated respectively: Figure 3As shown, for the setup time constraint, the maximum time delay (Max time) needs to be taken, because the setup time needs to ensure that all combinational logic inputs are correct logical values. For the hold time constraint, the minimum time delay needs to be taken, because the hold time focuses on the fastest arriving signal, that is, the minimum time delay (Min time), and does not care whether the signal is the expected correct logical value. Therefore, the Max time of any combinational logic output is equal to the maximum value of the arrival time of all input signals plus the delay size of the combinational logic itself. Similarly, the Min time of the combinational logic output is equal to the minimum value of the arrival time of all input signals plus the delay size of the combinational logic itself. The specific steps are:

[0059] S2.1. Traverse all signal transmission paths between adjacent triggers;

[0060] S2.2. Add the delay size of the combinatorial logic contained in each signal transmission path and the delay size on the routing route to form the delay size of each signal transmission path;

[0061] S2.3. Take the maximum and minimum values ​​of the signal transmission path delay as the maximum time delay and minimum time delay between adjacent triggers respectively.

[0062] like Figure 3 There are two signal transmission paths between the two flip-flops shown. The calculated maximum time delay Max time is 17, and the minimum time delay Min time is 16.

[0063] S3. Build a timing analysis model between adjacent triggers, establish linear programming constraints of the timing analysis model based on the maximum time delay and the minimum time delay, solve the timing analysis model based on the linear programming constraints, and obtain the expected arrival time of the clock signal of each node. The specific steps are as follows:

[0064] S3.1. Figure 4 As shown, the delay of the signal transmission path of two adjacent triggers is the sum of the delay T1 of the combinational logic and the delay T2 on the routing route. Based on the calculation result of S2, it can be seen that Min time ≤T1+ T2≤Maxtime; set the clock source CLK and the clock period P, and the two ends of the clock source CLK are connected to the two adjacent triggers F1 and F2 respectively. The clock delay of the clock source CLK to the previous trigger F1 is T3, and the clock delay to the next trigger F2 is T4;

[0065] S3.2. Establish the linear programming constraints of the timing analysis model. The constraint formula is:

[0066] (1),

[0067] Among them, Max time represents the maximum time delay between adjacent triggers, Min time represents the minimum time delay between adjacent triggers, TCQ represents the time for data to be transferred from the input end to the output end of each trigger after being triggered by the sampling clock, Tsetup represents the time for each trigger to be established, and Thold represents the holding time of each trigger; for the above timing analysis model, the unknown variables are the transmission delay T3, the receiving time T4 and the clock period P, because the routing route from CLK to the trigger is unknown;

[0068] S3.3. With the goal of maximizing the clock cycle, obtain the results of the linear programming through existing linear programming solving tools (such as CPLEX, Gurobi, MATLAB, etc.), and obtain the clock delays T3 and T4 of adjacent flip-flops, as well as the maximized P;

[0069] S3.4. Take the average value of the clock delay of all triggers in the node as the expected arrival time of the clock signal of the node, and mark the expected arrival time of the clock signal of each node to Figure 2 In the graph structure of Figure 5 The partition layout diagram with the expected arrival time of the clock is shown. Figure 5 The expected arrival time of the clock signal at each node is only used for illustration.

[0070] S4. Extract two nodes with the shortest expected arrival time of the two clock signals from the nodes, and calculate a virtual circle with the two nodes as the center based on the expected arrival time of the clock signals of the two nodes and the path delay of the shortest path of signal transmission, merge the two nodes to form a new node, and use the position of the original node closest to the tangent point of the two virtual circles as the position of the new node. The specific steps are as follows:

[0071] S4.1. Mark all nodes as nodes that have not completed clock routing;

[0072] S4.2. Extract the two nodes with the shortest expected arrival time of the clock signal from all the nodes that have not completed the clock routing, and find the shortest routing path between the two nodes, where the short routing path refers to the routing path with the shortest delay;

[0073] S4.3. Calculate the expected arrival time of the clock signal of the new node after the two nodes are merged. The calculation formula is:

[0074] Tex ij = ( Tex i + Tex j + Tex i→j) / twenty two);

[0075] in, Tex i and Tex j Respectively represent the extracted numbers i and j The expected arrival time of the clock signals of the two nodes is Tex i→j Indicates the number i and j The delay of the shortest routing path between two nodes, Tex ij Indicates the number i and j The expected arrival time of the clock signal of the node after the two nodes are merged;

[0076] S4.4. Calculate the radius of the two virtual circles, and draw a virtual circle with the two nodes as the center, and find the position of the node closest to the tangent point of the two virtual circles as the position of the new node. The calculation formula of the radius of the virtual circle is:

[0077] r i = Tex ij - Tex i (3);

[0078] r j = Tex ij - Tex j (4);

[0079] in, r i and r j Respectively represent the extracted numbers i and j The radius of the virtual circle with the two nodes as the center;

[0080] S4.5. Mark the two nodes before merging as nodes that have completed clock routing, and mark the new node formed by the merger as a node that has not completed clock routing.

[0081] S5. Determine whether the number of remaining nodes is 1. If not, return to S4. If it is 1, enter S6. In this process: Figure 5Taking the split layout diagram with the marked expected arrival time of the clock as an example, assuming that node C is the clock source point, the two nodes with the shortest expected arrival time of the clock signal are node D and node F, and the shortest path between the two nodes is DGF. The expected arrival time of the clock signal of the new node after the two nodes are merged is calculated as: (0+1+4+2) / 2=3.5, the radius of the virtual circle with node D as the center is 3.5-0=3.5, and the radius of the virtual circle with node F as the center is 3.5-1=2.5. Draw two virtual circles, and the node closest to the tangent point of the two virtual circles is node G. Therefore, merge node D and node F into a new node DF. The position of the new node is the same as that of node G. The expected arrival time of the clock of the new node is 3.5. The way of merging nodes is as follows Figure 6 As shown, nodes D and F are marked as nodes that have completed clock routing, and node DF is marked as a node that has not completed clock routing.

[0082] At this time, the two nodes with the shortest expected arrival time of the clock signal are node A and node B, and the shortest path between the two nodes is ACB. The expected arrival time of the clock signal of the new node after the two nodes are merged is calculated as: (2+3+3+2) / 2=5. The radius of the virtual circle with node A as the center is 5-2=3, and the radius of the virtual circle with node B as the center is 5-3=2. Draw two virtual circles, and the node closest to the tangent point of the two virtual circles is node C. Therefore, merge node A and node B into a new node AB. The position of the new node AB is the same as that of node C. The expected arrival time of the clock of the new node AB is 5. Mark nodes A and B as nodes that have completed clock routing, and mark node AB as a node that has not completed clock routing, such as Figure 7 shown.

[0083] At this time, the two nodes with the shortest expected arrival time of the clock signal are node DF and node E, and the shortest path between the two nodes is DF-E. The expected arrival time of the clock signal of the new node after the two nodes are merged is calculated as: (3.5+4+3) / 2=5.25. The radius of the virtual circle with node DF as the center is 5.25-3.5=1.75, and the radius of the virtual circle with node E as the center is 5.25-4=1.25. Draw two virtual circles, and the node closest to the tangent point of the two virtual circles is node E. Therefore, merge node DF and node E into a new node DFE. The position of the new node DFE is the same as that of node E. The expected arrival time of the clock of the new node DFE is 5.25. Mark nodes DF and node E as nodes that have completed clock routing, and mark node DFE as a node that has not completed clock routing, such as Figure 8 shown.

[0084] At this time, the two nodes with the shortest expected arrival time of the clock signal are node AB and node G, and the shortest path between the two nodes is AB-DFE-G. The expected arrival time of the clock signal of the new node after the two nodes are merged is calculated as: (5+5+1+3) / 2=7. The radius of the virtual circle with node AB as the center is 7-5=2, and the radius of the virtual circle with node G as the center is 7-5=2. Draw two virtual circles, and the node closest to the tangent point of the two virtual circles is node DFE. Therefore, merge node AB and node G into a new node ABG. The position of the new node ABG is the same as that of node DFE. The expected arrival time of the clock of the new node ABG is 7. Mark nodes AB and node G as nodes that have completed clock routing, and mark node ABG as a node that has not completed clock routing, such as Fig. 9 As shown, at this time, the positions of node ABG and node DFE are both on the original node E. Therefore, node ABG and node DFE are merged to the position of the original node E to form a new node ABGDFE. At this time, all nodes except the clock source point converge to the position of node E.

[0085] S6. The clock signal starts from the clock source and is routed in the reverse order of the node merging order. The clock signal starts from the clock source and first reaches the location of the node ABGDFE. Because the node ABGDFE is formed by the merger of ABG and DFE, their locations are both node E, so the clock signal remains in E; then, the ABG node is formed by the merger of nodes AB and G, and the clock signal is separated into two directions from the E node location, and reaches the location of the node AB, that is, the location of the C node, and the location of the G node according to the shortest path respectively; then, because the DFE node is formed by the merger of the DF and E nodes, the clock signal remains in E, and because the clock signal has been transmitted to G, two repeated transmissions are unnecessary, so no routing is required; finally, the AB node is composed of A and B, and the DF node is composed of D and F. The clock signal is transmitted in two directions to reach nodes A, B, D, and F respectively, completing the clock routing, and the effect is as follows Fig.10 As shown. Then we can get the weights Tclk of all the edges that the clock routing route passes through and the actual arrival time Tac of each node clock, Tclk=2+3+1+1+3+2+4=16;

[0086] Then calculate the cutting cost. The calculation formula of the cutting cost is:

[0087] Cost = α*Tclk + β*Slack_setup+ γ*Slack_hold (5),

[0088] Among them, Cost represents the cutting cost, Tclk represents the weight of all edges through which the clock signal is routed, the weight of the edge is the delay of signal transmission between sub-designs, Slack_setup represents the timing margin of the setup time recalculated according to the actual clock arrival time of each trigger, Slack_hold represents the timing margin of the hold time recalculated according to the actual clock arrival time of each trigger, α, β and γ all represent weight coefficients, and satisfy: α+ β+ γ= 1, α≥0, β≥0, γ≥0; the timing margin of the setup time Slack_setup and the timing margin of the hold time Slack_hold are calculated according to formula 1, and the calculation formula is:

[0089] Setup_slack = T4+P-TCQ-Max Time - T3 – Tsetup;

[0090] Slack_hold = TCQ + Min time + T3 - T4 - Thold.

[0091] The calculated cutting cost is used to judge the quality of the temporal segmentation.

[0092] The present invention is described in detail above in conjunction with the embodiments, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made according to the scope of application of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A time-driven segmentation cost calculation method, characterized in that: It includes the following steps: S1. Input the netlist after timing segmentation, abstract the sub-designs in the top layer into nodes, abstract the signal transmission relationship between the sub-designs into edges, and establish a graph structure. Each of the sub-designs contains at least one trigger, and adjacent triggers are connected by combinational logic and routing routes; S2. Based on the delay size on the combinational logic and routing route, the maximum time delay and minimum time delay between adjacent triggers are calculated respectively; S3. construct a timing analysis model between adjacent triggers, establish linear programming constraints of the timing analysis model based on the maximum time delay and the minimum time delay, solve the timing analysis model based on the linear programming constraints, and obtain the expected arrival time of the clock signal of each node; S4. Extract two nodes whose expected arrival time of two clock signals is the shortest from the nodes, and calculate a virtual circle with the two nodes as the center based on the expected arrival time of the clock signals of the two nodes and the path delay of the shortest path of signal transmission, merge the two nodes to form a new node, and use the position of the original node closest to the tangent point of the two virtual circles as the position of the new node; S5. Determine whether the number of remaining nodes is 1. If not, return to S4. If it is 1, proceed to S6. S6. The clock signal starts from the clock source and is routed in the reverse order of the node merging order. The weights of all edges passed by the clock routing route and the actual arrival time of each node clock are obtained, and the cutting cost is calculated. The calculated cutting cost is used to judge the quality of timing segmentation. The calculation formula of the cutting cost is: （5）， Among them, Cost represents the cutting cost, Tclk represents the weight of all edges through which the clock signal is routed, the weight of the edge is the delay of signal transmission between sub-designs, Slack_setup represents the timing margin of the setup time recalculated according to the actual clock arrival time of each trigger, Slack_hold represents the timing margin of the hold time recalculated according to the actual clock arrival time of each trigger, α, β and γ all represent weight coefficients, and satisfy: α+ β+ γ= 1, α≥0, β≥0, γ≥0; The calculation formulas for the setup time timing margin Slack_setup and the hold time timing margin Slack_hold are: Setup_slack = T4+P-TCQ-Max Time - T3 – Tsetup; Slack_hold= TCQ + Min time + T3 - T4 – Thold; Where P is the clock period, T3 is the clock delay from the clock source to the previous trigger, T4 is the clock delay from the clock source to the next trigger, TCQ represents the time for data to be transferred from the input to the output of each trigger after being triggered by the sampling clock, Max time represents the maximum time delay between adjacent triggers, Min time represents the minimum time delay between adjacent triggers, Tsetup represents the setup time of each trigger, and Thold represents the hold time of each trigger.

2. The time-driven segmentation cost calculation method according to claim 1, characterized in that: The specific steps of S2 calculating the maximum time delay and the minimum time delay between adjacent triggers are: S2.

1. Traverse all signal transmission paths between adjacent triggers; S2.

2. Add the delay size of the combinatorial logic contained in each signal transmission path and the delay size on the routing route to form the delay size of each signal transmission path; S2.

3. Take the maximum and minimum values ​​of the signal transmission path delay as the maximum time delay and minimum time delay between adjacent triggers respectively.

3. The time-driven segmentation cost calculation method according to claim 1, characterized in that: The specific steps of constructing a timing analysis model between adjacent triggers in S3 are: S3.

1. Set the clock source and clock period P. The two ends of the clock source are connected to two adjacent triggers respectively. The clock delay from the clock source to the previous trigger is T3, and the clock delay from the clock source to the next trigger is T4.

4. The time-driven segmentation cost calculation method according to claim 3, characterized in that: The specific steps of S3 for establishing the linear programming constraint conditions of the timing analysis model based on the maximum time delay and the minimum time delay are: S3.

2. Establish the linear programming constraints of the timing analysis model. The constraint formula is: （1）。 5. The time-driven segmentation cost calculation method according to claim 4, characterized in that: In S3, the timing analysis model is solved with the goal of maximizing the clock period to obtain the expected arrival time of the clock signal of each sub-design. The specific steps are: S3.

3. Obtain the result of linear programming by using a linear programming solver to obtain the clock delay of adjacent flip-flops; S3.

4. The average of the clock delays of all flip-flops in a node is taken as the expected arrival time of the clock signal of the node.

6. The time-driven segmentation cost calculation method according to claim 1, characterized in that: The specific steps of S4 are: S4.

1. Mark all nodes as nodes that have not completed clock routing; S4.

2. Extract the two nodes with the shortest expected arrival time of the clock signal from all the nodes that have not completed the clock routing, and find the shortest routing path between the two nodes, where the shortest routing path refers to the routing path with the shortest delay; S4.

3. Calculate the expected arrival time of the clock signal of the new node after the two nodes are merged. The calculation formula is: Tex ij =（ Tex i + Tex j + Tex i→j ） / 2 （2）； in, Tex i and Tex j Respectively represent the extracted numbers i and j The expected arrival time of the clock signals of the two nodes is Tex i→j Indicates the number i and j The delay of the shortest routing path between two nodes, Tex ij Indicates the number i and j The expected arrival time of the clock signal of the node after the two nodes are merged; S4.

4. Calculate the radius of the two virtual circles, and draw a virtual circle with the two nodes as the center, and find the position of the node closest to the tangent point of the two virtual circles as the position of the new node. The calculation formula of the radius of the virtual circle is: r i = Tex ij - Tex i （3）； r j = Tex ij - Tex j （4）； in, r i and r j Respectively represent the extracted numbers i and j The radius of the virtual circle with the two nodes as the center; S4.

5. Mark the two nodes before merging as nodes that have completed clock routing, and mark the new node formed by the merger as a node that has not completed clock routing.

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