3D chip layout model, construction method thereof and 3D chip layout method

Abstract

The invention discloses a 3D chip layout model, a construction method thereof and a 3D chip layout method, and relates to the technical field of 3D chip physical design. The 3D chip layout model comprises a first sub-model and a second sub-model, the Kth iteration result of the first sub-model is used as the iteration input parameter of the Kth iteration of the second sub-model, the Kth iteration result of the second sub-model is used as the iteration input parameter of the (K + 1) th iteration of the first sub-model, and K is greater than or equal to 1; the first sub-model is used for determining hierarchical coordinates of each unit according to network information and horizontal coordinates of each unit on the basis of the shortest line length and the minimum terminal rule, and the network information comprises unit information forming the network; and the second sub-model is used for performing iterative optimization calculation on the integrated horizontal coordinate according to the hierarchical coordinate and the line network information of each unit. By adopting the 3D chip layout model, better unit coordinates and terminal quantity can be determined, and better layout planning of the 3D chip is realized.

Description

Technical Field

[0001] The present application relates to the technical field of 3D chip physical design, and in particular to a 3D chip layout model and a construction method thereof, and a 3D chip layout method. Background Art

[0002] With the advancement of advanced process nodes, the scale of nano-scale chip basic devices has reached billions. Compared with traditional 2D chips (two-dimensional integrated circuits), 3D chip (three-dimensional integrated circuit) technology has attracted a lot of attention due to its advantages in chip design. Compared with 2D chips, 3D chips can provide higher integration density, shorter wire length and better energy efficiency.

[0003] The integrated circuit layout design is developing towards large-scale, multiple design constraints and goals, and close connection between front-end and back-end design processes. First, the design process that uses 2D chip physical design process to achieve pseudo 3D effect often leads to poor quality of layout design results.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of this application is to provide an invention title, which aims to solve the technical problem of poor quality of 3D chip physical design results in related technologies.

[0006] To achieve the above object, the present application proposes a 3D chip layout model, the 3D chip layout model includes a first sub-model and a second sub-model, the first sub-model includes a function representing the relationship between the wire mesh length and the unit coordinates and the terminal coordinates, the second sub-model includes an iterative function of the integrated horizontal coordinates, wherein the integrated horizontal coordinates include the horizontal coordinates of each unit and the terminal coordinates;

[0007] The K-th iteration result of the first sub-model is used as the iteration input parameter of the K-th iteration of the second sub-model, and the K-th iteration result of the second sub-model is used as the iteration input parameter of the K+1-th iteration of the first sub-model, K≥1;

[0008] The first sub-model is used to determine the hierarchical coordinates of each of the units according to the wire net information and the horizontal coordinates of each of the units based on the shortest wire length and the least terminal rules, wherein the wire net information includes the unit information constituting the wire net;

[0009] The second sub-model is used to perform iterative optimization calculation on the integrated horizontal coordinates according to the hierarchical coordinates of each of the units and the wire mesh information;

[0010] Each of the units of the 3D chip layout model is allocated to one wafer and a 2D layout solution obtained by doubling a memory density threshold is used as an initial horizontal coordinate of each of the units.

[0011] In one embodiment, the first sub-model includes a traversal adjustment module and a first optimization module;

[0012] The traversal adjustment module is used to traverse and adjust the level coordinates of each unit;

[0013] The first optimization module is used to obtain the adjustment benefit parameter of each of the units according to a preset evaluation algorithm, and determine the optimization level coordinates of each of the units based on the adjustment benefit parameter of each of the units;

[0014] The second sub-model is also used for hierarchically optimizing the horizontal coordinates of each of the units according to the optimized hierarchical coordinates of each of the units.

[0015] In one embodiment, the 3D chip layout model further includes a third sub-model, and the third sub-model includes a partitioning module and an optimization module;

[0016] The division module is used to divide each metal layer of the wafer into grids, and obtain the resources of each grid according to the wiring track information and the effective utilization rate of each grid, wherein the resources of the grid are the number of wiring tracks covered by the grid;

[0017] The optimization module is used to determine the prior probability distribution of each of the wire nets according to the demand of each of the wire nets, determine the congestion area according to the prior probability distribution and the resources of each of the squares, determine the posterior probability distribution of each of the wire nets according to the congestion area and the prior probability distribution, and use the posterior probability distribution of each of the wire nets as a resource weight graph to perform routing optimization operations, wherein the demand of each of the wire nets is determined based on the length of the rectangular Steiner minimum tree, and the routing optimization operation includes merging the resource weight graph with the congestion graph to generate a routing weight graph for the wire net; determining the next routing distribution according to the routing weight graph, updating the congestion graph based on the determined routing distribution, and returning to execute the step of merging the resource weight graph with the congestion graph to generate a routing weight graph for the wire net.

[0018] In one embodiment, the optimization module is further used to obtain pin information of each of the chips, establish a 3D minimum weight Steiner tree according to the pin information and the wiring weight graph, and obtain global wiring information.

[0019] In one embodiment, the 3D chip layout model further includes a fourth sub-model;

[0020] The fourth sub-model is a terminal allocation model constructed based on the minimum cost weighted bipartite graph matching problem, and the fourth sub-model is used to optimize the coordinates of each terminal, wherein the cost is calculated based on the minimum spanning tree length between the unit pins of the wire network and the terminal set, and each wire network has a maximum number of terminals with restricted matching.

[0021] In a second aspect, the present application also provides a method for constructing a 3D chip layout model, the method comprising:

[0022] Based on the wire length feature in the 3D chip layout, the wire net, the unit coordinates and the terminal coordinates are defined to construct an initial definition model of the 3D chip wire net, wherein the first planning model includes a first objective function and a first constraint function, the first objective function is a function representing the relationship between the wire length of the wire net and the unit coordinates and the terminal coordinates, and the first constraint function includes a unit area constraint function, a grid density constraint function and a terminal quantity constraint function;

[0023] Dividing the coordinate variables in the initial definition model into horizontal coordinate variables and hierarchical coordinate variables to construct a two-level programming model;

[0024] A 3D chip layout model is constructed according to the double-layer planning model and the horizontal coordinate iteration model, wherein the horizontal coordinate iteration module is an iteration model constructed based on a two-dimensional layout planning method.

[0025] In a third aspect, the present application further provides a 3D chip layout method, the method comprising:

[0026] Acquire input parameters, wherein the input parameters include wire mesh information, and the wire mesh information includes unit information constituting the wire mesh;

[0027] Inputting the input parameters into a 3D chip layout model so that the 3D chip layout model performs iterative calculation until a preset iterative convergence condition is satisfied, wherein the 3D chip layout model is the 3D chip layout model described in the first aspect;

[0028] When a preset iteration convergence condition is met, target layout information is determined according to the iteration result of the 3D chip layout model, and the target layout information includes unit coordinates and the number of terminals.

[0029] In one embodiment, the iteration convergence condition is that the number of iterations of the 3D chip layout model reaches a preset threshold.

[0030] In a fourth aspect, the present application further provides a computer device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the method for constructing a 3D chip layout model as described in the second aspect or the steps of the 3D chip layout method as described in the third aspect.

[0031] In a fifth aspect, the present application further provides a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and the computer program is configured to implement the method for constructing a 3D chip layout model as described in the second aspect or the steps of the 3D chip layout method as described in the third aspect.

[0032] The above-mentioned 3D chip layout model includes a first sub-model and a second sub-model. By allocating each unit of the 3D chip layout model to a chip and doubling the memory density threshold to obtain a 2D layout solution as the initial horizontal coordinate of each unit, the first sub-model can determine the hierarchical coordinates of each unit based on the shortest line length and the least terminal rules according to the wire network information and the horizontal coordinates of each unit, and the second sub-model can iteratively optimize and calculate the integrated horizontal coordinates according to the hierarchical coordinates and wire network information of each unit. Since the Kth iteration result of the first sub-model is used as the iteration input parameter of the Kth iteration of the second sub-model, and the Kth iteration result of the second sub-model is used as the iteration input parameter of the K+1th iteration of the first sub-model, the first sub-model and the second sub-model realize the solution of each unit coordinate and the number of terminals by alternating optimization and solving. After multiple iterative solutions, the better unit coordinates and the number of terminals can be determined to achieve a better layout planning for the 3D chip.

[0033] The above-mentioned method for constructing a 3D chip layout model constructs an initial definition model of the 3D chip network based on the line length features in the 3D chip layout, and then constructs a double-layer planning model by dividing the coordinate variables into horizontal coordinate variables and hierarchical coordinate variables. After dividing the horizontal coordinate variables and the hierarchical coordinate variables, the horizontal coordinate variables and the hierarchical coordinate variables can be solved by alternating optimization. Therefore, the 3D chip layout model can be constructed according to the double-layer planning model and the horizontal coordinate iteration model, so that the constructed 3D chip layout model can realize the solution of each unit coordinate and terminal coordinate by alternating optimization solution. After multiple iterative solutions, the better unit coordinates and terminal coordinates can be determined.

[0034] The above-mentioned 3D chip layout method, computer device and storage medium obtain the initial horizontal coordinates through a 2D solution method. The initial horizontal coordinates are the 2D layout solution obtained by allocating each unit of the 3D chip to a chip and doubling the memory density threshold. The initial horizontal coordinates are then input into the 3D chip layout model for iterative calculation, thereby realizing iterative solution of each unit coordinate and terminal coordinate through the 3D chip layout model in an alternating optimization solution manner. When the preset iterative convergence conditions are met, the 3D chip layout model can obtain a better iterative result, so that a better unit coordinate and terminal quantity can be determined based on the iterative result. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0037] Figure 1 A schematic diagram of a process for 3D design using a 2D chip physical design process in related technologies;

[0038] Figure 2 This is a structural schematic diagram of a 3D chip layout model in an embodiment of the present application;

[0039] Figure 3 This is a schematic diagram of the structure of a 2D wire mesh and a 3D wire mesh in an embodiment of the present application;

[0040] Figure 4 This is a schematic diagram of the principle of optimizing wiring in one embodiment of the present application;

[0041] Figure 5 A schematic diagram of the principle of determining routing according to a wiring weight graph in one embodiment of the present application;

[0042] Figure 6 This is a schematic diagram of the principle of optimizing the terminal position in one embodiment of the present application;

[0043] Figure 7 Schematic diagram of a process for constructing a 3D chip layout model in an embodiment of the present application;

[0044] Figure 8 This is a flow chart of a 3D chip layout method according to an embodiment of the present application;

[0045] Fig. 9This is a schematic diagram of the module structure of the 3D chip layout device according to an embodiment of the present application;

[0046] Fig.10 Schematic diagram of the device structure of the hardware operating environment involved in the 3D chip layout method in the embodiment of the present application.

[0047] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0048] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0049] At present, with the advancement of advanced process nodes, integrated circuit layout design is developing towards a trend of large-scale, multiple design constraints and goals, and close connection between front-end and back-end design processes. First of all, the scale of nano-scale chip basic devices has reached billions, so the demand for fast and efficient 3D chip physical design tools such as face-to-face bonding stacking (F2F) is becoming more and more urgent. The heterogeneous manufacturing requirements in 3D chips make it crucial to study physical design technologies that support good heterogeneous designs; currently, physical design EDA tools that can meet the requirements of the above trends are still in their infancy. Similar to the physical design of 2D chips, the main concerns of 3D chip physical design are performance, power consumption, area, and cost (Performance-Power-Area-Cost, referred to as PPAC). However, due to the lack of support for 3D chip physical design tools and technologies in the entire EDA (Electronic design automation) industry, such as Figure 1 As shown, currently, 2D chip design tools and technologies are mainly used for 3D chip physical design, and certain 3D factors are considered and optimized during the design process.

[0050] However, the design process of achieving a pseudo 3D effect by calling a 2D chip physical design process often results in poor quality of layout design results.

[0051] Based on this, Figure 2 As shown, an embodiment of the present application provides a 3D chip layout model 1, the 3D chip layout model 1 includes a first sub-model 11 and a second sub-model 12, the first sub-model 11 includes a function representing the relationship between the wire network length and the unit coordinates and the terminal coordinates, the second sub-model 12 includes an iterative function of an integrated horizontal coordinate, wherein the integrated horizontal coordinate includes the horizontal coordinates of each unit and the terminal coordinates.

[0052] The Kth iteration result of the first sub-model 11 is used as the iteration input parameter of the Kth iteration of the second sub-model 12, and the Kth iteration result of the second sub-model 12 is used as the iteration input parameter of the K+1th iteration of the first sub-model 11, K≥1.

[0053] The first sub-model 11 is used to determine the hierarchical coordinates of each unit based on the shortest line length and the least terminal rules according to the wire mesh information and the horizontal coordinates of each unit, wherein the wire mesh information includes the unit information constituting the wire mesh. The second sub-model 12 is used to perform iterative optimization calculation on the integrated horizontal coordinates according to the hierarchical coordinates of each unit and the wire mesh information.

[0054] Each unit of the 3D chip layout model 1 is allocated to one wafer and a 2D layout solution obtained by doubling the memory density threshold is used as the initial horizontal coordinate of each unit.

[0055] In the application, the relational function included in the first sub-model 11 is expressed as the following sub-problem 1, and the iterative function included in the second sub-model 12 can be expressed as the following sub-problem 2.

[0056] Sub-question 1:

[0057]

[0058] Sub-question 2:

[0059]

[0060] The 3D chip layout model 1 can be applied to the layout design of F2F chips. The following takes the F2F chip layout as an example to illustrate the process of determining sub-problems 1 and 2. The F2F chip layout problem requires that the cells be allocated to two layers of wafers (Die), and bonding terminals be created for cross-layer connection to connect the upper wafer and the lower wafer of the interconnection network. Therefore, after determining the relevant information of the 3D wire network, the number of terminals can be determined based on the information of the 3D wire network. Define H = (V, E) to represent the wire network connecting the cells, where the cells are represented by the set V = {c 1 , c 2 , ..., c n} indicates that unit c i The coordinates are expressed as (x i ,y i , z i ), where x i ,y i Represents the horizontal coordinate, z i ∈{0, 1} represents the layer where the unit is located, that is, the level coordinate. Figure 3 As shown, the 2D wire mesh is located on a single chip, and the 3D wire mesh is connected across layers. The wire mesh can be represented by the set E = {e 1 , e 2 , ..., em} means that if e j ∈E contains the top (corresponding to the top layer) and the bottom (corresponding to the bottom layer) cells, then it is a 3D wire mesh. and To represent the 3D line network j ∈E. The set T = {t 1 , t 2 , ..., t m} is used to indicate the terminal set used by the 3D wire network. Indicates terminal t j The coordinates of WL t (e j ; ·) and WL(e j ; ·) represents the wire network e j The line length in 3D and 2D forms respectively. The line length of the 3D line network is equal to the sum of its line length in the bottom substrate part and the line length in the top substrate part. Their relationship is defined as follows:

[0061]

[0062] in,

[0063] Then, the F2F layout can be expressed as the following optimization problem (1).

[0064] Optimization problem (1):

[0065]

[0066] Among them, D b (·) represents the density of the grid (bin) b and M b is the threshold density of grid b, S b is the collection of all grids in the top, bottom, and terminal layers. A 1 (c i ) and A 0 (c i ) represents unit c i The area of ​​the top and bottom floors, is an indicative function. In addition, ρ represents the cost of a terminal, u t and u b Indicates the area utilization of the upper and lower wafers. A refers to the area of ​​the upper and lower wafers, and N t is the upper limit of the number of available terminals, ε(e j ; z) = 1 means that the line network needs 1 terminal to connect the upper and lower layers of chips.

[0067] It can be understood that the optimization goal of the optimization problem (1) is mainly to optimize the 3D line length and the number of terminals. Constraint (1.1) indicates that the density of each grid bin cannot exceed the preset threshold density M. b Constraints (1.2) and (1.3) indicate that the unit area of ​​the upper and lower wafers cannot exceed the area multiplied by the utilization factor. Constraint (1.4) indicates that the number of terminals used cannot exceed N. t .

[0068] Since the optimization problem (1) has nonlinear objectives and integer variables, it is very challenging to solve it directly. The partition-based algorithm in the related art is easy to solve, but loses the globality of the solution space. Therefore, a modeling method that is easy to solve and retains the integrity of the solution space is necessary. By analyzing the original optimization problem, we can know that WL t (·) is the key to the calculation. Fortunately, once the level coordinate (the level where the unit is located) z is determined, the function becomes easy to calculate, and the remaining subproblems are similar to the traditional layout problem. Therefore, there is a dominance relationship between the decision variables, which corresponds to the definition of bilevel programming. The variables of the inner optimization problem can be defined as x l =(x,y,x t ,y t ), and the outer optimization problem variable is z, so the objective function of the optimization problem (1) can be rewritten as:

[0069]

[0070] The inner optimization problem can be defined as follows:

[0071]

[0072] In addition, the solution to the above problem There is F(x l , z) = g(z), where

[0073]

[0074] Using this property, this scheme can transform the F2F layout optimization problem (1) into the following form of optimization problem (2):

[0075]

[0076] stx l ∈Ψ(z),

[0077]

[0078] It must be pointed out that evaluating g(z) is very time-consuming, so this plan will construct a proxy function The proxy function contains two parameters, the unit and the horizontal position x of the terminal. l , and the vertical coordinate z of the cell. In addition, as shown above, the constraint and objective functions are separable because x l It has no effect on the objective and other constraints. Therefore, this plan divides the original problem into subproblem 1 and subproblem 2, and replaces the objective function of subproblem 1 with The above-mentioned sub-problems 1 and 2 can be obtained.

[0079] It can be understood that the first sub-model 11 can be constructed based on sub-problem 1, and the second sub-model 12 can be constructed based on sub-problem 2. The initial horizontal coordinates of each unit are used as the horizontal coordinates of each unit in the first sub-model 11, and the hierarchical coordinates of each unit can be determined through the horizontal coordinates of each unit to achieve the initial iteration of the hierarchical coordinates. The second sub-model 12 can receive the hierarchical coordinate information after the iteration, and can perform iterative optimization calculation on the integrated horizontal coordinates according to the hierarchical coordinates and wire network information of each unit, so as to further optimize the integrated horizontal coordinates. The first sub-model 11 and the second sub-model 12 can solve the coordinates of each unit and the number of terminals by alternating optimization solutions. After multiple iterative solutions, the better unit coordinates and the number of terminals can be determined to achieve a better layout planning for the 3D chip.

[0080] The above-mentioned 3D chip layout model 1 includes a first sub-model 11 and a second sub-model 12. By allocating each unit of the 3D chip layout model 1 to a chip and doubling the memory density threshold to obtain a 2D layout solution as the initial horizontal coordinate of each unit, the first sub-model 11 can determine the hierarchical coordinates of each unit according to the wire network information and the horizontal coordinates of each unit based on the shortest wire length and the least terminal rules, and the second sub-model 12 can iteratively optimize and calculate the integrated horizontal coordinates according to the hierarchical coordinates and wire network information of each unit. Since the Kth iteration result of the first sub-model 11 is used as the iteration input parameter of the Kth iteration of the second sub-model 12, and the Kth iteration result of the second sub-model 12 is used as the iteration input parameter of the K+1th iteration of the first sub-model 11, the first sub-model 11 and the second sub-model 12 realize the solution of each unit coordinate and the number of terminals by alternating optimization and solving. After multiple iterations of solving, the better unit coordinates and the number of terminals can be determined to achieve a better layout planning for the 3D chip.

[0081] In one embodiment, the first sub-model 11 includes an ergodic adjustment module and a first optimization module.

[0082] The traversal adjustment module is used to traverse and adjust the hierarchical coordinates of each unit. The first optimization module is used to obtain the adjustment benefit parameters of each unit according to a preset evaluation algorithm, and determine the optimized hierarchical coordinates of each unit based on the adjustment benefit parameters of each unit.

[0083] It is understandable that in a 2D plane layout, the size of the region is still larger than the size of the grid bin, which may lead to inaccurate estimation of the proxy function. Therefore, in order to make the proxy function as accurate as possible. For performance and stability considerations, this application optimizes the hierarchical coordinates of each unit by traversing and adjusting the hierarchical coordinates of each unit and evaluating the adjusted benefits.

[0084] Specifically, the evaluation algorithm includes a priority function, which is a set function used to evaluate the benefits of moving units contained in the set S across the wafer. The priority function p(S) can be as follows:

[0085]

[0086] Where T(S) is the terminal coordinate set S determined during the acquisition process. In addition, when the hierarchical coordinates of a cell change, only the cells in the same network or the same area need to be re-evaluated. This is the key to reducing the number of calculations, and it can be parallelized. Next, in order to evaluate the benefits, this application gives a form based on discrete gradients as follows:

[0087]

[0088] Where ΔWL, Δ|BT| are the changes in line length and number of terminals, h r , A r , M r They represent the row height of region r, the total area of ​​the cells in the region, and the maximum available area respectively. It is unit c i The discrete gradient of the priority function above analyzes several factors that may affect the result, including total bus length and number of terminals, area overflow within a region, and overlap between cells.

[0089] Based on the above-mentioned priority function and its discrete gradient form, an evaluation algorithm can be constructed to evaluate the adjusted benefit parameters of each unit. The first optimization module can obtain the adjusted benefit parameters of each unit according to a preset evaluation algorithm, and determine the optimization level coordinates of each unit based on the adjusted benefit parameters of each unit.

[0090] The second sub-model 12 is also used to hierarchically optimize the horizontal coordinates of each unit according to the optimized hierarchical coordinates of each unit.

[0091] It can be understood that after determining the optimized hierarchical coordinates of each unit, the layer where each unit is located can be determined, and then the 2D layout specification method can be used to optimize the horizontal coordinates of each unit separately in layers to achieve layered horizontal coordinate optimization, and then achieve iterative calculation of integrated horizontal coordinates. Therefore, the first sub-model 11 and the second sub-model 12 achieve the solution of each unit coordinate and the number of terminals through alternating optimization solutions. After multiple iterative solutions, the optimal unit coordinates and terminal number can be determined to achieve a better layout planning for the 3D chip.

[0092] In the application, after determining the coordinates of each unit, that is, after placing all units, it is necessary to determine the position of the terminal. The terminal legalization problem can be expressed as the following problem (3):

[0093]

[0094] It should be noted that the objective functions between different terminals do not affect each other. In other words, the objective functions can be calculated separately. In addition, all terminals are the same size. Due to these two factors, if the coordinates of all terminals in this application are restricted to an integer multiple C of the spacing constraint, an optimal solution for weighted bipartite graph matching can be obtained. Specifically, by dividing the layout into uniform square grids with a length of C. Then, k candidate grids are selected for each terminal around its terminal optimal region (TOR). The cost of a candidate grid is the Manhattan distance to its TOR. Therefore, part of the bipartite graph is a candidate grid, and the other part is defined as a terminal. The above method can preliminarily determine the number and position of the terminals, thereby realizing the routing planning of the wire network.

[0095] In one embodiment, the 3D chip layout model 1 further includes a third sub-model, and the third sub-model includes a partitioning module and an optimization module.

[0096] The partitioning module is used to divide each metal layer of the wafer into grids, and obtain the resources of each grid according to the wiring track information and the effective utilization rate of each grid, wherein the resources of the grid are the number of wiring tracks covered by the grid.

[0097] In F2F chip design, the metal wires of each chip are usually placed on a routing track. There are evenly distributed routing tracks on different metal layers, and the routing track information is often known. In the global routing stage, the entire design is divided into grids (GCell). The resources occupied by a grid correspond to the number of routing tracks covered by this grid. The track resources of the metal wiring layer of each chip are pressed onto the chip where it is located to form two planar grids, and the bonding terminal layer is a separate layer. In global routing, the wire nets are assigned to available routing tracks evenly distributed on different layers. Each GCell contains multiple routing tracks, which are used as initial resources. According to the design rules, there are some routing obstacles on the layout, which will block the routing resources on one or more layers and make these areas unable to be routed. Therefore, it is necessary to consider the impact of these obstacles on GCell resources, as shown below:

[0098]

[0099] where r i is the routing track resource (referred to as resource) of the i-th GCell, g i ∈G, G is the set of GCells. Num(track i ) is g i The number of routing tracks in Area(g i ) and Area(obs i ) are g i The area and g i The effective utilization rate is 1-g i Obstacle area / g i The area in .

[0100] The optimization module is used to determine the prior probability distribution of each network according to the demand of each network, determine the congestion area according to the prior probability distribution and the resources of each grid, determine the posterior probability distribution of each network according to the congestion area and the prior probability distribution, and use the posterior probability distribution of each network as the resource weight map to perform routing optimization operations, wherein the demand of each network is determined based on the length of the rectangular Steiner minimum tree, and the routing optimization operation includes merging the resource weight map with the congestion map to generate a wiring weight map for the network; determining the next routing distribution according to the wiring weight map, updating the congestion map based on the determined routing distribution, and returning to execute the step of merging the resource weight map with the congestion map to generate a wiring weight map for the network.

[0101] like Figure 4As shown in the figure, the two rectangles on the far left represent the routing probability distribution diagrams of the nets n1 and n2, that is, the prior probability distribution. In the initial stage, the prior probability distribution of each net is uniform, but the prior probability distributions of n1 and n2 overlap. Each GCell in the chip is not uniform. If n1 and n2 are routed to the overlapping area, congestion is likely to occur. Therefore, the probability distribution is adjusted according to the congested area and the prior probability distribution, and the posterior probability distribution of each net can be determined, as shown in Figure 4 As shown in the figure on the right, through resource allocation, the total demand distribution of GCells in the entire chip is relatively uniform, while the demand for line network n 1 and n 2 , the distribution of uniform demand in the initial stage to the posterior distribution of differentiated demand in the right figure can allocate resources more evenly and avoid congestion. In addition, the differentiated distribution of wire nets after resource allocation can be used to guide subsequent wiring, and the wire net demand can be converted into the corresponding weight map.

[0102] It should be noted that Figure 4 In the figure, the darker the color, the greater the demand. In the initial stage, the left line network n 1 and n 2 The demand prior distribution of is uniform. In the overlapping area, the total demand of GCell is equal to the sum of the demands of the network it covers. 1 and g 2 The total demand exceeds the available resources, resulting in routing congestion. After iterative optimization of resource allocation, the resources in the GCell in the right figure will be more reasonably allocated to different wire nets.

[0103] Among them, the line network n j The demand of ∈N (N is the set of nets) is determined by the total routing length of the rectangular Steiner tree after routing. The length of the rectangular Steiner minimum tree (RSMT) is used as the demand of each net, which will serve as a lower bound on the final routing length of the net. Net n j Demand j The calculation is as follows:

[0104] d j =WL(RSMT j )

[0105] It can be seen that WL(RSMT j ) is the wire network n j In order to obtain an actual requirement that is closer to the final wiring requirement, the present application counts the total length of all wire nets after wiring.

[0106] From the analysis of a global routing result with good detailed routing performance, the results of the wire net routing in the design are evenly superimposed on the plane grid, so that all routing results in the design can have enough resources for detailed routing to avoid congestion, and the resources in the GCell will be used more reasonably. Therefore, it is necessary to guide the routing results of each wire net to be even after being superimposed globally. During the routing process, the wire nets will be routed in a certain order, and the order will have an impact on the wire net routing. By pre-allocating the wire nets with their routable virtual resources and converting this virtual resource into a resource cost map during routing, routing conflicts can be resolved before routing, thereby avoiding congestion.

[0107] Specifically, the optimization module can obtain the demand of each network based on the aforementioned calculation method, and can determine the prior probability distribution of each network according to the demand of each network, wherein the prior probability distribution of the network is the routing probability map of the network, and the sum of the prior probability distribution of the network is equal to the demand of the network, and the demand of the network remains unchanged. It can be understood that in the application, the prior probability distribution of the network may overlap in the target area, and if the resources in the overlapping area are not sufficient to support the routing of the network, congestion may occur. Therefore, the prior probability distribution of each network and the resources of each grid can be used to determine the congested area. By reducing the probability of the congested area and increasing the routing probability of the unobstructed area (i.e., the non-congested area), the probability of wiring the network in the congested area can be reduced, thereby adjusting and reducing the probability of congestion in the congested area. That is, the probability distribution is adjusted according to the congested area and the prior probability distribution, and the posterior probability density of each network can be determined. As Figure 5 As shown in FIG. 1 , the posterior probability density of each network is used as a resource weight map. The resource weight map is combined with the congestion map to generate a wiring weight map of the network. Then, the next routing distribution is determined according to the wiring weight map.

[0108] It should be noted that the congestion map is a determined routing distribution. Therefore, after the next routing distribution is determined based on the routing weight map, the next routing is also determined. At this time, the congestion map needs to be updated based on the next routing distribution so that the resource weight map can be merged with the updated congestion map to determine the subsequent routing distribution.

[0109] In order to obtain the optimal demand posterior distribution for each network, this plan allocates the limited resources of GCell to its corresponding network. By analyzing the relationship between GCell resources and network demand, it is modeled as a mathematical programming problem as follows:

[0110]

[0111] In the above function, the objective function is to minimize the sum of the squares of the gap between the total allocated resources and the resources of each GCell. The constraint is that the sum of the allocated resources of the network covering the GCell should be equal to the total demand of the network. By solving the constraint programming problem, the resources of the GCell can be fully utilized while meeting the needs of all networks. i,j is the number of resources allocated to the j-th network on the i-th GCell, r i is the total number of resources of the i-th GCell, that is, the total demand of all networks on the i-th GCell should be close to the total number of GCell resources, so that the network can make full use of the resources of the GCell and will not exceed the resources that the GCell can provide. j is the jth network, and d j is the total demand of the jth network. In addition, the pre-allocation model should satisfy the constraint that the network demand remains unchanged. Resource pre-allocation does not reduce the demand of the network, that is, the total length of the network remains unchanged. The GCell set corresponding to the network is composed of the GCells covered by the BBox of this network.

[0112] The above optimization problem (4) can be transformed into the following problem (5). The optimization problem (5) is already a linear programming problem. This linear programming problem can be solved by a linear programming solver or algorithm, and then the pre-allocated resources of each network in each GCell area can be obtained, which can be used to guide network routing later.

[0113]

[0114] It can be understood that the optimization module can be constructed based on the above problem (5), so as to perform subsequent resource pre-allocation according to the prior probability distribution and the resources of each grid. After the resources are allocated, the posterior probability density of each network is used as the resource weight map. The resource weight map is merged with the congestion map to generate the wiring weight map of the network, so that the optimal routing planning of the network can be achieved according to the wiring weight map.

[0115] In one embodiment, the optimization module is further used to obtain pin information of each chip, establish a 3D minimum weight Steiner tree according to the pin information and the wiring weight graph, and obtain global wiring information.

[0116] The routing weight graph and pin coordinates are used to build a 3D minimum weight Steiner tree (RSMT). The tree is then decomposed into multiple two-pin nets and weighted A* routing is performed. The global routing process is as follows Figure 5 As shown, each 3D net and 2D net has its corresponding priority routing weight map in the chip layer where it is located. After the previous net is routed, the impact on the subsequent net will be updated.

[0117] To more accurately calculate the resources of each GCell, the number of resources in each horizontal / vertical direction in each wafer layer is determined by the number of routing tracks, and the resources used in the GCell are d. g . Through the demand of common through hole d via and wiring conductor requirements wire You can calculate d g , and then the congestion weight function W can be calculated c as follows:

[0118] d g =d wire +λ·d via

[0119]

[0120] The weight of GCell in this application needs to consider not only the routing congestion but also the result of resource allocation. In order to fully consider these effects, this application proposes an effective routing cost function Wg as follows, where W r is the resource weight function, c and r are the congestion and resource factors respectively.

[0121]

[0122] A global router using related technology can quickly obtain RSMT and establish a Steiner tree lookup table for a net with less than 9 points. However, the global router only uses a single Steiner tree topology for each point combination, which is not enough to meet the needs when processing different weights. To solve this problem, the present application will construct an improved lookup table that includes additional Steiner tree topologies. The Steiner lookup table of the present application can generate a more comprehensive Steiner tree topology for each point combination, thereby obtaining better results, and can find the minimum weighted Steiner tree under the optimal wire length. After obtaining the topology of the Steiner tree, it is decomposed into multiple dual-pin nets, and then 3D weighted A* routing is performed to obtain the global routing results.

[0123] In one embodiment, the 3D chip layout model 1 further includes a fourth sub-model.

[0124] The fourth sub-model is a terminal allocation model constructed based on the weighted bipartite graph matching problem with minimum cost. The fourth sub-model is used to optimize the coordinates of each terminal, wherein the cost is calculated based on the minimum spanning tree length between the unit pins of the wire network and the terminal set, and each wire network has a maximum number of terminals with restricted matching.

[0125] After the division and layout stage, 3D mesh and 2D mesh routing are required. The main difference between the routing process of 2D mesh and 3D mesh is the criticality of bonding terminals. Unlike traditional multi-metal layer routing, in F2F chip design, the units are divided into two different wafers. In this case, F2F chip routing requires inter-chip wafer connections through bonding terminals. On the other hand, the size and spacing of bonding terminals are much larger than the metal through-hole spacing, which makes the available terminal resources very limited. Therefore, terminal and mesh allocation become important factors affecting the quality of the final routing solution, such as Figure 6 As shown, Figure 6 The left picture is the 3D wire mesh without optimized terminal positions, and the right picture is the 3D wire mesh after optimizing terminal positions. It can be found that the wire length of the 3D wire mesh is significantly reduced. Terminal allocation can be naturally expressed as a weighted bipartite graph matching problem with minimum cost. First, a set of candidate bonding terminals is initialized. k ∈T represents the terminal, x ik Indicates terminal t k to n i The match of w ij Indicates the matching weight. In addition, this plan defines T i Indicates that it can be connected with the line network n i A collection of matching bonding terminals. This plan uses c(T i ) to indicate the allocation of T i The estimated wiring cost is determined by the wire net n i Pin and bonding terminal set T i The minimum spanning tree length between each network is approximately calculated. i There is a limit on the maximum number of bonding terminals u i The problem aims to find a match from the bonding terminal to the wire net so that the sum of the costs is minimized. The problem can be described as follows:

[0126]

[0127] x ik ∈{0,1}

[0128] The fourth sub-model can be constructed through the above functional relationship. The fourth sub-model can be optimized based on the number and positions of terminals preliminarily determined in the above-mentioned embodiment, and the positions of the terminals can be adjusted to further optimize the line length of the 3D wire network.

[0129] In one embodiment, the present application also provides a method for constructing a 3D chip layout model, such as Figure 7 As shown, the method for constructing the 3D chip layout model includes the following steps S701 to S703.

[0130] S701: Based on the wire length features in the 3D chip layout, the wire network, unit coordinates and terminal coordinates are defined, and an initial definition model of the 3D chip wire network is constructed, wherein the first planning model includes a first objective function and a first constraint function, the first objective function is a function representing the relationship between the wire length of the wire network and the unit coordinates and terminal coordinates, and the first constraint function includes a unit area constraint function, a grid density constraint function and a terminal quantity constraint function.

[0131] S702: Divide the coordinate variables in the initial definition model into horizontal coordinate variables and hierarchical coordinate variables to construct a two-level planning model.

[0132] S703: Construct a 3D chip layout model according to the double-layer planning model and the horizontal coordinate iteration model, wherein the horizontal coordinate iteration module is an iteration model constructed based on a two-dimensional layout planning method.

[0133] The process of constructing the 3D chip layout model can be found in the description of the aforementioned solution, which will not be repeated here.

[0134] The above-mentioned method for constructing a 3D chip layout model constructs an initial definition model of the 3D chip network based on the line length features in the 3D chip layout, and then constructs a double-layer planning model by dividing the coordinate variables into horizontal coordinate variables and hierarchical coordinate variables. After dividing the horizontal coordinate variables and the hierarchical coordinate variables, the horizontal coordinate variables and the hierarchical coordinate variables can be solved by alternating optimization. Therefore, the 3D chip layout model can be constructed according to the double-layer planning model and the horizontal coordinate iteration model, so that the constructed 3D chip layout model can realize the solution of each unit coordinate and terminal coordinate by alternating optimization solution. After multiple iterative solutions, the better unit coordinates and terminal coordinates can be determined.

[0135] In one embodiment, the present application further provides a 3D chip layout method, which includes the following steps S801 to S803.

[0136] S801: Obtain input parameters, wherein the input parameters include wire mesh information, and the wire mesh information includes unit information constituting the wire mesh.

[0137] In the application, the input parameters may also include constraint parameters to adjust the relevant constraint conditions in the 3D chip layout model. Further, the input parameters may also include the initial horizontal coordinates of each unit, so as to directly determine the initial horizontal coordinates of each unit without calculating and determining through the 3D chip layout model.

[0138] S802: Inputting input parameters into a 3D chip layout model so that the 3D chip layout model performs iterative calculations until a preset iterative convergence condition is met, wherein the 3D chip layout model is a 3D chip layout model in any of the above solutions.

[0139] S803: When a preset iteration convergence condition is met, target layout information is determined according to the iteration result of the 3D chip layout model, where the target layout information at least includes cell coordinates and the number of terminals.

[0140] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device that can realize the above functions.

[0141] The above-mentioned 3D chip layout method obtains the initial horizontal coordinates through a 2D solution method. The initial horizontal coordinates are the 2D layout solution obtained by allocating each unit of the 3D chip to a chip and doubling the memory density threshold. The initial horizontal coordinates are then input into the 3D chip layout model for iterative calculation, thereby realizing iterative solution of each unit coordinate and terminal coordinate through the 3D chip layout model in an alternating optimization solution manner. When the preset iterative convergence conditions are met, the 3D chip layout model can obtain a better iterative result, so that a better unit coordinate and terminal quantity can be determined based on the iterative result.

[0142] In one embodiment, the iteration convergence condition is that the number of iterations of the 3D chip layout model reaches a preset threshold.

[0143] In another embodiment, the iterative convergence condition includes a first sub-condition and a second sub-condition, the first sub-condition being that the line length change is less than a first preset threshold, and the second sub-condition being that the number of terminals is less than a second preset threshold.

[0144] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the 3D chip layout method of the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0145] This application also provides a 3D chip layout device, please refer to Fig. 9 , the 3D chip layout device comprises:

[0146] An acquisition module 10 is used to acquire an initial horizontal coordinate, wherein the initial horizontal coordinate is a 2D layout solution obtained by allocating all cells to one chip and doubling a memory density threshold;

[0147] A calculation module 20, configured to input the initial horizontal coordinate into a 3D chip layout model for iterative calculation until an iterative result of the 3D chip layout model satisfies a preset convergence condition, wherein the 3D chip layout model is the 3D chip layout model described in any of the above schemes;

[0148] The determination module 30 is used to determine target layout information according to the iteration result when the iteration result of the 3D chip layout model meets the preset convergence condition. The target layout information includes cell coordinates and the number of terminals.

[0149] The 3D chip layout device provided by the present application adopts the 3D chip layout method in the above embodiment, which can solve the technical problem of 3D chip layout. Compared with the related art, the beneficial effects of the 3D chip layout device provided by the present application are the same as the beneficial effects of the 3D chip layout method provided by the above embodiment, and other technical features in the 3D chip layout device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0150] The present application provides a computer device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the 3D chip layout model construction method or the 3D chip layout method in any of the above-mentioned schemes.

[0151] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, the computer-readable program instructions being used to execute the 3D chip layout model construction method or the 3D chip layout method in any of the above-mentioned schemes.

[0152] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the 3D chip layout model construction method or the 3D chip layout method as described above.

[0153] The computer program product provided by this application can solve the technical problem of poor quality of 3D chip physical design results in the related art. Compared with the related art, the beneficial effects of the computer program product provided by this application are the same as the beneficial effects of the 3D chip layout method provided by the above embodiment, which will not be repeated here.

[0154] Reference below Fig.10, which shows a schematic diagram of the structure of a computer device suitable for implementing the embodiments of the present application. The computer device in the embodiments of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.10 The computer device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0155] like Fig.10 As shown, the computer device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the computer device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the computer device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a computer device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0156] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0157] The computer device provided by the present application adopts the 3D chip layout method in the above embodiment, which can solve the technical problem of poor quality of 3D chip physical design results in the related art. Compared with the prior art, the beneficial effects of the computer device provided by the present application are the same as the beneficial effects of the 3D chip layout method provided by the above embodiment, and other technical features in the computer device are the same as the features disclosed in the 3D chip layout method in the above embodiment, which will not be repeated here.

[0158] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0159] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0160] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0161] The computer-readable storage medium may be included in the computer device; or may exist independently without being installed in the computer device.

[0162] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by a computer device, the computer device executes the 3D chip layout model construction method or 3D chip layout method in any of the above schemes.

[0163] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0164] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0165] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0166] The readable storage medium provided in the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned 3D chip layout method, and can solve the technical problem of poor quality of 3D chip physical design results in the related art. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the present application are the same as the beneficial effects of the 3D chip layout method provided in the above-mentioned embodiment, and will not be repeated here.

[0167] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A 3D chip layout model, characterized in that: The 3D chip layout model includes a first sub-model and a second sub-model, wherein the first sub-model includes a function representing the relationship between the wire mesh length and the unit coordinates and the terminal coordinates, and the second sub-model includes an iterative function of integrating horizontal coordinates, wherein the integrated horizontal coordinates include the horizontal coordinates of each unit and the terminal coordinates; The K-th iteration result of the first sub-model is used as the iteration input parameter of the K-th iteration of the second sub-model, and the K-th iteration result of the second sub-model is used as the iteration input parameter of the K+1-th iteration of the first sub-model, K≥1; The first sub-model is used to determine the hierarchical coordinates of each of the units according to the wire net information and the horizontal coordinates of each of the units based on the shortest wire length and the least terminal rules, wherein the wire net information includes the unit information constituting the wire net; The second sub-model is used to perform iterative optimization calculation on the integrated horizontal coordinates according to the hierarchical coordinates of each of the units and the wire mesh information; Each of the units of the 3D chip layout model is allocated to one wafer and a 2D layout solution obtained by doubling a memory density threshold is used as an initial horizontal coordinate of each of the units.

2. The 3D chip layout model according to claim 1, characterized in that: The first sub-model includes a traversal adjustment module and a first optimization module; The traversal adjustment module is used to traverse and adjust the level coordinates of each unit; The first optimization module is used to obtain the adjustment benefit parameter of each of the units according to a preset evaluation algorithm, and determine the optimization level coordinates of each of the units based on the adjustment benefit parameter of each of the units; The second sub-model is also used for hierarchically optimizing the horizontal coordinates of each of the units according to the optimized hierarchical coordinates of each of the units.

3. The 3D chip layout model according to claim 1, characterized in that: The 3D chip layout model further includes a third sub-model, and the third sub-model includes a partitioning module and an optimization module; The division module is used to divide each metal layer of the wafer into grids, and obtain the resources of each grid according to the wiring track information and the effective utilization rate of each grid, wherein the resources of the grid are the number of wiring tracks covered by the grid; The optimization module is used to determine the prior probability distribution of each of the wire nets according to the demand of each of the wire nets, determine the congestion area according to the prior probability distribution and the resources of each of the squares, determine the posterior probability distribution of each of the wire nets according to the congestion area and the prior probability distribution, and use the posterior probability distribution of each of the wire nets as a resource weight graph to perform routing optimization operations, wherein the demand of each of the wire nets is determined based on the length of the rectangular Steiner minimum tree, and the routing optimization operation includes merging the resource weight graph with the congestion graph to generate a routing weight graph for the wire net; determining the next routing distribution according to the routing weight graph, updating the congestion graph based on the determined routing distribution, and returning to execute the step of merging the resource weight graph with the congestion graph to generate a routing weight graph for the wire net.

4. The 3D chip layout model according to claim 3, characterized in that: The optimization module is also used to obtain the pin information of each of the chips, establish a 3D minimum weight Steiner tree according to the pin information and the wiring weight graph, and obtain global wiring information.

5. The 3D chip layout model according to claim 1, characterized in that: The 3D chip layout model also includes a fourth sub-model; The fourth sub-model is a terminal allocation model constructed based on the minimum cost weighted bipartite graph matching problem, and the fourth sub-model is used to optimize the coordinates of each terminal, wherein the cost is calculated based on the minimum spanning tree length between the unit pins of the wire network and the terminal set, and each wire network has a maximum number of terminals with restricted matching.

6. A method for constructing a 3D chip layout model, characterized in that: The method comprises: Based on the wire length feature in the 3D chip layout, the wire net, the unit coordinates and the terminal coordinates are defined to construct an initial definition model of the 3D chip wire net, wherein the first planning model includes a first objective function and a first constraint function, the first objective function is a function representing the relationship between the wire length of the wire net and the unit coordinates and the terminal coordinates, and the first constraint function includes a unit area constraint function, a grid density constraint function and a terminal quantity constraint function; Dividing the coordinate variables in the initial definition model into horizontal coordinate variables and hierarchical coordinate variables to construct a two-level programming model; A 3D chip layout model is constructed according to the double-layer planning model and the horizontal coordinate iteration model, wherein the horizontal coordinate iteration module is an iteration model constructed based on a two-dimensional layout planning method.

7. A 3D chip layout method, characterized in that: The method comprises: Acquire input parameters, wherein the input parameters include wire mesh information, and the wire mesh information includes unit information constituting the wire mesh; Inputting the input parameters into a 3D chip layout model so that the 3D chip layout model performs iterative calculation until a preset iterative convergence condition is satisfied, wherein the 3D chip layout model is the 3D chip layout model according to any one of claims 1 to 5; When a preset iteration convergence condition is met, target layout information is determined according to the iteration result of the 3D chip layout model, and the target layout information includes unit coordinates and the number of terminals.

8. The 3D chip layout method according to claim 7, characterized in that: The iteration convergence condition is that the number of iterations of the 3D chip layout model reaches a preset threshold.

9. A computer device, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the method for constructing a 3D chip layout model according to claim 6 or the steps of the 3D chip layout method according to any one of claims 7 to 8.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, on which a computer program is stored, and the computer program is configured to implement the method for constructing a 3D chip layout model according to claim 6 or the steps of the 3D chip layout method according to any one of claims 7 to 8.

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