Efficient image compression and decompression method based on FPGA

Abstract

The invention relates to the technical field of image processing, in particular to an efficient image compression and decompression method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: S1, preprocessing and blocking image data: dividing the image data into a plurality of size-adjustable sub-blocks; s2, initializing a distributed compression task: initializing the distributed compression task; s3, distributed compression scheduling based on current switching frequency optimization: monitoring the current switching frequency in an FPGA chip in real time, and dynamically adjusting a scheduling scheme of a distributed compression task; s4, fault-tolerant data verification and redundancy detection: automatically completing error marking and correction operations; s5, performing distributed data decompression and synchronous output: performing distributed decompression operation on the compressed image data; according to the invention, the instantaneous impact of high-frequency current switching on the power supply is reduced, and the problem of local overload is avoided, so that the stability of the system under a high-load condition is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and in particular to an efficient image compression and decompression method based on FPGA. Background Art

[0002] In modern image processing applications, with the continuous increase in data volume, image compression and decompression have become key technologies in the storage and transmission process. Especially in real-time processing scenarios, such as high-definition video transmission, real-time monitoring systems, medical image analysis and other fields, there is an urgent need for efficient and stable image compression and decompression methods. FPGA (field programmable gate array) has gradually become an ideal platform for high-performance image processing due to its parallel processing capabilities and reconfigurability. However, how to use the parallel computing advantages of FPGA to efficiently complete image compression and decompression tasks is still a complex and challenging problem.

[0003] Most existing image compression and decompression technologies focus on algorithm optimization, but when implemented on FPGA, practical issues such as efficient allocation of hardware resources, load balancing, and power stability are often ignored. Traditional compression methods are prone to overload of a single processing unit when encountering large amounts of image data and high complexity, affecting the overall performance of the system. They also lack a dynamic scheduling mechanism and cannot effectively respond to the dynamic resource demands of different tasks. In addition, under high load and complex environments, existing systems lack a complete fault-tolerant mechanism, and data is prone to errors due to power fluctuations or external interference, resulting in reduced image quality and waste of resources, making it difficult to meet the application requirements of high real-time performance and high reliability.

[0004] The purpose of the present invention is to provide an efficient image compression and decompression method based on FPGA, which improves the resource utilization and operation reliability of the system while improving the compression efficiency and data stability. Summary of the invention

[0005] The invention provides a high-efficiency image compression and decompression method based on FPGA.

[0006] An efficient image compression and decompression method based on FPGA includes the following steps:

[0007] S1, preprocessing and block division of image data: preprocessing the image data to be processed, including color space conversion and noise filtering. After the preprocessing is completed, the image data is divided into a number of sub-blocks with adjustable sizes;

[0008] S2, initialization of distributed compression task: Initialize the distributed compression task according to the data characteristics after the image data is divided into blocks, and allocate each sub-block to different processing units in the FPGA;

[0009] S3, distributed compression scheduling based on current switching frequency optimization: real-time monitoring of the current switching frequency within the FPGA chip, dynamic adjustment of the scheduling scheme of distributed compression tasks, and redistribution of compression tasks to each processing unit to reduce the instantaneous impact of high-frequency current switching on the power supply. Specifically, it includes:

[0010] S31, current switching frequency monitoring: real-time monitoring of the current switching frequency of each processing unit in the FPGA chip, and using the on-chip sensor to detect and record the current fluctuation;

[0011] S32, power load analysis: based on the monitored current switching frequency and fluctuation, analyze the power load status of each area to evaluate the impact of the distributed compression task on the power supply;

[0012] S33, compression task load distribution: dynamically adjust the distribution of distributed compression tasks based on current switching frequency monitoring and power supply load analysis;

[0013] S4, fault-tolerant data verification and redundancy detection: During the compression process, real-time verification is performed on the compressed data of different processing units. The real-time monitoring unit of the FPGA is used to detect compressed data errors caused by external interference such as power supply fluctuations and signal jitter, and error marking and correction operations are automatically completed;

[0014] S5, distributed data decompression and synchronous output: performing a distributed decompression operation on the compressed image data, and synchronously outputting the decompressed image data.

[0015] Optionally, the preprocessing and segmentation of the image data in S1 includes:

[0016] S11, color space conversion: performing color space conversion on the image data, converting the original RGB color space into a YUV color space;

[0017] S12, noise filtering: applying Gaussian filtering algorithm to filter the noise in the image data;

[0018] S13, data segmentation: after completing the preprocessing, the image data is divided into a number of sub-blocks of adjustable size to meet the compression requirements of different regions.

[0019] Optionally, the data segmentation in S13 includes:

[0020] S131, complexity calculation: calculating the complexity value C of each block area of ​​the image to determine the size of the block;

[0021] S132, dynamic block adjustment: dynamically adjust the size of the sub-block according to the calculated complexity value, specifically including:

[0022] S1321, define complexity threshold: define the complexity threshold upper limit T of the block area H And the complexity threshold lower limit T L ;

[0023] S1322, Complexity Partitioning and Data Blocking: When C ≥ T H When C≤T L When T L <C<T H When , it is regarded as a medium complexity area and a block size of 8×8 pixels is selected.

[0024] Optionally, the initialization of the distributed compression task in S2 includes:

[0025] S21, resource requirement calculation: calculating the resource requirement R of each sub-block based on the complexity value C of the sub-block;

[0026] S22, task allocation strategy: according to the calculated resource demand R, a weighted load allocation method is applied to calculate the load allocation ratio of the FPGA processing unit;

[0027] S23, compression task initialization: After the resource demand and load distribution ratio are determined, the compression task of each sub-block is initialized to the assigned FPGA processing unit. Each processing unit starts the corresponding compression process according to the resource demand of its assigned sub-block and executes the compression tasks of each sub-block in parallel.

[0028] Optionally, the current switching frequency monitoring in S31 includes:

[0029] S311, sensor placement and signal acquisition: placing an on-chip current sensor near each processing unit in the FPGA chip to collect the current signal of each processing unit in real time;

[0030] S312, current fluctuation detection: detecting the current change of the processing unit through the on-chip current sensor, calculating the number of current switching times per unit time, and obtaining the current switching frequency f;

[0031] S313, current fluctuation collection and recording: while calculating the current switching frequency, the current fluctuation amplitude A of each processing unit is collected.

[0032] Optionally, the power load analysis in S32 includes:

[0033] S321, load intensity calculation: according to the current switching frequency f and the current fluctuation amplitude A of each processing unit, calculate the load intensity L of the processing unit;

[0034] S322, power supply impact assessment: combining the load intensity values ​​of all processing units, and evaluating the overall impact of the current distributed compression task on the power supply through a power supply impact assessment model.

[0035] Optionally, the power supply impact assessment model in S322 adopts a Bayesian network model, and the Bayesian network model includes:

[0036] S3221, Node definition and structure construction: Define the key nodes in the Bayesian network to represent the main factors affecting the power supply, including load intensity L (load demand of the processing unit), current fluctuation amplitude A (power supply fluctuation during current switching), current fluctuation frequency T within a time interval (reflecting the dynamic characteristics of the power supply), and power supply load influence degree E (characterizing the overall impact of the compression task on the power supply, as the final output node of the Bayesian network), and construct node relationships, define conditional dependencies, set E as the target node, and L, A, and T as its parent nodes, respectively, to represent the direct effect relationship on the power supply;

[0037] S3222, prior probability distribution setting: setting the initial prior probability of load intensity and fluctuation amplitude based on Bayesian smoothing;

[0038] S3223, conditional probability table optimization: According to the real-time load intensity L and the current fluctuation amplitude A, the conditional probability P(E|L,A,T) is dynamically calculated, the power load impact is expressed as the joint conditional probability of the load intensity, fluctuation amplitude and time interval, and the load intensity L and the fluctuation amplitude A are assigned different weights α and β for dynamic adjustment of the conditional probability;

[0039] S3224, real-time update and posterior probability calculation: real-time update of the posterior probability of the power load impact, based on the current load intensity, fluctuation amplitude and time interval data;

[0040] S3225, calculation of power supply load impact degree: calculating the expected value of the final power supply load impact degree E, which is used to evaluate the overall impact of the current compression task on the power supply.

[0041] Optionally, the compression task load distribution in S33 includes:

[0042] S331, calculation of processing unit load priority: according to the results of current switching frequency and power load analysis, a priority U is set for each processing unit. i ;

[0043] S332, task load demand calculation: Calculate the load demand R for each block compression task ′ j ;

[0044] S333, dynamic load distribution strategy: according to the load demand R of the task ′ j and the priority U of the processing unit i , apply the dynamic load distribution algorithm, calculate the allocation probability P of task j to processing unit i, and if the allocation probability exceeds the allocation probability threshold, then assign task j to processing unit i.

[0045] Optionally, the fault-tolerance data verification and redundancy detection in S4 includes:

[0046] S41, real-time data verification: when each processing unit performs a compression task, the real-time monitoring unit of the FPGA is used to step-by-step verify the compressed data, and the parity check code is used to identify data anomalies caused by power supply fluctuations and signal jitter;

[0047] S42, error detection and marking: when the monitoring unit detects an abnormal value in the compressed data, the error data is automatically marked;

[0048] S43, redundancy check and error correction: perform redundancy check on the marked erroneous data and correct the error using a data redundancy mechanism, wherein the data redundancy mechanism uses Hamming code.

[0049] Optionally, the distributed data decompression and synchronous output in S5 includes:

[0050] S51, distributed data decompression: distribute the compressed image data to multiple processing units in the FPGA, and each processing unit independently performs a decompression operation on the data block it receives;

[0051] S52, data integrity check: during the decompression process, integrity check is performed on the data block decompressed by each processing unit;

[0052] S53, sequential output of decompressed data: after all processing units have completed decompression, the data blocks are output in a preset order.

[0053] Beneficial effects of the present invention:

[0054] The present invention realizes an efficient image compression and decompression process through the parallel computing capability of FPGA and the optimized task scheduling strategy. Through the preprocessing and blocking of image data, the chromaticity redundant information is reduced and the key brightness characteristics of the image are retained. In addition, the dynamically adjusted blocking method can reasonably allocate resources according to the complexity of the image area, thereby improving the compression efficiency and compression quality, making the data more suitable for the distributed processing of FPGA and improving the resource utilization of the system.

[0055] The present invention realizes dynamic scheduling optimization of distributed compression tasks through current switching frequency monitoring, power load analysis and task load distribution. By real-time monitoring of the current switching frequency of each processing unit and combining the power load analysis results, high-load tasks are preferentially distributed to low-load processing units to reduce the instantaneous impact of high-frequency current switching on the power supply and avoid local overload problems, thereby ensuring the stability of the system under high-load conditions. It is particularly suitable for real-time application scenarios with high requirements for power management and load balancing.

[0056] The present invention realizes real-time detection and correction of data errors in the compression process through a multi-level design of fault-tolerant data verification and redundancy detection, thereby ensuring data integrity and processing accuracy. Distributed data decompression and synchronous output ensure orderly recovery of decompressed image data through data integrity verification and sequential output, so that the system can still maintain high data reliability and stability in complex environments. This optimized fault-tolerant mechanism and synchronous output design effectively reduce error propagation and resource waste, and enhance the robustness and fault tolerance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 A schematic diagram of a compression and decompression method flow chart of an embodiment of the present invention;

[0059] Figure 2 Schematic diagram of distributed compression scheduling based on current switching frequency optimization according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. At the same time, it is explained here that in order to make the embodiments more detailed, the following embodiments are the best and preferred embodiments, and those skilled in the art may also adopt other alternatives to implement some known technologies; and the accompanying drawings are only for more specific description of the embodiments, and are not intended to specifically limit the present invention.

[0061] It should be noted that the references to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments" and the like in the specification indicate that the embodiments described may include specific features, structures or characteristics, but not every embodiment may include the specific features, structures or characteristics. In addition, when a specific feature, structure or characteristic is described in conjunction with an embodiment, it should be within the knowledge of a person skilled in the art to implement such feature, structure or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0062] In general, a term can be understood, at least in part, from its use in context. For example, depending, at least in part, on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular sense, or can be used to describe a combination of features, structures, or characteristics in the plural sense. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but can instead, depending, at least in part, on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0063] like Figure 1-Figure 2 As shown, an efficient image compression and decompression method based on FPGA includes the following steps:

[0064] S1, preprocessing and block division of image data: preprocess the image data to be processed, including color space conversion and noise filtering, to improve the compression performance of the data. After the preprocessing is completed, the image data is divided into several sub-blocks with adjustable sizes;

[0065] S2, initialization of distributed compression task: Initialize the distributed compression task according to the data characteristics after the image data is divided into blocks, and allocate each sub-block to different processing units in the FPGA;

[0066] S3, distributed compression scheduling based on current switching frequency optimization: real-time monitoring of the current switching frequency within the FPGA chip, dynamic adjustment of the scheduling scheme of distributed compression tasks, and redistribution of compression tasks to each processing unit to reduce the instantaneous impact of high-frequency current switching on the power supply. Specifically, it includes:

[0067] S31, current switching frequency monitoring: real-time monitoring of the current switching frequency of each processing unit in the FPGA chip, and using the on-chip sensor to detect and record the current fluctuation;

[0068] S32, power load analysis: based on the monitored current switching frequency and fluctuation, analyze the power load status of each area to evaluate the impact of the distributed compression task on the power supply;

[0069] S33, compression task load distribution: based on current switching frequency monitoring and power load analysis, dynamically adjust the distribution of distributed compression tasks to avoid instantaneous power supply shocks;

[0070] S4, fault-tolerant data verification and redundancy detection: During the compression process, real-time verification is performed on the compressed data of different processing units. The real-time monitoring unit of the FPGA is used to detect compressed data errors caused by external interference such as power supply fluctuations and signal jitters, and error marking and correction operations are automatically completed to ensure the integrity of the compressed data;

[0071] S5, distributed data decompression and synchronous output: performing distributed decompression operation on the compressed image data, and synchronously outputting the decompressed image data;

[0072] Through the above content, an efficient and stable image compression and decompression process is realized, which effectively reduces the instantaneous impact of high-frequency current switching on the power supply, improves the reliability and resource utilization of the system under high load conditions, thereby ensuring data integrity and output consistency, which is particularly suitable for application scenarios with high real-time and high stability requirements.

[0073] The preprocessing and segmentation of image data in S1 includes:

[0074] S11, color space conversion: perform color space conversion on the image data, converting the original RGB color space into the YUV color space, expressed as:

[0075] Y=0.299×R+0.587×G+0.114×B;

[0076] U=-0.14713×R-0.28886×G+0.436×B;

[0077] V=0.615×R-0.51499×G-0.10001×B;

[0078] Among them, Y represents the brightness component of the image, which is used to retain the brightness information, U represents the blue difference component of the image, which is used to describe the chromaticity information of the image, V represents the red difference component of the image, which is used to describe the chromaticity information of the image, R represents the pixel value of the image in the red channel, G represents the pixel value of the image in the green channel, and B represents the pixel value of the image in the blue channel;

[0079] S12, noise filtering: Apply the Gaussian filtering algorithm to filter the noise in the image data to reduce the interference of high-frequency noise on the compression process, expressed as:

[0080]

[0081] Where G(x,y) is a Gaussian function, which represents the Gaussian filter value at the position (x,y) and is used to smooth the image. σ is the standard deviation of the Gaussian kernel, which controls the smoothness of the filter. x is the horizontal distance from the center point of the Gaussian kernel, and y is the vertical distance from the center point of the Gaussian kernel.

[0082] S13, data segmentation: after completing the preprocessing, the image data is divided into a number of sub-blocks with adjustable sizes to meet the compression requirements of different regions;

[0083] Through the above content, the compression performance of image data is effectively optimized. Color space conversion reduces the redundancy of chromaticity information and retains the key characteristics of image brightness, making the data more suitable for compression. Noise filtering reduces the interference of high-frequency noise on the compression process and ensures image quality. The dynamically adjusted blocking method can reasonably allocate resources according to the complexity of the image, thereby improving compression efficiency and accuracy.

[0084] The data blocks in S13 include:

[0085] S131, complexity calculation: Calculate the complexity value C of each block area of ​​the image to determine the size of the block, expressed as:

[0086]

[0087] Among them, C represents the complexity of the current area, N is the total number of pixels in the area, and I i is the brightness value of the i-th pixel in the area, I avg is the average brightness value of all pixels in the area;

[0088] S132, dynamic block adjustment: dynamically adjust the size of the sub-block according to the calculated complexity value, specifically including:

[0089] S1321, define complexity threshold: define the complexity threshold upper limit T of the block area H And the complexity threshold lower limit T L ;

[0090] Complexity threshold upper limit T H And the complexity threshold lower limit T L By calculating the complexity mean μ of the entire image C and standard deviation σ C Set it up, expressed as:

[0091] T H =μ C +k×σ C ;

[0092] T L =μ C -k×σ C ;

[0093]

[0094] Where M is the number of all sub-blocks in the image, C j is the complexity of the jth sub-block, k is the adjustment coefficient, which is set to 1, 1.5 or 2 to adjust the sensitivity of the threshold;

[0095] S1322, Complexity Partitioning and Data Blocking: When C ≥ T H When C≤T, it is regarded as a high complexity area and a block size of 4×4 pixels is selected to preserve image details more finely. L When T is considered as a low complexity area, a block size of 16×16 pixels is selected to reduce the amount of data and improve compression efficiency. L <C<T H When , it is regarded as a medium complexity area, and the block size of 8×8 pixels is selected to balance the image quality and compression rate;

[0096] Through the above content, adaptive block adjustment is achieved. Smaller blocks are used in high-complexity areas to retain details, and larger blocks are used in low-complexity areas to reduce the amount of data, thereby optimizing compression efficiency, effectively improving block flexibility, adapting to the needs of different image areas, and ensuring a balance between image quality and compression ratio. It performs particularly well in scenarios with large differences in image complexity, which helps to improve system resource utilization and compression performance.

[0097] The initialization of the distributed compression task in S2 includes:

[0098] S21, resource requirement calculation: Calculate the resource requirement R of each sub-block based on the complexity value C of the sub-block, expressed as:

[0099] R = a·C + b;

[0100] Among them, a and b are empirical coefficients;

[0101] S22, task allocation strategy: according to the calculated resource demand R, the load allocation ratio of the FPGA processing unit is calculated by applying the weighted load allocation method, which is expressed as:

[0102]

[0103] Among them, R j is the total resource requirement allocated to the jth processing unit, M is the number of processing units;

[0104] S23, compression task initialization: after the resource demand and load distribution ratio are determined, the compression task of each sub-block is initialized to the allocated FPGA processing unit, and each processing unit starts the corresponding compression process according to the resource demand of its allocated sub-block, and executes the compression tasks of each sub-block in parallel to achieve load balancing and efficient use of resources;

[0105] Through the above content, accurate allocation of different sub-blocks is achieved, so that the FPGA processing unit can execute compression tasks in parallel as needed, effectively balancing the load, avoiding the overload problem of a single processing unit, and improving the system's resource utilization and overall compression efficiency. It is particularly suitable for real-time compression scenarios of highly complex and diverse image data.

[0106] The current switching frequency monitoring in S31 includes:

[0107] S311, sensor placement and signal acquisition: placing an on-chip current sensor near each processing unit in the FPGA chip to collect the current signal of each processing unit in real time;

[0108] S312, current fluctuation detection: Detect the current change of the processing unit through the on-chip current sensor, calculate the number of current switching times per unit time, and obtain the current switching frequency f, which is expressed as:

[0109]

[0110] Where f is the current switching frequency, ΔI is the current change value per unit time, and Δt is the time interval;

[0111] S313, current fluctuation collection and recording: while calculating the current switching frequency, the current fluctuation amplitude A of each processing unit is collected, expressed as:

[0112] A = max(I) - min(I);

[0113] Among them, max(I) and min(I) represent the maximum current value and the minimum current value within a period of acquisition time respectively;

[0114] Through the above content, the current changes of each processing unit in the FPGA chip can be accurately grasped, providing key data support for dynamically adjusting the scheduling of compression tasks. It not only improves the power supply stability of the system, but also effectively reduces the instantaneous impact risk caused by high-frequency current switching, ensuring the reliability and resource utilization of the system during high-load operation. It is particularly suitable for real-time processing tasks with high requirements for stability and load balancing.

[0115] Power supply load analysis in S32 includes:

[0116] S321, load intensity calculation: according to the current switching frequency f and the current fluctuation amplitude A of each processing unit, the load intensity L of the processing unit is calculated, which is expressed as:

[0117] L = d·f·A;

[0118] Among them, d is the empirical coefficient, which is used to adjust the influence weight of frequency and fluctuation amplitude on load intensity;

[0119] S322, power supply impact assessment: combining the load intensity values ​​of all processing units, and evaluating the overall impact of the current distributed compression task on the power supply through a power supply impact assessment model;

[0120] Through the above content, the load of the power system caused by the distributed compression task is accurately controlled, the power load status can be identified in time, the task scheduling can be optimized, and the power instability caused by excessive local load can be effectively avoided, thereby improving the stability of the system under high load operation and resource utilization efficiency. It is especially suitable for real-time processing scenarios with high requirements for power management.

[0121] The power impact assessment model in S322 adopts the Bayesian network model, which includes:

[0122] S3221, Node definition and structure construction: Define the key nodes in the Bayesian network to represent the main factors affecting the power supply, including load intensity L (load demand of the processing unit), current fluctuation amplitude A (power supply fluctuation during current switching), current fluctuation frequency T within a time interval (reflecting the dynamic characteristics of the power supply), and power supply load influence degree E (characterizing the overall impact of the compression task on the power supply, as the final output node of the Bayesian network), and construct node relationships, define conditional dependencies, set E as the target node, and L, A, and T as its parent nodes, respectively, to represent the direct effect relationship on the power supply;

[0123] S3222, prior probability distribution setting: The prior probability of the initial load intensity and fluctuation range is set based on the Bayesian smoothing prior, expressed as:

[0124]

[0125] Among them, P(L=L i ) is the load intensity L and its value is L i The prior probability, P(A=A j ) is the fluctuation range A, and its value is A j The prior probability of, N is the total number of observed samples of load intensity or fluctuation range, K is the number of types of values ​​of load intensity L, M is the number of types of values ​​of fluctuation range A, α is the smoothing coefficient, set to 1, used to prevent the probability of zero in the prior probability calculation, C(Li ) is the load intensity L and its value is L i The number of observations of j ) is the fluctuation range A, and its value is A j The number of observations of ;

[0126] S3223, conditional probability table optimization: According to the real-time load intensity L and current fluctuation amplitude A, the conditional probability P(E|L,A,T) is dynamically calculated, and the power load impact is expressed as the joint conditional probability of load intensity, fluctuation amplitude and time interval. Different weights α and β are assigned to the load intensity L and fluctuation amplitude A to dynamically adjust the conditional probability, which is expressed as:

[0127]

[0128] P(E|L,A,T)=α·P(L|E)+β·P(A|E)+(1-α-β)·P(T|E);

[0129] Among them, P(E|L,A,T) represents the conditional probability of the power load influence degree E under the conditions of given load intensity L, current fluctuation amplitude A and fluctuation frequency T, P(L|E) represents the conditional probability of load intensity L when the power influence degree is E, P(A|E) represents the conditional probability of current fluctuation amplitude A when the power influence degree is E, P(T|E) represents the conditional probability of fluctuation frequency T when the power influence degree is E, P(E) represents the prior probability of power load influence degree E, P(L), P(A) and P(T) are the prior probabilities of load intensity L, current fluctuation amplitude A and fluctuation frequency T respectively;

[0130] S3224, real-time update and posterior probability calculation: real-time update of the posterior probability of the power load impact, based on the current load intensity, fluctuation amplitude and time interval data, expressed as:

[0131]

[0132] Where P(E|data) represents the posterior probability of the power load effect E under the given monitoring data data, data represents the load intensity L, current fluctuation amplitude A and fluctuation frequency T currently observed in real time, and P(data|E) represents the conditional probability of the observed data data appearing under the given power load effect E;

[0133] S3225, calculation of the power load impact degree: Calculate the expected value of the final power load impact degree E, which is used to evaluate the overall impact of the current compression task on the power supply, expressed as:

[0134] E expected =∑ iE i ·P(E=E i |L,A,T);

[0135] Among them, E expected The expected value of the power load impact is used to represent the overall impact of the distributed compression task on the power supply. i The possible discrete values ​​of the power load effect, P(E=E i |L,A,T) means that under the conditions of given load intensity L, current fluctuation amplitude A and fluctuation frequency T, the power supply load impact is E i The conditional probability of

[0136] Through the above content, the overall impact of distributed compression tasks on the power supply system can be evaluated more accurately, effectively solving the problems of data sparsity and category imbalance, ensuring that reliable evaluation results can be provided when the load changes dynamically. At the same time, the conditional probability of load and fluctuation amplitude can be updated in real time, and the changing needs of the power supply system can be flexibly adapted, thereby optimizing task scheduling, reducing the risk of instantaneous power supply shocks, and improving system stability and resource utilization.

[0137] The compression task load distribution in S33 includes:

[0138] S331, calculation of processing unit load priority: according to the results of current switching frequency and power load analysis, a priority U is set for each processing unit. i , expressed as:

[0139]

[0140] Among them, U i is the priority of processing unit i, f i is the current switching frequency of processing unit i, L i is the current load intensity of processing unit i, E i The power influence coefficient obtained from the power load analysis;

[0141] S332, task load demand calculation: Calculate the load demand R for each block compression task ′ j , expressed as:

[0142] R ′ j =w1·C j +w2·S j ;

[0143] Among them, R ′ j represents the load demand of task j, C j is the complexity of the task, Sj is the size of the task, w1 and w2 are weight parameters;

[0144] S333, dynamic load distribution strategy: according to the load demand R of the task ′ j and the priority U of the processing unit i , apply the dynamic load distribution algorithm, calculate the distribution probability P of task j to processing unit i, if the distribution probability exceeds the distribution probability threshold, then the task j is assigned to the processing unit i, expressed as:

[0145]

[0146] Among them, U i is the priority of processing unit i, R ′ j is the load demand of the task, U k is the priority of processing unit k;

[0147] Assignment probability threshold P th The settings include:

[0148] Average value f of current switching frequency: Calculate the average value f of current switching frequency of all processing units;

[0149] Current system load rate ρ: indicates the overall degree of the current system load, defined as the ratio of the average load intensity of all processing units to the maximum load of the system, expressed as:

[0150]

[0151] Where N is the total number of processing units, L k is the current load intensity of the kth processing unit, L max The maximum load strength that the system can withstand;

[0152] Allocation probability threshold calculation: Set the allocation probability threshold P th , expressed as:

[0153]

[0154] Among them, P0 is the basic value of the allocation probability, w3 and w4 are adjustment coefficients;

[0155] Through the above content, the task allocation strategy is flexibly adjusted according to the real-time changes of the current switching frequency and the system load rate to ensure that high-load tasks are preferentially allocated to processing units with low load or low switching frequency, thereby reducing the instantaneous pressure on the power supply and effectively improving the stability of the system. At the same time, the allocation strategy adjusted on demand can optimize resource utilization when the load changes, so that the system can maintain smooth operation of the power supply while efficiently executing tasks.

[0156] The fault-tolerant data verification and redundancy detection in S4 include:

[0157] S41, real-time data verification: When each processing unit performs the compression task, the real-time monitoring unit of the FPGA is used to step-by-step verify the compressed data, and the parity check code is used to identify data anomalies caused by power supply fluctuations and signal jitter, which is expressed as:

[0158] P=d1⊕d2⊕…⊕d n ;

[0159] Among them, d1, d2, ..., d n are the 1st, 2nd, ..., nth bit data respectively, ⊕ is the bitwise XOR operation, P is the parity check code, if P = 0, it means that no error is detected in the data block, if P ≠ 0, it means that there is an error in the data block;

[0160] S42, error detection and marking: when the monitoring unit detects an abnormal value in the compressed data, the error data is automatically marked;

[0161] S43, redundancy check and error correction: Redundancy check is performed on the marked erroneous data, and the error is corrected using a data redundancy mechanism. The data redundancy mechanism uses Hamming code, which specifically includes:

[0162] Calculate the check bit: Each redundant bit p k Located at position 2 k-1 , satisfying the following relationship:

[0163]

[0164] Among them, S k The set of data bits controlled by the kth redundant bit is determined according to the rules of Hamming code;

[0165] Error position calculation: The error position index S is generated by the combination of check bits, expressed as:

[0166] S=p1·2 0 +p2·2 1 +…+p r 2 r-1 ;

[0167] If S=0, it means there is no error, and if S≠0, it means that the Sth bit of data has an error;

[0168] Error correction: If the error position S is not zero, flip the data bit at position S to complete the error correction;

[0169] Through the above content, data errors caused by power supply fluctuations or signal interference can be identified and marked in time to ensure the accuracy of data processing. Parity check is used to quickly detect errors, and redundant check mechanism is combined for automatic error correction, so that the system can still maintain high data reliability and integrity under high load or complex environment. This multi-level fault-tolerant detection and error correction design not only improves the stability of the FPGA system, but also reduces the data loss and waste of computing resources caused by error propagation.

[0170] Distributed data decompression and synchronous output in S5 include:

[0171] S51, distributed data decompression: distribute the compressed image data to multiple processing units in the FPGA, and each processing unit independently performs a decompression operation on the data block it receives;

[0172] S52, data integrity check: During the decompression process, integrity check is performed on the data block decompressed by each processing unit, which is expressed as:

[0173]

[0174] Among them, d i is each byte (8-bit data) in the data block, n is the total number of bytes in the data block, Q is the checksum (usually reserved as one byte), which is used to compare with the original checksum after decompression. If the checksum calculated after decompression is inconsistent with the original checksum, it means that there is an error in the data block;

[0175] S53, sequential output of decompressed data: after all processing units have completed decompression, the data blocks are output in a preset order;

[0176] Through the above content, the decompression speed and parallel processing efficiency are greatly improved. At the same time, data integrity verification ensures that the data is not disturbed or damaged during the decompression process, enhancing the reliability of the system. Finally, the decompressed data is output synchronously in a preset order to ensure that the image data is restored in an orderly and complete manner, realizing efficient distributed processing and data verification.

[0177] The present invention covers any substitution, modification, equivalent method and scheme made on the essence and scope of the present invention. In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without the description of these details. In addition, in order to avoid unnecessary confusion about the essence of the present invention, well-known methods, processes, procedures, components and circuits are not described in detail.

[0178] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An efficient image compression and decompression method based on FPGA, characterized in that: The following steps are involved: S1, preprocessing and block division of image data: preprocessing the image data to be processed, including color space conversion and noise filtering. After the preprocessing is completed, the image data is divided into a number of sub-blocks with adjustable sizes; S2, initialization of distributed compression task: Initialize the distributed compression task according to the data characteristics after the image data is divided into blocks, and allocate each sub-block to different processing units in the FPGA; S3, distributed compression scheduling based on current switching frequency optimization: real-time monitoring of the current switching frequency within the FPGA chip, dynamic adjustment of the scheduling scheme of distributed compression tasks, and redistribution of compression tasks to each processing unit to reduce the instantaneous impact of high-frequency current switching on the power supply. Specifically, it includes: S31, current switching frequency monitoring: real-time monitoring of the current switching frequency of each processing unit in the FPGA chip, and using the on-chip sensor to detect and record the current fluctuation; S32, power load analysis: based on the monitored current switching frequency and fluctuation, analyze the power load status of each area to evaluate the impact of the distributed compression task on the power supply; S33, compression task load distribution: dynamically adjust the distribution of distributed compression tasks based on current switching frequency monitoring and power supply load analysis; S4, fault-tolerant data verification and redundancy detection: During the compression process, real-time verification is performed on the compressed data of different processing units. The real-time monitoring unit of the FPGA is used to detect compressed data errors caused by external interference such as power supply fluctuations and signal jitter, and error marking and correction operations are automatically completed; S5, distributed data decompression and synchronous output: performing a distributed decompression operation on the compressed image data, and synchronously outputting the decompressed image data.

2. The FPGA-based efficient image compression and decompression method according to claim 1, characterized in that: The image data preprocessing and segmentation in S1 include: S11, color space conversion: performing color space conversion on the image data, converting the original RGB color space into a YUV color space; S12, noise filtering: applying Gaussian filtering algorithm to filter the noise in the image data; S13, data segmentation: after completing the preprocessing, the image data is divided into a number of sub-blocks of adjustable size to meet the compression requirements of different regions.

3. The efficient image compression and decompression method based on FPGA according to claim 2, characterized in that: The data blocks in S13 include: S131, complexity calculation: calculating the complexity value C of each block area of ​​the image to determine the size of the block; S132, dynamic block adjustment: dynamically adjust the size of the sub-block according to the calculated complexity value, specifically including: S1321, define complexity threshold: define the complexity threshold upper limit T of the block area H And the complexity threshold lower limit T L ; S1322, Complexity Partitioning and Data Blocking: When C ≥ T H When C≤T L When T L <C<T H When , it is regarded as a medium complexity area and a block size of 8×8 pixels is selected.

4. The FPGA-based efficient image compression and decompression method according to claim 3, characterized in that: The initialization of the distributed compression task in S2 includes: S21, resource requirement calculation: calculating the resource requirement R of each sub-block based on the complexity value C of the sub-block; S22, task allocation strategy: according to the calculated resource demand R, a weighted load allocation method is applied to calculate the load allocation ratio of the FPGA processing unit; S23, compression task initialization: After the resource demand and load distribution ratio are determined, the compression task of each sub-block is initialized to the assigned FPGA processing unit. Each processing unit starts the corresponding compression process according to the resource demand of its assigned sub-block and executes the compression tasks of each sub-block in parallel.

5. The efficient image compression and decompression method based on FPGA according to claim 1, characterized in that: The current switching frequency monitoring in S31 includes: S311, sensor placement and signal acquisition: placing an on-chip current sensor near each processing unit in the FPGA chip to collect the current signal of each processing unit in real time; S312, current fluctuation detection: detecting the current change of the processing unit through the on-chip current sensor, calculating the number of current switching times per unit time, and obtaining the current switching frequency f; S313, current fluctuation collection and recording: while calculating the current switching frequency, the current fluctuation amplitude A of each processing unit is collected.

6. The FPGA-based efficient image compression and decompression method according to claim 5, characterized in that: The power load analysis in S32 includes: S321, load intensity calculation: according to the current switching frequency f and the current fluctuation amplitude A of each processing unit, calculate the load intensity L of the processing unit; S322, power supply impact assessment: combining the load intensity values ​​of all processing units, and evaluating the overall impact of the current distributed compression task on the power supply through a power supply impact assessment model.

7. The FPGA-based efficient image compression and decompression method according to claim 6, characterized in that: The power supply impact assessment model in S322 adopts a Bayesian network model, and the Bayesian network model includes: S3221, Node definition and structure construction: Define the key nodes in the Bayesian network to represent the main factors affecting the power supply, including load intensity L, current fluctuation amplitude A, current fluctuation frequency within a time interval T, and power supply load influence degree E, and construct node relationships, define conditional dependencies, set E as the target node, L, A and T as its parent nodes, respectively, to represent the direct effect relationship on the power supply; S3222, prior probability distribution setting: setting the initial prior probability of load intensity and fluctuation amplitude based on Bayesian smoothing; S3223, conditional probability table optimization: According to the real-time load intensity L and the current fluctuation amplitude A, the conditional probability P(E|L,A,T) is dynamically calculated, the power load impact is expressed as the joint conditional probability of the load intensity, fluctuation amplitude and time interval, and the load intensity L and the fluctuation amplitude A are assigned different weights α and β for dynamic adjustment of the conditional probability; S3224, real-time update and posterior probability calculation: real-time update of the posterior probability of the power load impact, based on the current load intensity, fluctuation amplitude and time interval data; S3225, calculation of power supply load impact degree: calculating the expected value of the final power supply load impact degree E, which is used to evaluate the overall impact of the current compression task on the power supply.

8. The FPGA-based efficient image compression and decompression method according to claim 7, characterized in that: The compression task load distribution in S33 includes: S331, calculation of processing unit load priority: according to the results of current switching frequency and power load analysis, a priority U is set for each processing unit. i ; S332, task load demand calculation: Calculate the load demand R for each block compression task ′ j ; S333, dynamic load distribution strategy: according to the load demand R of the task ′ j and the priority U of the processing unit i , apply the dynamic load distribution algorithm, calculate the allocation probability P of task j to processing unit i, and if the allocation probability exceeds the allocation probability threshold, then assign task j to processing unit i.

9. The FPGA-based efficient image compression and decompression method according to claim 1, characterized in that: The fault-tolerant data verification and redundancy detection in S4 include: S41, real-time data verification: when each processing unit performs a compression task, the real-time monitoring unit of the FPGA is used to step-by-step verify the compressed data, and the parity check code is used to identify data anomalies caused by power supply fluctuations and signal jitter; S42, error detection and marking: when the monitoring unit detects an abnormal value in the compressed data, the error data is automatically marked; S43, redundancy check and error correction: perform redundancy check on the marked erroneous data and correct the error using a data redundancy mechanism, wherein the data redundancy mechanism uses Hamming code.

10. The FPGA-based efficient image compression and decompression method according to claim 1, characterized in that: The distributed data decompression and synchronous output in S5 include: S51, distributed data decompression: distribute the compressed image data to multiple processing units in the FPGA, and each processing unit independently performs a decompression operation on the data block it receives; S52, data integrity check: during the decompression process, integrity check is performed on the data block decompressed by each processing unit; S53, sequential output of decompressed data: after all processing units have completed decompression, the data blocks are output in a preset order.

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