An Efficient Image Compression and Decompression Method Based on FPGA

Abstract

The present invention relates to the field of image processing technology, and specifically relates to an efficient image compression and decompression method based on FPGA, including the following steps: S1, preprocessing and blocking of image data: dividing the image data into a number of sub-blocks with adjustable sizes; S2, initialization of distributed compression tasks: initializing the distributed compression tasks; S3, distributed compression scheduling optimized based on the current switching frequency: real-time monitoring the in-FPGA chip current switching frequency and dynamically adjusting the scheduling scheme of the distributed compression tasks; S4, fault-tolerant data verification and redundancy detection: automatically completing error marking and correction operations; S5, distributed data decompression and synchronous output: performing distributed decompression operations on the already-compressed image data; The present invention reduces the instantaneous impact of high-frequency current switching on the power supply and avoids local overload problems, thereby ensuring the stability of the system under high-load conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and particularly to an efficient image compression and decompression method based on FPGA. Background Art

[0002] In modern image processing applications, with the continuous increase in data volume, image compression and decompression have become key technologies in the storage and transmission processes. Especially in real-time processing scenarios, such as high-definition video transmission, real-time monitoring systems, medical image analysis and other fields, there is an urgent need for efficient and stable image compression and decompression methods. FPGA (Field Programmable Gate Array), due to its parallel processing ability and reconfigurability, has gradually become an ideal platform for realizing high-performance image processing. However, how to efficiently complete image compression and decompression tasks by leveraging the parallel computing advantages of FPGA remains a complex and challenging problem.

[0003] Most of the existing image compression and decompression technologies focus on algorithm optimization. However, when implemented on FPGA, practical problems such as efficient allocation of hardware resources, load balancing, and power supply stability are often overlooked. Traditional compression methods are prone to overloading a single processing unit when dealing with large amounts of complex image data, which affects the overall performance of the system. Moreover, they lack a dynamic scheduling mechanism and cannot effectively handle the dynamic resource requirements of different tasks. In addition, in high-load and complex environments, existing systems lack a perfect fault tolerance mechanism, and data is prone to errors due to power fluctuations or external interference, resulting in a decline in image quality and resource waste, making it difficult to meet the application requirements of high real-time and high reliability.

[0004] The object of the present invention is to provide an efficient image compression and decompression method based on FPGA, which improves the resource utilization rate and operation reliability of the system while enhancing the compression efficiency and data stability. Summary of the Invention

[0005] The present invention provides an efficient image compression and decompression method based on FPGA.

[0006] An efficient image compression and decompression method based on FPGA includes the following steps:

[0007] S1, preprocessing and blocking of image data: Preprocess the image data to be processed, including color space conversion and noise filtering. After the preprocessing is completed, divide the image data into several sub-blocks with adjustable sizes;

[0008] S2, initialization of distributed compression tasks: Initialize the distributed compression tasks according to the data characteristics of the image data after blocking, and allocate each sub-block to different processing units within the FPGA;

[0009] S3. Distributed compression scheduling based on optimized current switching frequency: Monitor the in-FPGA current switching frequency in real time, dynamically adjust the scheduling scheme of distributed compression tasks, and reallocate the compression tasks to each processing unit to reduce the instantaneous impact of high-frequency current switching on the power supply. Specifically, it includes:

[0010] S31. Current switching frequency monitoring: Monitor the current switching frequency of each processing unit in the FPGA in real time, and use on-chip sensors to detect and record current fluctuations.

[0011] S32. Power load analysis: Analyze the power load status of each area based on the monitored current switching frequency and fluctuations to evaluate the impact of distributed compression tasks on the power supply.

[0012] S33. Compression task load allocation: Dynamically adjust the allocation of distributed compression tasks based on current switching frequency monitoring and power load analysis.

[0013] S4. Fault-tolerant data verification and redundancy detection: During the compression process, perform real-time verification on the compressed data of different processing units. Use the real-time monitoring unit of the FPGA to detect compression data errors caused by external interferences such as power fluctuations and signal jitters, and automatically complete error marking and correction operations.

[0014] S5. Distributed data decompression and synchronous output: Perform distributed decompression operations on the compressed image data and synchronously output the decompressed image data.

[0015] Optionally, the preprocessing and block division of the image data in S1 include:

[0016] S11. Color space conversion: Perform color space conversion on the image data, converting the original RGB color space to the YUV color space.

[0017] S12. Noise filtering: Apply the Gaussian filtering algorithm to filter the noise in the image data.

[0018] S13. Data block division: After completing the preprocessing, divide the image data into several sub-blocks with adjustable sizes to adapt to the compression requirements of different regions.

[0019] Optionally, the data block division in S13 includes:

[0020] S131. Complexity calculation: Calculate the complexity value C for each block area of the image to determine the block size.

[0021] S132. Dynamic block adjustment: Dynamically adjust the size of the sub-blocks according to the calculated complexity value. Specifically, it includes:

[0022] S1321. Define the complexity threshold: Define the upper limit T of the complexity threshold for the divided regions and the lower limit T of the complexity threshold. H and the lower limit T of the complexity threshold L ;

[0023] S1322. Complexity division and data chunking: When C ≥ T H , it is regarded as a high-complexity region, and a block size of 4×4 pixels is selected. When C ≤ T L , it is regarded as a low-complexity region, and a block size of 16×16 pixels is selected. When T L < C < T H , it is regarded as a medium-complexity region, and a block size of 8×8 pixels is selected.

[0024] Optionally, the initialization of the distributed compression task in S2 includes:

[0025] S21. Resource requirement calculation: Calculate the resource requirement R of each sub-block based on the complexity value C of the sub-block.

[0026] S22. Task allocation strategy: According to the calculated resource requirement R, apply the weighted load distribution method to calculate the load distribution ratio of the FPGA processing units.

[0027] S23. Compression task initialization: After the resource requirement and the load distribution ratio are determined, initialize the compression task of each sub-block to the allocated FPGA processing unit. Each processing unit starts the corresponding compression process according to the resource requirement of the sub-block it is allocated, and executes the compression tasks of each sub-block in parallel.

[0028] Optionally, the current switching frequency monitoring in S31 includes:

[0029] S311. Sensor arrangement and signal acquisition: Arrange on-chip current sensors near each processing unit in the FPGA, and collect the current signals of each processing unit in real time.

[0030] S312. Current fluctuation detection: Detect the current change of the processing unit through the on-chip current sensor, calculate the number of current switching times per unit time, and obtain the current switching frequency f.

[0031] S313. Current fluctuation situation acquisition and recording: While calculating the current switching frequency, collect the current fluctuation amplitude A of each processing unit.

[0032] Optionally, the power load analysis in S32 includes:

[0033] S321. Load intensity calculation: Calculate the load intensity L of the processing unit based on the current switching frequency f and the current fluctuation amplitude A of each processing unit.

[0034] S322, Power Impact Assessment: Combining the load intensity values of all processing units, evaluate the overall impact of the current distributed compression task on the power supply through a power impact assessment model.

[0035] Optionally, the power impact assessment model in S322 adopts a Bayesian network model, and the Bayesian network model includes:

[0036] S3221, Node Definition and Structure Construction: Define the key nodes in the Bayesian network to represent the main factors affecting the power supply, including the load intensity L (the load demand of the processing unit), the current fluctuation amplitude A (the fluctuation of the power supply during the current switching process), the current fluctuation frequency T within a time interval (reflecting the dynamic characteristics of the power supply), and the power load impact degree E (characterizing the overall impact of the compression task on the power supply, as the final output node of the Bayesian network), and construct the node relationship, define the conditional dependence, and set E as the target node, and L, A, and T as its parent nodes respectively, indicating the direct relationship of influence on the power supply;

[0037] S3222, Prior Probability Distribution Setting: Set the prior probabilities of the initial load intensity and fluctuation amplitude based on the prior of Bayesian smoothing;

[0038] S3223, Conditional Probability Table Optimization: Dynamically calculate the conditional probability P(E|L,A,T) according to the real-time load intensity L and current fluctuation amplitude A, represent the power load impact as the joint conditional probability of the load intensity, fluctuation amplitude, and time interval, and assign different weights α and β to the load intensity L and fluctuation amplitude A for dynamically adjusting the conditional probability;

[0039] S3224, Real-time Update and Posterior Probability Calculation: Real-time update the posterior probability of the power load impact, and update it based on the data of the current load intensity, fluctuation amplitude, and time interval;

[0040] S3225, Calculation of the Power Load Impact Degree: Calculate the expected value of the final power load impact degree E to evaluate the overall impact of the current compression task on the power supply.

[0041] Optionally, the compression task load distribution in S33 includes:

[0042] S331, Calculation of the Load Priority of the Processing Unit: Set the priority U for each processing unit according to the result of the current switching frequency and power load analysis i ;

[0043] S332, Calculation of the Task Load Demand: Calculate the load demand quantity R for each block of the compression task ′ j ;

[0044] S333, Dynamic load distribution strategy: According to the load demand R of the task ′ j and the priority U of the processing unit i , apply the dynamic load distribution algorithm to calculate the allocation probability P that task j is assigned to processing unit i. If the allocation probability exceeds the allocation probability threshold, then assign task j to processing unit i.

[0045] Optionally, the fault-tolerant data verification and redundancy detection in S4 include:

[0046] S41, Real-time data verification: When each processing unit executes the compression task, use the real-time monitoring unit of the FPGA to gradually verify the compressed data, and use the parity check code to identify data anomalies caused by power fluctuations and signal jitters;

[0047] S42, Error detection and marking: When the monitoring unit detects an abnormal value in the compressed data, automatically mark the error data;

[0048] S43, Redundancy verification and error correction: Perform redundancy detection on the marked error data, and use the data redundancy mechanism to correct the error. The data redundancy mechanism uses Hamming code.

[0049] Optionally, the distributed data decompression and synchronous output in S5 include:

[0050] S51, Distributed data decompression: Distribute the compressed image data to multiple processing units within the FPGA, and each processing unit independently performs the decompression operation on the data block it receives;

[0051] S52, Data integrity verification: During the decompression process, perform integrity verification on the data blocks decompressed by each processing unit;

[0052] S53, Sequential output of decompressed data: After all processing units complete decompression, output according to the preset order of the data blocks.

[0053] Advantages of the present invention:

[0054] In the present invention, through the parallel computing ability of the FPGA and the optimized task scheduling strategy, an efficient image compression and decompression process is realized. Through the preprocessing and block division of the image data, chromatic redundancy information is reduced, and the key brightness features of the image are retained. Moreover, the dynamically adjusted block division method can perform reasonable resource allocation according to the complexity of the image area, thereby improving the compression efficiency and compression quality, making the data more suitable for distributed processing by the FPGA, and improving the resource utilization rate of the system.

[0055] The present invention realizes the dynamic scheduling optimization of distributed compression tasks through current switching frequency monitoring, power load analysis, and task load allocation. By real-time monitoring the current switching frequency of each processing unit and combining the results of power load analysis, high-load tasks are preferentially allocated to low-load processing units to reduce the instantaneous impact of high-frequency current switching on the power supply and avoid local overload problems, thereby ensuring the stability of the system under high-load conditions. It is particularly suitable for real-time application scenarios with high requirements for power management and load balancing.

[0056] The present invention realizes the real-time detection and correction of data errors during the compression process through a multi-level design of fault-tolerant data verification and redundancy detection, ensuring data integrity and processing accuracy. Distributed data decompression and synchronous output ensure the orderly recovery of decompressed image data through data integrity verification and sequential output, enabling the system to maintain high data reliability and stability in complex environments. This optimized fault-tolerant mechanism and synchronous output design effectively reduce error propagation and resource waste, enhancing the robustness and fault tolerance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following described drawings are only those of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0058] Figure 1 It is a schematic flow chart of the compression and decompression method according to an embodiment of the present invention;

[0059] Figure 2 It is a schematic diagram of a distributed compression scheduling optimized based on current switching frequency according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0060] The following will describe the present invention in detail with reference to the drawings and specific embodiments. At the same time, it should be noted here that in order to make the embodiments more detailed, the following embodiments are the best and preferred embodiments. For some well-known technologies, those skilled in the art can also adopt other alternative methods for implementation; moreover, the drawing part is only for a more specific description of the embodiments and is not intended to specifically limit the present invention.

[0061] It should be noted that in the specification, references to "an embodiment", "embodiments", "exemplary embodiments", "some embodiments", etc. indicate that the described embodiments may include specific features, structures, or characteristics, but not necessarily every embodiment includes such specific features, structures, or characteristics. Additionally, when describing a specific feature, structure, or characteristic in connection with an embodiment, implementing such feature, structure, or characteristic in connection with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the relevant art.

[0062] Generally, terms can be understood at least in part from their use in context. For example, at least in part depending on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Additionally, the term "based on" can be understood as not necessarily intended to convey a set of exclusive factors, but rather can alternatively, at least in part depending on the context, allow for the existence of other factors that are not necessarily explicitly described.

[0063] As Figure 1 - Figure 2 shown, an efficient image compression and decompression method based on FPGA includes the following steps:

[0064] S1, preprocessing and chunking of image data: Preprocess the image data to be processed, including color space conversion and noise filtering, to improve the compression performance of the data. After the preprocessing is completed, divide the image data into several sub - blocks with adjustable sizes;

[0065] S2, initialization of distributed compression tasks: According to the data characteristics after the image data is chunked, initialize the distributed compression tasks and allocate each sub - block to different processing units within the FPGA;

[0066] S3, distributed compression scheduling based on current switching frequency optimization: Monitor the on - chip current switching frequency of the FPGA in real - time, dynamically adjust the scheduling scheme of the distributed compression tasks, and re - allocate the compression tasks to each processing unit to reduce the instantaneous impact of high - frequency current switching on the power supply. Specifically, it includes:

[0067] S31, current switching frequency monitoring: Monitor the on - chip current switching frequency of each processing unit in the FPGA in real - time, and use on - chip sensors to detect and record the current fluctuation conditions;

[0068] S32, power load analysis: According to the monitored current switching frequency and fluctuation conditions, analyze the power load status of each area to evaluate the impact of the distributed compression tasks on the power supply;

[0069] S33, compression task load allocation: Based on the current switching frequency monitoring and power load analysis, dynamically adjust the allocation of the distributed compression tasks to avoid instantaneous power supply shocks;

[0070] S4, Fault Tolerant Data Verification and Redundancy Detection: During the compression process, real-time verification is performed on the compressed data of different processing units. By using the real-time monitoring unit of the FPGA, errors in the compressed data caused by external interferences such as power fluctuations and signal jitters are detected, and error marking and correction operations are automatically completed to ensure the integrity of the compressed data.

[0071] S5, Distributed Data Decompression and Synchronous Output: Perform distributed decompression operations on the already compressed image data and synchronously output the decompressed image data.

[0072] Through the above content, an efficient and stable image compression and decompression process is achieved, effectively reducing the instantaneous impact of high-frequency current switching on the power supply, improving the reliability and resource utilization rate of the system under high-load conditions, thus ensuring data integrity and output consistency, and is particularly suitable for application scenarios with high real-time and high stability requirements.

[0073] The preprocessing and chunking of the image data in S1 include:

[0074] S11, Color Space Conversion: Perform color space conversion on the image data, converting the original RGB color space to the YUV color space, expressed as:

[0075] Y = 0.299×R + 0.587×G + 0.114×B;

[0076] U = -0.14713×R - 0.28886×G + 0.436×B;

[0077] V = 0.615×R - 0.51499×G - 0.10001×B;

[0078] Among them, Y represents the luminance component of the image, which is used to retain the luminance information, U represents the blue difference component of the image, which is used to describe the chromaticity information of the image, V represents the red difference component of the image, which is used to describe the chromaticity information of the image, R represents the pixel value in the red channel of the image, G represents the pixel value in the green channel of the image, and B represents the pixel value in the blue channel of the image.

[0079] S12, Noise Filtering: Apply the Gaussian filtering algorithm to filter the noise in the image data, reducing the interference of high-frequency noise on the compression process, expressed as:

[0080]

[0081] Among them, G(x, y) is the Gaussian function, representing the Gaussian filtering value at the position (x, y), which is used to smooth the image. σ is the standard deviation of the Gaussian kernel, controlling the smoothness of the filtering. x is the horizontal distance from the center point of the Gaussian kernel, and y is the vertical distance from the center point of the Gaussian kernel;

[0082] S13. Data chunking: After the preprocessing is completed, the image data is divided into several sub-chunks with adjustable sizes to meet the compression requirements of different regions;

[0083] Through the above content, the compression performance of the image data is effectively optimized. The color space conversion reduces the redundancy of chrominance information and retains the key features of the image brightness, making the data more suitable for compression. The noise filtering reduces the interference of high-frequency noise on the compression process and ensures the image quality. The dynamically adjusted chunking method can reasonably allocate resources according to the image complexity, improving the compression efficiency and accuracy.

[0084] The data chunking in S13 includes:

[0085] S131. Complexity calculation: Calculate the complexity value C of each chunk region of the image to determine the size of the chunk, expressed as:

[0086]

[0087] Among them, C represents the complexity of the current region, N is the total number of pixels in this region, I i is the brightness value of the i-th pixel in this region, and I avg is the average brightness value of all pixels in this region;

[0088] S132. Dynamic chunk adjustment: Dynamically adjust the size of the sub-chunks according to the calculated complexity value, specifically including:

[0089] S1321. Define complexity thresholds: Define the upper limit T H and the lower limit T L of the complexity threshold of the chunk region;

[0090] The upper limit T H and the lower limit T L of the complexity threshold are set by calculating the complexity mean μ C and the standard deviation σ C of the entire image, expressed as:

[0091] T H = μ C + k × σ C ;

[0092] T L = μ C - k × σ C ;

[0093]

[0094] Among them, M is the number of all sub - blocks in the image, C j is the complexity of the j - th sub - block, k is an adjustment coefficient, which is set to 1, 1.5 or 2 to adjust the sensitivity of the threshold;

[0095] S1322, complexity division and data block - partitioning: When C≥T H it is regarded as a high - complexity region, and a block size of 4×4 pixels is selected to more finely retain image details. When C≤T L it is regarded as a low - complexity region, and a block size of 16×16 pixels is selected to reduce the data volume and improve the compression efficiency. When T L <C<T H it is regarded as a medium - complexity region, and a block size of 8×8 pixels is selected to balance the image quality and the compression ratio;

[0096] Through the above content, adaptive block - adjustment is achieved. Smaller blocks are used in high - complexity regions to retain details, and larger blocks are used in low - complexity regions to reduce the data volume, thereby optimizing the compression efficiency, effectively improving the block - flexibility, adapting to the needs of different image regions, ensuring the balance between image quality and compression ratio, and performing particularly well in scenarios where the image complexity varies greatly, which helps to improve the system resource utilization rate and compression performance.

[0097] The initialization of the distributed compression task in S2 includes:

[0098] S21, resource - demand calculation: Based on the complexity value C of each sub - block, calculate the resource demand R of this sub - block, expressed as:

[0099] R = a·C + b;

[0100] Among them, a and b are empirical coefficients;

[0101] S22, task - allocation strategy: According to the calculated resource demand R, apply the weighted - load - allocation method to calculate the load - allocation ratio of the FPGA processing unit, expressed as:

[0102]

[0103] Among them, R j is the total resource demand allocated to the j - th processing unit, and M is the number of processing units;

[0104] S23. Compression task initialization: After determining the resource requirements and load distribution ratio, initialize the compression task of each sub-block to the allocated FPGA processing unit. Each processing unit starts the corresponding compression process according to the resource requirements of the sub-blocks it is allocated, and executes the compression tasks of each sub-block in parallel to achieve load balancing and efficient utilization of resources.

[0105] Through the above content, precise allocation of different sub-blocks is achieved, enabling the FPGA processing unit to execute compression tasks in parallel as needed, effectively balancing the load, avoiding the overload problem of a single processing unit, improving the resource utilization rate and overall compression efficiency of the system, and being particularly suitable for real-time compression scenarios of high-complexity and diverse image data.

[0106] The current switching frequency monitoring in S31 includes:

[0107] S311. Sensor arrangement and signal acquisition: Arrange on-chip current sensors near each processing unit within the FPGA to collect the current signals of each processing unit in real time.

[0108] S312. Current fluctuation detection: Detect the current change of the processing unit through the on-chip current sensor, calculate the number of current switching times per unit time, and obtain the current switching frequency f, expressed as:

[0109]

[0110] where f is the current switching frequency, ΔI is the current change value per unit time, and Δt is the time interval.

[0111] S313. Current fluctuation situation acquisition and recording: While calculating the current switching frequency, collect the current fluctuation amplitude A of each processing unit, expressed as:

[0112] A = max(I) - min(I);

[0113] where max(I) and min(I) respectively represent the maximum current value and the minimum current value during a period of acquisition time.

[0114] Through the above content, accurately grasp the current change situation of each processing unit within the FPGA, providing key data support for dynamically adjusting the scheduling of compression tasks, not only improving the power supply stability of the system, but also effectively reducing the risk of instantaneous impact caused by high-frequency current switching, ensuring the reliability and resource utilization rate of the system during high-load operation, and being particularly suitable for real-time processing tasks with high requirements for stability and load balancing.

[0115] The power load analysis in S32 includes:

[0116] S321, Load intensity calculation: Based on the current switching frequency f and the current fluctuation amplitude A of each processing unit, calculate the load intensity L of the processing unit, expressed as:

[0117] L = d·f·A;

[0118] Where d is an empirical coefficient used to adjust the influence weight of frequency and fluctuation amplitude on the load intensity;

[0119] S322, Power impact assessment: Combine the load intensity values of all processing units and evaluate the overall impact of the current distributed compression task on the power supply through the power impact assessment model;

[0120] Through the above content, the accurate control of the load situation of the power supply system by the distributed compression task is achieved. It can timely identify the power load status, optimize task scheduling, effectively avoid the power instability problem caused by excessive local load, and thus improve the stability and resource utilization efficiency of the system under high-load operation, which is particularly suitable for real-time processing scenarios with high requirements for power management.

[0121] The power impact assessment model in S322 adopts a Bayesian network model, and the Bayesian network model includes:

[0122] S3221, Node definition and structure construction: Define the key nodes in the Bayesian network, which are used to represent the main factors affecting the power supply, including the load intensity L (the load demand of the processing unit), the current fluctuation amplitude A (the power supply fluctuation during the current switching process), the current fluctuation frequency T within the time interval (reflecting the dynamic characteristics of the power supply), and the power load impact degree E (characterizing the overall impact of the compression task on the power supply, serving as the final output node of the Bayesian network), and construct the node relationship, define the conditional dependence, and set E as the target node, and L, A, and T as its parent nodes respectively, indicating the direct action relationship on the power supply impact;

[0123] S3222, Prior probability distribution setting: Based on the prior setting of Bayesian smoothing, set the prior probabilities of the initial load intensity and fluctuation amplitude, expressed as:

[0124]

[0125] Where P(L = L i ) is the prior probability that the load intensity L takes the value of L i , P(A = A j ) is the prior probability that the fluctuation amplitude A takes the value of A j , N is the total number of observation samples of the load intensity or fluctuation amplitude, K is the number of types of values of the load intensity L, M is the number of types of values of the fluctuation amplitude A, α is the smoothing coefficient, set to 1, used to prevent the occurrence of a probability of zero in the prior probability calculation, C(Li ) is the number of observations when the load intensity L takes the value of L i , and C(A j ) is the number of observations when the fluctuation amplitude A takes the value of A j ;

[0126] S3223, Conditional probability table optimization: According to the real-time load intensity L and current fluctuation amplitude A, dynamically calculate the conditional probability P(E|L,A,T), represent the power load impact as the joint conditional probability of load intensity, fluctuation amplitude and time interval, and assign different weights α and β to the load intensity L and fluctuation amplitude A for dynamically adjusting the conditional probability, expressed as:

[0127]

[0128] P(E|L,A,T) = α·P(L|E) + β·P(A|E) + (1 - α - β)·P(T|E);

[0129] Among them, P(E|L,A,T) represents the conditional probability of the power load impact degree E under the conditions of given load intensity L, current fluctuation amplitude A and fluctuation frequency T, P(L|E) represents the conditional probability of the load intensity L when the power impact degree is E, P(A|E) represents the conditional probability of the current fluctuation amplitude A when the power impact degree is E, P(T|E) represents the conditional probability of the fluctuation frequency T when the power impact degree is E, P(E) represents the prior probability of the power load impact degree E, and P(L), P(A) and P(T) are the prior probabilities of the load intensity L, current fluctuation amplitude A and fluctuation frequency T respectively;

[0130] S3224, Real-time update and posterior probability calculation: Real-time update the posterior probability of the power load impact, and update based on the data of the current load intensity, fluctuation amplitude and time interval, expressed as:

[0131]

[0132] Among them, P(E|data) represents the posterior probability of the power load impact E under the condition of given monitoring data data, data represents the currently real-time observed load intensity L, current fluctuation amplitude A and fluctuation frequency T, and P(data|E) represents the conditional probability of the observed data data appearing under the condition of given power load impact E;

[0133] S3225, Calculation of the power load impact degree: Calculate the expected value of the final power load impact degree E for evaluating the overall impact of the current compression task on the power supply, expressed as:

[0134] E expected = ∑ iE i ·P(E = E i |L, A, T);

[0135] Among them, E expected represents the expected value of the impact degree of the power load, which is used to represent the overall impact of the distributed compression task on the power supply. E i represents the possible discrete values of the power load impact, and P(E = E i |L, A, T) represents the conditional probability that the power load impact is E i under the conditions of the given load intensity L, current fluctuation amplitude A, and fluctuation frequency T;

[0136] Through the above content, the overall impact of the distributed compression task on the power supply system can be evaluated more accurately, effectively solving the problems of data sparsity and class imbalance, ensuring that reliable evaluation results can still be provided under the condition of dynamic load changes. At the same time, the conditional probabilities of the load and the fluctuation amplitude can be updated in real time to flexibly adapt to the changing requirements of the power supply system, thereby optimizing the task scheduling, reducing the risk of instantaneous power impact, and improving the stability and resource utilization rate of the system.

[0137] The compression task load allocation in S33 includes:

[0138] S331, calculation of the load priority of the processing unit: According to the results of the current switching frequency and power load analysis, set the priority U i for each processing unit, which is expressed as:

[0139]

[0140] Among them, U i is the priority of processing unit i, f i is the current switching frequency of processing unit i, L i is the current load intensity of processing unit i, and E i is the power impact coefficient obtained from the power load analysis;

[0141] S332, calculation of the task load demand: Calculate the load demand R ′ j for each block of the compression task, which is expressed as:

[0142] R ′ j = w1·C j + w2·S j ;

[0143] Among them, R ′ j represents the load demand of task j, C j is the complexity of the task, and Sj is the size of the task, and w1 and w2 are weight parameters;

[0144] S333, dynamic load distribution strategy: According to the load demand R of the task ′ j and the priority U of the processing unit i , apply the dynamic load distribution algorithm to calculate the allocation probability P of task j assigned to processing unit i. If the allocation probability exceeds the allocation probability threshold, then assign task j to processing unit i, which is expressed as:

[0145]

[0146] where U i is the priority of processing unit i, and R ′ j is the load demand of the task, and U k is the priority of processing unit k;

[0147] The allocation probability threshold P th is set specifically as follows:

[0148] The average value f of the current switching frequency: Calculate the average value f of the current switching frequencies of all processing units;

[0149] The current system load rate ρ: Represents the overall degree of the current system load, which is defined as the ratio of the average load intensity of all processing units to the maximum load of the system, and is expressed as:

[0150]

[0151] where N is the total number of processing units, and L k is the current load intensity of the kth processing unit, and L max is the maximum load intensity that the system can withstand;

[0152] Calculation of the allocation probability threshold: Set the allocation probability threshold P th , which is expressed as:

[0153]

[0154] where P0 is the base value of the allocation probability, and w3 and w4 are adjustment coefficients;

[0155] Through the above content, the task allocation strategy is flexibly adjusted according to the real-time changes of the current switching frequency and the system load rate, ensuring that high-load tasks are preferentially assigned to processing units with low load or low switching frequency, reducing the instantaneous pressure on the power supply, effectively improving the stability of the system. At the same time, the on-demand adjusted allocation strategy can optimize the resource utilization rate when the load changes, enabling the system to maintain the stable operation of the power supply while efficiently executing tasks.

[0156] Fault-tolerant data verification and redundancy detection in S4 include:

[0157] S41, real-time data verification: When each processing unit executes the compression task, the real-time monitoring unit of the FPGA is used to gradually verify the compressed data, and the parity check code is used to identify data anomalies caused by power fluctuations and signal jitters, expressed as:

[0158] P = d1⊕d2⊕…⊕d n ;

[0159] where d1, d2,..., d n are the data bits of the 1st, 2nd,..., nth positions respectively, ⊕ is the bitwise exclusive OR operation, P is the parity check code. If P = 0, it means no error is detected in the data block. If P ≠ 0, it means there is an error in the data block;

[0160] S42, error detection and marking: When the monitoring unit detects an abnormal value in the compressed data, the error data is automatically marked;

[0161] S43, redundancy verification and error correction: Redundancy detection is performed on the marked error data, and the data redundancy mechanism is used to correct the error. The data redundancy mechanism uses Hamming code, specifically including:

[0162] Calculating check bits: Each redundancy bit p k is located at position 2 k-1 , and satisfies the following relationship:

[0163]

[0164] where S k represents the set of data bits controlled by the kth redundancy bit, determined according to the rules of Hamming code;

[0165] Calculating the error position: The error position index S is generated through the combination of check bits, expressed as:

[0166] S = p1·2 0 +p2·2 1 +…+p r ·2 r-1 ;

[0167] where if S = 0, it means there is no error. If S ≠ 0, it means the data bit at the Sth position has an error;

[0168] Error correction: If the error position S is not zero, the data bit at position S is flipped to complete the error correction;

[0169] Through the above, data errors caused by power fluctuations or signal interference can be promptly identified and marked, ensuring the accuracy of data processing. Parity check is used to quickly detect errors, and combined with the redundant check mechanism for automatic error correction, enabling the system to maintain high data reliability and integrity in high-load or complex environments. This multi-level fault tolerance detection and error correction design not only improves the stability of the FPGA system but also reduces data loss and waste of computing resources caused by error propagation.

[0170] The distributed data decompression and synchronous output in S5 include:

[0171] S51, distributed data decompression: The compressed image data is distributed to multiple processing units within the FPGA, and each processing unit independently performs decompression operations on the data block it receives;

[0172] S52, data integrity check: During the decompression process, the integrity of the data block decompressed by each processing unit is checked, expressed as:

[0173]

[0174] where d i is each byte (8-bit data) in the data block, n is the total number of bytes in the data block, and Q is the checksum (usually reserved as one byte), which is used to compare with the original checksum after decompression. If the calculated checksum after decompression is inconsistent with the original checksum, it indicates that there is an error in the data block;

[0175] S53, sequential output of decompressed data: After all processing units have completed decompression, the output is performed in the preset order of the data blocks;

[0176] Through the above, the decompression speed and parallel processing efficiency are significantly improved. At the same time, the data integrity check ensures that the data is not interfered with or damaged during the decompression process, enhancing the reliability of the system. Finally, the decompressed data is synchronously output in the preset order to ensure the orderly and complete restoration of the image data, achieving efficient distributed processing and data verification.

[0177] This invention covers any substitutions, modifications, equivalent methods, and solutions made within the essence and scope of this invention. To enable the public to have a thorough understanding of this invention, specific details are described in detail in the following preferred embodiments of this invention. However, those skilled in the art can fully understand this invention without the description of these details. Additionally, to avoid unnecessary confusion to the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0178] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. An efficient image compression and decompression method based on FPGA, characterized in that, It includes the following steps: S1, Preprocessing and Blocking of Image Data: Preprocess the image data to be processed, including color space conversion and noise filtering. After the preprocessing is completed, divide the image data into several sub-blocks with adjustable sizes; S2, Initialization of Distributed Compression Task: Initialize the distributed compression task according to the data characteristics after the image data is blocked, and allocate each sub-block to different processing units within the FPGA; S3, Distributed Compression Scheduling Optimized Based on Current Switching Frequency: Monitor the in-FPGA current switching frequency in real time, dynamically adjust the scheduling scheme of the distributed compression task, and re-allocate the compression task to each processing unit to reduce the instantaneous impact of high-frequency current switching on the power supply. Specifically, it includes: S31, Current Switching Frequency Monitoring: Monitor the current switching frequency of each processing unit within the FPGA in real time, and use the on-chip sensor to detect and record the current fluctuation; S32, Power Load Analysis: Analyze the power load status of each area according to the monitored current switching frequency and fluctuation conditions to evaluate the impact of the distributed compression task on the power supply; S33, Compression Task Load Allocation: Dynamically adjust the allocation of the distributed compression task based on the current switching frequency monitoring and power load analysis; S4, Fault-Tolerant Data Verification and Redundancy Detection: During the compression process, perform real-time verification on the compressed data of different processing units. Use the real-time monitoring unit of the FPGA to detect compression data errors caused by external interferences such as power fluctuations and signal jitters, and automatically complete error marking and correction operations; S5, Distributed Data Decompression and Synchronous Output: Perform distributed decompression operations on the compressed image data, and synchronously output the decompressed image data; The preprocessing and blocking of the image data in S1 include: S11, Color Space Conversion: Perform color space conversion on the image data, converting the original RGB color space to the YUV color space; S12, Noise Filtering: Apply the Gaussian filtering algorithm to filter the noise in the image data; S13, Data Blocking: After the preprocessing is completed, divide the image data into several sub-blocks with adjustable sizes to meet the compression requirements of different regions; The data blocking in S13 includes: S131, Complexity Calculation: Calculate the complexity value C of each block area of the image to determine the size of the block; S132, Dynamic Block Adjustment: Dynamically adjust the size of the sub-block according to the calculated complexity value. Specifically, it includes: S1321, Define Complexity Thresholds: Define the upper complexity threshold limit TH and the lower complexity threshold limit TL of the block area; The upper complexity threshold limit TH and the lower complexity threshold limit TL are set by calculating the complexity mean μC and standard deviation σC of the entire image, expressed as: TH = μC + k × σC; TL = μC - k × σC; where M is the number of all sub-blocks in the image, Cj is the complexity of the j-th sub-block, and k is an adjustment coefficient used to adjust the sensitivity of the threshold; S1322, Complexity Division and Data Blocking: When C ≥ TH, it is regarded as a high-complexity region, and a block size of 4×4 pixels is selected. When C ≤ TL, it is regarded as a low-complexity region, and a block size of 16×16 pixels is selected. When TL < C < TH, it is regarded as a medium-complexity region, and a block size of 8×8 pixels is selected.

2. The efficient image compression and decompression method based on FPGA according to claim 1, characterized in that, The initialization of the distributed compression task in S2 includes: S21, Resource Requirement Calculation: Calculate the resource requirement R of each sub-block based on the complexity value C of each sub-block. S22, Task Allocation Strategy: According to the calculated resource requirement R, apply the weighted load allocation method to calculate the load allocation ratio of the FPGA processing unit. S23, Compression Task Initialization: After the resource requirement and load allocation ratio are determined, initialize the compression task of each sub-block to the allocated FPGA processing unit. Each processing unit starts the corresponding compression process according to the resource requirement of the sub-block it is allocated, and executes the compression tasks of each sub-block in parallel.

3. An efficient image compression and decompression method based on FPGA according to claim 1, characterized in that, The current switching frequency monitoring in S31 includes: S311, Sensor Arrangement and Signal Acquisition: Arrange on-chip current sensors near each processing unit within the FPGA, and collect the current signals of each processing unit in real time. S312, Current Fluctuation Detection: Detect the current change of the processing unit through the on-chip current sensor, calculate the number of current switching times per unit time, and obtain the current switching frequency f. S313, Current Fluctuation Situation Collection and Recording: While calculating the current switching frequency, collect the current fluctuation amplitude A of each processing unit.

4. An efficient image compression and decompression method based on FPGA according to claim 3, characterized in that The power load analysis in S32 includes: S321, Load Intensity Calculation: Calculate the load intensity L of the processing unit based on the current switching frequency f and current fluctuation amplitude A of each processing unit. S322, Power Impact Evaluation: Combine the load intensity values of all processing units, and evaluate the overall impact of the current distributed compression task on the power supply through the power impact evaluation model.

5. An efficient image compression and decompression method based on FPGA according to claim 4, characterized in that, The power impact evaluation model in S322 adopts a Bayesian network model. The Bayesian network model includes: S3221, Node Definition and Structure Construction: Define the key nodes in the Bayesian network, which are used to represent the main factors affecting the power supply, including load intensity L, current fluctuation amplitude A, current fluctuation frequency T within the time interval, and power load impact degree E. Build the node relationship, define the conditional dependence, and set E as the target node, and L, A, and T as its parent nodes respectively, indicating the direct action relationship on the power supply impact. S3222, Prior Probability Distribution Setting: Based on the prior of Bayesian smoothing, set the prior probabilities of the initial load intensity and fluctuation amplitude. S3223, Conditional Probability Table Optimization: According to the real-time load intensity L and current fluctuation amplitude A, dynamically calculate the conditional probability P(E|L,A,T), represent the power load impact as the joint conditional probability of load intensity, fluctuation amplitude, and time interval, and assign different weights α and β to the load intensity L and fluctuation amplitude A for dynamically adjusting the conditional probability. S3224, Real-time update and posterior probability calculation: Real-time update the posterior probability affected by the power load, and update it based on the data of the current load intensity, fluctuation amplitude, and time interval; S3225, Calculation of the degree of power load impact: Calculate the expected value of the final degree of power load impact E, which is used to evaluate the overall impact of the current compression task on the power supply.

6. An efficient image compression and decompression method based on FPGA according to claim 5, characterized in that The compression task load allocation in S33 includes: S331, Calculation of the load priority of the processing unit: Set the priority Ui for each processing unit according to the current switching frequency and the result of the power load analysis; S332, Task load requirement calculation: Calculate the load requirement for the compression task of each block ; S333, Dynamic load distribution strategy: According to the load demand of the task and the priority Ui of the processing unit, apply the dynamic load distribution algorithm to calculate the allocation probability P that task j is assigned to processing unit i. If the allocation probability exceeds the allocation probability threshold, then assign task j to processing unit i.

7. An efficient image compression and decompression method based on FPGA according to claim 1, characterized in that, The fault-tolerant data verification and redundancy detection in S4 includes: S41, Real-time data verification: When each processing unit executes the compression task, use the real-time monitoring unit of the FPGA to gradually verify the compressed data, and use the parity check code to identify data anomalies caused by power fluctuations and signal jitters; S42, Error detection and marking: When the monitoring unit detects an abnormal value in the compressed data, automatically mark the error data; S43, Redundancy verification and error correction: Perform redundancy detection on the marked error data, and use the data redundancy mechanism to correct the errors. The data redundancy mechanism uses the Hamming code.

8. An efficient image compression and decompression method based on FPGA according to claim 1, characterized in that, The distributed data decompression and synchronous output in S5 includes: S51, Distributed data decompression: Allocate the compressed image data to multiple processing units within the FPGA, and each processing unit independently performs the decompression operation on the data block it receives; S52, Data integrity verification: During the decompression process, perform integrity verification on the data blocks decompressed by each processing unit; S53, Sequential output of the decompressed data: After all processing units complete decompression, output according to the preset order of the data blocks.

Images