Cholesteric LCD display screen image display device based on FPGA

Abstract

The application discloses a cholesteric LCD display screen image display device based on FPGA, which comprises an image updating module, an image processing module, a timing control module and a source control signal generating module.The image updating module is used for converting received image bitmap data into RGB pixel data and then forwarding the RGB pixel data to the image processing module.The image processing module is used for receiving the RGB pixel data and storing the RGB pixel data into BRAM.The timing control module is used for obtaining a resolution score, generating a field synchronization signal and a line synchronization signal of a frame of image according to the resolution score, and transmitting the field synchronization signal and the line synchronization signal to the image processing module and the source control signal generating module.The timing control module is also used for generating a mode selection signal according to a working mode of a control system and transmitting the mode selection signal to the source control signal generating module.The display device can effectively control multi-gray scale display of the cholesteric LCD display screen, improve display efficiency and response speed, and has good scalability and flexibility.

Description

Technical Field

[0001] This invention relates to the field of LCD display technology, and more particularly to an image display device based on FPGA for cholesteric LCD display screens. Background Technology

[0002] FPGA devices are widely used in the field of digital signal processing due to their high flexibility, high-speed data processing capabilities, and low power consumption. Currently, the main interface protocols for image display based on FPGAs include DP, HDMI, DVI, and VGA. These technologies are widely used in various display devices, including but not limited to computer monitors, televisions, and projectors. However, in specific applications, such as cholesteric LCD displays, these traditional technologies have encountered challenges. In existing technologies, FPGA-based cholesteric LCD display systems can only display two gray levels, which significantly limits the image display quality and application scope. Summary of the Invention

[0003] To address the technical problems existing in the background art, the present invention proposes an image display device for a cholesteric LCD screen based on FPGA.

[0004] The present invention proposes an FPGA-based cholesteric phase LCD display image display device, comprising:

[0005] The image update module is used to convert the received image bitmap data into RGB pixel data and then forward it to the image processing module.

[0006] The image processing module is used to receive RGB pixel data and store the RGB pixel data in BRAM;

[0007] The timing control module is used to acquire the resolution score, generate a field synchronization signal and a line synchronization signal for a frame of image based on the resolution score, and transmit the field synchronization signal and the line synchronization signal to the image processing module and the source control signal generation module; it is also used to generate a mode selection signal according to the working mode of the control system, and transmit the mode selection signal to the source control signal generation module.

[0008] The image processing module is also used to generate a read address based on the field synchronization signal and the line synchronization signal, and then read the corresponding RGB pixel data from the BRAM according to the read address and output it to the source control signal generation module.

[0009] The source control signal generation module is used to generate source drive signals for driving the cholesteric LCD display based on the mode selection signal, field synchronization signal, line synchronization signal, RGB pixel data, and preset grayscale division strategy.

[0010] Preferably, the preset grayscale division strategy specifically includes:

[0011] Each pixel of the cholesteric LCD display is divided into regions so that each pixel corresponds to n display regions;

[0012] Assign display control signals to each of the n display areas one by one, so that the n display areas correspond to the n display control signals;

[0013] The RGB value corresponding to the current pixel is obtained from the RGB pixel data, and n display control signals are driven according to the specific value of the RGB value to realize the display of N gray levels on the cholesteric LCD screen; where N=2 n n is greater than or equal to 1 and is a natural number.

[0014] Preferably, the n display areas specifically include a first area A, a second area B, and a third area C; the step of driving and controlling n display control signals according to the specific values ​​of the RGB values ​​to achieve the display of N gray levels on the cholesteric LCD screen specifically includes:

[0015] Based on the specific values ​​of the RGB values, the display instructions corresponding to the first region A, the second region B, and the third region C of the current pixel are determined to enable the cholesteric LCD display to display 8 gray levels. The display instructions include turning on and turning off.

[0016] Preferably, the source drive signal includes an output control data signal DATA, a source clock output signal SCLK, an image latch enable signal LE, and a cascade control signal STL; the output control data signal DATA specifically includes n display control signals.

[0017] Preferably, the timing control module is also used to transmit the field synchronization signal and the line synchronization signal to the gate control signal generation module.

[0018] Preferably, it further includes:

[0019] The gate control signal generation module is used to generate a gate drive signal for driving the cholesteric LCD display based on the mode selection signal, the field synchronization signal, and the line synchronization signal. The gate drive signal includes a gate clock output signal GCLK and a cascaded control signal STV.

[0020] Preferably, the timing control module is also used to transmit the mode selection signal, the field synchronization signal, and the line synchronization signal to the PWM signal generation module.

[0021] Preferably, it further includes:

[0022] The PWM signal generation module is used to generate PWM signals based on the mode selection signal and the field synchronization signal, so as to control the voltage output of the power supply circuit in the cholesteric LCD display in the corresponding working mode.

[0023] Preferably, the working modes include image update mode, screen refresh mode, and image display mode.

[0024] This invention proposes an FPGA-based image display device for a cholesteric LCD screen. By dividing each pixel of the cholesteric LCD screen into regions, each pixel corresponds to n display areas. Then, by controlling the display of these n display areas, the cholesteric LCD screen can display multiple grayscale levels. This effectively controls the grayscale display of the cholesteric LCD screen, improving display efficiency and response speed, while also exhibiting good scalability and flexibility. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the device architecture for the cholesteric phase LCD display image display device based on FPGA proposed in this invention;

[0026] Figure 2 This is a schematic diagram of pixel region division for the cholesteric LCD display image display device based on FPGA proposed in this invention. Figure 1 ;

[0027] Figure 3 This is a schematic diagram of the output control data signal DATA of the cholesteric phase LCD display image display device based on FPGA proposed in this invention;

[0028] Figure 4 This is a schematic diagram of pixel region division for the cholesteric LCD display image display device based on FPGA proposed in this invention. Figure 2 . Detailed Implementation

[0029] Reference Figure 1-4 The present invention proposes an FPGA-based cholesteric LCD display image display device, comprising:

[0030] The image update module is used to convert the received image bitmap data into RGB pixel data and then forward it to the image processing module.

[0031] In this embodiment, the image update module receives image bitmap data sent by SPI.

[0032] The image processing module is used to receive RGB pixel data and store the RGB pixel data in BRAM.

[0033] The timing control module is used to acquire the resolution score, generate a field synchronization signal and a line synchronization signal for a frame of image based on the resolution score, and transmit the field synchronization signal and the line synchronization signal to the image processing module and the source control signal generation module; it is also used to generate a mode selection signal according to the working mode of the control system, and transmit the mode selection signal to the source control signal generation module.

[0034] The timing control module is also used to transmit the field synchronization signal and the horizontal synchronization signal to the gate control signal generation module.

[0035] The timing control module is also used to transmit the mode selection signal, field synchronization signal and line synchronization signal to the PWM signal generation module.

[0036] In this embodiment, the timing control module generates a field synchronization signal and a line synchronization signal for a frame of image, controls each module to generate the required signals, and then drives the cholesteric LCD display to achieve image display. Because the system can adapt to different resolutions, this module can receive resolution parameters to generate field synchronization and line synchronization signals of different resolutions; in addition, the timing control module outputs a mode selection signal to control the system's operating mode.

[0037] The image processing module is also used to generate a read address based on the field synchronization signal and the line synchronization signal, and then read the corresponding RGB pixel data from the BRAM according to the read address and output it to the source control signal generation module.

[0038] The source control signal generation module is used to generate source drive signals for driving the cholesteric LCD display based on the mode selection signal, field synchronization signal, line synchronization signal, RGB pixel data, and preset grayscale division strategy.

[0039] In this embodiment, the source drive signal includes the output control data signal DATA, the source clock output signal SCLK, the image latch enable signal LE, and the cascade control signal STL; the output control data signal DATA specifically includes n display control signals.

[0040] In this embodiment, the preset grayscale division strategy specifically includes: dividing each pixel of the cholesteric LCD display into regions, so that each pixel corresponds to n display regions; assigning display control signals to each of the n display regions, so that the n display regions correspond to n display control signals; obtaining the RGB value corresponding to the current pixel from the RGB pixel data, and driving the control of the n display control signals according to the specific value of the RGB value, so as to realize the cholesteric LCD display displaying N grayscale levels; where N=2 n n is greater than or equal to 1 and is a natural number.

[0041] In this embodiment, the n display areas specifically include a first area A, a second area B, and a third area C; the n display control signals are driven and controlled according to the specific values ​​of the RGB values ​​to achieve the display of N gray levels on the cholesteric LCD screen, specifically including:

[0042] Based on the specific values ​​of the RGB values, the display instructions corresponding to the first region A, the second region B, and the third region C of the current pixel are determined to enable the cholesteric LCD display to display 8 gray levels. The display instructions include turning on and off.

[0043] Specifically, such as Figure 2 As shown, different combinations of lighting in regions A, B, and C will display different gray levels, for a total of eight gray levels. For example: when the RGB value is less than the first threshold, A, B, and C are not lit; when the RGB value is greater than or equal to the first threshold and less than the second threshold, A is lit, while B and C are not lit; ..., when the RGB value is greater than or equal to the eighth threshold, all A, B, and C are lit. The values ​​corresponding to the first, second, ... eighth thresholds gradually increase. For example, the first threshold is 32, the second threshold is 64, and the eighth threshold is 224.

[0044] Since a pixel is displayed by three regions, a 3-bit wide signal source ([s3 s2 s1]) is defined in the FPGA to control it. The output DATA signal is composed as follows: Figure 3 As shown.

[0045] Specifically, such as Figure 4 As shown, since a pixel is displayed by four regions, different combinations of these regions (A, B, C, and D) will display different gray levels when lit, resulting in a total of 16 gray levels. For example, when RGB is less than 16, A, B, C, and D are not lit; when RGB is greater than or equal to 16 and less than 32, A is lit, while B, C, and D are not lit; ..., when RGB is greater than or equal to 16 and less than 224, A is not lit, while B, C, and D are lit; and when RGB is greater than or equal to 240, A, B, C, and D are lit.

[0046] In this embodiment, it also includes:

[0047] The gate control signal generation module is used to generate gate drive signals for driving the cholesteric LCD display based on the mode selection signal, field synchronization signal, and line synchronization signal. The gate drive signals include the gate clock output signal GCLK and the cascade control signal STV.

[0048] The PWM signal generation module is used to generate PWM signals based on the mode selection signal and the field synchronization signal, so as to control the voltage output of the power supply circuit in the cholesteric LCD display in the corresponding working mode.

[0049] In this embodiment, the working modes include image update mode, screen refresh mode, and image display mode.

[0050] Specifically, when the working mode is image update mode, the image update module receives the image bitmap data to be updated through the SPI interface, converts the image bitmap data into RGB pixel data according to the bitmap protocol and outputs it to the image processing module. After generating the write address, the image processing module stores the RGB image bitmap data in BRAM, which means the image update is complete.

[0051] Specifically, when the working mode is the screen refresh mode, due to the special nature of the screen, the screen refresh mode is entered first each time the image is refreshed. The PWM signal generation module first outputs the maximum positive voltage control signal to the screen, then the maximum negative voltage control signal, and then the 0V voltage control signal. The duration of each voltage control signal is one frame of signal refresh time.

[0052] Specifically, when the operating mode is image display mode, the timing control module generates field synchronization signals and line synchronization signals. The image processing module generates a read address based on the field synchronization signals and line synchronization signals, reads the corresponding RGB pixel data from the BRAM, and outputs it to the source control signal generation module. The source control signal generation module generates STL, LE, DATA, and SCLK signals to drive the cholesteric LCD display based on the field synchronization signals, line synchronization signals, and RGB pixel data. At the same time, the gate control signal generation module generates GCLK and STV signals to drive the cholesteric LCD display based on the field synchronization signals and line synchronization signals. The PWM signal generation module provides control signals for the image display voltage to the screen.

[0053] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A cholesteric phase LCD display image display device based on FPGA, characterized in that, include: The image update module is used to convert the received image bitmap data into RGB pixel data and then forward it to the image processing module. The image processing module is used to receive RGB pixel data and store the RGB pixel data in BRAM; The timing control module is used to acquire the resolution score, generate a field synchronization signal and a line synchronization signal for a frame of image based on the resolution score, and transmit the field synchronization signal and the line synchronization signal to the image processing module and the source control signal generation module; it is also used to generate a mode selection signal according to the working mode of the control system, and transmit the mode selection signal to the source control signal generation module. The image processing module is also used to generate a read address based on the field synchronization signal and the line synchronization signal, and then read the corresponding RGB pixel data from the BRAM according to the read address and output it to the source control signal generation module. The source control signal generation module is used to generate source drive signals for driving the cholesteric LCD display based on the mode selection signal, field synchronization signal, line synchronization signal, RGB pixel data and preset grayscale division strategy. The preset grayscale division strategy specifically includes: Each pixel of the cholesteric LCD display is divided into regions so that each pixel corresponds to n display regions; Assign display control signals to each of the n display areas one by one, so that the n display areas correspond to the n display control signals; The RGB value corresponding to the current pixel is obtained from the RGB pixel data, and n display control signals are driven according to the specific value of the RGB value to realize the display of N gray levels on the cholesteric LCD display screen; wherein, n is greater than or equal to 1 and is a natural number.

2. The FPGA-based cholesteric LCD display image display device according to claim 1, characterized in that, The n display areas specifically include a first area A, a second area B, and a third area C; the step of driving and controlling n display control signals according to the specific values ​​of the RGB values ​​to achieve the display of N gray levels on the cholesteric LCD screen specifically includes: Based on the specific values ​​of the RGB values, the display instructions corresponding to the first region A, the second region B, and the third region C of the current pixel are determined to enable the cholesteric LCD display to display 8 gray levels. The display instructions include turning on and turning off.

3. The FPGA-based cholesteric LCD display image display device according to claim 1, characterized in that, The source drive signal includes the output control data signal DATA, the source clock output signal SCLK, the image latch enable signal LE, and the cascade control signal STL; the output control data signal DATA specifically includes n display control signals.

4. The cholesteric phase LCD display image display device based on FPGA according to claim 1, characterized in that, The timing control module is also used to transmit the field synchronization signal and the horizontal synchronization signal to the gate control signal generation module.

5. The FPGA-based cholesteric LCD display image display device according to claim 4, characterized in that, Also includes: The gate control signal generation module is used to generate a gate drive signal for driving the cholesteric LCD display based on the mode selection signal, the field synchronization signal, and the line synchronization signal. The gate drive signal includes a gate clock output signal GCLK and a cascaded control signal STV.

6. The FPGA-based cholesteric LCD display image display device according to claim 5, characterized in that, The timing control module is also used to transmit the mode selection signal, field synchronization signal and line synchronization signal to the PWM signal generation module.

7. The FPGA-based cholesteric LCD display image display device according to claim 6, characterized in that, Also includes: The PWM signal generation module is used to generate PWM signals based on the mode selection signal and the field synchronization signal, so as to control the voltage output of the power supply circuit in the cholesteric LCD display in the corresponding working mode.

8. The cholesteric phase LCD display image display device based on FPGA according to claim 7, characterized in that, The operating modes include image update mode, screen refresh mode, and image display mode.

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