Memory system and memory device

Abstract

Embodiments provide a memory system and a memory device having high performance and high reliability. A memory system includes a non-volatile memory and a memory controller. A non-volatile memory includes a memory cell and a control circuit that writes n-bit first data to the memory cell through a first write operation and writes m-bit second data including the n-bit of the first data to the memory cell through a second write operation. The memory controller issues a first command sequence to the non-volatile memory to perform a first write operation, selects one of a first method and a second method for preparing second data for a second write operation based on an indicator related to reliability of the first data stored in the memory unit, and issue a second command sequence to the non-volatile memory to perform a second write operation, wherein the second command sequence indicates the selected method for preparing the second data.

Description

Technical Field

[0001]

[0013] Generally speaking, embodiments described herein relate to memory systems and memory devices. Background Art

[0002] A solid state drive (SSD) including a memory controller and a memory device is referred to as a type of memory system. The memory device is, for example, a nonvolatile memory. The nonvolatile memory is, for example, a NAND flash memory. Summary of the invention

[0003] Embodiments provide a memory system and a memory device having high performance and high reliability.

[0004] In general, according to one embodiment, a memory system includes a nonvolatile memory and a memory controller electrically connected to the nonvolatile memory. The nonvolatile memory includes: a storage unit for storing data in a nonvolatile manner, and a control circuit for writing n-bit (n is a real number of 1 or greater) first data to the storage unit through a first write operation, and writing m-bit (m is a real number greater than n) second data including the n-bit first data to the storage unit through a second write operation. The memory controller issues a first command sequence to the nonvolatile memory to perform a first write operation, selects one of a first method and a second method for preparing second data for a second write operation based on an indicator related to the reliability of the first data stored in the storage unit, and issues a second command sequence to the nonvolatile memory to perform a second write operation, wherein the second command sequence indicates the selected method for preparing the second data. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram showing a configuration example of a memory system according to the first embodiment.

[0006] Figure 2 is a block diagram showing a configuration example of a nonvolatile memory according to the first embodiment.

[0007] Figure 3 is a circuit diagram of a memory cell array of the nonvolatile memory according to the first embodiment.

[0008] Figure 4 is a diagram showing an example of the relationship between the threshold voltage and data of the memory cell according to the first embodiment.

[0009] Figure 5 This is a block diagram showing a configuration example of a write management circuit in the memory system according to the first embodiment.

[0010] Figure 6 It is a diagram showing a configuration example of a management table in the memory system according to the first embodiment.

[0011] Figure 7 : is a diagram showing an operation example of a first write operation in the memory system of the first embodiment.

[0012] Figure 8 2 is a diagram showing an operation example of the second write operation in the memory system of the first embodiment.

[0013] Fig. 9 : is a diagram showing an operation example of a write operation in the memory system of the first embodiment.

[0014] Fig.10 : is a sequence diagram showing an operation example of a write operation in the memory system of the first embodiment.

[0015] Fig.11 is a sequence diagram showing another operation example of the write operation in the memory system of the first embodiment.

[0016] Fig.12 is a sequence diagram showing another operation example of the write operation in the memory system of the first embodiment.

[0017] Fig.13 is a sequence diagram showing an example of a command sequence of a first write operation in the memory system of the first embodiment.

[0018] Fig.14 is a sequence diagram showing an example of a command sequence of a second write operation in the memory system of the first embodiment.

[0019] Fig.15A is a sequence diagram showing another example of the command sequence of the second write operation in the memory system of the first embodiment.

[0020] Fig. 15B is a sequence diagram showing another example of the command sequence of the second write operation in the memory system of the first embodiment.

[0021] Fig.16 : is a flowchart showing an operation example of a write operation in the memory system of the first embodiment.

[0022] Fig.17 is a flowchart showing an operation example of a first write operation in the memory system of the first embodiment.

[0023] Fig.18 : is a diagram showing an operation example of a first write operation in the memory system of the first embodiment.

[0024] Fig.19is a flowchart showing an operation example of the second write operation in the memory system of the first embodiment.

[0025] Fig. 20 2 is a diagram showing an operation example of the second write operation in the memory system of the first embodiment.

[0026] Fig.21 This is a block diagram showing a configuration example of a first modification of the memory system according to the first embodiment.

[0027] FIG. 22A to FIG. 22C It is a diagram showing a configuration example of a second modification example of the memory system according to the first embodiment.

[0028] Fig.23 This is a block diagram showing a configuration example of a third modification example of the memory system according to the first embodiment.

[0029] Fig.24 is a block diagram showing a configuration example of a memory system according to the second embodiment.

[0030] Fig.25 is a flowchart showing an operation example of a write operation in the memory system according to the second embodiment.

[0031] Fig.26 : is a diagram showing an operation example of a write operation in the memory system according to the second embodiment.

[0032] Fig. 27 This is a block diagram showing a configuration example of a first modification example of the memory system according to the second embodiment.

[0033] Fig.28 1 is a diagram showing an operation example of a write operation in the first modification example of the memory system according to the second embodiment.

[0034] Fig.29 This is a block diagram showing a configuration example of a second modification of the memory system according to the second embodiment.

[0035] Fig.30 : is a flowchart showing an operation example of a write operation in the second modification example of the memory system of the second embodiment.

[0036] Fig.31 is a block diagram showing a configuration example of a memory system according to a third embodiment.

[0037] Fig.32 is a flowchart showing an operation example of a write operation in the memory system according to the third embodiment.

[0038] Fig.33: is a flowchart showing an operation example of a write operation according to a modification of the memory system according to the third embodiment.

[0039] Fig.34 is a block diagram showing a configuration example of a memory system according to a fourth embodiment.

[0040] Fig.35 : is a diagram showing an operation example of a write operation in the memory system according to the fourth embodiment.

[0041] Fig.36 is a block diagram showing a configuration example of a memory system according to a fifth embodiment.

[0042] Fig.37 is a flowchart showing an operation example of a write operation in the memory system according to the fifth embodiment. DETAILED DESCRIPTION

[0043] Will refer to Figures 1 to 37 A memory system of an embodiment is described.

[0044] In the following description, the same reference symbols are used to represent elements having the same function and configuration. In addition, in each of the following embodiments, numbers / letters for distinguishing may be used at the end of the reference symbols of elements (e.g., circuits, wiring, various voltages and signals). When it may be impossible to distinguish these elements from each other, reference symbols without such numbers / letters at the end are used.

[0045] (1) First Embodiment

[0046] Will refer to Figures 1 to 23 A memory system of the first embodiment is described.

[0047] (a) Structural example

[0048] (a-1) Information processing system

[0049] like Figure 1 As shown in , the information processing system 9 includes a memory system 1 and a host 2 .

[0050] The memory system 1 is a device for storing data. For example, the memory system 1 is a solid state drive (SSD), a universal flash memory (UFS) device, a universal serial bus (USB) memory, a multimedia card (MMC), or a The memory system 1 may be connected to the host 2 via a host bus HBS. The memory system 1 performs processing based on a request (eg, a command or a host command) received from the host 2 or a spontaneous processing request generated inside the memory system 1.

[0051] The host 2 is a computing device that controls the memory system 1. For example, the host 2 is a personal computer, a server system, a mobile device, a vehicle-mounted device, or a digital camera.

[0052] (a-1-1) Internal structure of the memory system

[0053] The memory system 1 includes a memory controller 10 and a memory device 30. The memory device 30 is, for example, a nonvolatile memory. The memory device 30 is, for example, a nonvolatile semiconductor memory such as a NAND flash memory. Hereinafter, the memory device 30 is referred to as a nonvolatile memory 30 or a NAND memory 30.

[0054] The memory controller 10 is a device that controls the NAND memory 30. The memory controller 10 is configured to be connected to the host 2 via a host bus HBS. The memory controller 10 receives a request from the host 2 via the host bus HBS. The type of the host bus HBS depends on the application applied to the memory system 1. When the memory system 1 is an SSD, the host bus HBS complies with, for example, the Serial Attached SCSI (SAS) standard, the Serial ATA (SATA) standard, or the Peripheral Component Interconnect Express (PCIe) standard. TM ) standard. When the memory system 1 is a UFS device, the host bus HBS complies with the M-PHY standard. When the memory system 1 is a USB memory, the host bus HBS complies with the USB standard. When the memory system 1 is an MMC, the host bus HBS complies with the embedded Multimedia Card (eMMC) standard. When the memory system 1 is an SD TM Card, the host bus HBS complies with SD TM standard.

[0055] The memory controller 10 controls the NAND memory 30 via the NAND bus NBS based on a request received from the host 2 or a spontaneous processing request generated within the memory system 1. For example, the NAND bus NBS complies with the Switching NAND Flash Interface Standard or the Open NAND Flash Interface Specification.

[0056] The NAND memory 30 is a device for storing data. The NAND memory 30 includes a plurality of memory cells. Each of the plurality of memory cells stores data in a nonvolatile manner according to a threshold voltage of the memory cell. The NAND memory 30 stores data received from the memory controller 10 in the plurality of memory cells in a nonvolatile manner. The NAND memory 30 outputs the data read from the plurality of memory cells to the memory controller 10.

[0057] (a-1-2) Memory controller

[0058] An example of the internal configuration of the memory controller 10 will be described.

[0059] like Figure 1 As shown in , the memory controller 10 includes a host interface (I / F) circuit 11, a processor 12, a buffer memory 13, an error check and correction (ECC) circuit 14, a read-only memory (ROM) 15, a random access memory (RAM) 16, a NAND interface (I / F) circuit 17, and a write management circuit 18. The host interface circuit 11, the processor 12, the buffer memory 13, the ECC circuit 14, the ROM 15, the NAND interface circuit 17, and the write management circuit 18 may be configured as, for example, a system on chip (SoC) 100. In Figure 1 In the example shown, the RAM 16 is implemented outside the SoC 100, but the RAM 16 may be implemented inside the SoC 100. The memory controller 10 may be configured with a plurality of chips. The functions of each part of the memory controller 10 may be implemented by a dedicated hardware circuit, a processor executing a program (firmware), or a combination thereof.

[0060] The host interface circuit 11 is a circuit that controls communication between the memory controller 10 and the host 2. The host interface circuit 11 is configured to be connected to the host 2 via a host bus HBS.

[0061] The processor 12 is a control circuit of the memory controller 10. The processor 12 is, for example, a central processing unit (CPU). The processor 12 controls the operation of the entire memory controller 10 by executing a program (firmware) stored in the ROM 15. For example, the processor 12 controls a write operation based on a write request received from the host 2. The same applies to a read operation and an erase operation.

[0062] The buffer memory 13 is a memory that temporarily stores data. The buffer memory 13 is, for example, a static random access memory (SRAM). The buffer memory 13 temporarily stores write data, read data, and the like. The write data is data to be written to the NAND memory 30. The read data is data read from the NAND memory 30.

[0063] The ECC circuit 14 is a circuit that performs an error check and correction (ECC) process to correct data errors. The ECC circuit 14 generates an error correction code based on the write data during a data write operation. The ECC circuit 14 generates a syndrome based on the error correction code in a predetermined unit during a data read operation, and detects an error. The ECC circuit 14 corrects the detected error.

[0064] The ROM 15 is a nonvolatile memory. For example, the ROM 15 is an electrically erasable programmable read-only memory (EEPROM). TM ). The ROM 15 stores programs such as firmware.

[0065] The RAM 16 is a volatile memory. The RAM 16 is, for example, an SRAM or a dynamic random access memory (DRAM). The RAM 16 is used as a work area of ​​the processor 12. The RAM 16 stores firmware and various management information for managing the NAND memory 30. For example, the RAM 16 stores various tables TBL1.

[0066] The NAND interface circuit 17 is a circuit that controls communication between the memory controller 10 and the NAND memory 30. The NAND interface circuit 17 is connected to the NAND memory 30 via a NAND bus NBS. For example, the NAND interface circuit 17 controls the transmission of data, commands, addresses, etc. between the memory controller 10 and the NAND memory 30.

[0067] The write management circuit 18 performs various managements of write operations to be performed by the NAND memory 30 based on the state of data in the NAND memory 30 .

[0068] (a-1-3) NAND flash memory

[0069] Will refer to Figure 2 The configuration of the NAND memory 30 is described.

[0070] Figure 2 is a block diagram showing a configuration example of a NAND memory 30. The NAND memory 30 includes a memory cell array 31, an input / output circuit 32, a logic control circuit 33, a ready / busy control circuit 34, a register 35, a sequencer 36, a driver module 37, a row decoder module 38, a sense amplifier module 39, and a data latch 40.

[0071] The memory cell array 31 includes one or more blocks BLK0, BLK1, ..., and BLKk-1. Here, k is an integer of 1 or more. Block BLK is, for example, a collection of multiple memory cells that are erased together. For example, block BLK is used as a unit of data erase operation. A plurality of bit lines and a plurality of word lines are set in the memory cell array 31. Each memory cell is associated with, for example, a bit line and a word line. The memory cell array 31 will be described in detail later.

[0072] The input / output circuit 32 is a circuit that communicates with the memory controller 10. The input / output circuit 32 transmits and receives input / output signals DQ (e.g., 8-bit signals DQ0 to DQ7) and a data strobe signal DQS with the memory controller 10. The signal DQ contains data communicated between the NAND memory 30 and the memory controller 10. For example, the signal DQ is a command CMD, an address ADD, status information STS, and data DAT. The signal DQS is a signal (e.g., a synchronization signal) for controlling the communication timing of the signal DQ. For example, when writing data, the signal DQS is sent from the memory controller 10 to the NAND memory 30 together with the signal DQ including the write data. The NAND memory 30 receives the signal DQ including the write data synchronously with the signal DQS. When reading data, the signal DQS is sent from the NAND memory 30 together with the signal DQ including the read data to the memory controller 10. The memory controller 10 receives the signal DQ including the read data synchronously with the signal DQS. The input / output circuit 32 may receive the signal DQS from the memory controller 10 via the logic control circuit 33 .

[0073] The input / output circuit 32 sends the command CMD in the signal DQ to the command register 35A. The input / output circuit 32 sends the address ADD in the signal DQ to the address register 35B. The input / output circuit 32 receives the status information STS from the status register 35C. The input / output circuit 32 sends and receives the data DAT in the signal DQ to and from the data latch 40.

[0074] The logic control circuit 33 is a circuit for controlling the input / output circuit 32 and the sequencer 36 based on control signals. The logic control circuit 33 receives a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the memory controller 10. The signal CEn is a signal for enabling the NAND memory 30. The signal CLE is a signal indicating that the signal DQ received by the NAND memory 30 includes a command CMD. The signal ALE is a signal indicating that the signal DQ received by the NAND memory 30 includes an address ADD. The signal WEn is a signal for instructing the NAND memory 30 to input the signal DQ. The signal REn is a signal for instructing the NAND memory 30 to output the signal DQ. The NAND memory 30 generates a signal DQS based on the signal REn. The NAND memory 30 outputs the signal DQ to the memory controller 10 based on the generated signal DQS.

[0075] The ready / busy control circuit 34 is a circuit that notifies the memory controller 10 of the operating state of the sequencer 36. The ready / busy control circuit 34 sends a ready / busy signal RBn to the memory controller 10 based on the operating state of the sequencer 36. The signal RBn is a signal indicating whether the NAND memory 30 is in a ready state or a busy state. When the NAND memory 30 is in the ready state, the signal level of the signal RBn is set to, for example, a high level ("H" level). The ready state is a state in which the NAND memory 30 can receive a command from the memory controller 10. When the NAND memory 30 is in the busy state, the signal level of the signal RBn is set to, for example, a low level ("L" level). The busy state is a state in which the NAND memory 30 cannot receive a command from the memory controller 10.

[0076] The register 35 is a circuit for temporarily storing information and includes a command register 35A, an address register 35B, and a status register 35C.

[0077] The command register 35A is a circuit for storing a command CMD. For example, the command CMD includes a command for causing the sequencer 36 to perform a read operation, a write operation, or an erase operation.

[0078] The address register 35B is a circuit for storing the address ADD. For example, the address ADD includes a row address and a column address CAd. The row address includes a block address BAd and a page address PAd (also a word line address). For example, the block address BAd, the page address PAd and the column address CAd are used to select a block BLK, a word line and a bit line, respectively.

[0079] The status register 35C is a circuit that temporarily stores status information STS during, for example, a read operation, a write operation, or an erase operation. The status information STS is used to notify the memory controller 10 whether the operation has been normally completed.

[0080] The sequencer 36 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 36 controls the operation of the entire NAND memory 30. For example, the sequencer 36 controls the ready / busy control circuit 34, the driver module 37, the row decoder module 38, and the sense amplifier module 39 based on the command CMD stored in the command register 35A. For example, the sequencer 36 performs a read operation, a write operation, and an erase operation.

[0081] The driver module 37 is a circuit that generates voltages used in read operations, write operations, and erase operations. The driver module 37 applies the generated voltages to the signal lines corresponding to the selected word lines based on the page address PAd stored in the address register 35B.

[0082] The row decoder module 38 is a circuit that selects one block BLK in the memory cell array 31 based on the block address Bad stored in the address register 35B. The row decoder module 38 transfers a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0083] In a write operation, the sense amplifier module 39 receives write data DAT from the input / output circuit 32 via the data latch 40. The sense amplifier module 39 applies a voltage to the bit line based on the received write data DAT. In a read operation, the sense amplifier module 39 determines the data stored in the memory cell based on whether there is a current in the bit line or the voltage of the bit line. The sense amplifier module 39 transmits the determination result as read data DAT to the input / output circuit 32 via the data latch 40.

[0084] The data latch (also referred to as a data cache) 40 includes a plurality of latch circuits (not shown). Each latch circuit temporarily stores write data or read data. In a write operation, for example, the data latch 40 temporarily stores write data received from the input / output circuit 32 and sends the write data to the sense amplifier module 39. In addition, in a read operation, the data latch 40 temporarily stores read data received from the sense amplifier module 39 and sends the read data to the input / output circuit 32.

[0085] Example of the structure of a memory cell array

[0086] Will refer to Figure 3 The circuit configuration of the memory cell array 31 is described. Figure 3 is a circuit diagram of the memory cell array 31. Figure 3 1 is shown as an example of a circuit configuration of a block BLK0 provided in the memory cell array 31. Other blocks BLK also have the same Figure 3 The same configuration in .

[0087] Block BLK0 includes, for example, five string units SU0, SU1, SU2, SU3 and SU4. Each string unit SU is, for example, a set of multiple NAND strings NS selected together in a write operation or a read operation. Each string unit SU includes multiple NAND strings NS associated with bit lines BL0, BL1, ..., and BLm-1, respectively. Here, m is an integer of 1 or greater. The NAND string NS is a set of multiple memory cells connected in series. Each NAND string NS includes, for example, memory cells MC0, MC1, MC2, MC3, ..., MCn-2 and MCn-1, a selection transistor ST1 and a selection transistor ST2. Here, n is an integer of 1 or greater. The memory cell MC (also referred to as a memory cell transistor) is a field effect transistor including a control gate and a charge storage layer. The selection transistors ST1 and ST2 are switching elements. In various operations, each of the selection transistors ST1 and ST2 is used to select the string unit SU.

[0088] In each NAND string NS, MC0, ..., and MCn-1 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the memory cells MC0, ..., and MCn-1 connected in series. The drain of the selection transistor ST2 is connected to the other end of the memory cells MC0, ..., and MCn-1 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

[0089] In the same block BLK, the control gates of the memory cells MC0, MC1, MC2, MC3, ..., MCn-2 and MCn-1 are respectively connected to the word lines WL0, WL1, WL2, WL3, ..., WLn-2 and WLn-1 in common among the multiple NAND strings. The gates of the selection transistors ST1 in the string units SU0, SU1, SU2, SU3 and SU4 are respectively connected to the selection gate lines SGD0, SGD1, SGD2, SGD3 and SGD4 in common among the multiple NAND strings. The gates of the selection transistors ST2 set in the same block BLK are respectively connected to the selection gate line SGS in common among the multiple NAND strings.

[0090] In the circuit configuration of the memory cell array 31 described above, the bit line BL is shared by, for example, the NAND strings NS to which the same column address CAd is assigned in each string unit SU. The source line SL is shared among, for example, a plurality of blocks BLK.

[0091] In one string unit SU, a set of multiple memory cells MC commonly connected to a word line WL is called, for example, a unit cell (cell unit) CU. The block BLK includes multiple unit cells CU. The data stored in the unit cell CU including multiple memory cells MC that store 1 bit of data respectively according to the threshold voltage corresponds to one page of data. The unit cell CU can store two or more pages of data based on the number of data bits stored in each memory cell MC. In this embodiment, one memory cell MC can store 4 bits of data. That is, the memory cell MC in this embodiment is a quad-layer cell (QLC) that stores 4 bits of data. In this case, the data stored in the unit cell CU corresponds to four pages of data.

[0092] The number of data bits that can be stored in the memory cell MC can be any real number. For example, the memory cell MC can be a multi-level cell (MLC) storing 2 bits of data, a triple-level cell (TLC) storing 3 bits of data, or a five-level cell (PLC) storing 5 bits of data.

[0093] It should be noted that the circuit configuration of the memory cell array 31 is not limited to the above configuration. For example, the number of string units SU provided in each block BLK and the number of memory cells MC and selection transistors ST1 and ST2 provided in each NAND string NS may be any number.

[0094] Threshold voltage distribution of memory cells

[0095] Will refer to Figure 4 The threshold voltage distribution of the memory cells MC is described. Figure 4 is a diagram showing an example of the relationship between the threshold voltage distribution of the memory cells MC and the data stored in the memory cells MC. Figure 4 The horizontal axis represents the threshold voltage of the memory cell MC. Figure 4 The vertical axis represents the number of memory cells MC.

[0096] like Figure 4 As shown in , when the memory cell MC stores 4 bits of data, the distribution of the threshold voltage is divided into 16 distributions. In order from the lowest threshold voltage, these 16 threshold voltage distributions are called "St0" state, "St1" state, ..., "St14" state and "St15" state.

[0097] In addition, voltages V1, V2, ..., and V15 are voltages (hereinafter referred to as "verification voltages") used to verify the "St1" state, the "St2" state, and the "St15" state, respectively, during a write operation (for example, applied to the gate of the memory cell MC via the selected word line WL). The voltage VREAD is a voltage applied to the non-selected word line WL during a read operation. When the voltage VREAD is applied to the gate of the memory cell MC, the memory cell MC is turned on regardless of the data stored therein. The relationship between these voltage values ​​is V1 <V2<V3<V4<V5<V6<V7<V8<V9<V10<V11<V12<V13<V14<V15<VREAD。

[0098] The "St0" state corresponds to the erased state of the memory cell MC. The "St1" state, the "St2" state, ..., and the "St15" state correspond to the states in which charge is injected into the charge storage layer of the memory cell MC and data is written therein. The threshold voltage of the memory cell MC in the "St0" state is lower than the voltage V1. The threshold voltages of the memory cells MC in the "St1" state to the "St14" state are respectively equal to or higher than the voltage V1 to the voltage V14, and are respectively lower than the voltage V2 to the voltage V15. The threshold voltage of the memory cell MC in the "St15" state is equal to or higher than the voltage V15, and is lower than the voltage VREAD.

[0099] The set value of the verification voltage and the set value of the read voltage corresponding to each state applied to the gate of the memory cell MC via the selected word line WL during the write operation and the read operation respectively may be the same or different. In the following, in order to simplify the description, the case where the verification voltage and the read voltage have the same set value will be described.

[0100] Hereinafter, each read operation using voltages V1, V2, ..., and V15 is referred to as read operations R1, R2, ..., and R15. Read operation R1 determines whether the threshold voltage of memory cell MC is lower than voltage V1. Read operation R2 determines whether the threshold voltage of memory cell MC is lower than voltage V2. Read operation R3 determines whether the threshold voltage of memory cell MC is lower than voltage V3. The same applies to other read operations.

[0101] As described above, by having a threshold voltage belonging to any one of 16 threshold voltage distributions, each memory cell MC can be in 16 different states. By assigning these states to data of binary symbols "0000", ..., and "1111", each memory cell MC can store 4 bits of data. In the following, the 4-bit data is referred to as the low bit, the middle bit, the high bit, and the top bit in order from the lowest bit. In addition, the set of low bits stored in the memory cell MC set in the same unit cell CU is called the lower page, the set of middle bits is called the middle page, the set of high bits is called the upper page, and the set of top bits is called the top page.

[0102] exist Figure 4 In the example, data is assigned to the "lower / middle / upper / top bits" of the memory cell MC set in each state as shown below.

[0103] "St0" state: "1111" data

[0104] "St1" status: "1110" data

[0105] "St2" status: "1100" data

[0106] "St3" status: "1101" data

[0107] "St4" status: "1001" data

[0108] "St5" status: "1011" data

[0109] "St6" status: "0011" data

[0110] "St7" status: "0010" data

[0111] "St8" status: "1010" data

[0112] "St9" status: "1000" data

[0113] "St10" status: "0000" data

[0114] "St11" status: "0001" data

[0115] "St12" status: "0101" data

[0116] "St13" status: "0111" data

[0117] "St14" status: "0110" data

[0118] "St15" status: "0100" data

[0119] The data assigned to each state is not limited to this example.

[0120] When reading data distributed in this manner, the lower bits are determined by reading operations R6, R8, and R10. The middle bits are determined by reading operations R4 and R12. The upper bits are determined by reading operations R2, R5, R9, R13, and R15. The top bits are determined by reading operations R1, R3, R7, R11, and R14.

[0121] In the memory system 1 of the present embodiment, four pages of data are written to the NAND memory 30 through a first write operation (hereinafter also referred to as MLC programming) of writing data of the lower page and the middle page, and a second write operation (hereinafter also referred to as fine programming) of writing data of the lower page and the middle page and data of the upper page and the top page after the first write operation, which will be described later.

[0122] During the second write operation, lower page data and intermediate page data used in the second write operation are prepared by loading data from inside the NAND memory 30 or outside the NAND memory 30 .

[0123] The data loading methods for the next page / middle page data include internal data loading (IDL) and external data loading (EDL).

[0124] IDL is a method of loading (providing) lower / middle page data for the second write operation from the memory cell array 31 within the NAND memory 30 .

[0125] EDL is a method of loading (providing) lower / middle page data for the second write operation from the outside of the NAND memory 30 (eg, the RAM 16 of the memory controller 10).

[0126] In the memory system 1 of this embodiment, a data loading method for the lower page data and the middle page data for the second write operation is determined based on a certain indicator related to the reliability of the lower page data and the middle page data written to the NAND memory 30 by the first write operation.

[0127] For example, the reliability of data written to the memory cell array 31 of the NAND memory 30 varies according to the time the data is stored in the memory cell array 31 or the operating state of the NAND memory 30 (eg, temperature and / or usage time).

[0128] (a-1-4) Write management circuit

[0129] Figure 51 is a block diagram showing a configuration example of the write management circuit 18 of the memory controller 10 in the memory system 1 according to the present embodiment.

[0130] like Figure 5 As shown in , the write management circuit 18 includes a data load selector 181 and a global clock 182 .

[0131] The data loading selector 181 selects a data loading method of either IDL or EDL based on a certain index related to the reliability of the lower page data and the intermediate page data written by the first write operation.

[0132] The global clock 182 is a timer. The global clock 182 measures time, for example, from the first power-on of the memory system 1. When the power of the memory system 1 is turned off, the global clock 182 may temporarily stop measuring time. The time measured until the power is turned off may be stored in the NAND memory 30. When the power supply is restarted from the power-off state in the memory system 1, the global clock 182 may restart the measurement of the time. The global clock 182 may restart the measurement of time from the time measured until the power is turned off.

[0133] In the write management circuit 18, the data load selector 181 records the completion time of the first write operation measured by the global clock 182 in the management table TBL1. The management table TBL1 is stored in, for example, the RAM 16. The management table TBL1 may be stored in a storage area (for example, a register) provided in the write management circuit 18.

[0134] Figure 6 1 is a diagram showing a management table TBL1 in the memory system 1 according to the present embodiment.

[0135] The management table TBL1 is a log table that records corresponding values ​​for each of the following items: the word line number (word line address) that is the object of the first write operation, the number of the string unit number that is the object of the first write operation, and the completion time of the first write operation. For example, for one write destination block, one management table TBL1 is prepared. This is because multiple write target blocks can be used in parallel.

[0136] Hereinafter, the management table TBL1 is also referred to as an MLC program log table TBL1.

[0137] The data loading selector 181 refers to the MLC programming log table TBL1 and selects the data loading method for the lower page data and the middle page data during the second writing operation. The data loading selector 181 determines the data loading method at the second writing operation based on the current time indicated by the global clock 182 (i.e., the time immediately before the second writing operation is performed, or the time when the data loading method is selected) and the completion time of the first writing operation at the corresponding address of the MLC programming log table TBL1.

[0138] For example, the data loading selector 181 compares the difference between the current moment and the completion moment of the first write operation with a threshold value for determining the data loading method. When the difference is greater than the threshold value, the data loading selector 181 selects EDL. Therefore, in the second write operation, EDL is used as the data loading method for the lower / middle page data. When the difference is equal to or less than the threshold value, the data loading selector 181 selects IDL. Therefore, in the second write operation, IDL is used as the data loading method for the lower / middle page data.

[0139] (b) Operation

[0140] Will refer to Figures 7 to 20 An operation example of the memory system 1 of the present embodiment is described.

[0141] (b-1) Overview of write operation

[0142] An overview of a write operation of the NAND memory 30 in the memory system 1 of the present embodiment will be described.

[0143] The write operation (write sequence) of the NAND memory 30 includes a program operation and a verification operation (also referred to as program verification). By repeating a combination of the program operation and the verification operation, the threshold voltage of the memory cell MC is increased to a target level.

[0144] The programming operation is an operation of increasing the threshold voltage of the memory cell MC (or maintaining the threshold voltage by prohibiting injection) by injecting electrons into the charge storage layer of the memory cell MC. Hereinafter, the operation of increasing the threshold voltage of the memory cell MC is referred to as "0" programming. For example, increasing the threshold voltage of the memory cell MC in the "St0" state to be included in the "St1" state is referred to as "0" programming. From the sense amplifier module 39, a voltage (e.g., voltage VSS) for "0" programming is applied to the bit line BL as the "0" programming target. At the same time, the operation of maintaining the threshold voltage of the memory cell MC is referred to as "1" programming or write prohibition. From the sense amplifier module 39, a voltage (e.g., a positive voltage) for "1" programming is applied to the bit line BL as the "1" programming target.

[0145] The verification operation is an operation to determine whether the threshold voltage of the memory cell MC reaches the target level by reading data from the memory cell MC after the programming operation. The memory cell MC whose threshold voltage reaches the target level is set to be write-prohibited.

[0146] In this embodiment, the above-mentioned writing operation is performed in two separate phases. Specifically, in two phases of the first writing operation (MLC programming) and the second writing operation (fine programming), the writing operation of four pages of data corresponding to a specific unit cell CU is performed.

[0147] (b-1-1) First Write Operation

[0148] Will refer to Figure 7 The first write operation (MLC programming) of the memory system 1 of the present embodiment is described.

[0149] Figure 7 is a graph showing changes in threshold voltage distribution of memory cells MC due to the first write operation.

[0150] When the first write operation is performed, the threshold voltage of the memory cell MC increases based on the write data, and four threshold voltage distributions are formed.

[0151] like Figure 7 As shown in , the first write operation forms an "M0" state, an "M1" state, an "M2" state, and an "M3" state. For example, in the first write operation, a threshold voltage distribution of the "M0" state is formed by multiple memory cells MC that write "11" data. Here, the "kh" data indicates that the low bit is "k" data, and the middle bit is "h" data. A threshold voltage distribution of the "M1" state is formed by multiple memory cells MC that write "10" data. A threshold voltage distribution of the "M2" state is formed by multiple memory cells MC that write "00" data. A threshold voltage distribution of the "M3" state is formed by multiple memory cells MC that write "01" data.

[0152] The sequencer 36 uses voltages VM1, VM2, and VM3 as verification voltages. Voltage VM1 is a verification voltage used when writing "10" data. Voltage VM1 is equal to or higher than voltage V1, and lower than voltage V4. Voltage VM2 is a verification voltage used when writing "00" data. Voltage VM2 is equal to or higher than voltage V4, and lower than voltage V6. Voltage VM3 is a verification voltage used when writing "01" data. Voltage VM3 is equal to or higher than voltage V6, and lower than voltage V12.

[0153] The threshold voltage of the memory cell MC in the "M0" state is lower than the voltage V1. The threshold voltage of the memory cell MC in the "M1" state is equal to or higher than the voltage VM1 and lower than the voltage V5. The threshold voltage of the memory cell MC in the "M2" state is equal to or higher than the voltage VM2 and lower than the voltage V7. The threshold voltage of the memory cell MC in the "M3" state is equal to or higher than the voltage VM3 and lower than the voltage V13.

[0154] Hereinafter, the phase in which the first write operation is performed is referred to as the MLC phase. The memory cell MC on which the first write operation has been performed and on which the second write operation has not yet been performed is referred to as a memory cell MC in the MLC state.

[0155] (b-1-2) Second Writing Operation

[0156] Will refer to Figure 8 The second write operation (fine programming) of the memory system 1 of the present embodiment is described.

[0157] Figure 8 is a graph showing changes in threshold voltage distribution of memory cells MC due to the second write operation.

[0158] When the second write operation is performed, the threshold voltage of the memory cell MC is increased based on the write data, and 16 threshold voltage distributions are formed.

[0159] like Figure 8 As shown in, in the second write operation, for example, according to the threshold voltage distribution of the "M0" state, the threshold voltage distributions of the "St0" state, the "St1" state, the "St2" state, and the "St3" state are formed. According to the threshold voltage distribution of the "M1" state, the threshold voltage distributions of the "St4" state, the "St5" state, the "St8" state, and the "St9" state are formed. According to the threshold voltage distribution of the "M2" state, the threshold voltage distributions of the "St6" state, the "St7" state, the "St10" state, and the "St11" state are formed. According to the threshold voltage distribution of the "M3" state, the threshold voltage distributions of the "St12" state, the "St13" state, the "St14" state, and the "St15" state are formed.

[0160] For example, when the threshold voltage distribution of the "M0" state changes to the threshold voltage distribution of the "St3" state, the data stored in the memory cell MC changes from the data of the "M0" state ("11" data) to the data of the "St3" state ("1101" data).

[0161] For example, when the threshold voltage distribution of the "M1" state changes to the threshold voltage distribution of the "St4" state, the data stored in the memory cell MC changes from the data of the "M1" state ("10" data) to the data of the "St3" state ("1001" data).

[0162] For example, when the threshold voltage distribution of the "M2" state changes to the threshold voltage distribution of the "St7" state, the data stored in the memory cell MC changes from the data of the "M2" state ("00" data) to the data of the "St7" state ("0010" data).

[0163] For example, when the threshold voltage distribution of the "M3" state changes to the threshold voltage distribution of the "St14" state, the data stored in the memory cell MC changes from the data of the "M3" state ("01" data) to the data of the "St14" state ("0110" data).

[0164] Hereinafter, the phase in which the second write operation is performed is referred to as a fine phase.

[0165] (b-1-3) Write operation execution order

[0166] Fig. 9 An example of the selection order of the word line WL and the string unit SU when writing data in a certain block BLK is shown. The solid line quadrilateral box corresponding to the intersection between each word line WL and each string unit SU represents a unit cell CU. The upper segment separated by the dotted line of the quadrilateral box represents the write operation in the MLC stage. The lower segment separated by the dotted line of the quadrilateral box represents the write operation in the fine stage. The values ​​of the upper and lower segments of the quadrilateral box represent the execution order of MLC programming and fine programming of multiple memory cells MC in each unit cell CU of a certain block BLK (hereinafter referred to as "write order").

[0167] like Fig. 9 As shown in , as first to fifth operations, the sequencer 36 performs a first write operation of selecting the word line WL0 and sequentially selecting the string units SU0 to SU4.

[0168] As a sixth operation, the sequencer 36 performs a first write operation of selecting the string unit SU0 and selecting the word line WL1. As a seventh operation, the sequencer 36 performs a second write operation of selecting the string unit SU0 and selecting the word line WL0.

[0169] As eighth to fifteenth operations, the sequencer 36 sequentially selects the string units SU1 , . . . , and SU4 , and alternately performs a first write operation of selecting the word line WL1 and a second write operation of selecting the word line WL0 in the same order as the sixth and seventh operations.

[0170] As sixteenth to twenty-fifth operations, the sequencer 36 sequentially selects the string units SU1 , . . . , and SU4 in the same manner as the sixth to fifteenth operations, and alternately performs a first write operation selecting the word line WL2 and a second write operation selecting the word line WL1 .

[0171] Thereafter, in the same manner as the (26+10p)th to (35+10p)th operations, the sequencer 36 sequentially selects the string units SU1, ..., and SU4, alternately performing a first write operation of selecting the word line WL(3+p) and a second write operation of selecting the word line WL(2+p). Here, p is an integer of 0 or greater.

[0172] In the above order, the first write operation and the second write operation are sequentially performed on the unit cell CU designated by the data write target address (hereinafter also referred to as the selected address).

[0173] It should be noted that the NAND memory 30 performs a second write operation on the unit cell CU specified by the selected address without performing an erase operation on the block BLK including the unit cell CU between the first write operation (MLC programming) and the second write operation (fine programming) performed on the unit cell CU.

[0174] (b-2) Data loading method

[0175] Will refer to Figures 10 to 12 Describes the data loading method in a write operation.

[0176] As described above, in the second write operation (fine programming), the lower page data and the intermediate page data are prepared inside the NAND memory 30 by IDL or are prepared outside the NAND memory 20 by EDL.

[0177] (b-2-1)IDL

[0178] Will refer to Fig.10 The IDL when fine programming is performed in the memory system 1 of the present embodiment is described.

[0179] Fig.10 is a sequence diagram showing IDL in elaborate programming.

[0180] like Fig.10 As shown in , the memory system 1 of the present embodiment performs MLC programming (first writing operation) before performing fine programming (second writing operation).

[0181] In the MLC programming, the SoC 100 of the memory controller 10 loads the lower page data and the middle page data from the RAM 16. The RAM 16 stores the lower page data and the middle page data received from the host 2.

[0182] For MLC programming, SoC 100 sends the lower page data and the middle page data loaded from RAM 16 together with the command and address to NAND memory 30. Thus, sense amplifier module 39 of NAND memory 30 receives the lower page data and the middle page data via data latch 40 (referred to as data loading).

[0183] The NAND memory 30 programs the lower page data and the middle page data in the sense amplifier module 39 into the unit cell CU specified by the address received from the NAND interface circuit 17. Thus, the memory cell array 31 stores two pages of data of the lower page / middle page data.

[0184] In the memory system 1 of the present embodiment, MLC programming is completed as described above.

[0185] The memory system 1 of the present embodiment performs fine programming on the unit cell CU specified by the address for performing MLC programming.

[0186] The SoC 100 loads the upper page data and the top page data from the RAM 16. The RAM 16 stores the upper page data and the top page data received from the host 2.

[0187] When fine programming is performed using IDL, SoC 100 sends upper and top page data loaded from RAM 16 to NAND memory 30 together with commands and addresses without transferring lower / middle page data to NAND memory 30. Thus, sense amplifier module 39 receives upper and top page data.

[0188] When fine programming using IDL is performed, lower / middle page data is loaded from the memory cell array 31 into the sense amplifier module 39 within the NAND memory 30 .

[0189] Thus, the sense amplifier module 39 stores upper / top page data from the SoC 100 and lower / middle page data from the memory cell array 31 .

[0190] The NAND memory 30 programs the lower page data, middle page data, upper page data, and top page data in the sense amplifier module 39 into the unit cell CU specified by the address received from the NAND interface circuit 17. Thus, the memory cell array 31 stores four pages of data of the lower page / middle page / upper page / top page data.

[0191] As reference Fig.10 As described, the IDL prepares the lower page data and the middle page data for fine programming by reading the lower page data and the middle page data from the memory cell array 31 in the NAND memory 30 and loading them into the sense amplifier module 39 .

[0192] (b-2-2)EDL

[0193] Will refer to Fig.11 and Fig.12 The EDL when fine programming is performed in the memory system 1 of the present embodiment is described.

[0194] The EDL for fine programming prepares the lower / middle page data from the RAM 16. The EDL may also include ECC processing for the lower / middle page data.

[0195] like Fig.11 As shown in the figure, through MLC programming, to Fig.10 In the same manner as in the example of , the lower page data and the middle page data are programmed into the memory cell array 31.

[0196] When fine programming is performed, the SoC 100 loads the upper page / top page data provided from the host 2 from the RAM 16 .

[0197] As described above, the EDL is outside the NAND memory 30 and prepares the next page data and the intermediate page data.

[0198] exist Fig.11 In the example of , the RAM 16 stores the lower / middle page data provided from the host 2. The lower / middle page data is the same as the lower / middle page data stored in the unit cell CU specified by the selected address, where the selected address is the address where fine programming will be performed. The NAND interface circuit 17 loads the lower / middle page data from the RAM 16.

[0199] The SoC 100 transmits the lower / middle / upper / top page data loaded from the RAM 16 together with the command and the address to the NAND memory 30. Thus, the sense amplifier module 39 receives the lower / middle / upper / top page data.

[0200] The NAND memory 30 programs the lower / middle / upper / top page data in the sense amplifier module 39 into the unit cell CU specified by the address received from the NAND interface circuit 17. Thus, the memory cell array 31 stores four pages of lower / middle / upper / top page data.

[0201] Fig.12 Shows the Fig.11 Examples of different EDL data loading methods.

[0202] like Fig.12 As shown in the figure, through MLC programming, to Fig.10 and Fig.11In the same manner as in the example of , the lower page data and the middle page data are programmed into the memory cell array 31.

[0203] exist Fig.12 In the example of , when a request is made to perform fine programming, the memory controller 10 (SoC 100) reads the lower page data and the middle page data from the unit cell CU specified by the corresponding address of the NAND memory 30. The ECC circuit 14 of the SoC 100 performs ECC processing on the lower page data and the middle page data. Thus, the lower page data and the middle page data processed by ECC are generated.

[0204] The SoC 100 sends the ECC processed lower / middle page data to the NAND memory 30. The sense amplifier module 39 receives the ECC processed lower / middle page data. Before sending the ECC processed lower / middle page data to the sense amplifier module 39, it may be stored in the RAM 16.

[0205] The SoC 100 loads the upper / top page data from the RAM 16. The SoC 100 sends the upper / top page data together with the command and the address to the NAND memory 30. The sense amplifier module 39 receives the upper / top page data.

[0206] The NAND memory 30 programs the lower / middle / upper / top page data in the sense amplifier module 39 into the unit cell CU specified by the address received from the NAND interface circuit 17. Thus, the memory cell array 31 stores four pages of lower / middle / upper / top page data.

[0207] use Fig.11 or Fig.12 The fine programming of any one of the EDLs can be applied to the memory system 1. For example, when the RAM 16 has a large storage capacity, the memory system 1 performs Fig.11 The memory system 1 can be configured so that the method of fine programming to be performed is switched to the method of fine programming to be performed according to a request from the host 2 or the operating state of the memory system 1. Fig.11 Examples and Fig.12 any of the examples.

[0208] As reference Fig.11 and Fig.12 As described, the EDL is outside the NAND memory 30 and prepares lower page data and intermediate page data for fine programming.

[0209] (b-3) Command sequence

[0210] Will refer to Figures 13 to 15B A command sequence of the memory system 1 of the present embodiment will be described.

[0211] (b-3-1) Command Sequence of the First Write Operation

[0212] Fig.13 1 is a diagram showing a command sequence of a first write operation (MLC programming) in the memory system 1 of the present embodiment.

[0213] like Fig.13 As shown in FIG. 1 , when the memory controller 10 instructs the NAND memory 30 to perform MLC programming, the memory controller 10 sends a plurality of command sets 500 ( 500 - 1 , 500 - 2 ) to the NAND memory 30 in the stage of performing the MLC programming (MLC stage).

[0214] The memory controller 10 sends a command set 500-1 to the NAND memory 30. The command set 500-1 is a signal group related to writing the lower page data.

[0215] The command set 500 - 1 includes commands 501 , 502 - 1 , 503 , and 507 , addresses 504 ( 504 - 1 and 504 - 2 ) and 505 ( 505 - 1 , 505 - 2 , 505 - 3 , and 505 - 4 ), and write data 506 - 1 .

[0216] Commands 501, 502-1, and 503 include command codes "A1h", "01h", and "80h", respectively. The NAND memory 30 receives commands 501, 502-1, and 503. Command 501 with a command code "A1h" is a prefix command to be added when a command for a write operation in the MLC stage (or a read operation from a memory cell MC in the MLC state) is given. Command 502-1 with a command code "01h" is a command for instructing the NAND memory 30 to perform an operation corresponding to the data on the first page (lower page). Command 503 with a command code "80h" is a command instructing the start of inputting a write target address.

[0217] After sending command 503 of command code "80h", the memory controller 10 sends addresses 504 and 505 to the NAND memory 30. Address 504 includes addresses 504-1 and 504-2. Address 505 includes addresses 505-1, 505-2, 505-3 and 505-4. The NAND memory 30 receives addresses 504 and 505. Addresses 504-1 and 504-2 are column addresses. Addresses 505-1, 505-2, 505-3 and 505-4 are row addresses. Column address 504 is sent in two cycles. Row address 505 is sent in four cycles. Depending on the size of the memory cell array 31 (e.g., the number of blocks BLK, the number of word lines WL), the number of cycles used to send each address is appropriately changed.

[0218] After sending the addresses 504 and 505, the memory controller 10 sends the lower page data 506-1 as write data to the NAND memory 30. The NAND memory 30 receives the lower page data 506-1.

[0219] After sending the next page data 506-1, the memory controller 10 sends a command 507 of a command code "1Ah" to the NAND memory 30. The NAND memory 30 receives the command 507. The command 507 of the command code "1Ah" is a command for transferring data from the data latch 40 in the NAND memory 30 to the sense amplifier module 39.

[0220] After the NAND memory 30 receives the command 507 of the command code "1Ah", the NAND memory 30 enters the busy state. Therefore, the NAND memory 30 changes the signal level of the ready / busy signal RBn from the "H" level to the "L" level.

[0221] During the period when the signal level of the ready / busy signal RBn is at the “L” level, the next page data 506 - 1 is transmitted from the data latch 40 to the sense amplifier module 39 .

[0222] After the sense amplifier module 39 stores the next page data 506-1, the NAND memory 30 enters the ready state. Therefore, the NAND memory 30 changes the signal level of the ready / busy signal RBn from the "L" level to the "H" level.

[0223] After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-2 to the NAND memory 30 in the ready state. The command set 500-2 is a signal group related to writing intermediate page data.

[0224] The command set 500 - 2 includes commands 502 - 2 , 503 , and 508 , addresses 504 and 505 , and write data 506 - 2 .

[0225] The commands 502-2 and 503 include command codes “02h” and “80h”, respectively. The NAND memory 30 receives the commands 502-2 and 503. The command 502-2 of the command code “02h” is a command for instructing the NAND memory 30 to perform an operation corresponding to data of the second page (middle page).

[0226] After sending command 503 of command code "80h", memory controller 10 sends addresses 504 and 505 to NAND memory 30. NAND memory 30 receives addresses 504 and 505. The values ​​of addresses 504 and 505 provided in command set 500-2 coincide with the values ​​of addresses 502 and 505 provided in command set 500-1.

[0227] After sending the addresses 504 and 505, the memory controller 10 sends the intermediate page data 506-2 as write data to the NAND memory 30. The NAND memory 30 receives the intermediate page data 506-2.

[0228] After transferring the intermediate page data 506-2, the memory controller 10 sends a command 508 of a command code "10h" to the NAND memory 30. The NAND memory 30 receives the command 508. The command 508 of the command code "10h" is a command for performing a program operation.

[0229] The NAND memory 30 performs writing of the lower page / middle page data (MLC programming) in the sense amplifier module 39 based on reception of the command 508 of the command code "10h". The NAND memory 30 enters a busy state during execution of the MLC programming. During the period tPROG during execution of the MLC programming, the NAND memory 30 changes the signal level of the ready / busy signal RBn from the "H" level to the "L" level.

[0230] During the period tPROG in which the signal level of the ready / busy signal RBn is at the “L” level, two pages of data are written into the unit cell CU designated by the write target address in the memory cell array 31 .

[0231] When the MLC programming is completed, the NAND memory 30 enters the ready state. Therefore, the NAND memory 30 changes the signal level of the ready / busy signal RBn from the "L" level to the "H" level.

[0232] As described above, the memory system 1 of this embodiment can be based on Fig.13 command sequence to perform MLC programming.

[0233] (b-3-2) Command Sequence of Second Write Operation

[0234] When a request is made to write the upper / top page data to the address storing the lower / middle page data, based on Fig.14 or Fig.15A or Fig. 15B , performs a second write operation (fine programming) on ​​this address.

[0235] (b-3-2-1) Command sequence for the second write operation using IDL

[0236] Fig.14 1 is a diagram showing a command sequence of fine programming using IDL in the memory system 1 of the present embodiment.

[0237] When targeting through Fig.13 When data is written to an address where MLC programming has been performed in the command sequence, the memory system 1 of the present embodiment performs fine programming on the address.

[0238] like Fig.14 As shown in , when the memory controller 10 instructs the NAND memory 30 to perform fine programming using IDL, in the stage of performing fine programming (fine stage), the memory controller 10 sends a plurality of command sets 500 (500-3, 500-4) for performing fine programming to the NAND memory 30.

[0239] In this embodiment, the memory controller 10 sends a signal 555 to the NAND memory 30 for notifying the selection of the IDL in the fine programming. The NAND memory 30 receives the signal 555. The signal 555 is a flag or a prefix command indicating that the data loading method for the fine programming is the IDL. The signal 555 is a signal of 1 bit or more bits.

[0240] After sending the signal 555, the memory controller 10 sends a command set 500-3 to the NAND memory 30. The command set 500-3 is a signal group related to writing of upper page data.

[0241] The command set 500 - 3 includes commands 502 - 3 , 503 , and 507 , addresses 504 ( 504 - 1 and 504 - 2 ) and 505 ( 505 - 1 , 505 - 2 , 505 - 3 , and 505 - 4 ), and write data 506 - 3 .

[0242] The commands 502-3 and 503 include command codes “03h” and “80h”, respectively. The NAND memory 30 receives the commands 502-3 and 503. The command 502-3 of the command code “03h” is a command for instructing the NAND memory 30 to perform an operation corresponding to data of the third page (upper page).

[0243] After sending the command 503 of the command code "80h", the memory controller 10 sends addresses 504 and 505 to the NAND memory 30. The NAND memory 30 receives the addresses 504 and 505. For example, the values ​​of the addresses 504 and 505 provided in the command set 500-3 are the same as the values ​​of the addresses 504 and 505 provided in the command sets 500-1 and 500-2 for MLC programming.

[0244] After sending the addresses 504 and 505, the memory controller 10 sends the upper page data 506-3 as write data to the NAND memory 30. The NAND memory 30 receives the upper page data 506-3.

[0245] After sending the upper page data 506 - 3 , the memory controller 10 sends a command 507 of a command code “1Ah” to the NAND memory 30 . The NAND memory 30 receives the command 507 .

[0246] After the NAND memory 30 receives the command 507 of the command code "1Ah", the NAND memory 30 enters a busy state.

[0247] During the period in which the signal level of the ready / busy signal RBn is at the “L” level, the upper page data 506 - 3 is transferred from the data latch 40 in the NAND memory 30 to the sense amplifier module 39 .

[0248] After the sense amplifier module 39 stores the upper page data 506 - 3 , the NAND memory 30 enters a ready state.

[0249] After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-4 to the NAND memory 30 in the ready state. The command set 500-4 is a signal group related to writing of top page data.

[0250] The command set 500 - 4 includes commands 502 - 4 , 503 , and 508 , addresses 504 and 505 , and write data 506 - 4 .

[0251] Commands 502-4 and 503 include command codes “04h” and “80h”, respectively. The NAND memory 30 receives the commands 502-4 and 503. The command 502-4 of the command code “04h” is a command for instructing the NAND memory 30 to perform an operation corresponding to data of the fourth page (top page).

[0252] After sending the command 503 of the command code "80h", the memory controller 10 sends addresses 504 and 505 to the NAND memory 30. The NAND memory 30 receives the addresses 504 and 504. The values ​​of the addresses 504 and 505 provided in the command set 500-4 are the same as the values ​​of the addresses 504 and 505 provided in the command sets 500-1, 500-2, and 500-3.

[0253] After sending the addresses 504 and 505, the memory controller 10 sends the top page data 506-4 as write data to the NAND memory 30. The NAND memory 30 receives the top page data 506-4.

[0254] After sending the top page data 506 - 4 , the memory controller 10 sends a command 508 of a command code “10h” to the NAND memory 30 . The NAND memory 30 receives the command 508 .

[0255] For example, in the fine stage using IDL, the lower / middle page data is loaded from the memory cell array 31 to the sense amplifier module 39 at a timing after the command sets 500 - 3 and 500 - 4 related to the upper / top page data are transmitted.

[0256] Upon receiving the command 508 with the command code "10h", the NAND memory 30 performs writing (fine programming) of the lower / middle / upper / top page data in the sense amplifier module 39. Upon receiving the command 508 with the command code "10h", the NAND memory 30 enters a busy state.

[0257] During the period tPROG in which the signal level of the ready / busy signal RBn is at the “L” level, data of four pages are written into the unit cells CU designated by the write target address of the memory cell array 31 .

[0258] When the fine programming is completed, the NAND memory 30 enters a ready state.

[0259] In the memory system 1 of the present embodiment, fine programming using IDL is performed as described above.

[0260] As described above, the memory system 1 of this embodiment can be based on Fig.14 The command sequence in , uses IDL to perform fine-grained programming.

[0261] (b-3-2-2) Command sequence for the second write operation using EDL

[0262] Fig.15A 1 is a diagram showing a command sequence of fine programming using EDL in the memory system 1 of the present embodiment.

[0263] In the case where the lower page / intermediate page data prepared by EDL is generated by ECC processing (see Fig.12 ), the memory system 1 performs an operation of reading the lower page / middle page data from the NAND memory 30.

[0264] like Fig.15A As shown in FIG. 1 , in the fine stage using EDL, the memory controller 10 sends a plurality of command sets 700 ( 700 - 1 , 700 - 2 , 700 - 3 , 700 - 4 ) to the NAND memory 30 for reading lower / middle page data from the NAND memory 30 .

[0265] The memory controller 10 sends a command set 700 - 1 to the NAND memory 30 . The command set 700 - 1 is a signal group related to reading the next page data from the memory cell array 31 to the sense amplifier module 39 .

[0266] The command set 700 - 1 includes commands 501 , 502 - 1 , 701 , and 702 , and addresses 504 and 505 .

[0267] The commands 501, 502-1, and 701 include command codes "A1h," "01h," and "00h," respectively. The NAND memory 30 receives the commands 501, 502-1, and 701. The command 701 of the command code "00h" is a command instructing to start inputting a read target address.

[0268] After sending the command 701 of the command code “00h”, the memory controller 10 sends the read target addresses 504 and 505 of the lower page data to the NAND memory 30 . The NAND memory 30 receives the addresses 504 and 505 .

[0269] After sending the addresses 504 and 505, the memory controller 10 sends a command 702 of a command code “30h” to the NAND memory 30. The NAND memory 30 receives the command 702. The command 702 of the command code “30h” is a command for instructing the NAND memory 30 to output the data of the read target address from the memory cell array 31 to the data latch 40 (sense amplifier module 39).

[0270] After the NAND memory 30 receives the command 702 with the command code “30h”, the NAND memory 30 enters the busy state. In the period tR, the NAND memory 30 reads the next page data from the unit cells CU indicated by the addresses 504 and 505 to the sense amplifier module 39 .

[0271] After the sense amplifier module 39 stores the next page data, the NAND memory 30 enters a ready state.

[0272] After the signal level of the ready / busy signal RBn changes from the “L” level to the “H” level, the memory controller 10 sends a command set 700-2 to the NAND memory 30. The command set 700-2 is a signal group related to data transfer from the NAND memory 30 to the memory controller 10.

[0273] Command set 700 - 2 includes commands 703 and 704 and addresses 504 and 505 .

[0274] The memory controller 10 sends a command 703 of command code “05h” to the NAND memory 30 . The command 703 of command code “05h” is a command for instructing the NAND memory 30 to execute an operation (cache read) of outputting data from the designated column address 504 of the data latch 40 to the memory controller 10 .

[0275] After sending the command 703 of the command code "05h", the memory controller 10 sends addresses 504 and 505 to the NAND memory 30. The values ​​of addresses 504 and 505 of the command set 700-2 are the same as those of the command set 700-1.

[0276] After sending the addresses 504 and 505, the memory controller 10 sends a command 704 of a command code “E0h” to the NAND memory 30. The command 704 of the command code “E0h” is a command for instructing the NAND memory 30 to output data to the memory controller 10.

[0277] The NAND memory 30 sequentially receives the command 703, the addresses 504 and 505, and the command 704. The NAND memory 30 transmits the lower page data 705-1 in the sense amplifier module 39 to the memory controller 10 via the data latch 40 based on the commands 703 and 704 of the command codes "05h" and "E0h". The memory controller 10 receives the lower page data 705-1.

[0278] After receiving the read lower page data 705 - 1 , the memory controller 10 sends a command set 700 - 3 to the NAND memory 30 . The command set 700 - 3 is a signal group related to reading the middle page data from the memory cell array 31 to the sense amplifier module 39 .

[0279] The command set 700 - 3 includes commands 501 , 502 - 2 , 701 , and 702 , and addresses 504 and 505 .

[0280] In the same manner as reading the lower page data according to the command set 700-1, after the sense amplifier module 39 stores the middle page data according to the command set 700-3, the NAND memory 30 enters the ready state.

[0281] After the signal level of the ready / busy signal RBn changes to the “H” level, the memory controller 10 sends a command set 700 - 4 to the NAND memory 30 . The command set 700 - 4 includes commands 703 and 704 and addresses 504 and 505 .

[0282] In the same manner as reading the lower page data according to the command set 700-2, the NAND memory 30 sends the middle page data 705-2 to the memory controller 10 according to the command set 700-4. The memory controller 10 receives the middle page data 705-2.

[0283] The memory controller 10 performs an ECC process on each of the received lower page data 705 - 1 and intermediate page data 705 - 2 .

[0284] By performing the ECC process, ECC-processed lower page data and intermediate page data are generated.

[0285] After the ECC process, the memory controller 10 performs writing of lower / middle / upper / top page data (fine programming).

[0286] For example, in the present embodiment, the memory controller 10 sends a signal 777 to the NAND memory 30 to notify the selection of the EDL in the fine programming. The NAND memory 30 receives the signal 777. The signal 777 is a flag or a prefix command indicating that the data loading method for the fine programming is the EDL. The signal 777 is a signal of 1 bit or more bits.

[0287] Therefore, in the present embodiment, the memory controller 10 can notify the NAND memory 30 of the execution of the fine programming using the EDL.

[0288] After sending signal 777, the memory controller 10 sends a command set 500-A related to the next page data to the NAND memory 30. The command set 500-A basically includes the reference Fig.13 The command set 500-1 described above has the same commands, addresses, and write data, but does not include the command 501 with the command code "A1h". In addition, the write data 506-A provided in the command set 500-A is the next page data after ECC processing. It should be noted that the signal 777 can be a signal (command) provided in the command set 500-A. The NAND memory 30 receives the command set 500-A.

[0289] After receiving the command 507 with the command code "1Ah" provided in the command set 500-A, the NAND memory 30 Fig.13 In the same manner as described, the next page data 506 -A after ECC processing is stored in the sense amplifier module 39 .

[0290] After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-B related to the intermediate page data to the NAND memory 30. The command set 500-B includes the reference Fig.13The command set 500-2 described above has the same commands, addresses and write data. The write data 506-B provided in the command set 500-B is the intermediate page data after ECC processing. The NAND memory 30 receives the command set 500-B.

[0291] After receiving the command 507 with the command code "1Ah" provided in the command set 500-B, the NAND memory 30 Fig.13 In the same manner as described above, the middle page data 506 -B after ECC processing is stored in the sense amplifier module 39 .

[0292] After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-C related to the upper page data to the NAND memory 30. The command set 500-C includes the reference Fig.14 Command set 500-3 describes the same commands, addresses, and write data.

[0293] After receiving the command 507 with the command code "1Ah" provided in the command set 500-C, the NAND memory 30 Fig.14 In the same manner as described above, the upper page data 506 -C is stored in the sense amplifier module 39 .

[0294] After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-D related to the top page data to the NAND memory 30. The command set 500-D includes the reference Fig.14 Command set 500 - 4 describes the same commands, addresses, and write data.

[0295] The NAND memory 30 is based on the command 508 of the command code "10h" provided in the command set 500-D to communicate with the reference Fig.14 In the same manner as described above, the lower page / middle page / upper page / top page data in the sense amplifier module 39 is written into the memory cell array 31 through fine programming.

[0296] In the memory system 1 of the present embodiment, fine programming using EDL is completed as described above.

[0297] It should be noted that when the memory controller 10 transfers the lower page data and the middle page data from the RAM 16 to the NAND memory 30, the memory system 1 of the present embodiment performs fine programming using EDL based on command sets 500-A, 500-B, 500-C and 500-D, without performing operations based on command sets 700-1, 700-2, 700-3 and 700-4.

[0298] As described above, the memory system 1 of this embodiment can be based on Fig.15A A command sequence is provided to perform fine-grained programming using EDL.

[0299] Fig. 15B A modification example of the command sequence of fine programming using EDL in the memory system 1 of the present embodiment is shown.

[0300] like Fig. 15B As shown in , before reading the middle page data, the ECC processed lower page data 506-A can be sent from the RAM 16 to the NAND memory 30. After the command set 500-A sends the ECC processed lower page data 506-A to the NAND memory 30, the middle page data 705-2 is sent from the NAND memory 30 to the memory controller 10 through a read operation according to the command sets 700-3 and 700-4. The memory controller 10 performs ECC processing on the middle page data 705-2. The memory controller 10 sends the ECC processed middle page data 506-B to the NAND memory 30 by using the command set 500-B. Afterwards, the memory controller 10 sends the upper page data 506-C and the top page data 506-D to the NAND memory 30.

[0301] (b-4) Processing flow of write operation

[0302] Will refer to Figures 16 to 20 The processing flow of the write operation in the memory system 1 of the present embodiment will be described.

[0303] (b-4-1) Basic flow of write operation

[0304] Fig.16 : is a flowchart describing a write operation in the memory system 1 of the present embodiment.

[0305] The memory controller 10 receives a write request from the host 2 (S1). For example, the memory controller 10 receives a write request from the host 2 (S1). Fig. 9 The described write sequence determines that the write-requested data is written to the NAND memory 30 as lower page data and middle page data.

[0306] The memory controller 10 sends a command set for performing MLC programming (first write operation) to the NAND memory 30 based on the write request (S2).

[0307] The NAND memory 30 executes MLC programming according to the command set from the memory controller 10 ( S3 ). As a result, the lower page data and the middle page data are written to the memory cell array 31 of the NAND memory 30 .

[0308] The memory controller 10 receives a write request from the host 2 (S4). For example, the memory controller 10 receives a write request from the host 2 (S4). Fig. 9 The write sequence described determines that the data requested to be written is written as the upper page data and the top page data to the NAND memory 30 (the address where the MLC programming is performed). The memory controller 10 is ready to perform fine programming (the second write operation). It should be noted that the writing of the lower page data, the middle page data, the upper page data, and the top page data is determined based on a single write request from the host 2.

[0309] When performing fine programming, the memory controller 10 determines which of IDL or EDL to use as a data loading method (S5) based on an index related to the reliability of the lower page data and the middle page data stored in the NAND memory 30. The memory controller 10 selects either IDL or EDL based on the index (S6).

[0310] For example, in this embodiment, either the IDL or the EDL is selected based on the period from when the MLC programming is completed to when the fine programming starts.

[0311] When the memory controller 10 determines to use IDL as the data loading method of fine programming (Yes in S6), the memory controller 10 sends a command set for instructing the NAND memory 30 to perform fine programming using IDL (S7A).

[0312] The NAND memory 30 performs fine programming using IDL based on the command set from the memory controller 10 (S8A).

[0313] When the memory controller 10 determines to use EDL as the data loading method of fine programming (No in S6), the memory controller 10 sends a command set for instructing the NAND memory 30 to perform fine programming using EDL (S7B).

[0314] The NAND memory 30 performs fine programming using EDL based on the command set from the memory controller 10 ( S8B).

[0315] After performing fine programming of the NAND memory 30, the memory system 1 ends the operation.

[0316] (b-4-2) Specific Example of First Writing Operation

[0317] As described above, the memory system 1 of the present embodiment selects the data loading method when executing fine programming based on the reliability index of the lower page / middle page data at the start time of fine programming.

[0318] Fig.17: is a flowchart showing an operation example of the memory system 1 of the present embodiment when MLC programming is performed. Fig.18 is a diagram showing an operation example of the memory system 1 of the present embodiment when MLC programming is performed.

[0319] like Fig.17 As shown in , when performing MLC programming, the memory system 1 of the present embodiment starts managing information on an index for selecting a data loading method when performing fine programming.

[0320] The memory controller 10 instructs the NAND memory 30 to perform MLC programming ( S100 ). Thus, the MLC programming is performed in the NAND memory 30 .

[0321] For example, in response to the level of the ready / busy signal RBn changing from the "L" level to the "H" level, the processor 12 of the memory controller 10 detects the completion of the MLC programming. The processor 12 notifies the data load selector 181 of the write management circuit 18 of the completion of the MLC programming. Fig.18 As shown in FIG. 1 , the processor 12 sends a notification signal ACK1 to the data loading selector 181 , indicating the completion of the MLC programming.

[0322] The data loading selector 181 receives the notification signal ACK1 indicating that the MLC programming is completed ( Fig.17 (S101 in ).

[0323] The data loading selector 181 acquires the current time (MLC programming completion time) t t which is regarded as the time when the MLC programming is completed from the global clock 182 of the write management circuit 18 based on the notification signal ACK1 indicating the completion of the MLC programming. MLC (S102).

[0324] like Fig.18 As shown in FIG. 1 , the data loading selector 181 records the word line number as the target of the MLC programming, the string cell number as the target of the MLC programming, and the acquired MLC programming completion time t in the management table (MLC programming log table) TBL1 related to the MLC programming in the RAM 16. MLC ( Fig.17 (S103 in ).

[0325] Therefore, when performing MLC programming, the memory system 1 of the present embodiment can obtain information for selecting a data loading method when performing fine programming (here, it is the MLC programming completion time t MLC ).

[0326] As described above, the processing of each cell of the memory controller 10 at the MLC programming time is completed.

[0327] (b-4-3) Specific Example of Second Writing Operation

[0328] Fig.19 : is a flowchart showing an operation example of the memory system 1 of the present embodiment when fine programming is performed. Fig. 20 2 is a diagram showing an operation example of the memory system 1 of the present embodiment when fine programming is performed.

[0329] like Fig.19 As shown in , when fine programming is performed, the memory system 1 of the present embodiment starts various processes for selecting a data loading method.

[0330] The memory system 1 determines whether to perform fine programming on a certain address ( S110 ).

[0331] When it is determined to perform fine programming in the memory system 1, the processor 12 notifies the data load selector 181 of the execution of fine programming. Fig. 20 As shown in FIG. 1 , the processor 12 sends a notification signal ACK2 to the data loading selector 181 to indicate the execution of the fine programming. The data loading selector 181 receives the notification signal ACK2.

[0332] The data loading selector 181 obtains the current time before the fine programming starts (the time immediately before the fine programming starts) t from the global clock 182 based on the notification signal ACK2. c ( Fig.19 (S111 in ).

[0333] The data load selector 181 searches for the MLC program completion time t associated with the word line number and string cell number as the fine programming target from the plurality of entries of the MLC program log table TBL1. MLC Thus, the data load selector 181 obtains the MLC programming completion time t associated with the target address of the fine programming. MLC (S112).

[0334] The data loading selector 181 uses the current time t c and the obtained MLC programming completion time t MLC For example, the data loading selector 181 executes the current time t c and MLC programming completion time t MLC Subtraction processing (Dx = t c -t MLC ). Thus, the data load selector 181 acquires the elapsed time Dx from the completion of the MLC programming to the present at the corresponding address as the result (difference value) Dx of the calculation process (S113).

[0335] When the difference (elapsed time) Dx is a relatively large value, the larger difference Dx indicates that the time elapsed from the completion of MLC programming is relatively long. When the difference Dx is a relatively small value, the smaller difference Dx indicates that the time elapsed from the completion of MLC programming is relatively short.

[0336] It should be noted that, generally speaking, in NAND-type flash memories, the reliability of data stored in memory cells decreases over time.

[0337] The data loading selector 181 compares the elapsed time Dx with a threshold value Dth for selecting a data loading method. For example, the data loading selector 181 determines whether the elapsed time Dx is greater than the threshold value Dth (S114).

[0338] When the elapsed time Dx is greater than the threshold value Dth (Yes in S114 ), the data load selector 181 selects EDL as the data load method of the lower / middle page data for fine programming ( S115 ).

[0339] When the elapsed time Dx is equal to or less than the threshold value Dth (No in S114 ), the data load selector 181 selects IDL as the data load method of the lower / middle page data for fine programming ( S116 ).

[0340] In step S117, the processor 12 (or the write management circuit 18) notifies the NAND memory 30 of the selection result of the data loading selector 181 by sending a tag or prefix command such as the above-described signals 555 and 777. The processor 12 sends multiple command sets to the NAND memory 30 according to the selected data loading method.

[0341] Thus, the memory controller 10 instructs the NAND memory 30 to perform fine programming using the data loading method selected between IDL and EDL. The NAND memory 30 performs fine programming by using the lower / middle page data prepared using the selected data loading method.

[0342] As described above, the processing of each unit of the memory controller 10 at the fine programming time is completed.

[0343] As described above, the memory system 1 of this embodiment uses the time Dx elapsed from the completion of MLC programming as an indicator of data reliability to select either IDL or EDL. Thus, the memory system 1 of this embodiment can achieve high write performance of the memory system and high reliability of data stored in the memory system.

[0344] (c) Modification

[0345] Will refer to Figure 21 to Figure 23 A modification example of the memory system 1 of the present embodiment will be described.

[0346] (c-1) Modification 1

[0347] Fig.21 This is a block diagram showing a modification of the memory system 1 according to the present embodiment.

[0348] In the memory system 1 according to the first modified example of the present embodiment, the data loading method at the time of fine programming is selected in consideration of the temperature of the memory system 1 .

[0349] When the temperature of the memory system 1 is high, or when the temperature variation between the write operation and the read operation of the memory system 1 is large, data errors are likely to occur. That is, the reliability of data may vary depending on the temperature of the memory system 1.

[0350] like Fig.21 As shown in FIG. 4 , the NAND memory 30 includes a temperature sensor 43. The MLC program log table TBL1A also includes a table for recording the chip temperature T when performing MLC programming. MLCchip fields.

[0351] For example, the write management circuit 18 calculates the chip temperature T based on the acquired chip temperature T MLCchip , to adjust the size of the judgment reference value of the data reliability index (for example, the threshold Dth relative to the elapsed time Dx).

[0352] The data loading selector 181 obtains the MLC programming completion time t MLC At the same time, the chip temperature T of the NAND memory 30 when performing MLC programming is obtained from the temperature sensor 43. MLCchip .

[0353] The data loading selector 181 loads the acquired chip temperature T MLCchip The MLC programming is completed at t MLC Together, they are recorded in the corresponding entries of the MLC programming log table TBL1A.

[0354] The data loading selector 181 (or the processor 12) is based on the acquired chip temperature T MLCchip , to adjust the threshold Dth when selecting the data loading method.

[0355] For example, an example of adjusting the threshold value Dth is as follows.

[0356] The data loading selector 181 sets the chip temperature T MLCchip With two thresholds T H and T L For comparison. Threshold T His the threshold value related to the high temperature side. L is the threshold value related to the low temperature side. MLCchip Above the threshold T H or chip temperature T MLCchip Below the threshold T L When the data load selector 181 sets the threshold value Dth with respect to the elapsed time Dx to a value smaller than the initial setting value. By reducing the threshold value Dth in this way, EDL is selected even in a shorter elapsed time Dx.

[0357] Another example of adjusting the threshold value Dth is as follows.

[0358] When fine programming is performed, the data loading selector 181 acquires the chip temperature Tx immediately before fine programming is performed (hereinafter referred to as the current chip temperature). The data loading selector 181 obtains the chip temperature Tx when the MLC programming is completed. MLCchip The temperature difference (herein referred to as D1) is calculated by subtracting the temperature difference D1 from the current chip temperature Tx. The data loading selector 81 compares the temperature difference D1 with a certain reference value (herein referred to as the threshold value D2). When the temperature difference D1 is greater than the threshold value D2, the data loading selector 181 sets the threshold value Dth with respect to the elapsed time Dx to be smaller than the initial setting value. Therefore, even if the elapsed time Dx is short, EDL is selected.

[0359] It should be noted that according to the chip temperature T MLCchip The temperature difference D1 can have a positive or negative value. The change amount of the threshold Dth can be adjusted according to the positive or negative polarity of the temperature difference D1. MLCchip The absolute value of the difference between the current chip temperature Tx indicates the temperature difference D1.

[0360] In this modification, the following example is described, in which the data loading method of the lower page / middle page data in fine programming is selected in consideration of the time when the memory cell MC stores data and the temperature of the memory system 1 (more specifically, the temperature of the NAND memory 30). However, the memory system 1 of this embodiment can select the data loading method of the lower page / middle page data in fine programming based only on the temperature of the memory system 1. For example, when the temperature of the memory system 1 is higher than the threshold, the data loading selector 181 selects EDL without selecting the data loading method based on the MLC programming completion time t MLC The elapsed time Dx is compared with the threshold value Dth. For example, when the temperature of the memory system 1 is equal to or lower than the threshold value, the data load selector 181 selects IDL instead of setting the MLC program completion time t MLC The elapsed time Dx is compared with the threshold value Dth.

[0361] As described above, the memory system 1 of the present embodiment can select a more appropriate one of the IDL and the EDL in consideration of the influence of the temperature of the NAND memory 30 on the data reliability.

[0362] (c-2) Modification 2

[0363] FIG. 22A to FIG. 22C It is a diagram showing a second modification of the memory system 1 according to the present embodiment.

[0364] The plurality of chips provided in the NAND memory 30 may have characteristic deviations. The plurality of blocks provided in the memory cell array 31 may also have characteristic deviations. The memory cells MC connected to the plurality of word lines WL provided in each block may also have characteristic deviations. Therefore, the error rate of data may have deviations among the plurality of chips, the plurality of blocks, and the plurality of word lines.

[0365] The memory system 1 according to the second modification of the present embodiment sets a threshold value for selecting a data loading method in fine programming in units of chips, blocks, or word lines in consideration of variations in error rates among chips, blocks, and word lines.

[0366] For example, Fig.22A As shown in , a threshold Dth may be set for each block BLK. In this case, a threshold Dth_BLK0 is set for block BLK0, and a threshold Dth_BLKi is set for block BLKi. Here, i is an integer of 0 or greater. The value of the threshold Dth_BLK0 may be the same as or different from the value of the threshold Dth_BLKi.

[0367] like Fig. 22B As shown in , a threshold value Dth may be set for each word line WL. In this case, a threshold value Dth_WL0 is set for the word line WL0, and a threshold value Dth_WLi is set for the word line WLi.

[0368] like Fig. 22C As shown in , the threshold value Dth may be set for each chip provided in the NAND memory 30. In this case, the threshold value Dth_Chip0 is set for a certain chip, and the threshold value Dth_Chipi is set for another chip.

[0369] For example, the threshold value Dth of a certain cell is determined when designing the memory system 1 or when screening the NAND memory 30 during manufacturing.

[0370] When the threshold Dth for selecting the data loading method is set in units of blocks or word lines, the value of the threshold Dth may be set so that the IDL or EDL is always selected for a specific block and a specific word line. For example, when the EDL is always selected for a specific block or a specific word line, the value of the threshold Dth is set to zero. For example, when the IDL is always selected for a specific block or a specific word line, the value of the threshold Dth is set to the maximum value of the numerical range used by the threshold Dth.

[0371] As described above, in the memory system 1 of the present embodiment, an index for selecting either the IDL or the EDL can be set in units of chips, blocks, and word lines.

[0372] (c-3) Modification 3

[0373] Fig.23 It is a diagram showing a third modified example of the memory system 1 according to the present embodiment.

[0374] The blocks BLK (and the memory cells MC) of the NAND memory 30 may wear out according to the use of the memory system 1 .

[0375] The memory system 1 of the third modification example dynamically adjusts the threshold value Dth for selecting either the IDL or the EDL according to the wear degree (wear extent) of the block BLK.

[0376] like Fig.23 As shown in , in the present embodiment, the memory controller 10 includes a program / erase times counter (P / E times counter) 44 in the write management circuit 18. When the power of the memory system 1 is cut off, the memory controller 10 can make the program / erase times counter 44 in the NAND memory 30 non-volatile, and can load the program / erase times counter 44 into the write management circuit 18 in response to the start of power supply of the memory system 1. The loading destination of the program / erase times counter 44 can be the RAM 16. The program / erase times counter 44 measures the number of times the program and erase operations are performed in each block BLK. For example, a combination of one write operation and one erase operation is measured as one operation cycle.

[0377] The memory controller 10 includes a management table TBL2 related to the number of program / erase times in the RAM 16. The management table TBL2 records the number of program and erase operations in each block BLK.

[0378] The data error rate in the block BLK varies according to the number of program / erase operations. For example, the data error rate increases as the number of program / erase operations increases.

[0379] For example, in the memory system 1 of the present modification, the memory controller 10 (the processor 12 or the data load selector 181 ) acquires the program / erase number counter of each block BLK by referring to the program / erase number counter 44 .

[0380] The memory controller 10 records the acquired number of program / erase times in the management table TBL2.

[0381] The data load selector 181 (or the processor 12 ) adjusts the value of the threshold value Dth corresponding to each block BLK based on the number of program / erase times recorded in the management table TBL2 .

[0382] For example, when the number of programming / erasing times of the block BLK is relatively large (when the wear degree of the block BLK is high), the threshold Dth is adjusted to a value smaller than the initial setting value. Therefore, for the block BLK with a high wear degree, EDL is more likely to be selected.

[0383] As described above, the memory system 1 of the present embodiment can select a more appropriate data loading method between IDL and EDL according to the wear degree of the block BLK.

[0384] (d) Summary

[0385] In the memory system 1 of this embodiment, based on indicators related to the reliability of the lower page / middle page data written into the memory cell array 31 by MLC programming, the lower page / middle page data for fine programming is selected to be loaded into or outside the NAND memory 30.

[0386] For example, in a NAND flash memory, after data is programmed into a memory cell MC, the threshold voltage of the memory cell MC tends to change over time, so the reliability of the data written into the memory cell MC may decrease over time.

[0387] When the lower / middle page data in the memory cell array 31 includes an error, there is a possibility that the correct four-page data is not written into the unit cell CU designated by the selected address of the memory cell array 31 at the time of fine programming.

[0388] On the other hand, when the memory controller 10 provides the lower page / middle page data to the NAND memory 30 during fine programming, the time before the fine programming is completed may be longer due to the ECC processing of the lower page / middle page data and / or the transmission of the command set including the lower page / middle page data from the memory controller 10 to the NAND memory 30.

[0389] In the present embodiment, when fine programming is performed on a certain address, the memory controller 10 evaluates the reliability of the lower / middle page data based on a comparison between the elapsed time Dx and the threshold value Dth, wherein the elapsed time Dx is the time t from when the lower / middle page data is written to the memory cell array 31. MLC It's time to start doing some fine-grained programming.

[0390] Therefore, the memory system 1 of the present embodiment can select a more appropriate data loading method between IDL and EDL for data loading (data preparation) of lower page / middle page data to be performed for fine programming.

[0391] As a result, the present embodiment can provide a memory system with high performance and high reliability.

[0392] (2) Second Embodiment

[0393] Will refer to Figures 24 to 30 A memory system of the second embodiment is described.

[0394] (a) Structural example

[0395] Will refer to Fig.24 A configuration example of the memory system 1 according to the present embodiment will be described.

[0396] Fig.24 : is a block diagram showing a configuration example of the memory system 1 according to the present embodiment.

[0397] The memory system 1 of the present embodiment selects a data loading method at a fine programming time based on a workload applied to the memory system 1 .

[0398] like Fig.24 As shown in , in the memory controller 10 of the memory system 1 of the present embodiment, the write management circuit 18 further includes a throughput monitor 183 .

[0399] The throughput monitor 183 measures the amount of write data provided from the host 2 to the memory system 1 within a certain time window (unit time). Hereinafter, the amount of write data provided within a certain time window is referred to as the host write throughput or simply as write throughput. For example, the throughput monitor 183 obtains the average value of the write throughput in the time window based on the measurement result of the amount of write data provided from the host 2.

[0400] The data load selector 181 of the write management circuit 18 compares the measured write throughput with a preset threshold value (TPth). When fine programming is performed, the data load selector 181 selects either IDL or EDL based on the comparison result between the write throughput (TP) and the threshold value (TPth).

[0401] (b) Operation examples

[0402] Will refer to Fig.25 and Fig.26 An operation example of the memory system 1 of the present embodiment is described.

[0403] Fig.25 : is a flowchart describing an operation example of the memory system 1 of the present embodiment. Fig.26 An example of the relationship between write throughput and time in the memory system 1 of the present embodiment is shown. Fig.26 , the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to write throughput.

[0404] like Fig.25 As shown in FIG. 1 , in the memory controller 10 of the memory system 1 of the present embodiment, the throughput monitor 183 of the write management circuit 18 measures the write throughput TP within a certain time window (S200). For example, the throughput monitor 183 obtains the amount of write data provided from the host 2 within a certain time window. The throughput monitor 183 stores the obtained measurement result in the write management circuit 18.

[0405] The data loading selector 181 compares the write throughput TP with the threshold TPth ( S201 ). The data loading selector 181 selects a finely programmed data loading method that can be executed in the next time window of a certain time window based on the comparison result.

[0406] like Fig.26 As shown in FIG. 1 , in a certain time window TW0, when the write throughput TP is higher than the threshold TPth, it is assumed that the time for the memory cell MC to be in the MLC state is short. Therefore, when the write throughput TP is higher than the threshold TPth, as in the time window TW0, the data loading selector 181 selects IDL as the data loading method for fine programming that can be performed in the next time window TW1 ( Fig.25 S202 in ).

[0407] like Fig.26 As shown in FIG. 1 , in a certain time window TW2, when the write throughput TP is equal to or lower than the threshold TPth, it is assumed that the memory cell MC is in the MLC state for a long time. Therefore, when the write throughput TP is equal to or lower than the threshold TPth, as in the time window TW2, the data loading selector 181 selects EDL as the data loading method for fine programming that can be performed in the next time window TW3 ( Fig.25 (S203 in).

[0408] The data loading selector 181 notifies the processor 12 of the selection result of the data loading method (S204). Thus, when fine programming is performed, the processor 12 instructs the NAND memory 30 to perform fine programming by using the data loading method indicated in the selection result.

[0409] The NAND memory 30 performs fine programming using the selected data loading method, thereby writing four pages of data to the write target address of the memory cell array 31 .

[0410] As described above, the memory system 1 of the present embodiment ends the operation.

[0411] It should be noted that the range of the time window can be changed without being fixed. In addition, the amount of written data per a certain number of commands can be measured as the write throughput instead of measuring the amount of written data in the time window.

[0412] Furthermore, in the same time window as the time window in which the write throughput is measured, a fine-programmed data loading method to be executed in the time window may be selected based on the measurement result of the write throughput.

[0413] (c) Modification

[0414] Will refer to Figures 27 to 30 A modification example of the memory system 1 of the second embodiment will be described.

[0415] (c-1) Modification 1

[0416] Fig. 27 : is a block diagram showing a configuration example of a memory system 1 according to a first modification.

[0417] The memory system 1 of this embodiment can consider not only the write throughput from the host 2 to the memory system 1 but also the performance of background processing executed in the memory system 1 such as garbage collection (compaction), thereby selecting the IDL or EDL with higher accuracy.

[0418] like Fig. 27As shown in , in the memory system 1 of the first variant, the write management circuit 18 also includes a WAF monitor 184. The WAF monitor 184 calculates the write amplification factor (WAF: write amplification factor) of the memory system 1. WAF is a value representing the ratio of the amount of writes to the NAND memory 30 to the amount of writes (transfer data amount) from the host 2 to the memory system 1. For example, WAF is obtained based on "the amount of writes to the NAND memory 30 / the amount of writes from the host 2 to the memory system 1". The WAF monitor 184 multiplies the write throughput obtained by the throughput monitor 183 by WAF. The result of the multiplication (product) represents the amount of data written to the NAND memory 30 within a certain time window (hereinafter referred to as NAND throughput).

[0419] The data loading selector 181 selects a data loading method of fine programming that can be executed in the next time window based on a comparison result between the NAND throughput and the threshold TPthz.

[0420] Fig.28 The relationship between NAND throughput and time in the memory system 1 of this embodiment is shown. Fig.28 , the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to NAND throughput.

[0421] The memory system 1 of the first modification is based on the reference Fig.25 The process flow described is essentially the same process flow, performing a comparison between the NAND throughput and the threshold TPthz, and the selection of the data loading method for fine programming.

[0422] like Fig.28 As shown in , when the NAND throughput in a certain time window TW0 is higher than the threshold TPthz, the data loading selector 181 selects IDL as the data loading method for fine programming that can be executed in the next time window TW1.

[0423] When the NAND throughput in a certain time window TW2 is equal to or lower than the threshold TPthz, the data loading selector 181 selects EDL as a data loading method for fine programming that can be performed in the next time window TW3.

[0424] As described above, the memory system 1 of the first modification example can select a data loading method that is more suitable for fine programming by further considering the processing volume of the background processing of the memory system 1 .

[0425] (c-2) Modification 2

[0426] Fig.29: is a block diagram showing a configuration example of a memory system 1 according to a second modification.

[0427] The data loading method of fine programming can be selected according to the size of write data requested by a command (request) sent from the host 2 (hereinafter referred to as command size) and the continuity of addresses.

[0428] like Fig.29 As shown in , in the memory controller 10 of the memory system 1 of the second modification example, the write management circuit 18 further includes a command size monitor 185 and an access pattern analyzer 186 .

[0429] The command size monitor 185 measures the command size of each of the plurality of commands (requests) sent from the host 2. For example, the command size monitor 185 stores the command sizes of the plurality of commands sent most recently and obtains an average value of the plurality of command sizes. The command size monitor 185 notifies the data load selector 181 whether the average value of the obtained command sizes is greater than a set threshold value.

[0430] The access pattern analyzer 186 analyzes, for example, a pattern of logical addresses associated with write target data. The access pattern analyzer 186 detects the continuity of the logical addresses associated with write target data based on the analysis result of the pattern of logical addresses. For example, when the logical address range of write data requested to be written by the first command and the logical address range of write data requested to be written by the second command are continuous, the access pattern analyzer 186 determines that the logical addresses respectively associated with the write target data are continuous. The access pattern analyzer 186 notifies the data load selector 181 whether the logical addresses respectively associated with the write target data are continuous.

[0431] When access with a relatively large command size (eg, 128KB) and consecutive logical addresses occurs, the frequency of writing data to logical addresses within the range tends to be relatively high. Therefore, it is believed that the impact of reduced reliability of data corresponding to the logical addresses may be small.

[0432] In the memory system 1 of the second modification, when the command size is larger than the set threshold value and the logical addresses associated with the write target data are continuous, the data load selector 181 selects IDL as the data load method at the fine program time.

[0433] When the command size is equal to or less than a set threshold, or when logical addresses associated with write target data are discontinuous, the data load selector 181 selects any one of the IDL or EDL based on the above-mentioned elapsed time from the start of MLC programming, write throughput, etc.

[0434] Fig.30: is a flowchart showing an operation example of the second modification example of the memory system 1 of the present embodiment.

[0435] The memory controller 10 determines to perform fine programming ( S230 ).

[0436] The command size monitor 185 monitors the command size provided in the write request from the host 2. The access pattern analyzer 186 analyzes the pattern (continuity of addresses) of the logical addresses of the write targets (S231).

[0437] The data load selector 181 determines whether the command size is greater than a specific threshold based on the monitoring result of the command size ( S232 ).

[0438] When the command size is larger than the threshold value (Yes in S232 ), the data load selector 181 determines whether the write target addresses are continuous based on the analysis result of the access pattern ( S233 ).

[0439] When the command size is large and the write target addresses are continuous, the data load selector 181 selects IDL as the data load method for fine programming ( S234 ).

[0440] When the command size is equal to or less than the threshold value ("No" in S232), or when the write target address is discontinuous ("No" in S233), in step S235, the data loading selector 181 selects either IDL or EDL as the data loading method for fine programming based on the indicators described above (e.g., the time elapsed since the completion of MLC programming).

[0441] The data loading selector 181 notifies the processor 12 of the selection result of the data loading method (S236). Thus, when fine programming is performed, the processor 12 instructs the NAND memory 30 to perform fine programming by using the data loading method indicated in the selection result.

[0442] As described above, the memory system 1 of the present modification example ends the operation.

[0443] (d) Summary

[0444] As described above, the memory system 1 of the present embodiment can select a data loading method for fine programming based on the write throughput in a time window.

[0445] Therefore, this embodiment can provide a memory system with high performance and high reliability.

[0446] (3) Third Embodiment

[0447] Will refer to Figure 31 to Figure 33 A memory system of a third embodiment is described.

[0448] (a) Structural example

[0449] Fig.31 : is a block diagram showing a configuration example of the memory system 1 according to the present embodiment.

[0450] The memory system 1 of the present embodiment controls the selection of the IDL or EDL according to whether the write operation is a write operation using write data from the host 2 or a write operation according to background processing. Hereinafter, the write operation requested by the host 2 is referred to as a host write. In addition, the write operation according to background processing is referred to as a background write.

[0451] Host write is an operation mode for writing write data transferred from host 2 to NAND memory 30. Background write is an operation mode for writing data prepared inside memory system 1 such as garbage collection (compaction), wear leveling or data refresh to NAND memory 30.

[0452] like Fig.31 As shown in , in the memory controller 10 of the memory system 1 of the present embodiment, the write management circuit 18 further includes a command analyzer 187 .

[0453] The command analyzer 187 analyzes whether the command generated by the NAND interface circuit 17 is a command for host writing or a command for background writing based on various information (e.g., attribute information) contained in the command generated by the NAND interface circuit 17. The command analyzer 187 sends the analysis result of the command to the data load selector 181.

[0454] The data loading selector 181 selects a data loading method for fine programming based on the analysis result of the command by the command analyzer 187 .

[0455] When the write operation to be performed is a background write, IDL is selected as a fine-grained programming data loading method for the write operation.

[0456] For example, the memory system 1 can adjust the progress of the background write. Therefore, for the memory cell MC that is the target of the background write, the memory controller 10 can control the elapsed time Dx from the completion of the MLC programming to the present to be relatively short.

[0457] Furthermore, in the IDL, loading of the next page / middle page data is performed within the NAND memory 30, so the NAND bus NBS occupied by the IDL is smaller than that occupied by the EDL. Therefore, especially in the case of a workload with a relatively short idle time (a workload in which the interval between host write requests is equal to or less than a certain threshold), the impact on the host write performance can be reduced by using the IDL for background writing.

[0458] It should be noted that when background writing is performed using fine programming of IDL, it is desirable to perform ECC processing on the data of the background writing. When error correction in the ECC processing fails, the memory controller 10 can perform background writing again by using the next page / middle page data stored in the source block, where the source block is the target of the background processing.

[0459] When the write operation to be performed is a host write, either IDL or EDL is selected as the data loading method for fine programming based on other above-described indicators such as the time elapsed since the completion of MLC programming or the write throughput.

[0460] (b) Operation examples

[0461] Fig.32 : is a flowchart showing an operation example of the memory system 1 according to the present embodiment.

[0462] like Fig.32 As shown in FIG. 1 , in the memory system 1 of the present embodiment, when the NAND interface circuit 17 generates a command, the command analyzer 187 analyzes the command ( S300 ). The command analyzer 187 sends the analysis result of the command to the data load selector 181 .

[0463] The data load selector 181 determines whether the write operation to be performed is background write based on the analysis result of the command ( S301 ).

[0464] When the write operation to be performed is background write (“Yes” in S301 ), the data load selector 181 selects IDL as the data load method for fine programming ( S302 ).

[0465] When the write operation to be performed is a host write (“No” in S301 ), in step S303 , the data load selector 181 selects either the IDL or the EDL based on one or more indicators described above (eg, the time elapsed since the completion of MLC programming).

[0466] The data loading selector 181 notifies the processor 12 of the selection result of the data loading method (S304). When fine programming is performed, the processor 12 instructs the NAND memory 30 to perform fine programming using the data loading method indicated in the selection result.

[0467] As described above, the memory system 1 of the present embodiment ends the operation.

[0468] (c) Modification

[0469] Fig.33 : is a flowchart showing an operation example in a modification of the memory system 1 of the present embodiment.

[0470] In the case of workloads with relatively long idle times (workloads where the interval between host write requests is greater than a certain threshold), the time to load data during fine programming is likely to affect the performance of the memory system from the host's perspective. Therefore, in workloads with relatively long idle times, it is desirable to use IDL for fine programming of host writes.

[0471] Furthermore, in the case of workloads with relatively long idle times, background processing is less likely to affect the performance of the memory system from the host's perspective. Therefore, in workloads with relatively long idle times, fine-grained programming of background writes using EDL is desirable.

[0472] The configuration of the memory system 1 of this modification example is similar to the reference Fig.31 The third embodiment described is the same.

[0473] like Fig.33 As shown in , in this variation, the data load selector 181 determines whether the write operation to be performed is background write ( S300 , S301 ).

[0474] When the write operation to be performed is background write (“Yes” in S301 ), the data load selector 181 selects EDL ( S302A).

[0475] When the write operation to be performed is not background write (No in S301 ), the data load selector 181 selects, for example, IDL ( S303A).

[0476] The data loading selector 181 notifies the processor 12 of the selection result of the data loading method (S304). When fine programming is performed, the processor 12 instructs the NAND memory 30 to perform fine programming using the data loading method indicated in the selection result.

[0477] As described above, the memory system 1 of the modified example ends the operation.

[0478] (d) Summary

[0479] The memory system 1 of the present embodiment selects IDL or EDL as the data loading method during fine programming based on whether the write operation to be performed is host write or background write.

[0480] Thus, the memory system 1 of the present embodiment can perform a requested write operation by a data loading method suitable for fine programming based on the type of write operation to be performed.

[0481] Therefore, the memory system 1 of the present embodiment can provide a memory system having high performance and high reliability.

[0482] (4) Fourth Embodiment

[0483] Will refer to Fig.34 and Fig.35 A memory system of a fourth embodiment is described.

[0484] (a) Structural example

[0485] Fig.34 : is a block diagram showing a configuration example of the memory system 1 according to the present embodiment.

[0486] The memory system 1 of the present embodiment selects either IDL or EDL as the data loading method for fine programming based on hint information from the host 2 .

[0487] The host 2 sends a pair of start flag SF and end flag EF as prompt information to the memory controller 10. The start flag SF is a signal for notifying the host 2 that it will start transmitting a large number of write commands to the memory system 1. The end flag EF is a signal for notifying the end of the transmission of the large number of write commands.

[0488] like Fig.34 As shown in , in the memory controller 10 of the memory system 1 of the present embodiment, the write management circuit 18 further includes a flag post 188 .

[0489] The flag bar 188 receives the start flag SF and the end flag EF as prompt information and sends a notification signal ACK3 to the data loading selector 181 so that the IDL is selected based on the received start flag SF during the period from receiving the start flag SF to receiving the end flag EF.

[0490] The data loading selector 181 selects IDL in the period from when the start flag SF is received to when the end flag EF is received, based on the notification signal ACK3 from the flag post 188 .

[0491] (b) Operation examples

[0492] Fig.35 : is a schematic diagram showing an operation example of the memory system 1 of the present embodiment.

[0493] like Fig.35 As shown in FIG. 1 , the host 2 sends a start flag SF as prompt information to the memory system 1 at a certain time t10a. The start flag SF notifies the memory system 1 that a large number of write commands will be issued from this time.

[0494] At a certain time t10b, the memory controller 10 receives the start flag SF.

[0495] The flag bar 188 analyzes the start flag SF. The flag bar 188 transmits a notification signal ACK3 to the data loading selector 181 based on the analysis result of the start flag SF.

[0496] The data load selector 181 recognizes, based on the notification signal ACK3 , that the IDL is selected when fine programming is performed.

[0497] During the period from time t11 a to time t12 a , the host 2 sends a large number of write commands WC to the memory system 1 .

[0498] During the period from time t11b to time t12b, the memory system 1 receives a large number of write commands WC.

[0499] During the period from time t11 b to time t12 b , the data load selector 181 continues to select IDL as the data load method of fine programming to be performed.

[0500] At time t13a after all write commands WC are sent, the host 2 sends an end flag EF as prompt information to the memory system 1.

[0501] At a certain time t13b, the memory controller 10 receives the end flag EF. In the memory controller 10, the flag column 188 receives the end flag EF.

[0502] The flag bar 188 analyzes the end flag EF. Based on the analysis result of the end flag, the flag bar 188 stops providing the notification signal ACK3.

[0503] The data load selector 181 recognizes that the write operation according to the mass write command WC has ended based on the stop of the supply of the notification signal ACK3 , and thus stops the continuous selection of the IDL.

[0504] Thereafter, before receiving a new notification signal ACK3 from the flag post 188 , the data loading selector 181 selects either IDL or EDL based on the index for selecting the data loading method described above (eg, the time elapsed since the MLC programming is completed).

[0505] It should be noted that the memory system 1 of the present embodiment can select EDL as the data loading method during fine programming based on the prompt information from the host 2 .

[0506] (c) Summary

[0507] As described above, the memory system 1 of the present embodiment can select a data loading method suitable for a write operation to be performed in the IDL or EDL based on the hint information from the host 2 .

[0508] Therefore, the memory system 1 of the present embodiment can provide a memory system having high performance and high reliability.

[0509] (5) Fifth Embodiment

[0510] Will refer to Fig.36 and Fig.37 A memory system of a fifth embodiment is described.

[0511] (a) Structural example

[0512] Fig.36 : is a block diagram showing a configuration example of the memory system 1 according to the present embodiment.

[0513] The memory system 1 of the present embodiment controls the selection of the IDL and the EDL at the time of executing the fine programming according to the states of the power supply cutoff and the power supply recovery.

[0514] like Fig.36 As shown in , in the memory controller 10 of the memory system 1 of the present embodiment, the write management circuit 18 further includes a power supply monitor 189 .

[0515] When detecting that the power supply to the memory system 1 is shut off, the power supply monitor 189 sends a power supply shutoff signal PS to the processor 12 .

[0516] The processor 12 generates a management table TBL3 according to the power supply cutoff signal PS, wherein the management table TBL3 indicates the word lines WL and string units SU connected to the memory cells MC in the MLC state. Hereinafter, the management table TBL3 indicating the word lines WL and string units SU connected to the memory cells MC in the MLC state is referred to as the MLC state list TBL3.

[0517] For example, the MLC status list TBL3 is temporarily stored in the RAM 16. For example, when the power supply of the memory system 1 is cut off, the memory controller 10 writes the generated MLC status list TBL3 to the NAND memory 30, or sends the MLC status list TBL3 to the host 2. When the memory system 2 is started by power supply recovery, the memory controller 10 reads the MLC status list TBL3 from the NAND memory 30, or receives the MLC status list TBL3 from the host 2.

[0518] When the memory controller 10 receives a write command from the host 2 after the power supply is restored, the data load selector 181 refers to the MLC state list TBL3 .

[0519] For the memory cells MC managed in the MLC status list TBL3, the elapsed time Dx from the completion of the MLC programming to the present is unknown. Therefore, when the write target address corresponding to the write command from the host 2 corresponds to the word line number and the string cell number managed in the MLC status list TBL3, the data loading selector 181 selects EDL, which has higher data reliability than IDL, as the data loading method for fine programming.

[0520] After power supply is restored, after fine programming using EDL is performed on all unit cells CU specified by the addresses corresponding to the word lines WL and string units SU recorded in the MLC status list TBL3, the data loading selector 181 selects either IDL or EDL as the data loading method for fine programming based on the indicators described above (e.g., the time elapsed from the completion of MLC programming).

[0521] It should be noted that there is a case where the processor 12 cannot generate the MLC state list TBL3 due to an unexpected power outage (for example, a power supply failure). In this case, first, the processor 12 determines the block BLK (hereinafter referred to as the last write block) on which a write operation was last performed before power failure, for example based on some log information. Next, the processor 12 calculates the number of memory cells MC that are turned on by applying one or more read voltages to each word line WL included in the last write block for each unit cell CU. Then, based on the calculation result, the processor 12 determines the unit cell CU (hereinafter referred to as the last MLC cell) that last became the MLC state before power failure. The processor 12 performs fine programming of the last MLC cell according to the reference Fig. 9 The described write sequence is used to perform all fine programming on the unit cell CU using EDL. For example, the unit cell CU corresponding to the word line WL1 and the string unit SU0 is referenced Fig. 9 In the case of the last MLC cell of the 6th write operation described above, the processor 12 performs all fine programming (i.e., the 7th, 9th, 11th, 13th, 15th, and 17th write operations) on the unit cell CU using the EDL before the last MLC cell (the 17th write operation). For the unit cell CU after the last MLC unit cell (e.g., the 19th or subsequent write operation), the processor 12 selects either the IDL or the EDL based on the indicator described above (e.g., the time elapsed since the MLC programming was completed (e.g., the 8th or subsequent write operation)).

[0522] It should be noted that when the number of string units SU included in one block BLK is N (N is an integer of 1 or greater, Fig. 95), the number of word lines WL of the unit cell CU on which a write operation is performed after performing MLC programming on a unit cell CU and before performing fine programming on the unit cell CU is M (M is an integer of 1 or greater than 1, and Fig. 9 2) in the example shown, the processor 12 uses EDL for all fine programming performed on L unit cell CUs calculated by L=(M-1)xN+1 before the last MLC unit cell. In the case where the last MLC unit cell is located at either end of the word line WL, the number of unit cell CUs to which the EDL is applied may be less than L. However, to simplify processing, the processor 12 may apply the EDL to the L unit cell CUs regardless of the position of the last MLC unit cell within the word line WL. Alternatively, the processor 12 may use EDL for all fine programming performed on L' unit cell CUs calculated by L'=(M'-1)xN+1 before the last MLC unit cell. Here, M' is an integer greater than M. Alternatively, the processor 12 may use EDL for all fine programming performed on L" unit cell CUs before the last MLC unit cell. Here, L" is an integer greater than L. To further simplify processing, the processor 12 may use EDL for all fine programming performed on all unit cells to be included in the last write block.

[0523] In addition, even if the management table related to the write target address (e.g., the MLC status list) is not updated each time a power supply cut-off is detected, a data loading method for fine programming after power supply restoration can be selected based on the write operation history before the power supply cut-off, similar to the case of an unexpected power outage.

[0524] (b) Operation examples

[0525] Fig.37 : is a flowchart showing an operation example of the memory system 1 of the present embodiment.

[0526] like Fig.37 As shown in FIG. 5 , when the power supply monitor 189 detects power supply cutoff, the processor 12 generates a management table TBL3 (MLC state list TBL3) in response to a power supply cutoff signal PS from the power supply monitor 189. The generated MLC state list TBL3 is transmitted to the NAND memory 30 or the host 2 (S500).

[0527] When the memory system 1 is started up by power supply recovery, the MLC state list TBL3 is stored in the RAM 16 of the memory system 1 .

[0528] After the power supply is restored, when the memory controller 10 receives a write request from the host 2 , the data load selector 181 refers to the MLC state list TBL3 ( S501 ).

[0529] The data load selector 181 determines whether a write target address (word line number and string cell number) exists in the MLC state list TBL3 ( S502 ).

[0530] When the word line number and the string cell number as the write target exist in the MLC state list TBL3 (“Yes” in S502 ), the data load selector 181 selects EDL as the data load method of fine programming to be performed ( S503 ).

[0531] The data load selector 181 updates the MLC state list TBL3 (S504). For example, the data load selector 181 deletes the word line number and the string cell number which are the write targets for the fine programming performed by the selected EDL from the MLC state list TBL3.

[0532] When the word line number and string cell number as the write target do not exist in the MLC state list TBL3 (No in S502), the data load selector 181 selects either the IDL or the EDL based on indicators such as the time elapsed from the completion of MLC programming or the write throughput (S505).

[0533] The data loading selector 181 notifies the processor 12 of the selection result of the data loading method (S506). Thus, when fine programming is performed, the processor 12 instructs the NAND memory 30 to perform fine programming by using the data loading method indicated in the selection result.

[0534] As described above, the memory system 1 of the present embodiment ends the operation.

[0535] (c) Summary

[0536] As described above, the memory system 1 of the present embodiment can provide a memory system having high performance and high reliability even when the power supply to the memory system 1 is cut off.

[0537] (6) Others

[0538] In the memory system of the embodiment, the nonvolatile memory is not limited to a NAND flash memory, and may be other memory devices.

[0539] In the memory system of the embodiment, when data is written to the memory cell through a plurality of write phases (write operations), the data written to the memory cell may be 2-bit data, 3-bit data, 5-bit data, or 6-bit data.

[0540] Although certain embodiments have been described, these embodiments are presented only by way of example, and they are not intended to limit the scope of protection of the present disclosure. In fact, the novel embodiments described herein may be embodied in a variety of other forms; moreover, various omissions, substitutions, and changes in the form of the embodiments described herein may be made without departing from the spirit of the present disclosure. The attached claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present disclosure.

[0541] Description of symbols

[0542] 1: memory system, 2: host, 10: memory controller, 30: NAND memory, 11: host interface (I / F) circuit, 12: processor, 13: buffer memory, 14: ECC circuit, 15: read-only memory (ROM), 16: random access memory (RAM), 17: NAND interface (I / F) circuit, 18: write management circuit, 181: data load selector, 182: global clock, 183: throughput monitor, 184: WAF monitor, 185: command size monitor, 186: access pattern analyzer, 187: command analyzer, 188: flag column, 189: power supply monitor, 31: storage cell array, 33: logic control circuit, 36: sequencer, 43: temperature sensor, 44: program / erase count counter (P / E count counter).

Claims

1. A memory system, comprising: a nonvolatile memory and a memory controller electrically connected to the nonvolatile memory, The non-volatile memory comprises: a memory cell to store data in a non-volatile manner, and a control circuit that writes n-bit first data into the storage unit through a first write operation, and writes m-bit second data including the n bits of the first data into the storage unit through a second write operation, wherein n is a real number of 1 or greater, and m is a real number greater than n; The memory controller is composed of: issuing a first command sequence to the non-volatile memory to perform the first write operation; selecting one of a first method and a second method for preparing the second data for the second write operation based on an indicator related to reliability of the first data stored in the storage unit; and A second command sequence is issued to the nonvolatile memory to perform the second write operation, wherein the second command sequence indicates the selected method for preparing the second data.

2. The memory system according to claim 1, wherein: The indicator is the time elapsed since the first write operation on the storage unit was completed, When the elapsed time is equal to or less than a first threshold, the memory controller selects the first method; When the elapsed time is greater than the first threshold, the memory controller selects the second method.

3. The memory system according to claim 1, further comprising: a first memory; as well as A clock that measures time. The storage unit is one of a plurality of storage units, the memory controller, storing a first management table in the first memory, the first management table having a plurality of entries respectively corresponding to the plurality of storage cells, each of the entries indicating an address of a storage cell and a first time associated with the first write operation performed on the storage cell specified by the address of the storage cell; When a difference between a second time associated with the second write operation to be performed on a target storage unit among the plurality of storage units and the first time stored in an entry corresponding to the target storage unit is equal to or less than a second threshold, selecting the first method to perform the second write operation on the target storage unit; as well as When the difference is greater than the second threshold, the second method is selected to perform the second write operation on the target storage unit.

4. The memory system according to claim 3, further comprising: a temperature sensor, measuring a temperature of the nonvolatile memory, The memory controller adjusts the second threshold based on a measurement result of the temperature sensor.

5. The memory system according to claim 4, wherein: When a first temperature measured by the temperature sensor when performing the first write operation is higher than a third threshold, the memory controller decreases the second threshold; The memory controller decreases the second threshold when the first temperature is lower than a fourth threshold, wherein the fourth threshold is lower than the third threshold.

6. The memory system according to claim 4, wherein: the memory controller obtaining a temperature difference between a first temperature measured by the temperature sensor when performing the first write operation and a second temperature measured by the temperature sensor in preparation for issuing the second command sequence for the second write operation; When the temperature difference is greater than a fifth threshold, the memory controller decreases the second threshold.

7. The memory system according to claim 3, wherein: The memory controller tracks the number of times an erase operation is performed on the memory cell; When the number of times the erase operation is performed on the memory cell is greater than a sixth threshold, the memory controller decreases the second threshold.

8. The memory system according to claim 1, wherein: The indicator is the throughput of data from the host in the first period, When the throughput is higher than a seventh threshold, the memory controller selects the first method in a second period after the first period; When the throughput is equal to or lower than the seventh threshold, the memory controller selects the second method in the second period.

9. The memory system according to claim 1, wherein: The indicator is a throughput of writing data to the non-volatile memory during a first period, When the throughput is higher than an eighth threshold, the memory controller selects the first method in a second period after the first period; When the throughput is equal to or lower than the eighth threshold, the memory controller selects the second method in the second period.

10. The memory system according to claim 1, wherein: The memory controller selects the first method when a size of first write data specified by a first command from the host is greater than a ninth threshold value, and a logical address associated with second write data specified by a second command from the host and a logical address associated with the first write data are consecutive; When the size of the first write data is equal to or less than the ninth threshold, or when the logical address associated with the second write data and the logical address associated with the first write data are not continuous, the memory controller selects one of the first method and the second method based on the indicator.

11. The memory system according to claim 1, wherein: When the second write operation is initiated by background processing, the memory controller selects the first method; When the second write operation is initiated in response to a command from a host, the memory controller selects one of the first method and the second method based on the indicator.

12. The memory system according to claim 11, wherein: The memory controller determines whether an interval of write requests from the host is equal to or less than a tenth threshold; When the interval is equal to or smaller than the tenth threshold, The memory controller selects the first method for the second write operation initiated by the background process; as well as The memory controller selects one of the first method and the second method based on the indicator for the second write operation initiated in response to the command from the host.

13. The memory system according to claim 1, wherein: When the second write operation is initiated in response to a command from a host, the memory controller selects the first method; The memory controller selects the second method when the second write operation is initiated by a background process.

14. The memory system according to claim 13, wherein: The memory controller determines whether an interval of write requests from the host is greater than an eleventh threshold; When the interval is greater than the eleventh threshold, The memory controller selects the first method for the second write operation initiated in response to the command from the host; and The memory controller selects the second method for the second write operation initiated by the background process.

15. The memory system according to claim 1, wherein: Upon receiving a first flag indicating transmission of a plurality of commands from a host, the memory controller continuously selects the first method; Upon receiving a second marker indicating completion of sending the plurality of commands from the host, the memory controller releases the continuous selection of the first method.

16. The memory system of claim 1, wherein The storage unit is one of a plurality of storage units, When the power supply to the memory system is stopped, the memory controller records in a third management table the addresses of the storage units that have performed the first write operation and have not yet performed the second write operation; After the power supply to the memory system is restored, the memory controller selects the second method when an address of a target memory cell among the plurality of memory cells that is a target of the second write operation is recorded in the third management table; When the address of the target storage unit is not recorded in the third management table, the memory controller selects one of the first method and the second method based on the indicator.

17. The memory system according to claim 1, wherein: The nonvolatile memory does not perform an erase operation on the storage unit between the first write operation and the second write operation.

18. The memory system of claim 1, wherein In the first method, preparing the second data for the second write operation in the nonvolatile memory, In the second method, the second data for the second write operation is prepared outside the nonvolatile memory.

19. The memory system of claim 18, wherein: The nonvolatile memory further includes a data latch, In the first method, The control circuit is composed of: Read the first data from the storage unit; storing the read first data in the data latch; receiving third data from the memory controller; preparing in the data latch the second data including the read first data and the received third data; as well as writing the second data prepared by the control circuit in the data latch into the memory cell in response to receiving the second command sequence from the memory controller, In the second method, The memory controller is composed of: After performing the first write operation of the first data on the storage unit, preparing the second data; and transferring the second data to the non-volatile memory, The control circuit is composed of: In response to receiving the second command sequence from the memory controller, the second data prepared by the memory controller is written to the storage unit.

20. A storage device, connectable to a controller, the storage device comprising: a storage unit for storing data in a non-volatile manner; as well as The control circuit is composed of: The n-bit first data is written into the storage unit through a first write operation, wherein n is a real number of 1 or greater; and Writing m-bit second data including the n-bits of the first data into the storage unit through a second writing operation, wherein m is a real number greater than n; The control circuit is further configured to select one of a first method and a second method for preparing the second data for the second write operation based on a command from the controller.

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