Operation method of memory device, memory device and memory system

Abstract

The embodiment of the invention provides an operation method of a memory device, the memory device and a memory system. The memory device comprises a first memory unit and a second memory unit which belong to the same memory string and are adjacent to each other, the method comprises the following steps: executing a first programming operation, so that the first storage unit is programmed to a first data state; executing a second programming operation; the second programming operation comprises the step of programming the second storage unit; and verifying the second storage unit according to first reference verification information determined by the first data state.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to an operating method of a memory device, a memory device and a memory system. Background Art

[0002] As the storage density of memory devices increases, the number of storage bits of each memory cell gradually increases. In order to achieve multi-bit storage in each memory cell, a page is divided into multiple data states. In order to correctly read the data stored in the memory cell, the distribution width of the threshold voltage of each data state needs to be compressed to improve the read window margin (RWM). However, the threshold voltage Vt corresponding to the highest data state is usually relatively high, which leads to rapid charge loss, making the retention of the memory device relatively poor. Summary of the invention

[0003] Embodiments of the present application provide a method for operating a memory device, a memory device, and a memory system.

[0004] In one aspect, an embodiment of the present application provides an operating method of a memory device, wherein the memory device includes a first memory unit and a second memory unit that belong to the same memory string and are adjacent to each other; the method includes:

[0005] Performing a first programming operation so that the first memory cell is programmed to a first data state;

[0006] A second programming operation is performed; the second programming operation includes: programming the second storage cell; and verifying the second storage cell according to first reference verification information determined by the first data state.

[0007] In the above scheme, the memory cell of the memory device can be programmed to any one of a plurality of data states including the first data state; the method further comprises:

[0008] Obtaining a first mapping relationship between the plurality of data states and reference verification information for verifying a programming result of a memory cell;

[0009] The first reference verification information is determined according to the first data state and the first mapping relationship.

[0010] In the above solution, the reference verification information includes a reference verification voltage or a reference sensing time; and obtaining a first mapping relationship between the plurality of data states and the reference verification information for verifying a programming result of a memory cell includes:

[0011] Dividing the multiple data states to form multiple data groups;

[0012] Obtaining a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; or obtaining a second sub-mapping relationship between the plurality of data groups and the reference sensing time;

[0013] The first mapping relationship includes: a first sub-mapping relationship and / or the second sub-mapping relationship.

[0014] In the above solution, the multiple data states are divided to form multiple data groups, including:

[0015] The multiple data states are divided into a first data group and a second data group, wherein a threshold voltage corresponding to the data state in the first data group is smaller than a threshold voltage corresponding to the data state in the second data group.

[0016] In the above solution, the first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or a second sub-mapping relationship between the first data group, the second data group and the reference sensing time;

[0017] Among them, the first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

[0018] In the above solution, the memory string further includes a third memory cell adjacent to the second memory cell; and the method further includes:

[0019] performing a third programming operation so that the first memory cell is programmed to a first target programming state;

[0020] performing a fourth programming operation so that the third memory cell is programmed to a second data state;

[0021] Wherein, in the second programming operation, the second storage unit is not programmed to a second target data state; and the second data state is not a target data state.

[0022] In the above solution, the memory string further includes: a fourth memory cell adjacent to the first memory cell; before performing the first programming operation, the method further includes:

[0023] performing a fifth programming operation so that the fourth memory cell is programmed to a third data state;

[0024] performing a sixth programming operation so that the second memory cell is programmed to a fourth data state;

[0025] performing a seventh programming operation so that the fourth memory cell is programmed to a third target data state;

[0026] The first data state, the third data state, and the fourth data state are not target data states; in the second programming operation, the memory cell is programmed to a second target data state.

[0027] In the above solution, the first data group and the second data group in the plurality of data groups contain the same number of data states.

[0028] In the above solution, the multiple data states include 16 data states from L0 to L15; the first data group includes data states from L0 to L7; and the second data group includes data states from L8 to L15.

[0029] In the above solution, determining the first reference verification information according to the first data state and the first mapping relationship includes:

[0030] Determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes a correspondence relationship between the multiple data groups and the multiple data states;

[0031] Determine the first reference verification information according to the data group to which it belongs and the first sub-mapping relationship, or determine the first reference verification information according to the data group to which it belongs and the second sub-mapping relationship;

[0032] Among them, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

[0033] On the other hand, an embodiment of the present application further provides a memory device, including:

[0034] A memory array, comprising: a first memory cell and a second memory cell belonging to the same memory string and adjacent to each other;

[0035] The peripheral circuit, coupled to the memory array, is configured to:

[0036] Performing a first programming operation so that the first memory cell is programmed to a first data state;

[0037] A second programming operation is performed; the second programming operation includes: programming the second storage cell; and verifying the second storage cell according to first reference verification information determined by the first data state.

[0038] In the above scheme, the storage cell of the memory device can be programmed to any one of a plurality of data states including the first data state; the peripheral circuit is further configured to: obtain a first mapping relationship between the plurality of data states and reference verification information for verifying the programming result of the storage cell; and determine the first reference verification information based on the first data state and the first mapping relationship.

[0039] In the above scheme, the reference verification information includes a reference verification voltage or a reference sensing time; the peripheral circuit is also configured to: divide the multiple data states to form multiple data groups; obtain a first sub-mapping relationship between the multiple data groups and the reference verification voltage; or, obtain a second sub-mapping relationship between the multiple data groups and the reference sensing time; wherein the first mapping relationship includes: a first sub-mapping relationship and / or the second sub-mapping relationship.

[0040] In the above scheme, the peripheral circuit is also configured to: divide the multiple data states to form a first data group and a second data group, wherein the threshold voltage corresponding to the data state in the first data group is smaller than the threshold voltage corresponding to the data state in the second data group.

[0041] In the above solution, the first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or a second sub-mapping relationship between the first data group, the second data group and the reference sensing time;

[0042] Among them, the first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

[0043] In the above scheme, the memory string also includes a third storage cell adjacent to the second storage cell; the peripheral circuit is further configured to: perform a third programming operation so that the first storage cell is programmed to a first target programming state; perform a fourth programming operation so that the third storage cell is programmed to a second data state; wherein, under the second programming operation, the second storage cell is not programmed to the second target data state; and the second data state is not a target data state.

[0044] In the above solution, the memory string further includes: a fourth memory cell adjacent to the first memory cell; the peripheral circuit is further configured to: before executing the first programming operation,

[0045] performing a fifth programming operation so that the fourth memory cell is programmed to a third data state;

[0046] performing a sixth programming operation so that the second memory cell is programmed to a fourth data state;

[0047] performing a seventh programming operation so that the fourth memory cell is programmed to a third target data state;

[0048] The first data state, the third data state, and the fourth data state are not target data states; in the second programming operation, the memory cell is programmed to a second target data state.

[0049] In the above solution, the peripheral circuit is further configured to: determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes a correspondence relationship between the multiple data groups and the multiple data states;

[0050] Determine the first reference verification information according to the data group to which it belongs and the first sub-mapping relationship, or determine the first reference verification information according to the data group to which it belongs and the second sub-mapping relationship;

[0051] Among them, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

[0052] On the other hand, an embodiment of the present application further provides a memory system, comprising one or more memory devices of any of the foregoing items.

[0053] In the above solution, the memory system is included in a solid state drive SSD or a memory card.

[0054] The embodiments of the present application provide an operation method of a memory device, a memory device and a memory system. The memory device includes a first memory cell and a second memory cell that belong to the same memory string and are adjacent to each other; the method includes: performing a first programming operation so that the first memory cell is programmed to a first data state; performing a second programming operation; the second programming operation includes: programming the second memory cell; and verifying the second memory cell according to the first reference verification information determined by the first data state. In the operation method provided by the embodiments of the present application, for two adjacent memory cells in the same memory string, the reference verification information used in the verification operation of the latter programmed memory cell is obtained according to the data state to which the former programmed memory cell is programmed, thereby guiding the latter programmed memory cell to obtain appropriate reference verification information according to the programming status of the former memory cell to improve the retention characteristics of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0056] Figure 1 A schematic diagram of an exemplary system having a memory system according to some aspects of the embodiments of the present application;

[0057] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to some aspects of the embodiments of the present application;

[0058] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to some aspects of the embodiments of the present application;

[0059] Figure 3 A schematic diagram of an exemplary memory device including a peripheral circuit according to some aspects of the embodiments of the present application;

[0060] Figure 4 A schematic diagram of the structure of a memory string, a word line, and a bit line in a memory device according to some aspects of the embodiments of the present application;

[0061] Figure 5A cross-sectional schematic diagram of a memory array provided according to some aspects of the embodiments of the present application;

[0062] Figure 6 A schematic diagram of an exemplary memory device including a memory array and a peripheral circuit according to some aspects of the embodiments of the present application;

[0063] Figure 7 A voltage threshold distribution diagram of a storage cell of TCL type;

[0064] Figure 8 A voltage threshold distribution diagram of a QLC type storage unit;

[0065] Fig. 9 Schematic diagram of the definition of RWM provided for some aspects of the embodiments of the present application

[0066] Fig.10 A schematic flow chart of an operating method of a memory device according to some aspects of the embodiments of the present application;

[0067] Fig.11 A schematic diagram of a 4BL BIAS programming method provided for some aspects of the embodiments of the present application;

[0068] Fig.12 A schematic diagram of the relationship between the potential of a sensing node and the discharge duration provided for some aspects of the embodiments of the present application;

[0069] Fig.13 and Fig.14 A schematic diagram of some causes of charge loss of a memory cell provided for some aspects of the embodiments of the present application;

[0070] Fig.15 A schematic diagram of a two-side programming algorithm provided for some aspects of the embodiments of the present application;

[0071] Figures 16 to 19 An exemplary flowchart of the operation method of the embodiments of the present application is provided for some aspects of the embodiments of the present application;

[0072] Fig. 20 and Fig.21 For some aspects of the embodiments of the present application, Figures 16 to 19 Schematic diagram of the effect of the process;

[0073] Fig. 22 A schematic diagram of the structure of a memory device provided for some aspects of the embodiments of the present application. DETAILED DESCRIPTION

[0074] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to more thoroughly understand the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0075] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described: that is, all features of the actual embodiments not described here, and known functions and structures are not described in detail.

[0076] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0077] It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to ", "coupled to " or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be intermediate elements or layers. On the contrary, when an element is "directly on ... ", "directly adjacent to ... ", "directly connected to " or "directly coupled to" other elements or layers, there is no intermediate element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. When discussing a second element, component, region, layer or section, it does not necessarily mean that the first element, component, region, layer or section must be present.

[0078] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0079] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0080] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0081] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0082] Figure 1 A block diagram of an exemplary system having a memory system is shown. Figure 1 In the embodiment, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system therein. Figure 1As shown, the system 100 may include a host 108 and a memory system 102, wherein the host 108 may include a processor, such as a central processing unit (CPU) or a system on chip (SoC), wherein the system on chip may be, for example, an application processor (AP). The host 108 also includes at least one operating system (OS) that can generally manage and control functions and operations performed in the host 108. The OS can enable the host 108 coupled to the memory system 102 and the user who needs and uses the memory system 102 to interoperate. The OS can support functions and operations corresponding to the user's request, such as but not limited to, depending on whether the type of the host 102 is a removable host, the OS can be classified into a general operating system and a mobile operating system, wherein the general operating system may include a personal operating system and an enterprise operating system, wherein the personal operating system may be an operating system including Windows and Chrome for general purposes to support services; the enterprise operating system may be an operating system including Windows Server, Linux, Unix, etc., which is dedicated to ensuring and supporting higher performance. The mobile operating system may refer to an operating system for services or functions for mobility (e.g., power saving function). Generally speaking, the mobile operating system may be an operating system such as Android, iOS, Windows Mobile, etc. In some embodiments, the host 108 may include multiple OSs; correspondingly, the host 108 may run multiple operating systems related to the memory system 102. In other embodiments, the host 108 converts the user's request into one or more commands, and transmits the one or more commands to the memory system 102, so that the memory system 102 performs operations related to the one or more commands.

[0083] The memory system 102 can operate or perform specific functions or perform various internal operations in response to a request from the host 108. In some embodiments, the memory system 102 can store data accessed by the host 108. The memory system 102 can be used as a main memory system or an auxiliary memory system of the host 108. The memory system 102 can be electrically connected and communicated with the host 108 according to a corresponding protocol. The memory system 102 can be implemented and packaged into different types of terminal electronic products, such as but not limited to: solid state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced size MMC (RSMMC), micro MMC, secure digital (SD) card, mini SD, micro SD, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash (CF) card, smart media (SM) card and memory stick, etc.

[0084] In some embodiments, the memory system 102 may also be configured as part of, for example, a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured in a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured in a home network, one of various electronic devices configured in a computer network, one of various electronic devices configured in a telematics network, a radio frequency identification (RFID) device, or one of various components configured in a computing system.

[0085] Return as Figure 1 As shown, the memory system 102 may have one or more memory devices 104 and a memory controller 106. The memory controller 106 may respond to a request from a host 108, and thereby control the memory device 104. For example, the memory controller 106 may read data from the memory device 104 and transmit the read data to the host 108; it may also receive data to be stored from the host 108, and store the data to be stored in the memory device 104. In other words, the memory controller 106 is capable of controlling the write (or programming) operation, read operation, erase operation, background operation, and the like of the memory device 104. And the memory system 102 may be implemented and packaged into different types of terminal electronic products. In the example Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0086] Among them, Figure 3 As shown, the memory controller 106 may include a host I / F (or front-end interface) 301, a memory I / F (or back-end interface) 302, a processor 303, and a memory 304, wherein the above components 301, 302, 303, and 304 in the memory controller 106 may share transmission signals within the memory controller 106 through an internal bus. In some embodiments, the host I / F 301 may interface the host 108 with the memory system 102 in response to a protocol of the host 108, and the host I / F 301 exchanges transmission commands and data operations between the host 108 and the memory system 102. The host I / F 301 may process commands and data sent by the host 108, and may include at least one of the following: a universal serial bus (USB), a multimedia card (MMC), a high-speed peripheral component interconnect (PCI-e or PCIe), a small computer system interface (SCSI), a serial SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE). In some embodiments, the host I / F 301 is a component used by the memory system 102 to exchange data with the host 108 and may be implemented by firmware referred to as a host interface layer (HIL).

[0087] The memory I / F 302 may be an interface for commands and data transmitted between the memory controller 106 and the memory device 104, allowing the memory controller 106 to control the memory device 104 in response to a request passed from the host 108. The memory I / F 302 may generate a control signal for controlling the memory device 104. In some embodiments, if the memory device 104 is a NAND flash memory, the memory I / F 302 may write data to the memory device 104 or read data from the memory device 104 under the control of the processor 303. The memory I / F 302 may process commands and data between the memory controller 106 and the memory device 104, for example, operations of a NAND flash memory interface, especially operations between the memory controller 106 and the memory device 104. According to an embodiment, the memory I / F 302 may be implemented as a component for exchanging data with the memory device 104 by firmware referred to as a flash interface layer (FIL).

[0088] The processor 303 may be implemented as a microprocessor or a central processing unit (CPU). The memory system 102 may include one or more processors 303. The processor 303 may control the overall operation of the memory system 102. As an example and not limitation, the processor 303 may control the programming operation or the reading operation of the memory device 104 in response to a write request or a read request from the host 108. According to an embodiment, the processor 303 may use or run firmware to control the overall operation of the memory system 102. In this application, the firmware may be referred to as a flash translation layer (FTL). The FTL may perform operations as an interface between the host 108 and the memory device 104. The host 108 may transmit requests related to write operations and read operations to the memory device 104 through the FTL. For example, when performing an operation requested from the host 108 in the memory device 104, the memory controller 106 uses the processor 303. The processor 303 coupled to the memory device 104 may process instructions or commands related to commands from the host 108. The memory controller 106 may perform foreground operations such as command operations corresponding to commands input from the host 108, for example, a program operation corresponding to a write command, a read operation corresponding to a read command, an erase / discard operation corresponding to an erase / discard command, and a parameter setting operation corresponding to a set parameter command or a set feature command having a set command.

[0089] For another example, the memory controller 106 may perform background operations on the memory device 104 through the processor 303. As an example and not a limitation, these background operations may include garbage collection (GC) operations, wear leveling (WL) operations, map clearing operations, and bad block management operations for checking or searching for bad blocks. The garbage collection operation may include an operation of copying and processing data stored in a certain storage block in the memory device 104 to another storage block. The wear leveling operation may include an operation of exchanging and processing stored data between storage blocks of the memory device 104. The map clearing operation may include an operation of storing the mapping data stored in the memory controller 106 in the storage block of the memory device 104. The bad block management operation may include an operation of checking and processing bad blocks in the storage block of the memory device 104. The memory controller 106 may respond to an operation of accessing a storage block of the memory device 104, wherein the operation of accessing a storage block of the memory device 104 may include a foreground operation or a background operation performed on the storage block of the memory device 104.

[0090] The memory 304 may be a working memory of the memory controller 106, configured to store data for driving the memory controller 106. More specifically, when the memory controller 106 controls the memory device 104 in response to a request from the host 108, the memory 304 may store firmware driven by the processor 303 and data required to drive the firmware (e.g., metadata). The memory 304 may also be a buffer memory of the memory controller 106, configured to temporarily store write data transmitted from the host 108 to the memory device 104 and read data transmitted from the memory device 104 to the host 108. The memory 304 may include a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, and a mapping buffer / cache for storing write data and read data. The memory 304 may be implemented using a volatile memory. The memory 304 may be implemented using a static random access memory (SRAM), a dynamic random access memory (DRAM), or both.

[0091] Although Figure 3 The memory 304 is shown to be included in the memory controller 106, but the application is not limited thereto. In an embodiment, the memory 304 may be included outside the memory controller 106, and the memory controller 106 may input and output data to the memory 304 through a separate memory interface (not shown).

[0092] Return to see Figure 1 , the memory device 104 may include a non-volatile memory that can retain the data stored therein even if power is not supplied. The memory device 104 may also include a volatile memory. The memory device 104 may store data provided from the host 108 through a write operation; the memory device 104 may also provide the stored data to the host 108 through a read operation. In an embodiment of the present application, the memory device 104 may include any disclosed memory, such as a volatile memory device of a dynamic random access memory (DRAM) and a static RAM (SRAM), or a non-volatile memory device such as a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM or ReRAM), and a flash memory (e.g., a three-dimensional NAND flash memory).

[0093] A memory device is illustrated using three-dimensional NAND flash memory, see Figure 4, which shows a schematic circuit diagram of an exemplary memory device 400 including peripheral circuits according to some aspects of the present application. The memory device 400 may be Figure 1 4. An example of a memory device 104 in FIG. 4. The memory device 400 may include a memory array 401 and a peripheral circuit 402 coupled to the memory array 401. The memory array 401 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0094] In some embodiments, each memory cell 406 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 406 is a two-bit memory cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per memory cell, three bits per memory cell (also known as a three-bit memory cell (TLC), four bits per cell (also known as a four-bit memory cell (QLC), or five bits per cell (also known as a five-bit memory cell (PLC). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value can be used for an erased state. In some embodiments, the memory state is also referred to as a data state, and the data state includes an erased state and a programming state, wherein the erased state is also the aforementioned erased state; the programming state is programmed from the erased state to one of the other data states.

[0095] like Figure 4As shown in , each NAND memory string 408 may include a lower select gate (BSG) 410 at its source terminal and an upper select gate (TSG) 412 at its drain terminal. BSG 410 and TSG 412 may be configured to activate a selected NAND memory string 408 during read and program operations. In some embodiments, the sources of the NAND memory strings 408 in the same memory block 404 are coupled by the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the TSG 412 of each NAND memory string 408 is coupled to a corresponding bit line (BL) 416, and data can be read from or written to the bit line 416 via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 412) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 412 via one or more TSG lines 413 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 410) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 410 via one or more BSG lines 415.

[0096] like Figure 4As shown in , a NAND memory string 408 can be organized into a plurality of memory blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is a basic data unit for an erase operation, i.e., all memory cells 406 on the same memory block 404 are erased at the same time. In order to erase the memory cells 406 in a selected memory block 404, the source lines 414 coupled to the selected memory block 404 and the unselected memory blocks 404 in the same plane as the selected memory block 404 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 406 of adjacent NAND memory strings 408 can be coupled by word lines 418, which select which row of memory cells 406 is affected by read and program operations. In some embodiments, each word line 418 is coupled to a page 420 of a memory cell 406, and the page 420 may be a basic data unit for a programming operation. The size of a page 420 in bits may be related to the number of NAND memory strings 408 coupled by word lines 418 in a memory block 404. Each word line 418 may include a plurality of control gates (gate electrodes) at each memory cell 406 in a corresponding page 420 and a gate line coupling the control gates. It should be noted that with the development of control technology, the minimum unit of programming may also be smaller than the page 420, and the operating method provided in the embodiment of the present application may also be applicable. The description of the page in the embodiment of the present application is only exemplary, and the embodiment of the present application is not limited to other ways of defining it.

[0097] Figure 5 4 shows a cross-sectional schematic diagram of an exemplary memory array 401 including NAND memory strings 408 according to some aspects of the present application. Figure 5 As shown, the NAND memory string 408 may include a stacked structure 510, which includes a plurality of gate layers 511 and a plurality of insulating layers 512 that are alternately stacked in sequence, and a memory string 408 that vertically penetrates the gate layers 511 and the insulating layers 512. The gate layers 511 and the insulating layers 512 may be alternately stacked, and two adjacent gate layers 511 are separated by a layer of insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 may determine the number of memory cells included in the memory array 401.

[0098] The constituent material of the gate layer 511 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 at the top of the stacked structure 510 may extend laterally as an upper selection gate line 513, the gate layer 511 at the bottom of the stacked structure 510 may extend laterally as a lower selection gate line 514, and the gate layer 511 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer 503.

[0099] In some embodiments, the stacked structure 510 may be disposed on a substrate 501. The substrate 501 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0100] In some embodiments, the NAND memory string 408 includes a channel structure extending vertically through the stacked structure 510. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0101] Return to reference Figure 3, the peripheral circuit 302 may be coupled to the memory array 401 via the bit line 316, the word line 418, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 401 by applying a voltage signal and / or a current signal to each target memory cell 406 and sensing a voltage signal and / or a current signal from each target memory cell 406 via the bit line 316, the word line 418, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, it may also include Figure 6 Additional circuitry not shown.

[0102] The page buffer / sense amplifier 604 may be configured to read data from the memory array 401 and program (write) data to the memory array 401 according to control signals from the control logic 612. In one example, the page buffer / sense amplifier 604 may store programming data (write data) to be programmed into the memory array 401. In another example, the page buffer / sense amplifier 604 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 604 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 406 and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 606 may be configured to be controlled by the control logic 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from the voltage generator 610.

[0103] The row decoder / word line driver 608 may be configured to be controlled by the control logic 612 and select / deselect the memory block 404 of the memory array 401 and select / deselect the word line 418 of the memory block 404. The row decoder / word line driver 608 may also be configured to drive the word line 418 using the word line voltage generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 may also select / deselect and drive the BSG line 315 and the TSG line 313. The row decoder / word line driver 608 may be configured to perform a programming operation on the memory cell 406 coupled to the selected word line(s) 418. The voltage generator 610 may be configured to be controlled by the control logic 612 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boost voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 401.

[0104] The control logic 612 may be coupled to the various circuits described above and configured to control the operation of the various circuits. The register 614 may be coupled to the control logic 612 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 616 may be coupled to the control logic 612 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 612, and to buffer status information received from the control logic 612 and relay them to the host. The interface 616 may also be coupled to the column decoder / bit line driver 606 via a data bus 618 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 401 or relay or buffer data from the memory array 401.

[0105] In 3D NAND memory devices, single-bit cell (SLC) occupies a certain share in the memory market due to its advantages such as fast read and write speed, high reliability and long service life; while two-bit cell (MLC), three-bit cell (TLC) and four-bit cell (QLC) have become the development trend of the memory market due to their higher storage density and larger storage capacity.

[0106] As the number of storage bits of the memory cell increases and the number of stacking layers increases, in order to achieve multi-bit storage, a page 420 is divided into multiple data states, such as Figure 7 The TLC and Figure 8The QLC shown in the figure, wherein the TLC includes 8 data states (P0, P1, P2, P3, P4, P5, P6, P7), and the threshold voltages of the storage cells corresponding to the data states P0 to P7 are getting higher and higher; the QLC includes 16 data states (P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15), and the threshold voltages of the storage cells corresponding to the data states P0 to P15 are getting higher and higher.

[0107] Based on the above settings, in order to correctly store and read a certain data state, the threshold voltage distribution width of each data state of multiple data states needs to be compressed to improve the read window margin (RWM). Among them, RWM is an important parameter for the memory device to correctly read the storage data of the memory cell. There are two definitions of RWM: the first one is that RWM is the sum of the intervals between the threshold voltage distributions corresponding to two adjacent data states of the memory cell, for example, Fig. 9 The threshold voltage distribution of the MLC type memory cell is described as shown in FIG. Fig. 9 As shown, the first RWM of the MLC type memory cell can be the voltage interval between the erase state P1 and the data state P2. Second, the RWM can be defined as the voltage interval between the programming verification voltage of the programming state of the memory cell and the read voltage used to distinguish the programming state from its adjacent data state, such as Fig. 9 The RWM included in is: the voltage interval between VRD1 and VFY1, the voltage interval between VRD2 and VFY2, and the voltage interval between VRD3 and VFY3, wherein VRD1, VRD2, and VRD3 are the read voltages for distinguishing the erase state P1 from the data state P2, the read voltages for distinguishing the data state P2 from the data state P3, and the read voltages for distinguishing the data state P3 from the data state P4; VFY1, VFY2, and VFY3 are the programming verification voltages for the data state P2, the programming verification voltages for the data state P3, and the programming verification voltages for the data state P4, respectively. As the density of data that can be stored in a single memory cell further increases, the width of the RWM decreases, such as Figure 7 The threshold voltage distribution of the TLC type memory cell is shown in FIG. Figure 8 The threshold voltage distribution of the QLC type memory cell shown in the figure shows the RWM ratio of the two. Fig. 9 The MLC type memory cell shown has a narrower RWM.

[0108] like Figure 7 and Figure 8As shown, the threshold voltage Vt of the memory cell corresponding to the highest data state (such as P8 or P15) is usually relatively high. In this case, more charges enter the storage layer of the memory cell. The more charges there are, and if it is baked at high temperature, the charge movement is more intense, resulting in a more serious charge loss of the memory cell, which in turn leads to a poor retention characteristic of the memory device. Of course, it should be understood that the memory cells corresponding to other data states will also lose charge, and will lose charge even if they are not baked, and the higher the data state, the more serious the charge loss of the corresponding memory cell. It is even more serious under high temperature conditions. The operating method provided in the embodiment of the present application is applicable to any of the above situations.

[0109] In order to solve one or more of the above problems, an embodiment of the present application provides an operating method of a memory device, in which, for two adjacent memory cells in the same memory string, the reference verification information used in the verification operation of the latter programmed memory cell is obtained according to the data state to which the former programmed memory cell is programmed, thereby obtaining appropriate reference verification information according to the data state of the former memory cell, and verifying the latter memory cell according to the determined reference verification information to improve the retention characteristics of the memory device.

[0110] The memory device includes a first memory unit and a second memory unit that belong to the same memory string and are adjacent to each other. Fig.10 As shown, the operation method may include:

[0111] S1001: Execute a first programming operation so that the first memory cell is programmed to a first data state;

[0112] S1002: Execute a second programming operation; the second programming operation includes: programming the second storage unit; and verifying the second storage unit according to first reference verification information determined according to the first data state.

[0113] Here, the memory string is such as the aforementioned memory string 408. The operation method may be a programming and verification method for a memory device, wherein the programming and verification method for the memory device may adopt a multi-pass programming algorithm to achieve a tighter threshold voltage distribution. Specifically, the multi-pass programming algorithm may include two-pass programming, three-pass programming, and the like, wherein the two-pass programming may include coarse programming and fine programming; the three-pass programming may include a first coarse programming, a second coarse programming, and fine programming. Here, the last programming in the multi-pass programming is fine programming; the first coarse programming and the second coarse programming are collectively referred to as coarse programming, and may also be referred to as non-last programming. In some embodiments, both non-last programming and fine programming may be incremental step pulse programming (ISPP), and the ISPP scheme may be based on a step voltage to gradually increase the word line bias voltage while programming the memory cells in the selected memory page several times. In order to balance the programming speed and having a wider RWM, in some embodiments, in non-final programming (each coarse programming stage), a programming voltage pulse with a larger set step size (for example, 0.5 volts (V)) is applied to the selected word line (the word line selected to be coupled with the storage cell to be programmed) to quickly program the storage cell coupled to the selected word line to an intermediate data state; in the fine programming stage performed after each coarse programming stage, a programming voltage pulse with a smaller set step size (for example, 0.2V) is applied to the selected word line to accurately program the storage cell coupled to the selected word line to a final data state or a target data state, that is, in some embodiments, in each programming pass of the multiple programming passes, the programming voltage / pulse applied in the programming operation is increased according to a different set step size, and the specific set step size can be set by the designer according to the actual programming situation. The intermediate data state is one or more data states before the programmed memory cell is programmed to the final data state. For example, when programming a TLC type memory cell, the final data state of a memory cell is P3, then the intermediate data state can be at least one of P1 and P2; or other verifiable data states. The final data state is the data state to which the user expects the programmed memory cell to be programmed. For example, when programming the TLC type memory cell, the final data state is P3.

[0114] It should be understood that during programming of a memory cell, in order to understand whether the programmed memory cell is programmed to the target programming data state, a verification operation is added between applying two programming voltage pulses (the process of applying programming voltage pulses is also referred to as a programming operation) to determine whether the programmed memory cell is programmed to the target data state, that is, the programming operation and the verification operation are performed alternately. The verification operation may be one or a group of verification voltage pulses. Based on the foregoing description, that is, the multi-pass programming may include at least one coarse programming pass and one fine programming pass, and each programming pass includes at least one programming operation and at least one verification operation.

[0115] Here, the first programming operation can program the first storage unit to the first data state, that is, perform programming and verification on the first storage unit, and the verification is successful, so that the first storage unit can be in the first data state. The first data state can refer to the intermediate data state or the target data state of the first storage unit, which is related to the programming and verification algorithm used for the entire memory string. The specific detailed description will not be repeated here.

[0116] The technical solution described here can also be understood as: for two adjacent storage cells, the data state of the first storage cell that is first programmed to the first data state will guide the programming of the second storage cell that is programmed later, that is, the first data state is used to determine the first reference verification information used for programming verification of the second storage cell, that is: the operation method may include: first performing a first programming operation on the first storage cell to program the first storage cell to the first data state, and then performing a second programming operation on the second storage cell, wherein in the second programming operation, the second storage cell is programmed, and the second storage cell is verified according to the first reference verification information determined by the first data state to determine whether the programming is successful. In this way, according to the data state of the storage cell that is programmed first in the two adjacent storage cells, the programming verification of the storage cell that is programmed later is guided to reduce the charge loss of the storage cell that is programmed later during high temperature baking.

[0117] In some embodiments, a memory cell of the memory device can be programmed to any one of a plurality of data states including the first data state; the method may further include:

[0118] Obtaining a first mapping relationship between the plurality of data states and reference verification information for verifying a programming result of a memory cell;

[0119] The first reference verification information is determined according to the first data state and the first mapping relationship.

[0120] It should be noted that, based on the above description of the storage cell type. When the storage cell type is MLC, TLC, QLC, etc., which can store more bits, the storage cells included in a page 420 can be programmed to multiple data states, and one of the storage cells can be programmed to any one of the multiple data states, that is, the storage cells of the memory device can be programmed to any one of the multiple data states, and these multiple data states should include the first data state. For example, such as the above Figure 4 As shown in the same page 420, they are coupled to the Figure 3 On the same word line 418 shown, these memory cells can be programmed to any of a plurality of data states, wherein one or more memory cells are programmed to a first data state. In a specific implementation operation, when the word line coupled to the first memory cell is a selected word line, a group of programming pulses is applied to the selected word line to perform a first programming operation, so that the first memory cell is programmed to the first data state, while other memory cells coupled to the same word line as the first memory cell are prohibited from programming under the control of the bit line voltage.

[0121] Under this condition, the determination of the first reference verification information may include: obtaining a first mapping relationship, and determining the first reference verification information according to the first mapping relationship and the first data state. That is, in the embodiment of the present application, before obtaining the first reference verification information, it is necessary to first obtain the first mapping relationship between the multiple data states and the reference verification information used to verify the programming result of the storage unit, and then, perform the first data state and the first mapping relationship to obtain the first reference verification information for later use. Of course, it is understandable that the first mapping relationship can be pre-stored, or it can be determined according to multiple data states when it is needed.

[0122] Here, in some embodiments, the reference verification information may include a reference verification voltage or a reference sensing time; and obtaining a first mapping relationship between the plurality of data states and the reference verification information for verifying a programming result of a memory cell may include:

[0123] Dividing the multiple data states to form multiple data groups;

[0124] Obtaining a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; or obtaining a second sub-mapping relationship between the plurality of data groups and the reference sensing time;

[0125] The first mapping relationship includes: a first sub-mapping relationship and / or the second sub-mapping relationship.

[0126] It should be noted that the verification of the memory cell usually requires precharging the sensing node coupled to the memory cell to a higher potential (e.g., an initial precharge position), and then the sensing node performs at least one discharge operation, so as to sense the voltage at the sensing node (SO, Sensing Node) corresponding to the memory cell at different discharge stages through the sensing circuit, so as to determine whether the verification of the memory cell is completed based on the sensing result. The verification result can be stored in the page buffer to reflect the programming result of the memory cell.

[0127] For example, Fig.11 The verification operation of the 4BL BIAS programming method shown in the figure requires three sensing operations, namely 3BL sensing, 4BL sensing, and Pass sensing, to determine whether the threshold voltage of the memory cell being verified is programmed to the 3BL interval, 4BL interval, or Pass interval, respectively. It should be noted that the 3BL sensing process corresponds to Fig.11 The 3BL verification (VFY) shown in the figure; the 4BL sensing process corresponds to Fig.11 4BL VFY shown in the figure; the Pass sensing process corresponds to Figure 1 The Pass VFY shown in . The 3BL interval can refer to Fig.11 The area to the left of the 3BL VFY; the 4BL range can refer to Fig.11 The overlapping area between the right side of 3BL VFY and the left side of 4BL VFY; the Pass interval can refer to Fig.11 The overlapped area between the right side of 4BL VFY and the left side of Pass VFY shown in FIG. When the memory cells in different intervals perform programming operations again, the bias voltages applied to the bit lines are different, so as to more accurately program the memory cells to the target programming state. For example, when the memory cells in the 3BL interval perform programming operations, 0 volts (V) are applied to the corresponding bit lines; when the memory cells in the 4BL interval perform programming operations, the corresponding bit lines are applied with voltage VBL3; when the memory cells in the Pass interval perform programming operations, the corresponding bit lines are applied with voltage VBL4.

[0128] The reference verification information for verification may include a reference verification voltage or a reference sensing time. Therefore, the first mapping relationship may include a first sub-mapping relationship between multiple data groups and reference verification voltages, and / or a second sub-mapping relationship between multiple data groups and reference sensing times.

[0129] Here, the reference verification voltage may refer to a target verification voltage that is compared with a potential after SO is discharged from an initial precharge position for a period of time to determine whether the programming of the memory cell is successful, specifically, Fig.12 The relationship between the discharge time and the potential of SO is shown in FIG. 1 . The potential of SO is negatively correlated with the discharge time, that is, the longer the discharge time, the lower the potential of SO. Based on this, in the verification process, a preset potential is set, and the potential of SO is discharged from the initial precharge position. After a period of discharge, if the potential of SO is greater than or equal to the set potential, the storage cell is turned on, and the storage cell passes the verification of the target verification voltage, and the storage cell is successfully programmed; if the potential of SO is less than the set potential, the storage cell is turned off, and the storage cell fails to pass the verification of the target verification voltage, and the storage cell is not successfully programmed. In addition, the higher the target verification voltage, the higher the threshold voltage of the successfully programmed storage cell.

[0130] Here, the reference sensing time may refer to a target discharge time set for discharging SO from an initial pre-charge position. Fig.12 The relationship shown in FIG. 1 is that during the verification process, a preset potential is set, and the potential of SO starts to discharge from the initial precharge position or the potential after the discharge in the previous stage. Within the target discharge time, if the potential of SO is not programmed to the preset potential, the storage unit is turned off, and the storage unit is not programmed and verified successfully; within the target discharge time, if the potential of SO is programmed to the preset potential, the storage unit is turned on, and the storage unit is programmed and verified successfully. Moreover, under the condition of a certain predetermined potential, the longer the target discharge time, the smaller the induced current, and the lower the threshold voltage of the successfully programmed storage unit; the shorter the target discharge time, the larger the induced current, and the higher the threshold voltage of the successfully programmed storage unit.

[0131] Here, there may be multiple combinations of the division of multiple data states. A practical division method, wherein the division of the multiple data states to form multiple data groups may include:

[0132] The multiple data states are divided into a first data group and a second data group, wherein a threshold voltage corresponding to the data state in the first data group is smaller than a threshold voltage corresponding to the data state in the second data group.

[0133] In this case, the first mapping relationship may include: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or a second sub-mapping relationship between the first data group, the second data group and the reference sensing time;

[0134] Among them, the first sub-mapping relationship may include: the correspondence between the first data group and the first reference verification voltage, the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

[0135] That is, in the first sub-mapping relationship, the first reference verification voltage corresponding to the data state contained in the first data group is greater than the second reference verification voltage corresponding to the data state contained in the second data group; in the second sub-mapping relationship, the first reference sensing time corresponding to the data state contained in the first data group is greater than the second reference sensing time corresponding to the data state contained in the second data group.

[0136] In some embodiments, the first data group and the second data group in the plurality of data groups contain the same number of data states. In other embodiments, the first data group and the second data group in the plurality of data groups may contain different numbers of data states.

[0137] In some embodiments, the plurality of data states include 16 data states L0 to L15; the first data group includes data states L0 to L7; and the second data group includes data states L8 to L15.

[0138] In some embodiments, determining the first reference verification information according to the first data state and the first mapping relationship may include:

[0139] Determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes a correspondence relationship between the multiple data groups and the multiple data states;

[0140] Determine the first reference verification information according to the data group to which it belongs and the first sub-mapping relationship, or determine the first reference verification information according to the data group to which it belongs and the second sub-mapping relationship;

[0141] Among them, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

[0142] Here, after research, it is found that the reasons for the poor retention characteristics caused by the charge loss of the memory cell are mainly two aspects: vertical charge loss and lateral charge loss. Fig.13 and Fig.14 As shown, vertical charge loss can refer to the charge loss of the memory cell in the direction perpendicular to the memory string; lateral charge loss can refer to the charge loss of the memory cell in the direction parallel to the memory string. According to research, in the vertical direction, the charge loss of the memory cell is related to the threshold voltage Vt of the memory cell. The higher the Vt, the more serious the charge loss; in the lateral direction, the charge loss of the memory cell is not only related to the threshold voltage of the memory cell, but also to the data state of the adjacent memory cell. Specifically, when the adjacent memory cell is in a high data state (already programmed to a high data state), the lateral charge loss corresponding to the memory cell being programmed is very small, and when the adjacent memory cell is in a low data state (already programmed to a low data state), the lateral change loss corresponding to the memory cell being programmed is very serious. In this case, the lateral charge loss will be more serious than the charge loss caused by the vertical charge loss, and the charge loss will be more serious after high-temperature baking, thereby causing the threshold voltage distribution of the memory cell to widen, and then causing serious RWM loss. It should be noted that in Fig.13 In the figure, H represents a memory cell with a high data state; L represents a memory cell with a low data state; and R represents a memory cell being programmed. At this time, the memory cell can be programmed to any possible data state. The arrows perpendicular to the memory string represent vertical charge loss; the arrows parallel to the memory string represent lateral charge loss. Fig.14In the figure, WLn represents the word line coupled to the memory cell being programmed, or is called the selected word line. The curve represents the threshold voltage distribution of the memory cell corresponding to WLn, wherein the dotted line 1 represents the threshold voltage distribution of the memory cell corresponding to WLn when the memory cell corresponding to the adjacent WLn+1 is in a high data state; the dotted line 2 represents the threshold voltage distribution of the memory cell corresponding to WLn when the memory cell corresponding to the adjacent WLn+1 is in a low data state; in actual application, the memory cells corresponding to the adjacent WLn+1 include those in a high data state and those in a low data state, therefore, the solid line 3 represents the threshold voltage distribution of the memory cell corresponding to WLn when the memory cell corresponding to the adjacent WLn+1 in the statistical memory cells is in a high data state and / or a low data state. By Fig.14 As shown, after high-temperature baking, the threshold voltage of the memory cell corresponding to WLn is further widened.

[0143] Based on this, when the first sub-mapping relationship is adopted, when the first data state belongs to the first data group, the first reference verification information is the first reference verification voltage; when the first data state belongs to the second data group, the first reference verification information is the second reference verification voltage. When the second sub-mapping relationship is adopted, when the first data state belongs to the first data group, the first reference verification information is the first reference sensing time; when the first data state belongs to the second data group, the first reference verification information is the second reference sensing time.

[0144] In some embodiments, the memory string may further include a third memory cell adjacent to the second memory cell; and the method may further include:

[0145] performing a third programming operation so that the first memory cell is programmed to a first target programming state;

[0146] performing a fourth programming operation so that the third memory cell is programmed to a second data state;

[0147] Wherein, in the second programming operation, the second storage unit is not programmed to a second target data state; and the second data state is not a target data state.

[0148] In some embodiments, the memory string further includes: a fourth memory cell adjacent to the first memory cell; before performing the first programming operation, the method further includes:

[0149] performing a fifth programming operation so that the fourth memory cell is programmed to a third data state;

[0150] performing a sixth programming operation so that the second memory cell is programmed to a fourth data state;

[0151] performing a seventh programming operation so that the fourth memory cell is programmed to a third target data state;

[0152] The first data state, the third data state, and the fourth data state are not target data states; in the second programming operation, the memory cell is programmed to a second target data state.

[0153] It should be noted that, as described above, the programming and verification method of the memory device can adopt a multi-pass programming algorithm. Therefore, the implementation of the above operation method can be applicable to both coarse programming and fine programming in the multi-pass programming algorithm.

[0154] In the operating method provided in the embodiment of the present application, when the first data state is not the target data state, when executing Fig.10 After the steps shown, a subsequent third programming operation may also be included to program the first storage cell to the first target state; and a fourth programming operation may be included to program the third storage cell adjacent to the second storage cell to the second data state, wherein, under this operation, the second storage cell is not programmed to the second target data state under the second programming operation, and the second data state is not the target data state. The above process is equivalent to two steps in two-side programming: the first step includes the first programming operation and the second programming operation, that is, rough programming of the first storage cell and the second storage cell; the second step includes the third programming operation and the fourth programming operation, that is, fine programming of the first storage cell and rough programming of the third storage cell.

[0155] When the first data state is not the target data state, when executing Fig.10 Before the steps shown, it may also include: executing a fifth programming operation to program the fourth storage cell to a third data state; a sixth programming operation to program the second storage cell to a fourth data state; and a seventh programming operation to program the fourth storage cell to a third target data state. The above process is equivalent to two steps in two-side programming: the first step includes the fifth programming operation, the sixth programming operation, and the seventh programming operation, that is, coarse programming of the fourth storage cell, coarse programming of the second storage cell, and fine programming of the fourth storage cell; the second step includes the first programming operation and the second programming operation, that is, coarse programming of the first storage cell and fine programming of the second storage cell.

[0156] It should be noted that the first data state may also be the target data state. Specifically, when the first storage unit, the second storage unit, and the third storage unit are adjacent to each other in sequence, the data state of the fine programming of the first storage unit is used as a guide in the fine programming of the second storage unit.

[0157] Understanding of the above situation, such as Fig.15 As shown, it shows a schematic diagram of the process of two-side programming provided in an embodiment of the present application.

[0158] exist Fig.15 In the process of programming on both sides, the first step includes: coarse programming of WLn-1 and WLn; the second step includes: fine programming of WLn-1 and coarse programming of WLn+1; then, the third step includes fine programming of WLn and coarse programming of WLn+2, and so on. In this position structure, the first storage unit can be the storage unit corresponding to WLn-1; the second storage unit is the storage unit corresponding to WLn; the third storage unit is the storage unit corresponding to WLn+1. Fig.10 The operation performed is the first step in two-side programming, that is, coarse programming of the storage cells corresponding to WLn-1 and the storage cells corresponding to WLn; the third programming operation and the fourth programming operation are the second step in two-side programming, that is, fine programming of the storage cells corresponding to WLn-1 and coarse programming of the storage cells corresponding to WLn+1.

[0159] exist Fig.15 In the position structure shown, the first storage unit may also be the storage unit corresponding to WLn+1, the second storage unit may be the storage unit corresponding to WLn; and the fourth storage unit may be the storage unit corresponding to WLn-1. In this case, Fig.10 Before the operation is executed, the coarse programming of the memory cell corresponding to WLn-1, the coarse programming of the memory cell corresponding to WLn, and the fine programming of the memory cell corresponding to WLn-1 are first executed; then Fig.10 Rough programming is performed on the memory cells corresponding to WLn+1, and fine programming is performed on the memory cells corresponding to WLn.

[0160] That is, no matter what kind of programming and verification algorithm is used, the embodiments of the present application are applicable, and the data state of the memory cell successfully programmed in the previous step is used to program the next memory cell to improve the retention.

[0161] In order to understand the operation method provided in the embodiment of the present application, a QLC type storage unit and the use of the storage unit of this type as follows are used. Fig.15 The two-side programming and verification algorithm shown in the figure is used as an example for explanation. Moreover, according to the description of the previous operation method, the 16 data states are divided into a first data group and a second data group, and the first data group includes data states L0 to L7; the second data group includes data states L8 to L15. Moreover, the first data group corresponds to a first reference verification voltage V1 or a first reference sensing time T1; the second data group corresponds to a second reference verification voltage V2 or a second reference sensing time T2. For the specific implementation process, please refer to, Figures 16 to 19 As shown. Among them, Fig.16 A schematic diagram of a programming verification process when a memory cell corresponding to WLn is coarsely programmed and a reference verification voltage is used for verification according to an embodiment of the present application; Fig.17 A schematic diagram of a programming verification process when a memory cell corresponding to WLn is coarsely programmed and a reference sensing time is used for verification according to an embodiment of the present application; Fig.18 A schematic diagram of a programming verification process when fine programming is performed on a memory cell corresponding to WLn and verification is performed using a reference verification voltage according to an embodiment of the present application; Fig.19 A schematic diagram of a program verification process when fine programming is performed on a memory cell corresponding to WLn and verification is performed using a reference sensing time according to an embodiment of the present application.

[0162] exist Fig.16 The specific implementation process may include:

[0163] S1601: 16 data states of the storage cell corresponding to WLn-1 are divided into a first data group G1 and a second data group G2, wherein the first data group includes data states L0 to L7; the second data group includes data states L8 to L15;

[0164] S1602: when performing a verification operation on the memory cell corresponding to WLn after coarse programming, in the same memory string, when the data state of the memory cell corresponding to WLn-1 belongs to the first data group, select the first reference verification voltage V1 to verify the memory cell corresponding to WLn; when the data state of the memory cell corresponding to WLn-1 belongs to the second data group, select the second reference verification voltage V2 to verify the memory cell corresponding to WLn;

[0165] S1603: When the verification is successful, the program operation is prohibited for the storage unit, and the process ends;

[0166] S1604: When verification fails, proceed to the next programming cycle.

[0167] It should be noted that, in the specific implementation, G1 corresponds to V1, and G2 corresponds to V2, which have been stored in the circuit or control logic. In specific use, "0" is latched in the latch of the page buffer in the memory device. At this time, V1 corresponding to G1 is selected to verify the storage unit corresponding to WLn; when "1" is latched in the latch of the page buffer in the memory device, V2 corresponding to G2 is selected to verify the storage unit corresponding to WLn.

[0168] exist Fig.17 The specific implementation process may include:

[0169] S1701: 16 data states of the storage cell corresponding to WLn-1 are divided into a first data group G1 and a second data group G2, wherein the first data group includes data states L0 to L7; the second data group includes data states L8 to L15;

[0170] S1702: when performing a verification operation on the memory cell corresponding to WLn after coarse programming, in the same memory string, when the data state of the memory cell corresponding to WLn-1 belongs to the first data group, select the first reference sensing time T1 to verify the memory cell corresponding to WLn; when the data state of the memory cell corresponding to WLn-1 belongs to the second data group, select the second reference sensing time T2 to verify the memory cell corresponding to WLn;

[0171] S1703: When the verification is successful, the program operation is prohibited for the storage unit, and the process ends;

[0172] S1704: When verification fails, proceed to the next programming cycle.

[0173] It should be noted that the embodiments of the present application provide Fig.17 The process and Fig.16 The process is basically the same, the difference is: Fig.17 The reference sensing time is used for verification, that is, Fig.16 The reference verification voltage in can be replaced by the reference sensing time (the first reference sensing time T1 or the second reference sensing time T2).

[0174] exist Fig.18 The specific implementation process may include:

[0175] S1801: 16 data states of the storage cell corresponding to WLn+1 are divided into a first data group G1 and a second data group G2, wherein the first data group includes data states L0 to L7; the second data group includes data states L8 to L15;

[0176] S1802: when performing a verification operation after fine programming on the memory cell corresponding to WLn, in the same memory string, when the data state of the memory cell corresponding to WLn+1 belongs to the first data group, select the first reference verification voltage V1 to verify the memory cell corresponding to WLn; when the data state of the memory cell corresponding to WLn+1 belongs to the second data group, select the second reference verification voltage V2 to verify the memory cell corresponding to WLn;

[0177] S1803: When the verification is successful, the program operation is prohibited for the storage unit, and the process ends;

[0178] S1804: When verification fails, proceed to the next programming cycle.

[0179] It should be noted that Fig.18 These are some procedures for selecting a reference verification voltage when performing a verification operation after fine programming on the memory cell corresponding to WLn. The reference verification voltage used here is determined according to the data group to which the data state of the memory cell corresponding to WLn+1 belongs.

[0180] exist Fig.19 The specific implementation process may include:

[0181] S1901: 16 data states of the storage cell corresponding to WLn+1 are divided into a first data group G1 and a second data group G2, wherein the first data group includes data states L0 to L7; the second data group includes data states L8 to L15;

[0182] S1902: when performing a verification operation on the memory cell corresponding to WLn after fine programming, in the same memory string, when the data state of the memory cell corresponding to WLn+1 belongs to the first data group, select the first reference sensing time T1 to verify the memory cell corresponding to WLn; when the data state of the memory cell corresponding to WLn+1 belongs to the second data group, select the second reference sensing time T2 to verify the memory cell corresponding to WLn;

[0183] S1903: When the verification is successful, the program operation is prohibited for the storage unit, and the process ends;

[0184] S1904: When verification fails, proceed to the next programming cycle.

[0185] It should be noted that the embodiments of the present application provide Fig.19 The process and Fig.18 The process is basically the same, the difference is: Fig.19 The reference sensing time is used for verification, that is, Fig.18 The reference verification voltage in can be replaced by the reference sensing time (the first reference sensing time T1 or the second reference sensing time T2).

[0186] The operating method provided in the embodiment of the present application can be summarized as follows: Fig. 20 and Fig.21 As shown. Curve 1 corresponds to the threshold voltage distribution of the memory cell WLn corresponding to the low (data) state of the memory cell WLn+1; Curve 2 corresponds to the threshold voltage distribution of the memory cell WLn corresponding to the high (data) state of WLn+1. Solid line 3 is the threshold voltage distribution of the memory cell corresponding to WLn when the adjacent memory cell corresponding to WLn+1 in the statistical memory cell is in the high data state and / or the low data state.

[0187] When selecting WLn to start rough programming, the adjacent WLn-1 has been programmed. Using the data written in WLn-1, the 16 programming states of WLn-1 are divided into multiple groups (G1, G2, not limited to 2 groups). For each programming state of WLn, there are multiple verify levels (V1 < V2). For the group where WLn-1 is in the low state (G1), the rough programming verify level of WLn is V2. For the group where WLn-1 is in the high state (G2), the rough programming verify level of WLn is V1. Similarly, immediately following is the fine programming of WLn-1 and the rough programming of WLn+1. Before starting the fine programming of WLn, similarly, the data of WLn+1 is divided into multiple groups (G1’, G2’, not limited to 2 groups). For each programming state of WLn, there are multiple verify levels (V1’ < V2’). For the group where WLn+1 is in the low state (G1’), the pgm verify level of WLn is V2’. For the group where WLn+1 is in the high state (G2’), the pgm verify level of WLn is V1’. Using this correspondence between WLn and the adjacent WL Vt to improve the high-temperature retention characteristics.

[0188] Alternatively, when selecting WLn to start rough programming, the adjacent WLn-1 has been programmed. Using the data written in WLn-1, the 16 programming states of WLn-1 are divided into multiple groups (G1, G2, not limited to 2 groups). For each programming state of WLn, there are multiple sensing times (T1 < T2). For the group where WLn-1 is in the low state (G1), the rough programming verify sensing time of WLn is long (T2). For the group where WLn-1 is in the high state (G2), the rough programming verify sensing time of WLn is short (T1). Similarly, immediately following is the fine programming of WLn-1 and the rough programming of WLn+1. Before starting the fine programming of WLn, similarly, the data of WLn+1 is divided into multiple groups (G1’, G2’, not limited to 2 groups). For each programming state of WLn, there are multiple verify levels (T1’ < T2’). For the group where WLn+1 is in the low state (G1’), the fine programming verify sensing time of WLn is long (T2’). For the group where WLn+1 is in the high state (G2’), the fine programming verify sensing time of WLn is short (T1’). Using this correspondence between WLn and the adjacent WL Vt to improve the high-temperature retention characteristics.

[0189] Based on the same inventive concept, such as Fig. 22As shown, the embodiment of the present application further provides a memory device 2200, including:

[0190] The memory array 2201 includes: a first memory cell and a second memory cell that belong to the same memory string and are adjacent to each other;

[0191] The peripheral circuit 2202, coupled to the memory array, is configured as follows:

[0192] Performing a first programming operation so that the first memory cell is programmed to a first data state;

[0193] A second programming operation is performed; the second programming operation includes: programming the second storage cell; and verifying the second storage cell according to first reference verification information determined by the first data state.

[0194] In some embodiments, a storage cell of the memory device can be programmed to any one of a plurality of data states including the first data state; the peripheral circuit is further configured to: obtain a first mapping relationship between the plurality of data states and reference verification information for verifying a programming result of the storage cell; and determine the first reference verification information based on the first data state and the first mapping relationship.

[0195] In some embodiments, the reference verification information includes a reference verification voltage or a reference sensing time; the peripheral circuit is further configured to: divide the multiple data states to form multiple data groups; obtain a first sub-mapping relationship between the multiple data groups and the reference verification voltage; or, obtain a second sub-mapping relationship between the multiple data groups and the reference sensing time; wherein the first mapping relationship includes: a first sub-mapping relationship and / or the second sub-mapping relationship.

[0196] In some embodiments, the peripheral circuit is further configured to: divide the multiple data states to form a first data group and a second data group, wherein the threshold voltage corresponding to the data state in the first data group is smaller than the threshold voltage corresponding to the data state in the second data group.

[0197] In some embodiments, the first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or a second sub-mapping relationship between the first data group, the second data group and the reference sensing time;

[0198] Among them, the first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

[0199] In some embodiments, the memory string also includes a third storage cell adjacent to the second storage cell; the peripheral circuit is further configured to: perform a third programming operation so that the first storage cell is programmed to a first target programming state; perform a fourth programming operation so that the third storage cell is programmed to a second data state; wherein, under the second programming operation, the second storage cell is not programmed to a second target data state; and the second data state is not a target data state.

[0200] In some embodiments, the memory string further includes: a fourth memory cell adjacent to the first memory cell; the peripheral circuit is further configured to: before executing the first programming operation,

[0201] performing a fifth programming operation so that the fourth memory cell is programmed to a third data state;

[0202] performing a sixth programming operation so that the second memory cell is programmed to a fourth data state;

[0203] performing a seventh programming operation so that the fourth memory cell is programmed to a third target data state;

[0204] The first data state, the third data state, and the fourth data state are not target data states; in the second programming operation, the memory cell is programmed to a second target data state.

[0205] In some embodiments, the peripheral circuit is further configured to: determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes a correspondence relationship between the multiple data groups and the multiple data states;

[0206] Determine the first reference verification information according to the data group to which it belongs and the first sub-mapping relationship, or determine the first reference verification information according to the data group to which it belongs and the second sub-mapping relationship;

[0207] Among them, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

[0208] It should be noted that the memory device provided in the embodiment of the present application is used to execute the aforementioned operating method. Therefore, the features appearing here have been described above and can be understood by referring to the above and will not be repeated here.

[0209] An embodiment of the present application also provides a memory system, comprising: one or more memory devices of any of the foregoing items.

[0210] In some embodiments, the memory system is included in a solid state drive (SSD) or a memory card.

[0211] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as those available to those skilled in the art when reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features can be combined together to simplify the application. This should not be interpreted as meaning that the disclosed features that are not claimed for protection are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the detailed description, wherein each claim is independently used as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or permutations. The scope of the present application should be determined with reference to the attached claims and the full scope of the equivalents given by these claims.

Claims

1. A method for operating a memory device, characterized in that: The memory device includes a first memory cell and a second memory cell that belong to the same memory string and are adjacent to each other; the method includes: Performing a first programming operation so that the first memory cell is programmed to a first data state; A second programming operation is performed; the second programming operation includes: programming the second storage cell; and verifying the second storage cell according to first reference verification information determined by the first data state.

2. The operating method according to claim 1, characterized in that: The memory cell of the memory device can be programmed to any one of a plurality of data states including the first data state; the method further comprising: Obtaining a first mapping relationship between the plurality of data states and reference verification information for verifying a programming result of a memory cell; The first reference verification information is determined according to the first data state and the first mapping relationship.

3. The operating method according to claim 2, characterized in that: The reference verification information includes a reference verification voltage or a reference sensing time; and obtaining a first mapping relationship between the plurality of data states and the reference verification information for verifying a programming result of a memory cell includes: Dividing the multiple data states to form multiple data groups; Obtaining a first sub-mapping relationship between the plurality of data groups and the reference verification voltage; or obtaining a second sub-mapping relationship between the plurality of data groups and the reference sensing time; The first mapping relationship includes: a first sub-mapping relationship and / or the second sub-mapping relationship.

4. The operating method according to claim 3, characterized in that: The dividing the multiple data states to form multiple data groups includes: The multiple data states are divided into a first data group and a second data group, wherein a threshold voltage corresponding to the data state in the first data group is smaller than a threshold voltage corresponding to the data state in the second data group.

5. The operating method according to claim 4, characterized in that: The first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or a second sub-mapping relationship between the first data group, the second data group and the reference sensing time; Among them, the first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

6. The operating method according to claim 1, characterized in that: The memory string further includes a third memory cell adjacent to the second memory cell; the method further includes: performing a third programming operation so that the first memory cell is programmed to a first target programming state; performing a fourth programming operation so that the third memory cell is programmed to a second data state; Wherein, in the second programming operation, the second storage unit is not programmed to a second target data state; and the second data state is not a target data state.

7. The operating method according to claim 1, characterized in that: The memory string further includes: a fourth memory cell adjacent to the first memory cell; before performing the first programming operation, the method further includes: performing a fifth programming operation so that the fourth memory cell is programmed to a third data state; performing a sixth programming operation so that the second memory cell is programmed to a fourth data state; performing a seventh programming operation so that the fourth memory cell is programmed to a third target data state; The first data state, the third data state, and the fourth data state are not target data states; in the second programming operation, the memory cell is programmed to a second target data state.

8. The operating method according to claim 3, characterized in that: The first data group and the second data group of the plurality of data groups contain the same number of data states.

9. The operating method according to claim 8, characterized in that: The multiple data states include 16 data states from L0 to L15; the first data group includes data states from L0 to L7; and the second data group includes data states from L8 to L15.

10. The operating method according to claim 5, characterized in that: The determining the first reference verification information according to the first data state and the first mapping relationship includes: Determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes a correspondence relationship between the multiple data groups and the multiple data states; Determine the first reference verification information according to the data group to which it belongs and the first sub-mapping relationship, or determine the first reference verification information according to the data group to which it belongs and the second sub-mapping relationship; Among them, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

11. A memory device, characterized in that: include: A memory array, comprising: a first memory cell and a second memory cell belonging to the same memory string and adjacent to each other; The peripheral circuit, coupled to the memory array, is configured to: Performing a first programming operation so that the first memory cell is programmed to a first data state; A second programming operation is performed; the second programming operation includes: programming the second storage cell; and verifying the second storage cell according to first reference verification information determined by the first data state.

12. The memory device according to claim 11, wherein: The storage cell of the memory device can be programmed to any one of a plurality of data states including the first data state; the peripheral circuit is further configured to: obtain a first mapping relationship between the plurality of data states and reference verification information for verifying the programming result of the storage cell; and determine the first reference verification information based on the first data state and the first mapping relationship.

13. The memory device according to claim 12, wherein: The reference verification information includes a reference verification voltage or a reference sensing time; the peripheral circuit is further configured to: divide the multiple data states to form multiple data groups; obtain a first sub-mapping relationship between the multiple data groups and the reference verification voltage; Or, a second sub-mapping relationship between the multiple data groups and the reference sensing time is obtained; wherein the first mapping relationship includes: a first sub-mapping relationship and / or the second sub-mapping relationship.

14. The memory device according to claim 13, wherein: The peripheral circuit is further configured to: divide the multiple data states to form a first data group and a second data group, wherein a threshold voltage corresponding to the data state in the first data group is smaller than a threshold voltage corresponding to the data state in the second data group.

15. The memory device according to claim 14, wherein: The first mapping relationship includes: a first sub-mapping relationship between the first data group, the second data and the reference verification voltage; and / or a second sub-mapping relationship between the first data group, the second data group and the reference sensing time; Among them, the first sub-mapping relationship includes: the correspondence between the first data group and the first reference verification voltage, the correspondence between the second data group and the second reference verification voltage; the first reference verification voltage is greater than the second reference verification voltage; the second sub-mapping relationship includes: the correspondence between the first data group and the first reference sensing time, the second data group and the second reference sensing time, wherein the first reference sensing time is greater than the second reference sensing time.

16. The memory device according to claim 11, wherein: The memory string also includes a third storage cell adjacent to the second storage cell; the peripheral circuit is further configured to: perform a third programming operation so that the first storage cell is programmed to a first target programming state; perform a fourth programming operation so that the third storage cell is programmed to a second data state; wherein, under the second programming operation, the second storage cell is not programmed to a second target data state; and the second data state is not a target data state.

17. The memory device according to claim 11, wherein: The memory string further includes: a fourth memory cell adjacent to the first memory cell; the peripheral circuit is further configured to: before executing the first programming operation, performing a fifth programming operation so that the fourth memory cell is programmed to a third data state; performing a sixth programming operation so that the second memory cell is programmed to a fourth data state; performing a seventh programming operation so that the fourth memory cell is programmed to a third target data state; The first data state, the third data state, and the fourth data state are not target data states; in the second programming operation, the memory cell is programmed to a second target data state.

18. The memory device according to claim 14, wherein: The peripheral circuit is further configured to: determine the data group to which the first data state belongs according to a preset second mapping relationship, wherein the second mapping relationship includes a correspondence relationship between the multiple data groups and the multiple data states; Determine the first reference verification information according to the data group to which it belongs and the first sub-mapping relationship, or determine the first reference verification information according to the data group to which it belongs and the second sub-mapping relationship; Among them, in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference verification voltage; in the case of the first sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference verification voltage; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the first data group, the first reference verification information is determined to be the first reference sensing time; in the case of the second sub-mapping relationship and the data group to which the first data state belongs is the second data group, the first reference verification information is determined to be the second reference sensing time.

19. A memory system, characterized in that: include: A memory device as claimed in any one or more of claims 11 to 18.

20. The memory system according to claim 19, wherein: The memory system is included in a solid state drive SSD or a memory card.

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