Chip verification method, device and system and electronic equipment

Abstract

The embodiment of the invention provides a chip verification method, device and system and electronic equipment. The verification method comprises the steps of obtaining a pre-configured basic verification environment of a to-be-tested chip; acquiring configuration information of a verification environment of the to-be-tested chip; modifying the basic verification environment based on the configuration information to obtain an actual verification environment; and testing the chip to be tested according to the actual verification environment. By configuring the basic verification environment in advance, modification can be subsequently performed based on the configuration information of the to-be-tested chip to obtain the actual verification environment, so that the verification time consumption and cost are reduced, and the verification efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip verification technology, and in particular to a chip verification method, device and system, and electronic equipment. Background Art

[0002] In the field of automotive microcontroller unit (MCU) chips, in pursuit of high performance and low power consumption, embedded flash memory (eFLASH) has been widely promoted and used. It is mainly used to store manufacturer startup programs, user data, chip internal adjustment values, keys and other information.

[0003] Different MCU chips may use eFLASH from different manufacturers, which not only leads to differences in eFLASH control logic, but also differences in size specifications and business characteristics.

[0004] When faced with eFLASH from different manufacturers or with different specifications, during the chip verification process, it is necessary to build a verification environment based on the Universal Verification Methodology (UVM) from scratch, and develop corresponding drivers and test cases to adapt to the characteristics of the eFLASH to be verified. Since each chip needs to rebuild the environment, driver and test cases, the verification takes a long time, the verification efficiency is low, and the verification cost is increased. Summary of the invention

[0005] The embodiments of the present application provide a chip verification method, device and system, and electronic device. By pre-configuring a basic verification environment, the actual verification environment can be subsequently modified based on the configuration information of the chip to be tested, thereby reducing verification time and cost and improving verification efficiency.

[0006] In a first aspect, an embodiment of the present application provides a chip verification method, which includes: obtaining a pre-configured basic verification environment of a chip to be tested; obtaining configuration information of the verification environment of the chip to be tested; modifying the basic verification environment based on the configuration information to obtain an actual verification environment; and testing the chip to be tested according to the actual verification environment.

[0007] In some embodiments, obtaining a pre-configured basic verification environment for a chip to be tested includes: constructing basic components in the basic verification environment, the basic components including a reference model, a scoreboard, and a first bus agent, wherein the first bus agent is configured to communicate with the chip to be tested; constructing adaptive components in the basic verification environment, the adaptive components including a test case list, a sequence list, a control task, a second bus agent, and a third bus agent, wherein the second bus agent is configured to communicate with the reference model and the chip to be tested, respectively, and the third bus agent is configured to communicate with the scoreboard and the chip to be tested, respectively.

[0008] In some embodiments, modifying the basic verification environment based on the configuration information to obtain the actual verification environment includes: modifying the adaptive component based on the configuration information to obtain the actual verification environment.

[0009] In some embodiments, the first bus agent is an APB agent, the second bus agent includes a first AHB agent or a first AXI agent, and the third bus agent includes a second AHB agent or a second AXI agent.

[0010] In some embodiments, the testing the chip to be tested according to the actual verification environment includes: executing a test on the chip to be tested based on a test case list in the actual verification environment.

[0011] In some embodiments, the testing of the chip to be tested according to the actual verification environment further includes: obtaining a new test case input by a user; and performing a test on the chip to be tested based on the new test case and the actual verification environment.

[0012] In a second aspect, the embodiment of the present application further provides a chip verification device, which includes: a first acquisition device, a second acquisition device, a modification device, and a test device. The first acquisition device is configured to acquire a pre-configured basic verification environment of a chip to be tested; the second acquisition device is configured to acquire configuration information of the verification environment of the chip to be tested; the modification device is configured to modify the basic verification environment based on the configuration information to obtain an actual verification environment; and the test device is configured to test the chip to be tested according to the actual verification environment.

[0013] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in any one of the embodiments of the first aspect above.

[0014] In a fourth aspect, an embodiment of the present application further provides a chip verification system, which includes: a chip to be tested, and the electronic device as described in the third aspect; the chip to be tested is electrically connected to the electronic device.

[0015] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method described in the first aspect above.

[0016] In a sixth aspect, an embodiment of the present application further provides a computer program product, wherein the computer program product comprises a computer program stored on a computer-readable storage medium, wherein the computer program comprises program instructions, and when the program instructions are executed by a computer, the computer executes the method described in the first aspect above.

[0017] Compared with the prior art, the beneficial effects of the present application are as follows: Different from the prior art, the embodiments of the present application provide a chip verification method, device, system, and electronic device, and the verification method includes: obtaining a pre-configured basic verification environment of the chip to be tested; obtaining configuration information of the verification environment of the chip to be tested; modifying the basic verification environment based on the configuration information to obtain an actual verification environment; and testing the chip to be tested according to the actual verification environment. By pre-configuring the basic verification environment, the actual verification environment can be subsequently modified based on the configuration information of the chip to be tested, thereby reducing verification time and cost and improving verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements / modules and steps with the same reference numerals in the drawings are represented as similar elements / modules and steps. Unless otherwise specified, the figures in the drawings do not constitute proportional limitations.

[0019] Figure 1 is a flow chart of a chip verification method provided by an embodiment of the present application;

[0020] Figure 2 It is a structural block diagram of a chip verification environment provided by an embodiment of the present application;

[0021] Figure 3 is a structural block diagram of a chip verification device provided in an embodiment of the present application;

[0022] Figure 4 is a structural block diagram of an electronic device provided in an embodiment of the present application;

[0023] Figure 5It is a structural block diagram of a chip verification system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The present application is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements can also be made without departing from the concept of the present application. These all belong to the protection scope of the present application.

[0025] For ease of understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those generally understood by those skilled in the art of the present application. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not used to limit the present application. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0026] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional module division is performed in the device schematic, in some cases, the module division can be different from that in the device. In addition, the words "first", "second", etc. used herein do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0027] In a first aspect, an embodiment of the present application provides a chip verification method, which can be executed by the electronic device provided by the present application, see Figure 1 , the verification method comprises the following steps:

[0028] Step S100: Acquire a pre-configured basic verification environment of the chip to be tested.

[0029] The chip to be tested can be an MCU chip equipped with eFLASH. Chip verification is a key step to ensure that the chip to be tested can correctly perform its functions in actual applications. By simulating real application scenarios and conditions through software, it can be verified whether the behavior of the chip to be tested in key operations such as eFLASH programming, erasing and reading is in line with expectations, thereby ensuring the reliability and stability of the chip in subsequent products.

[0030] The basic verification environment refers to a general and standardized test environment pre-configured for the chip to be tested. The basic verification environment includes the basic components required for chip verification and is a verification environment built based on the Universal Verification Methodology (UVM).

[0031] The electronic device can obtain the basic verification environment from a preset storage location or database.

[0032] Step S200: Acquire configuration information of the verification environment of the chip to be tested.

[0033] Configuration information refers to the parameters, settings or instructions specific to the verification requirements of the chip to be tested. The configuration information can be used to guide how to modify the basic verification environment according to the characteristics of the chip to be tested and the test requirements, so as to create an actual verification environment that matches the actual test requirements. The configuration information may include parameters such as the model of the chip to be tested, eFLASH specifications, and test characteristics. Specifically, the electronic device can obtain the configuration information through the user's input information.

[0034] Step S300: Modify the basic verification environment based on the configuration information to obtain the actual verification environment.

[0035] The actual verification environment refers to a specific verification environment customized based on the basic verification environment and configuration information, which is specially used to test the chip to be tested. The actual verification environment has been adjusted according to the characteristics of the chip to be tested and the test requirements, and can accurately simulate the working environment and conditions of the chip in actual applications. Tests conducted in the actual verification environment can more accurately reflect the performance and reliability of the chip.

[0036] After obtaining the configuration information, the electronic device will adaptively modify some components in the basic verification environment according to the configuration information, such as configuring specific test cases, adjusting the interface library, and other operations to match the specifications of the chip to be tested, thereby obtaining an actual verification environment that matches the actual test requirements.

[0037] Step S400: testing the chip to be tested according to the actual verification environment.

[0038] Specifically, in an actual verification environment, the electronic device will perform a series of tests on the chip to be tested to verify whether its behavior in key operations such as eFLASH programming, erasing, and reading is as expected, and the test results can be output later.

[0039] Although the underlying driving logic of FLASH programming, erasing and reading initiated by eFLASH of different manufacturers and different specifications is different, the application scenarios of FLASH programming, erasing and reading are basically the same. Therefore, the verification environment can be layered to pre-build a normalized basic verification environment. When facing different chips to be tested, there is no need to modify the application layer in the basic verification environment. You only need to modify the underlying driving code in the basic verification environment according to the configuration information to obtain the actual verification environment. That is, in the verification method provided by this application, the actual verification environment and test cases of the chip to be tested can be automatically generated by the user configuring the relevant parameters of the chip to be tested, so as to realize the verification of eFLASH of different manufacturers, different specifications and different characteristics. The same basic verification environment combined with multiple sets of configuration information can generate multiple sets of customized eFLASH actual verification environments, reduce the time and labor cost of verification, and improve the verification efficiency and verification quality.

[0040] In some embodiments, step S100 may include the following steps: Step S110: construct basic components in a basic verification environment. Step S120: construct adaptive components in the basic verification environment.

[0041] Basic components are the same components when verifying multiple chips of different specifications or different manufacturers, and do not need to be changed according to the configuration information of the chip to be tested. Adaptive components are different components when verifying multiple chips of different specifications or different manufacturers, and need to be modified according to the configuration information of the chip to be tested. For details, see Figure 2 The basic components include a reference model 11, a scoreboard 12 and a first bus agent 13, wherein the first bus agent 13 is configured to communicate with the chip to be tested 20, and the adaptive components include a test case list 14, a sequence list 15, a control task 16, a second bus agent 17 and a third bus agent 18, wherein the second bus agent 17 is configured to communicate with the reference model 11 and the chip to be tested 20 respectively, and the third bus agent 18 is configured to communicate with the scoreboard 12 and the chip to be tested 20 respectively.

[0042] The reference model 11 is configured to simulate the expected behavior or output of the chip under test, which provides a benchmark for comparison with the actual behavior or output of the chip under test 20 during the verification process.

[0043] The scoreboard 12 is a component for collecting, organizing and comparing test results. It is used to record various data of the reference model 11 and the chip to be tested 20 during the verification process, such as input, output and state changes, and compare the actual output of the chip to be tested 20 with the expected output of the reference model 11 to evaluate whether the test passes or not. It can also provide a detailed test result report to help testers understand problems and differences in the test process.

[0044] The first bus agent 13 may be an APB agent, which may serve as an interface between the verification environment 10 and the APB device. The APB agent may be used to convert transactions generated by the test sequence into signals on the APB bus and send them to the APB device (the chip to be tested 20), and is responsible for capturing signals on the APB bus and feeding them back to the verification environment 10. By setting up the APB agent, the verification environment 10 may be able to perform APB communication with the test chip 20, ensuring that test data can be accurately transmitted to the test chip 20, and receiving response data from the test chip 20.

[0045] The test case list 14 is a collection of multiple test cases, each of which defines a set of specific input conditions and expected output results.

[0046] The sequence list 15 is a list that defines the order in which the test cases are to be executed, and generally includes a series of identifiers or references of the test cases. The sequence list 15 ensures that the test cases can be executed in a predetermined order, thereby avoiding confusion and errors during the test process, optimizing the test process, and improving the test efficiency.

[0047] The control task 16 is a component specifically responsible for controlling the execution process of the test, managing the transmission of data, and collecting test results. The component is also integrated with the underlying driver code required in the verification process to support the execution of the test operation. Specifically, when the test involves the operation of the eFLASH memory, the control task 16 can output a control signal of a specific timing according to the requirements of the eFLASH manual through the built-in eFLASH underlying driver to realize the programming, erasing and reading operations of the FLASH. The eFLASH underlying driver has the permission access rights related to the eFLASH chip application, so that the verification environment can be allowed to perform eFLASH programming, erasing and reading operations on the eFLASH. In addition, the eFLASH underlying driver also includes a verification set for verifying the relevant characteristics of eFLASH programming, erasing and reading. In addition, the eFLASH underlying driver also has the function of interacting with the trim path, so as to read the chip configuration information stored in the FLASH for user use. In addition, the eFLASH underlying driver also supports A / B storage partitions, allowing the verification environment to perform independent read, write and erase operations on these two partitions, and verify the functions of A / B partition switching and updating.

[0048] The second bus agent 17 may include a first AHB agent or a first AXI agent, which may be used to convert the transaction generated by the test sequence into a signal on the AHB bus or the AXI bus, and send the signal to the reference model 11 and the chip to be tested 20, respectively. By setting the second bus agent 17, the verification environment 10 may be able to send the test case to the chip to be tested 20.

[0049] The third bus agent 18 may include a second AHB agent or a second AXI agent, which may be used to monitor signals on the AHB bus or the AXI bus and send the signals to the scoreboard 12. By setting the third bus agent 18, the scoreboard 12 may accurately obtain data output by the chip under test 20.

[0050] In this embodiment, by constructing basic components and adaptive components separately, the verification environment can be made more modular, so that each component can be independently developed and maintained, and the basic components constitute the core of the actual verification environment, which can provide the basic functions required for verifying the chip 20 to be tested. In addition, the adaptive components allow users to modify them according to the specifications and requirements of the specific chip, thereby improving the flexibility and scalability of the verification process.

[0051] In some of the embodiments, step S300 includes step S310: modifying the adaptive component based on the configuration information to obtain an actual verification environment.

[0052] The configuration information may include information such as the communication mode between the second bus agent and the chip to be tested, the communication mode between the third bus agent and the chip to be tested, the newly added test case, and the specification of eFLASH. It can be understood that the actual verification environment has the same structure as the basic verification environment, that is, it includes components such as a reference model, a scoreboard, a first bus agent, a test case list, a sequence list, a control task, a second bus agent, and a third bus agent. After obtaining the configuration information, the electronic device uses the configuration information to modify the components that need to be modified, and obtains the modified components, and integrates the modified components with the components that do not need to be modified to obtain the actual verification environment. For example, after obtaining the communication mode between the second bus agent and the chip to be tested, it can be determined whether the second bus agent in the actual verification environment adopts the first AHB agent in the basic verification environment or the first AXI agent in the basic verification environment. After obtaining the specification of eFLASH, the underlying driver code of the control task in the basic verification environment can be modified to obtain the underlying driver code of the control task in the actual verification environment. After obtaining the newly added test case, it can be added to the test case list of the basic verification environment to obtain the test case list of the actual verification environment.

[0053] In this embodiment, the actual verification environment can be flexibly constructed by dynamically modifying the adaptive components based on the configuration information. This flexibility enables the verification process to easily adapt to different test requirements, chip characteristics, and communication protocols, without having to build a verification environment from scratch for each test chip, thereby improving verification efficiency.

[0054] In some of the embodiments, step S400 includes step S410: executing a test on the chip to be tested based on a list of test cases in an actual verification environment.

[0055] The electronic device can use the script to start the test case list in the actual verification environment to complete the automatic test of the chip to be tested. Specifically, based on the sequence table in the actual verification environment, the electronic device can send the test case list in the actual verification environment to the reference model and the chip to be tested in the actual verification environment through the second bus agent in sequence, and then the reference model sends the expected output to the scoreboard in the actual verification environment. At the same time, the third bus agent collects the actual output of the chip to be tested and sends the actual output to the scoreboard. The scoreboard compares the actual output of the chip to be tested with the expected output of the reference model to evaluate whether the test passes or not.

[0056] After completing the test of the chip to be tested, a corresponding test report can be generated. Specifically, the format and required content of the test report can be determined in advance. The test report can usually include test results, error information, performance indicators, etc. In actual applications, the structure and data format of the test report can be defined according to project requirements. The data format of the test report can be a suitable format such as HTML format, PDF format or Excel format. After the test is completed, a script or tool can be used to automatically extract the necessary information from the test results, and automatically generate a test report based on a predefined test report template, reducing the workload of manual operations and the possibility of human errors, improving efficiency, saving time and energy; and the report template can be customized according to specific requirements, improving the flexibility of the test report format and content, and being able to adapt to the needs of different projects.

[0057] In this embodiment, the verification of the chip to be tested can be completed through the above method.

[0058] In some of the embodiments, step S400 further includes step S420: obtaining a new test case input by a user; and step S430: executing a test on the chip to be tested based on the new test case and an actual verification environment.

[0059] New test cases refer to test cases that are added or created based on the existing test case set according to the test requirements, functional changes, performance requirements or other test objectives of the chip to be tested. These new test cases are designed to cover code paths, functional points or performance scenarios that have not been tested or verified by the test cases in the basic verification environment, to ensure that the software or chip can work properly and meet the design requirements in more and more complex scenarios.

[0060] Specifically, if the user has a new test case requirement, the new test case can be input or uploaded through the user interface of the electronic device, so that the electronic device can obtain the new test case. Then, the electronic device sends the new test case to the reference model and the chip to be tested in the actual verification environment through the second bus agent. Then, the reference model sends the expected output to the scoreboard in the actual verification environment. At the same time, the third bus agent collects the actual output of the chip to be tested and sends the actual output to the scoreboard. The scoreboard compares the actual output of the chip to be tested with the expected output of the reference model to evaluate whether the test passes or not. A test report can be output based on the test results later.

[0061] In this embodiment, during verification, the user is allowed to add new test cases according to actual needs or functional changes without redesigning the entire verification environment, thereby improving the flexibility and efficiency of the verification process.

[0062] In a second aspect, the present application also provides a chip verification device, see Figure 3 The chip verification device 1000 includes: a first acquisition device 1100, a second acquisition device 1200, a modification device 1300 and a test device 1400. The first acquisition device 1100 is configured to acquire a pre-configured basic verification environment of the chip to be tested; the second acquisition device 1200 is configured to acquire configuration information of the verification environment of the chip to be tested; the modification device 1300 is configured to modify the basic verification environment based on the configuration information to obtain an actual verification environment; the test device 1400 is configured to test the chip to be tested according to the actual verification environment.

[0063] In some embodiments, the first acquisition device includes a first construction device and a second construction device, the first construction device is configured to construct basic components in a basic verification environment, the basic components include a reference model, a scoreboard and a first bus agent, wherein the first bus agent is configured to communicate with the chip to be tested; the second construction device is configured to construct adaptive components in the basic verification environment, the adaptive components include a test case list, a sequence list, a control task, a second bus agent and a third bus agent, wherein the second bus agent is configured to communicate with the reference model and the chip to be tested, respectively, and the third bus agent is configured to communicate with the scoreboard and the chip to be tested, respectively.

[0064] In some of the embodiments, the modification device is further configured to modify the adaptive component based on the configuration information to obtain an actual verification environment.

[0065] In some embodiments, the first bus agent is an APB agent, the second bus agent includes a first AHB agent or a first AXI agent, and the third bus agent includes a second AHB agent or a second AXI agent.

[0066] In some of the embodiments, the testing apparatus is further configured to execute testing on the chip to be tested based on a list of test cases in an actual verification environment.

[0067] In some of the embodiments, the testing device is further configured to obtain a new test case input by a user; and perform a test on the chip to be tested based on the new test case and an actual verification environment.

[0068] In a third aspect, the present application provides an electronic device, Figure 4 A hardware structure of the electronic device 30 is shown. Figure 4 The electronic device 30 includes a processor 31 and a memory 32, and the processor 31 and the memory 32 are connected via a line. Figure 4 In the embodiment shown, the processor 31 and the memory 32 are connected to each other through a bus. The memory 32 stores instructions that can be executed by the processor 31, and the instructions are executed by the processor 31 so that the processor 31 can perform the chip verification method described in any embodiment of the present application.

[0069] The memory 32 is used to store software programs, computer executable program instructions, etc. The memory 32 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the electronic device 30, etc.

[0070] The memory 32 may be a read-only memory 32 (ROM), or other types of static storage devices that can store static information and instructions, or a random access memory 32 (RAM), or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory 32 (EEPROM), and the specifics are not limited here.

[0071] Exemplarily, the aforementioned memory 32 may be a double rate synchronous dynamic random access memory 32. The memory 32 may exist independently but be connected to the processor 31. Optionally, the memory 32 may also be integrated with the processor 31. For example, integrated into one or more chips.

[0072] In some embodiments, the memory 32 may include a memory 32 remotely located relative to the processor 31, and these remote memories 32 may be connected to the electronic device 30 via a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0073] The processor 31 uses various interfaces and lines to connect various parts of the entire electronic device 30, and executes various functions and processes data of the electronic device 30 by running or executing software programs stored in the memory 32, and calling data stored in the memory 32, such as implementing the method described in any embodiment of the present application.

[0074] The processor 31 may be a field programmable gate array (FPGA), a digital signal processor (DSP), a central processing unit (CPU), or the like.

[0075] The processor 31 may be a single-core processor or a multi-core processor. For example, the processor 31 may be composed of multiple FPGAs or multiple DSPs. In addition, the processor 31 may refer to one or more devices, circuits and / or processing cores for processing data (e.g., computer program instructions). The processor 31 may be a separate semiconductor chip or may be integrated into a semiconductor chip together with other circuits. For example, it may form a system-on-a-chip (SoC) with other circuits (such as codec circuits, hardware acceleration circuits, or various buses and interface circuits), or it may be integrated into an application specific integrated circuit (ASIC) as a built-in processor of the ASIC. The ASIC with the integrated processor may be packaged separately or packaged together with other circuits.

[0076] The electronic device 30 can execute the method provided in the embodiment of the present application, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not described in detail in the present embodiment, please refer to the method provided in the embodiment of the present application.

[0077] In a fourth aspect, the present application also provides a chip verification system, see Figure 5 The chip verification system 100 includes: a chip to be tested 20, and an electronic device 30 as described in the third aspect; the chip to be tested 20 is electrically connected to the electronic device 30.

[0078] In this embodiment, the electronic device 30 has the same structure and function as the electronic device described in the third aspect, which will not be described in detail herein.

[0079] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable an electronic device to execute the chip verification method provided by the embodiment of the present application.

[0080] In some embodiments, the storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EE PROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or may be various devices including one or any combination of the above memories.

[0081] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0082] As an example, executable instructions may, but need not necessarily, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0083] As an example, executable instructions may be deployed to be executed on a computing device (including devices such as smart terminals and servers), or on multiple computing devices located in one location, or on multiple computing devices distributed in multiple locations and interconnected by a communication network.

[0084] In a sixth aspect, an embodiment of the present application further provides a computer program product, the computer program product comprising a computer program stored on a computer-readable storage medium, the computer program comprising program instructions, and when the program instructions are executed by a computer, the computer executes a chip verification method as in the aforementioned embodiment.

[0085] It should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0086] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions to use at least one computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as described above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip verification method, characterized in that: include: Obtain a pre-configured basic verification environment for the chip to be tested; Obtaining configuration information of the verification environment of the chip to be tested; Modify the basic verification environment based on the configuration information to obtain an actual verification environment; The chip to be tested is tested according to the actual verification environment.

2. The method according to claim 1, characterized in that The step of obtaining a pre-configured basic verification environment of the chip to be tested includes: Constructing basic components in the basic verification environment, wherein the basic components include a reference model, a scoreboard, and a first bus agent, wherein the first bus agent is configured to communicate with the chip to be tested; Construct an adaptive component in the basic verification environment, wherein the adaptive component includes a test case list, a sequence list, a control task, a second bus agent and a third bus agent, wherein the second bus agent is configured to communicate with the reference model and the chip to be tested, respectively, and the third bus agent is configured to communicate with the scoreboard and the chip to be tested, respectively.

3. The method according to claim 2, characterized in that The step of modifying the basic verification environment based on the configuration information to obtain an actual verification environment includes: The adaptive component is modified based on the configuration information to obtain the actual verification environment.

4. The method according to claim 2, characterized in that: The first bus agent is an APB agent, the second bus agent includes a first AHB agent or a first AXI agent, and the third bus agent includes a second AHB agent or a second AXI agent.

5. The method according to any one of claims 1 to 4, characterized in that: The testing of the chip to be tested according to the actual verification environment includes: Based on the test case list in the actual verification environment, the chip to be tested is tested.

6. The method according to claim 5, characterized in that The testing of the chip to be tested according to the actual verification environment further includes: Added new test cases for getting user input; The chip to be tested is tested based on the newly added test case and the actual verification environment.

7. A chip verification device, characterized in that: include: The first acquisition device is configured to acquire a pre-configured basic verification environment of the chip to be tested; The second acquisition device is configured to acquire configuration information of the verification environment of the chip to be tested; The modification device is configured to modify the basic verification environment based on the configuration information to obtain an actual verification environment; The testing device is configured to test the chip to be tested according to the actual verification environment.

8. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A chip verification system, characterized in that: include: A chip to be tested, and an electronic device as claimed in claim 8; The chip to be tested is electrically connected to the electronic device.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method according to any one of claims 1 to 6.

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