A memory and a method for testing the firmware downgrading time of the memory

Abstract

The present invention provides a memory and a method for testing the firmware download time of the memory, relating to the technical field of memories. The memory includes: a buffer for buffering the data to be tested written by a host; a flash memory module for receiving the data to be tested that continues to be written after the buffer is full; and a main control module for initializing the memory, and when the data to be tested is written into the buffer and after a preset delay time has passed, performing an initialization operation to determine whether the data to be tested is completely downloaded from the buffer to the flash memory module. If not, the preset delay time is reconfigured and the data to be tested is rewritten until the data to be tested is completely downloaded into the flash memory module. The memory provided by the present invention can implement the testing of the data download time of the firmware with the cache function enabled by means of step-by-step power-off after reading and writing.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and particularly to a memory and a method for testing the firmware download time of the memory. Background Art

[0002] MMC is the abbreviation of MultiMediaCard. Essentially, it is a memory card specification for solid-state non-volatile storage, defining various aspects such as the form factor, size, capacity, electrical signals, and communication protocol with the host of the card. eMMC is the abbreviation of "embedded multimedia controller", referring to a package composed of a flash memory and a flash memory controller integrated on the same silicon chip. The eMMC solution includes at least three components: an MMC (multimedia card) interface, a flash memory, and a flash memory controller. eMMC includes a controller and a NAND (i.e., negative-AND memory) chip, and has characteristics such as a unified and high-speed data interface, backward and forward compatibility, and high storage density. Cache is called a cache memory. The cache memory is a primary memory between the main memory and the CPU, composed of static storage chips (SRAM), with a relatively small capacity but much higher speed than the main memory, approaching the speed of the CPU.

[0003] Currently, many manufacturers' eMMC chips default to enabling the cache function to reduce the NAND download frequency and improve the product lifespan. However, during use, there will be SPOR (sudden power-off) tests, and it is easy to have problems such as data loss due to the inability to fully download data to the NAND. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a memory and a method for testing the firmware download time of the memory, which are used to solve the problem in the prior art that during the use of eMMC chips, there will be SPOR (sudden power-off) tests, and it is easy to have problems such as data loss due to the inability to fully download data to the NAND.

[0005] To achieve the above and other related objectives, the present invention provides a memory, comprising: a buffer for buffering the data to be tested written by a host; a flash memory module for receiving the data to be tested that continues to be written after the buffer is full; and a main control module for initializing the memory, and when the data to be tested is written to the buffer and after a preset delay time, performing an initialization operation to determine whether the data to be tested is completely flushed from the buffer to the flash memory module. If not, reconfiguring the preset delay time and rewriting the data to be tested until the data to be tested is completely flushed into the flash memory module; when the main control module performs the initialization operation, powering on the flash memory module again and reading back the written data that was flushed to the flash memory module before the previous power-off; when the main control module determines that the data to be tested is completely flushed from the buffer to the flash memory module, comparing whether the written data is consistent with the data to be tested. If the written data is consistent with the data to be tested, the flush is successful; if the written data is inconsistent with the data to be tested, the flush fails.

[0006] In an embodiment of the present invention, when the main control module determines that the data to be tested is completely flushed from the buffer to the flash memory module, it reconfigures the preset delay time to decrease sequentially, and uses the decreased preset delay time to perform the initialization operation after writing the data to be tested and to determine whether the data to be tested is completely flushed from the buffer to the flash memory module.

[0007] In an embodiment of the present invention, when the main control module reconfigures the preset delay time to decrease sequentially, it decreases the preset delay time sequentially according to the set self-decrement value and the number of self-decrement times.

[0008] In an embodiment of the present invention, when the main control module determines that the data to be tested cannot be completely flushed from the buffer to the flash memory module, as the number of self-decrement times decreases successively, it outputs the preset delay time corresponding to the previous self-decrement number before the data to be tested fails to be completely flushed for the first time as the shortest delay time.

[0009] In an embodiment of the present invention, when the main control module determines that the data to be tested is not completely flushed from the buffer to the flash memory module and reconfigures the preset delay time and rewrites the data to be tested, it reconfigures the preset delay time to increase sequentially, and uses the increased preset delay time to perform the initialization operation after writing the data to be tested and to determine whether the data to be tested is completely flushed from the buffer to the flash memory module.

[0010] In an embodiment of the present invention, when the main control module reconfigures the preset delay time to increase sequentially, it increases the preset delay time sequentially according to the set increment value and the number of self-increment times.

[0011] In one embodiment of the present invention, when the main control module determines that the data to be tested is completely downloaded from the buffer to the flash memory module, as the increment number increases successively, it outputs the delay preset time corresponding to the first complete download of the data to be tested to the flash memory module as the shortest delay time.

[0012] In one embodiment of the present invention, when the main control module initializes the memory, it sends various control instructions and the parameters corresponding to the control instructions to communicate with the flash memory module.

[0013] The present invention also provides a method for testing the firmware download time of a memory, including the following steps:

[0014] Receive the data to be tested written by the host and cache the data to be tested in the buffer;

[0015] Receive the data to be tested after the buffer is full and continue to write the data to be tested into the flash memory module;

[0016] Through the main control module, initialize the memory, and when the data to be tested is written to the buffer and after a delay preset time, perform the initialization operation;

[0017] Through the main control module, determine whether the data to be tested is completely downloaded from the buffer to the flash memory module. If not, reconfigure the delay preset time and rewrite the data to be tested until the data to be tested is completely downloaded to the flash memory module;

[0018] When the main control module performs the initialization operation, power on the flash memory module again and read back the write data downloaded to the flash memory module before the previous power-off;

[0019] When the main control module determines that the data to be tested is completely downloaded from the buffer to the flash memory module, compare whether the write data is consistent with the data to be tested. If the write data is consistent with the data to be tested, the download is successful; if the write data is inconsistent with the data to be tested, the download fails.

[0020] Advantages of the present invention: A memory and a method for testing the firmware download time of the memory proposed by the present invention can effectively use the step-by-step power-off method to test the data download time of the flash memory module with the buffer enabled, reducing data loss.

[0021] Of course, when implementing any product of the present invention, it is not necessarily required to achieve all the above advantages at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic connection structure diagram of the main control module Host (host) and the eMMC chip of the present invention.

[0023] Figure 2It is a schematic structural diagram of the memory of the present invention.

[0024] Figure 3 It is a flowchart of the firmware downgrading time test method for the memory of the present invention.

[0025] Figure 4 For the present invention Figure 3 It is a step schematic diagram of steps S3 and S4 in the present invention.

[0026] Figure 5 Provided by a preferred embodiment of the present invention Figure 3 It is a specific step schematic diagram of step S4 in the present invention.

[0027] Element number description

[0028] Host 10; Memory 20; Buffer 21; Flash module 22; Main control module 23. Specific implementation manners

[0029] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0030] It should be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0031] In the following description, a large number of details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0032] Please refer to Figure 1 , Figure 1Schematic diagram of the connection structure between the Host main control module and the flash memory module in an embodiment of the present invention. The flash memory module can use an eMMC chip. The eMMC chip has a total of 11 buses, namely CMD (Command), DATA0-7, CLK, and Data Strobe. Among them, CMD is a single-line bidirectional transmission, that is, it is used for the Host main control module to send commands to the eMMX and for the eMMC to send corresponding Responses to the Host main control module. In one clock cycle, both the CMD and DATA0-7 signals can support the transmission of 1 bit, that is, the SDR (Single Data Rate) mode. In addition, the DATA0-7 signals also support being configured in the DDR (Double Data Rate) mode, and 2 bits can be transmitted in one clock cycle. The Host main control module can dynamically adjust the frequency of the clock signal during communication. By adjusting the clock frequency, functions such as power saving or data flow control (to avoid Over-run or Under-run) can be achieved. In some scenarios, the Host main control module can also turn off the clock, for example, when the eMMC is in the Busy state or when it enters the Programming State after receiving data. The DATA0-7 signals are mainly used for data transmission between the Host main control module and the eMMC. After the eMMC is powered on or soft reset, only DATA0 can perform data transmission. After initialization, DATA0-3 or DATA0-7 can be configured for data transmission, that is, the data bus can be configured in 4 bits or 8 bits mode. The DataStrobe (a data transmission encoding method) clock signal is sent from the eMMC to the Host, and its frequency is the same as the CLK signal, and is used for synchronization of data reception at the Host side. The CLK signal is used to output the clock signal from the Host main control module side for synchronization of data transmission and driving of device operation. The Data Strobe signal can only be configured and enabled in the HS400 (a multi-chip package memory) mode. After being enabled, it can improve the stability of data transmission and eliminate the bus tuning process.

[0033] Please refer to Figures 1 to 5, a memory and a method for testing the firmware download time of the memory provided by the present invention can be applied to solid-state storage fields such as eMMC (Embedded Multi Media Card), UFS (Universal Flash Storage), and SDD (Solid State Disk). The present invention can use a step-by-step power-off method to effectively test the data download time of the flash memory module when the memory test enables the buffer, reducing data loss. The following is a detailed description through specific embodiments.

[0034] Please refer to Figure 2 , the present invention provides a memory 20, including a buffer 21, a flash memory module 22, and a main control module 23. The buffer 21 is used to cache the data to be tested written by the host 10. The flash memory module 22 is used to receive the data to be tested that continues to be written after the buffer 21 is full. The main control module 23 is used to initialize the memory 20 and, when the data to be tested is written to the buffer 21 and after a preset delay time has passed, perform an initialization operation. The main control module 23 is also used to determine whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22. If not, it reconfigures the preset delay time and rewrites the data to be tested until the data to be tested is completely downloaded to the flash memory module 22.

[0035] In an embodiment of the present invention, the main control module 23 is the control center of the memory 20, responsible for controlling the writing of the data to be tested sent by the host 10 into the flash memory module 22 and for reading the data in the flash memory module 22. Specifically, when the data to be tested is written into the flash memory module 22, the data to be tested will first be cached in the buffer 21. After the buffer 21 is full, the data to be tested continues to be written into the flash memory module 22. During this process, the main control module 23 will initialize the memory 20 before writing the data to be tested into the flash memory module 22 and then write the data to be tested. When writing the data to be tested, it is first written into the buffer 21. By setting a preset delay time and starting from when the data is written into the buffer 21, after this preset delay time, the memory 20 is initialized again. Then, the main control module 23 reads the data in the flash memory module 22 and determines whether the data to be tested has been completely downloaded from the buffer 21 to the flash memory module 22. And by continuously adjusting this preset delay time and rewriting the data to be tested, the data to be tested can be completely downloaded from the buffer 21 to the flash memory module 22.

[0036] Please refer to Figure 2, in an embodiment of the present invention, before writing the data to be tested into the flash memory module 22, it is necessary to initialize the memory 20 through the main control module 23. When the data to be tested is written into the buffer 21, after a preset delay time, it is also necessary to initialize the memory 20 through the main control module 23. Specifically, when the main control module 23 initializes the memory, it sends a variety of control instructions and the corresponding parameters of the control instructions to communicate with the flash memory module 22. For example, the main control module 23 will send the cmd0+0 instruction to the flash memory module 22 to reset the device (eMMC flash chip), where "cmd0" is the control instruction and the other "0" after the "+" is the parameter corresponding to the control instruction.

[0037] When the main control module 23 performs the initialization operation, it powers on the flash memory module 22 again and reads back the write data that was flushed to the flash memory module 22 before the previous power-off; when the main control module 22 determines that the data to be tested is completely flushed from the buffer 21 to the flash memory module 22, it compares whether the write data is consistent with the data to be tested. If the write data is consistent with the data to be tested, the flush is successful; if the write data is inconsistent with the data to be tested, the flush fails.

[0038] In an embodiment of the present invention, when the data to be tested is written into the buffer 21, it will automatically power off at the time node when the preset delay time ends according to the set preset delay time. After the power-off, the data to be tested buffered in the buffer 21 is lost. Subsequently, the flash memory module 22 is powered on again. And after the flash memory module 22 is powered on again after completing the initialization, the write data that was flushed from the buffer 21 to the flash memory module 22 before the power-off is read back. Since the length of the preset delay time will affect the integrity of the data to be tested when it is flushed to the flash memory module 22. That is to say, when the set preset delay time is short, when the data to be tested is written into the buffer 21, there may be a situation where it cannot be completely flushed to the flash memory module 22. Therefore, in this case, it is easy to cause the write data written in the flash memory module 22 to be inconsistent with the data to be tested. The main control module 23 will further judge whether the data to be tested is completely flushed from the buffer 21 to the flash memory module 22 according to this situation. That is, after the power-on again, by comparing the write data read back from the flash memory module 22 with the data to be tested originally written into the buffer 21 for consistency, when the two are consistent, it means that the data to be tested has been completely flushed from the buffer 21 to the flash memory module 22, or the flush is successful. Otherwise, it means that the data is incomplete when the data to be tested is flushed from the buffer 21 to the flash memory module 22, or the flush fails.

[0039] In an embodiment of the present invention, when the main control module 23 determines whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22, there are two cases where the initially set delay preset time is greater than or less than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22. That is to say, there are two cases for the initially set delay preset time. One is that when the main control module 23 determines that the data to be tested cannot be completely downloaded from the buffer 21 to the flash memory module 22, it means that the delay preset time can be greater than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22. The other is that when the main control module 23 determines that the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22, it means that the delay preset time can also be less than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22.

[0040] When the main control module 23 determines that the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22, it indicates that the initially set delay preset time for downloading is greater than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22. On the contrary, when the initially set delay preset time for downloading is greater than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22, the main control module 23 will first determine that the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22. Specifically, when the main control module 23 determines that the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22, it reconfigures to sequentially reduce the delay preset time, and uses the reduced delay preset time to perform the initialization operation after writing the data to be tested, and to determine whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22.

[0041] In an embodiment of the present invention, at the beginning of downloading, there will be a case where the preset delay time is greater than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22. After the main control module 23 confirms that the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22, it will continue to reconfigure the delay preset time to sequentially reduce the delay preset time. And then perform the write test of the data to be tested again with the sequentially reduced delay preset time. The specific write test is as follows: write the data to be tested into the buffer 21, and after the sequentially reduced delay preset time, perform the initialization operation. After the flash memory module 23 is powered on again, read back the written data in the flash memory module 23. And compare the written data with the data to be tested to determine again whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22.

[0042] At the beginning of the downward writing, the preset delay time will be greater than the time when the data to be measured is just completely written from the buffer 21 to the flash memory module 22, and it is necessary to further sequentially reduce the preset delay time according to whether the data to be measured is completely downward written from the buffer 21 to the flash memory module 22. When the main control module 23 reconfigures and sequentially reduces the preset delay time, the preset delay time is sequentially reduced according to the set self-decrement value and the number of self-decrement times. In this embodiment, it can be set to sequentially decrease from the first initial extended preset time → 0. The self-decrement value and the number of self-decrement times are used to reduce the preset delay time, that is, the reduced preset delay time is obtained.

[0043] When using the set self-decrement value and the number of self-decrement times to reduce the preset delay time, the data to be measured will have a situation where the data to be measured cannot be completely downward written from the buffer 21 to the flash memory module 22 when the number of self-decrement times . When the main control module 23 determines that the data to be measured cannot be completely downward written from the buffer 21 to the flash memory module 22, as the number of self-decrement times decreases successively, the preset delay time corresponding to the previous self-decrement number before the data to be measured cannot be completely downward written to the flash memory module 22 for the first time is output as the shortest delay time.

[0044] In an embodiment of the present invention, when the main control module 23 reduces the preset delay time according to the number of self-decrement times and the self-decrement value , assuming that the number of self-decrement times is , it causes the data to be measured to not be completely downward written into the flash memory module 22 for the first time. The preset delay time corresponding to this first failure to complete the downward writing . At the previous self-decrement number before this first failure to complete the downward writing, it corresponds to the situation where the data to be measured can be completely downward written to the flash memory module 22 for the last time. Then, the preset delay time for the last time when the data to be measured can be completely downward written to the flash memory module 22 can be obtained, and this is used as the shortest delay time for the data to be measured to be completely downward written from the buffer 21 to the flash memory module 22.

[0045] When the main control module 23 determines that the data to be tested is not completely downloaded from the buffer 21 to the flash memory module 22, it indicates that the initially set delay preset time is less than the time for the data to be tested to be just completely written from the buffer 21 to the flash memory module 22. Conversely, when the initially set delay preset time is less than the time for the data to be tested to be just completely written from the buffer 21 to the flash memory module 22, the main control module 23 will first determine that the data to be tested is not completely downloaded from the buffer 21 to the flash memory module 22. Specifically, when the main control module 23 determines that the data to be tested is not completely downloaded from the buffer 21 to the flash memory module 22 and reconfigures the delay preset time and rewrites the data to be tested, it reconfigures the delay preset time to increase it in sequence, and uses the increased delay preset time to perform the initialization operation after writing the data to be tested, and to determine whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22. When the main control module 23 determines that the data to be tested is not completely downloaded from the buffer 21 to the flash memory module 22, the corresponding Figure 5 specific process in which the main control module 23 controls the delay preset time to increase sequentially in steps S41 to S47.

[0046] In an embodiment of the present invention, at the beginning of the download, the preset delay time may be less than the time for the data to be tested to be just completely written from the buffer 21 to the flash memory module 22. After the main control module 23 confirms that the data to be tested is not completely downloaded from the buffer 21 to the flash memory module 22, it will continue to reconfigure the delay preset time to increase the delay preset time in sequence. And then re - execute the write test of the data to be tested through the sequentially increased delay preset time. The specific write test is as follows: Write the data to be tested into the buffer 21, and after the sequentially increased delay preset time, perform the initialization operation. After the flash memory module 23 is powered on again, read back the written data in the flash memory module 23. And compare the written data with the data to be tested to determine again whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22.

[0047] At the beginning of the download, the preset delay time may also be less than the time for the data to be tested to be just completely written from the buffer 21 to the flash memory module 22, and it is necessary to further increase the delay preset time in sequence according to whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22. When the main control module 23 reconfigures the delay preset time to increase it in sequence, it increases the delay preset time in sequence according to the set increment value and the number of self - increments. In this embodiment, it can be set to increase sequentially from the second initial extended preset time → The increment value and the number of self - increments can be set to increase the delay preset time, that is, to obtain the increased delay preset time . Among them, represents a value greater than Extended time limit value

[0048] When using the set auto - increment value and the number of auto - increments to increase the delay preset time, the data to be tested will reach a situation where the data to be tested can be completely downloaded from the buffer 21 to the flash memory module 22 when the number of auto - increments is reached. When the main control module 23 determines that the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22, as the number of auto - increments increases successively, it outputs the delay preset time corresponding to the first complete download of the data to be tested to the flash memory module 22 as the shortest delay time

[0049] In an embodiment of the present invention, when the main control module 23 increases the delay preset time according to the number of auto - increments and the auto - increment value , assuming the number of auto - increments is , the data to be tested can be first completely downloaded into the flash memory module 22. The delay preset time corresponding to this first successful download , and this is used as the shortest delay time for the complete download of the data to be tested from the buffer 21 to the flash memory module 22

[0050] As Figure 3 shown, the present invention also provides a method for testing the firmware download time of a memory 20, including the following steps

[0051] Step S1: Receive the data to be tested written by the host 10 and cache the data to be tested in the buffer 21

[0052] Step S2: Receive the data to be tested after the buffer 21 is full and continue to write the data to be tested into the flash memory module 22

[0053] Step S3: Through the main control module 23, initialize the memory 20, and when the data to be tested is written into the buffer 21 and after a delay preset time, perform the initialization operation

[0054] Step S4: Through the main control module 23, determine whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22. If not, re - configure the delay preset time and rewrite the data to be tested until the data to be tested is completely downloaded into the flash memory module 22

[0055] Step S1: Receive the data to be tested written by the host 10 and cache the data to be tested in the buffer

[0056] In an embodiment of the present invention, when the host 10 writes the data to be tested into the flash memory module 22, it will first be cached in the buffer 21. The data to be tested can be one or more data packets

[0057] Step S2: Receive the data to be tested after the buffer 21 is full, and continue to write the data to be tested into the flash memory module 22.

[0058] In an embodiment of the present invention, during the process of writing data into the buffer 21, after the buffer 21 is full, it will be further written from the buffer 21 into the flash memory module 22.

[0059] Step S3: Through the main control module 23, initialize the memory 20, and when the data to be tested is written into the buffer 21 and after a preset delay time, perform the initialization operation.

[0060] In an embodiment of the present invention, when the host 10 writes the data to be tested into the flash memory module 22, it will be first cached in the buffer 21. Therefore, starting from when the buffer 21 starts caching, after recording the preset delay time, power off the memory 10, and then power on to perform the initialization. While clearing the cache in the buffer 21, if there is data written from the buffer 21 into the flash memory module 22, the corresponding data written into the flash memory module 22 can be further read after power on.

[0061] Step S4: Through the main control module 23, determine whether the data to be tested is completely downloaded from the buffer 21 to the flash memory module 22. If not, reconfigure the preset delay time and rewrite the data to be tested until the data to be tested is completely downloaded to the flash memory module 22.

[0062] In an embodiment of the present invention, after a preset delay time and performing the initialization operation, that is, after the flash memory module 22 is powered on again, by reading whether there is complete data to be tested in the flash memory module 22. If there is no complete data to be tested, it means that the download from the buffer 21 to the flash memory module 22 is not completed. Or the initially configured preset delay time is not sufficient to achieve the complete download of the data to be tested to the flash memory module 22. Therefore, it is necessary to re-adjust and configure the preset delay time so that the download amount of the buffer 21 to the flash memory module 22 continuously increases until the configured preset delay time can satisfy the complete download of the data to be tested to the flash memory module 22.

[0063] Please refer to Figure 4 In a preferred embodiment given, the present invention also provides a step-by-step test method for the download time of the cache on (buffer open state) firmware based on the flash memory chip eMMC. As in the above step S3, it specifically includes the following steps:

[0064] Steps S301 - S310: The main control module Host initializes the eMMC chip;

[0065] Step S311: Prepare the data packet of the data to be tested and prepare to write it into the eMMC chip;

[0066] Step S312: After the Host issues a write command to write data into the eMMc chip, power off after a certain delay (execution pause).

[0067] Specifically, in steps S301 to S310:

[0068] Step S301: Power on the XU4 main control and power on the eMMc flash chip;

[0069] Step S302: The XU4 issues cmd0+0 to reset the device (eMMC flash chip);

[0070] Step S303: The XU4 issues cmd1+0x40FF8080;

[0071] Step S304: The XU4 issues cmd2+0x40FF8080 to obtain the CID;

[0072] Step S305: The XU4 issues cmd3+RCA;

[0073] Step S306: The XU4 issues cmd9+RCA to obtain the CSD register;

[0074] Step S307: The XU4 issues cmd13+RCA to obtain the current state RCA and obtain the current state;

[0075] Step S308: The XU4 issues cmd7+RCA to perform the select card action;

[0076] Step S309: The XU4 issues cmd13+RCA to obtain the current state;

[0077] Step S310: The XU4 issues cmd6+arg to set the transfer timing (memory timing) and buswidth (width of the data bus).

[0078] In steps S301 to S310, XU4 is the control card specifically used by the Host. After the main control module and the eMMC chip are powered on, the eMMC chip receives the cmd0+0 command sent by the main control module and performs a reset operation. Through cmd0+0, the eMMC chip enters the Idle state (i.e., the idle state). Then it receives the cmd1+0x40ff8080 command sent by the main control module. The parameter 0x40ff8080 of this command represents the voltage value to be used by the main control module. After receiving this command, the eMMC chip will return the response data R3 (a kind of register). If the busy bit in R3 is 0, it means the eMMC chip is not ready yet, and the main control module will repeatedly send cmd1 and wait for the eMMC chip to return ready. After the main control module receives the ready data of the eMMC chip, it continues to send the cmd2+0x40ff8080 command. After receiving this command, the eMMC chip will feedback the Device Identification (CID). After receiving the CID, the main control module will dynamically allocate a Relative device address (RCA) for the eMMC chip according to the CID, and transmit the allocated relative device address to the eMMC chip through the command cmd3+RCA. Specifically, after obtaining the relative device address according to the foregoing command sent by the main control module, according to the cmd9+RCA command sent by the main control module, the Device-specific-data (CSD) of the eMMC chip is sent to the CMD bus. The CSD register stores device-specific data, including information such as device operating conditions. Further, according to the cmd13+RCA command sent by the main control module Host, the eMMC sends the status register to the CMD bus, and the main control module Host can determine the current state of the eMMC chip according to the status register. Since the main control module Host can be connected to multiple eMMC chips at the same time, after obtaining the current state of the eMMC chip, the main control module Host can send the cmd7+ RCA command to select the eMMC chip through the current RCA. After completing the chip selection, the cmd13+RCA command is sent again, and the selected eMMC chip returns its current state. When the current state of the eMMC chip meets the requirements, the main control module Host sends the cmd6+arg (arg represents a parameter) command, and sets the initial data transfer rate and the bus bandwidth buswidth of data transfer through this command. Thus, the entire initialization process of the eMMC chip is completed.

[0079] Step S4 includes the following steps:

[0080] Step S401: After powering on, re-run S301 to S310, read back the just-written data and compare it;

[0081] Step S402: Determine whether the data comparison between the data to be measured and the written data passes;

[0082] Step S4021: If the data comparison passes, it indicates that the device has successfully flushed the data within the delay time;

[0083] Step S4022: If the data comparison fails, it indicates that the device has not successfully flushed the data within the delay time.

[0084] Please refer to Figure 5 In a preferred embodiment given below, specifically when performing step S4, the following steps are as follows:

[0085] Step S41: XU4 initializes the eMMC chip with a series of CMDs;

[0086] Step S42: Enter a cycle (the cycle value starts from 0) loop, prepare the data packet to be measured, and prepare to write it into the eMMC chip;

[0087] Step S43: After the Host issues a write command to write the data into the eMMC chip, delay for T ms (at the ms level, T starts from 0 with power off);

[0088] Step S44: After powering on, re - execute S41, read back the data just written and compare it;

[0089] Step S45: Determine whether the data comparison passes;

[0090] Step S451: If the data comparison passes, it indicates that the device has successfully flushed the data within the delay time;

[0091] Step S452: If the data comparison fails, it indicates that the device has not successfully flushed the data within the delay time;

[0092] Step S46: Record the result of S44, increment the T value by 1, and increment the cycle value by 1;

[0093] Step S47: Return to S42 until the cycle value is incremented to 1000.

[0094] In summary, the present invention proposes a memory and a method for testing the firmware flushing time of the memory, which can effectively test the data flushing time of the flash memory module when the memory test enables the buffer by using the step - by - step power - off method, and reduce data loss.

[0095] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: A buffer, used for caching the data to be tested written by the host; A flash memory module, used for receiving the data to be tested which is continuously written after the buffer is full; as well as A main control module, used to initialize the memory, and when the data to be tested is written into the buffer and after a preset delay time, perform an initialization operation to determine whether the data to be tested is completely flushed from the buffer to the flash memory module, and if not, reconfigure the preset delay time and rewrite the data to be tested until the data to be tested is completely flushed to the flash memory module; When the main control module performs the initialization operation, the flash memory module is powered on again, and the written data flushed to the flash memory module before the last power failure is read back; When the main control module determines whether the data to be tested is flushed from the buffer to the flash memory module, it compares whether the written data is consistent with the data to be tested. If the written data is consistent with the data to be tested, the flushing is successful; if the written data is inconsistent with the data to be tested, the flushing fails.

2. The memory according to claim 1, characterized in that: When the main control module determines that the data to be tested is completely flushed from the buffer to the flash memory module, it reconfigures the delay preset time to be reduced in sequence, and uses the reduced delay preset time to perform the initialization operation after the data to be tested is written, and to determine whether the data to be tested is completely flushed from the buffer to the flash memory module.

3. The memory according to claim 2, characterized in that: When the main control module is reconfigured to sequentially reduce the preset delay time, the preset delay time is sequentially reduced according to the set self-decrement value and the number of self-decrement times.

4. The memory according to claim 3, characterized in that: When the main control module determines that the data to be tested cannot be completely flushed from the cache to the flash memory module, as the self-decrement times decrease successively, it outputs a preset delay time corresponding to the last self-decrement times before the data to be tested could not be completely flushed to the flash memory module for the first time as the shortest delay time.

5. The memory according to claim 1, characterized in that: The main control module determines that the data to be tested is not completely flushed from the buffer to the flash memory module, and reconfigures the delay preset time. When the data to be tested is rewritten, the delay preset time is reconfigured to increase in sequence, and the increased delay preset time is used to perform the initialization operation after the data to be tested is written, and to determine whether the data to be tested is completely flushed from the buffer to the flash memory module.

6. The memory according to claim 5, characterized in that: When the main control module is reconfigured to sequentially increase the preset delay time, the preset delay time is sequentially increased according to the set increment value and the number of self-increment times.

7. The memory according to claim 6, characterized in that: When the main control module determines that the data to be tested is completely flushed from the buffer to the flash memory module, as the self-increment times increase successively, the delay preset time corresponding to the first complete flush of the data to be tested to the flash memory module is output as the shortest delay time.

8. The memory according to claim 1, characterized in that: When the main control module initializes the memory, it sends a variety of control instructions and parameters corresponding to the control instructions to communicate with the flash memory module.

9. A method for testing the firmware flash time of a memory, characterized in that: The steps include: Receiving the data to be tested written by the host, and buffering the data to be tested in a buffer; receiving the data to be tested after the buffer is full, and continuing to write the data to be tested into the flash memory module; Initializing the memory through the main control module, and performing an initialization operation when the data to be tested is written into the buffer and after a preset delay time; By means of the main control module, it is determined whether the data to be tested is completely flushed from the buffer to the flash memory module; if not, the preset delay time is reconfigured, and the data to be tested is rewritten until the data to be tested is completely flushed to the flash memory module; When the main control module performs the initialization operation, the flash memory module is powered on again, and the written data flushed to the flash memory module before the last power failure is read back; When the main control module determines whether the data to be tested is flushed from the buffer to the flash memory module, it compares whether the written data is consistent with the data to be tested. If the written data is consistent with the data to be tested, the flushing is successful; if the written data is inconsistent with the data to be tested, the flushing fails.

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