A method for improving the yield and reliability of a multi-stack flash memory packaging process

Abstract

The present application relates to chip packaging technical field, specifically a kind of method for improving the yield of multi-layer flash memory packaging process and product reliability.The method comprises the following steps: S1, a plurality of chips are misaligned and stacked;S2, adjacent chips are bonded by wire, and the solder pad and the wire form a solder joint;S3, the wire is optically inspected to observe whether there is foreign matter contamination at the solder joint;S4, if there is foreign matter contamination, the connection between the solder joint and the upper and lower chip pads is damaged, and step S5 is performed, if there is no foreign matter contamination, then the next process is performed;S5, optical inspection is performed again to confirm that the solder joint with foreign matter contamination has been completely isolated.Compared with the prior art, the upper and lower connections of a single defective solder joint are cut off in the packaging process, and the entire package is avoided. All the flash memory chips installed are scrapped, thereby improving the yield of the packaging process.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, in particular to a method for improving the process yield and product reliability of multi-layer flash memory packaging. Background Art

[0002] Currently, 3D flash memory packaging involves stacking multiple flash memory chips and bonding them to a substrate or PCB. Wire bonding is then used to complete the electrical connections between the flash memory chips in each layer and between the chips and the pads on the substrate or PCB. This multi-layer flash memory chip stacking method can achieve high-capacity integration in a single package.

[0003] However, as the number of stacked layers increases, the number of bond wires also increases, and the probability of bond failure increases accordingly. Contamination between the bond wires and the pads on the chip is irreparable. If a solder joint is detected as connected during subsequent electrical testing and deemed defective, there is a reliability risk to the subsequent use of the product. The current industry standard is to declare it defective, but this results in the loss of all flash memory chips in the package, reducing the yield of the packaging process. Summary of the Invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a method for improving the process yield and product reliability of multi-layer flash memory packaging.

[0005] To achieve the above objectives, a method for improving the process yield and product reliability of multi-layer flash memory packaging is designed, comprising the following steps:

[0006] S1, stacking several chips in a staggered manner;

[0007] S2, adjacent chips are bonded by wire bonding, and solder joints are formed between the chip pads and the wire bonding wires;

[0008] S3, perform optical inspection on the welding wire to observe whether there is any foreign matter contamination at the welding point;

[0009] S4, if there is foreign matter contamination, destroy the connection between the solder joint and the upper and lower chip pads, and proceed to step S5; if there is no foreign matter contamination, proceed to the next process;

[0010] S5, perform optical inspection again to confirm that the solder joints contaminated by foreign matter have been completely isolated.

[0011] In the step S4, the welding wires connected to the upper and lower welding points contaminated by foreign objects are removed by mechanical shearing or laser ablation.

[0012] The specific method of mechanical shearing or laser ablation is as follows: use a micro-gripper to clamp the middle of the weld wire arc on one side of the weld spot contaminated by foreign objects, use micro-scissors to cut or laser ablate the weld wire arc, so that 80% of the length of the entire weld wire arc falls off and is removed with a micro-gripper, and then the same treatment is performed on the weld wire arc on the other side of the weld spot.

[0013] In step S5, if the solder joint contaminated by foreign matter is not completely isolated, step S4 is repeated until the solder joint is completely isolated.

[0014] The chip is a flash memory chip.

[0015] The bottom chip is bonded to the substrate or PCB through bonding wires.

[0016] Compared with the prior art, the present invention cuts off the upper and lower connections of a single bad solder joint during the packaging process, thereby preventing all mounted flash memory chips in the entire package from being scrapped, thereby improving the packaging process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. 4 is a schematic diagram of the stacked chips of the present invention.

[0018] Figure 2 It is a schematic diagram of destroying the connection between the solder joint and the upper and lower chip pads of the present invention. DETAILED DESCRIPTION

[0019] The present invention will be further described below with reference to the accompanying drawings.

[0020] like Figures 1 to 2 As shown, the method for improving the process yield and product reliability of multi-layer flash memory packaging in this embodiment includes the following steps:

[0021] S1, stacking several chips 1 in a staggered manner;

[0022] S2, adjacent chips 1 are bonded by bonding wires 2, and solder joints 3 are formed between the chip pads and the bonding wires 2;

[0023] S3, optically inspect the welding wire 2 to see if there is any foreign matter contamination at the welding point 3;

[0024] S4, if there is foreign matter contamination, destroy the connection between the solder joint 3 and the upper and lower chip 1 pads, and proceed to step S5, if there is no foreign matter contamination, proceed to the next process;

[0025] S5, perform optical inspection again to confirm that the solder joint 3 contaminated by foreign matter has been completely isolated.

[0026] In step S4, the solder wires 2 connected to the upper and lower solder joints 3 contaminated by foreign matter are removed by mechanical shearing or laser ablation. The solder joints contaminated by foreign matter are cut off to prevent them from being judged as connected in subsequent electrical tests.

[0027] The mechanical shearing or laser ablation method is as follows: a micro-gripper is used to grasp the middle of the arc of weld wire 2 on one side of weld joint 3 contaminated with foreign matter. Micro-scissors are used to cut or laser ablate the arc of weld wire 2, cutting off 80% of the entire arc of weld wire 2. The micro-gripper is then used to remove the arc of weld wire 2. The same process is then repeated on the arc of weld wire 2 on the other side of weld joint 3. This embodiment utilizes mechanical shearing or laser ablation to destroy and remove the weld wire, which is simple to operate, easy to process, and low in cost.

[0028] In step S5, if the solder joint 3 contaminated by foreign matter is not completely isolated, step S4 is repeated until the solder joint 3 is completely isolated, thereby ensuring that the solder joint 3 contaminated by foreign matter is completely cut off from the upper and lower chips 1.

[0029] The chip 1 is a flash memory chip. The bottom chip 1 is bonded to a substrate or a PCB 4 via bonding wires 2.

[0030] This statement solves the problem of products with foreign object contaminated solder joints experiencing reliability failure at user terminals after passing electrical performance testing. It also solves the problem of products with foreign object contaminated solder joints being judged as poor overall and resulting in the loss of multi-layer flash memory chips, thereby improving the packaging process yield and product reliability.

Claims

1. A method for improving the process yield and product reliability of multi-layer flash memory packaging, characterized by: The steps include: S1, stacking several chips (1) in an offset manner; S2, adjacent chips (1) are bonded via bonding wires (2), and solder joints (3) are formed between chip pads and bonding wires (2); S3, optically inspecting the welding wire (2) to observe whether there is any foreign matter contamination at the welding point (3); S4, if there is foreign matter contamination, destroy the connection between the solder joint (3) and the upper and lower chip (1) pads, and proceed to step S5; if there is no foreign matter contamination, proceed to the next process; S5, perform optical inspection again to confirm that the solder joint (3) contaminated by foreign matter has been completely isolated; In the step S4, the welding wires (2) connected to the upper and lower parts of the welding points (3) contaminated by foreign matter are removed by mechanical shearing or laser ablation.

2. The method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 1, characterized in that: The specific method of mechanical shearing or laser ablation is as follows: use a micro-gripper to clamp the middle of the arc of the welding wire (2) on one side of the welding point (3) contaminated with foreign matter, use micro-scissors to cut or laser ablate the arc of the welding wire (2), so that 80% of the length of the entire arc of the welding wire (2) falls off and is removed with the micro-gripper, and then the same treatment is performed on the arc of the welding wire (2) on the other side of the welding point (3).

3. The method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 1, characterized in that: In the step S5, if the solder joint (3) contaminated by foreign matter is not completely isolated, step S4 is repeated until the solder joint (3) is completely isolated.

4. The method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 1, characterized in that: The chip (1) is a flash memory chip.

5. The method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 1 or 4, characterized in that: The bottommost chip (1) is bonded to the substrate or PCB (4) via a welding wire (2).

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