Package substrate and manufacturing method thereof

Abstract

Implementations of the invention relate to a package substrate and a method of manufacturing the same. A package substrate according to an embodiment includes a core layer including: a glass substrate including a first surface and a second surface facing each other; and two or more cavity parts that open in the direction of the first surface or the direction of the second surface and have different depths from each other. As a result, various types of cavity elements are mounted substantially without bending.

Description

Technical Field

[0001] The present embodiment relates to a packaging substrate and a method for manufacturing the packaging substrate, and more specifically, to a packaging substrate including a glass substrate and a method for manufacturing the same. Background Art

[0002] In the manufacture of electronic components, the process of realizing circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling wafers into a state that can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0003] Recently, the four core technologies in the semiconductor industry that enable the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms such as line widths of nanometer units below microns, more than tens of millions of cells, high-speed operation, and large amounts of heat dissipation, but there is no relatively perfect packaging technology to back it up. Therefore, compared to the performance of semiconductor technology itself, the electrical performance of semiconductors is also determined by packaging technology and its electrical connections.

[0004] Ceramic or resin is currently used as a material for a package substrate. However, research is recently underway to use silicon or glass as a package substrate for high-end use. In particular, a package substrate having a cavity structure is being developed by using a glass substrate.

[0005] On the other hand, the redistribution layer (RDL) in the packaging process is a general term for a technology that uses the wafer level package (WLP) process technology to change the position of an already formed electrical terminal (e.g., an aluminum pad) to an arbitrary position. This RDL is used as a method of eliminating design limitations in the semiconductor manufacturing process through packaging, that is, it is being applied to the stacking of semiconductor chips.

[0006] As related prior arts, there are U.S. Patent Publication US20230162992A1, Korean Patent Publication 10-2014-0082305, and the like. Summary of the invention

[0007] Problem that the invention aims to solve

[0008] An object of an implementation example is to provide a packaging substrate and a method for manufacturing the same, in which undulation occurring when mounting various types of components is alleviated in a glass substrate and a packaging substrate in which a plurality of components are mounted on the glass substrate.

[0009] In addition, an object of an implementation example is to provide a package substrate having cavities of various depths arranged in accordance with the design of components having various heights, and a method for manufacturing the same.

[0010] In addition, an object of the implementation example is to form a flat insulating layer on a glass substrate and to form a flat upper layer on the insulating layer.

[0011] Means used to solve problems

[0012] In order to achieve the above-mentioned purpose, according to an implementation example, a packaging substrate includes a core layer, and the core layer includes: a glass substrate, including a first surface and a second surface facing each other; and more than two cavity portions, having an opening portion, and the opening portion is open in the direction of the first surface or the second surface of the glass substrate.

[0013] The two or more cavity portions have different depths from each other.

[0014] The packaging substrate may include: a cavity element arranged in the cavity portion and including two or more individual elements having different heights from each other; and an insulating layer disposed on a surface of the glass substrate where the opening portion is formed and sunken into the cavity portion.

[0015] The cavity portion may include: a first cavity portion, which is open and recessed toward the first surface and has a first depth; and a second cavity portion, which is open and recessed toward the first surface or the second surface and has a second depth. The second depth is greater than the first depth.

[0016] At this time, the cavity element may include: a first cavity element arranged in the first cavity portion; and a second cavity element arranged in the second cavity portion.

[0017] One or more connection electrodes may be disposed on the first cavity element, and one or more connection electrodes may be disposed on the second cavity element.

[0018] According to another example, the cavity portion includes: a first cavity portion, which is open and recessed toward the first surface and has a first depth; a second cavity portion, which is open and recessed toward the first surface and has a second depth; and a third cavity portion, which has a third depth that passes through the first surface and the second surface. The second depth may be greater than the first depth.

[0019] A first cavity element may be arranged in the first cavity portion, a second cavity element may be arranged in the second cavity portion, and a third cavity element may be arranged in the third cavity portion.

[0020] One or more connection electrodes may be arranged on the first cavity element. One or more connection electrodes may be arranged on the second cavity element. One or more connection electrodes may be arranged on the third cavity element in the direction of the first surface.

[0021] One or more connection electrodes are arranged on the third cavity element toward the second surface.

[0022] One or more connection electrodes are respectively arranged on the third cavity element in two directions of the first surface and the second surface.

[0023] In order to achieve the above-mentioned purpose, a method for manufacturing a packaging substrate according to an implementation example may include: a defect forming step, preparing a glass substrate including a first surface and a second surface facing each other, and forming a plurality of defects of different degrees on the first surface or the second surface; and a cavity forming step, forming two or more cavity portions with different depths by etching the glass substrate.

[0024] The method for manufacturing the package substrate may further include an arrangement step and an insulation layer formation step after the cavity forming step.

[0025] The arranging step is a step of arranging a plurality of cavity elements in the cavity portion. The insulating layer forming step is a step of forming an insulating layer on a surface of the cavity portion where an opening is formed.

[0026] The plurality of cavity elements disposed in the cavity portion may have different heights from each other.

[0027] The cavity portion includes a first cavity portion and a second cavity portion, the first cavity portion is open and recessed in the direction of the first surface, and has a first depth; the second cavity portion is open and recessed in the direction of the first surface or the direction of the second surface, and has a second depth greater than the first depth.

[0028] The cavity element includes a first cavity element and a second cavity element. The first cavity element is arranged in the first cavity portion, and the second cavity element is arranged in the second cavity portion.

[0029] The method for manufacturing the package substrate may further include a connection electrode forming step.

[0030] The connection electrode forming step may be a step for forming one or more connection electrodes connected to the first cavity element and one or more connection electrodes connected to the second cavity element.

[0031] According to another example, the cavity portion includes a first cavity portion, a second cavity portion and a third cavity portion.

[0032] The first cavity portion is open and recessed toward the first surface and has a first depth.

[0033] The second cavity portion is open and recessed toward the first surface or the second surface, and has a second depth that is greater than the first depth.

[0034] The third cavity portion passes through the first surface and the second surface and has a third depth.

[0035] The cavity element may include: a first cavity element, a second cavity element and a third cavity element.

[0036] The first cavity element may be arranged in the first cavity portion.

[0037] The second cavity element may be arranged in the second cavity portion.

[0038] The third cavity element may be arranged in the third cavity portion.

[0039] The method for manufacturing the package substrate may further include a connection electrode forming step.

[0040] The connection electrode forming step may be a step for forming one or more connection electrodes connected to the first cavity element, one or more connection electrodes connected to the second cavity element, and one or more connection electrodes connected to the third cavity element.

[0041] In the connection electrode forming step, connection electrodes may be formed on two or more surfaces of the third cavity element, respectively.

[0042] Effects of the Invention

[0043] According to the package substrate and the manufacturing method thereof of the implementation example, it is possible to alleviate undulation that may occur when mounting various types of components.

[0044] An implementation example may provide a packaging substrate including a core layer having an overall flat surface while mounting components having various heights within a glass substrate.

[0045] In an implementation example, a core layer having a substantially flat surface can be provided by a structural feature of a cavity portion having various heights, and utilizing this feature, a packaging substrate having a substantially flat insulating layer and / or upper layer formed on the packaging substrate can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The exemplary embodiments are described in detail with reference to the accompanying drawings, so that the above and other objects, features and advantages of the present disclosure will be more apparent to those skilled in the art.

[0047] Figure 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an implementation example.

[0048] Figure 2 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another implementation example.

[0049] Figure 3 Parts (a) and (b) of FIG. 1 are conceptual diagrams illustrating a portion of a package substrate of each implementation example using a cross section.

[0050] Figure 4 1 is a flow chart for explaining, using a cross section, a process of generating a core distribution layer in a process of manufacturing a package substrate according to an implementation example.

[0051] Figure 5 The flowchart uses a cross section to explain a process of generating an insulating layer in a manufacturing process of a package substrate according to an implementation example.

[0052] Figure 6 Parts (a) to (c) of FIG. 1 are diagrams illustrating a portion of a package substrate according to an implementation example using a cross section.

[0053] Figure 7 Parts (a) to (c) of FIG. 1 are cross-sectional views of a portion of a packaging substrate according to another implementation example.

[0054] Figure 8 It is a flowchart illustrating the manufacturing process of the packaging substrate according to the implementation example using a cross section, S1 is a defect forming step, S2 is a cavity forming step, S3 is an arrangement step, S4 is an insulating layer forming step, and S5 is a connection electrode forming step.

[0055] Description of Reference Numerals

[0056] 100: Semiconductor devices

[0057] 10: Motherboard 20: Package substrate

[0058] 30: semiconductor element portion 32: first semiconductor element

[0059] 34: second semiconductor element 36: third semiconductor element

[0060] 21, 21a: Glass substrate 22: Core layer

[0061] 223: Core insulation

[0062] 23: Core through hole 24: Core distribution layer

[0063] 241: Core distribution pattern

[0064] 26: Upper layer 28: Cavity

[0065] 281: Internal space 282: Cavity distribution layer

[0066] 29a: first cavity 29b: second cavity

[0067] 29c: Third cavity

[0068] 213: First side 214: Second side

[0069] 25: Upper distribution layer 251: Upper distribution pattern

[0070] 253: Upper insulation layer

[0071] 27: Upper connection layer 271: Upper connection electrode

[0072] 272: Connection pattern above

[0073] 40: Cavity element 42: Connection electrode

[0074] 40a: first cavity element 40b: second cavity element

[0075] 40c: Third cavity element

[0076] 60: Cover layer 61a: Insulating film

[0077] 61, 63: Insulation layer DETAILED DESCRIPTION

[0078] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings so that those with common knowledge in the technical field to which the embodiments belong can easily implement them. However, the present invention can be implemented in various forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are given the same reference numerals.

[0079] Throughout this specification, the term "combination of these" included in the Markush form expression refers to a mixture or combination of one or more selected from the group consisting of the constituent elements described in the Markush form expression, and means that one or more selected from the group consisting of the constituent elements is included.

[0080] Throughout this specification, terms such as "first", "second" or "A", "B" etc. are used to distinguish the same terms from each other. In addition, unless otherwise clearly defined in the text, singular expressions include plural expressions.

[0081] In the present specification, "~" may refer to a compound containing a compound corresponding to "~" or a derivative of "~".

[0082] In this specification, disposing B on A means disposing B in direct contact with A or disposing B on A with another layer between A and B, and is not limited to disposing B in contact with the surface of A.

[0083] In this specification, connecting B on A means that A and B are directly connected or connected through other components. Unless otherwise specified, it is not limited to the direct connection between A and B.

[0084] In this specification, unless otherwise specified, an expression in the singular number is interpreted as including the singular or plural number explained in the text.

[0085] During the process of developing semiconductor devices that can achieve high performance with greater integration and thinner thickness, the inventors realized that in addition to the components themselves, the packaging part is an important factor in improving performance, and conducted research on this. In the process, they confirmed that unlike existing interposers and organic substrates, which use cores with more than two layers as packaging substrates on a mother board, methods such as using a single-layer glass core and a cavity structure can help make the packaging substrate thinner and improve the electrical characteristics of the semiconductor device.

[0086] Components that perform various functions can be installed in the cavity structure of the glass substrate, thereby making the overall thickness of the package substrate thinner. The multiple components installed in the cavity structure have various sizes and thicknesses (heights) depending on the type. Therefore, when the same cavity structure is applied, undulation may occur due to the height difference of the components, that is, defects such as bending or high and low fluctuations may occur. This bending affects the thinness of the package substrate and may weaken the electrical characteristics.

[0087] Based on this, as a result of repeated studies, it was confirmed that when forming a cavity structure for mounting a component on a glass substrate, the bending phenomenon can be improved by adjusting the etching degree in consideration of adjusting the height (thickness) or size of the component, thereby completing the present invention.

[0088] Figure 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an implementation example; Figure 2 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another implementation example; Figure 3 Parts (a) and (b) of FIG. 1 are conceptual diagrams illustrating a portion of a package substrate of each implementation example using a cross section.

[0089] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to the implementation example includes: a semiconductor element portion 30, including one or more semiconductor elements 32, 34, 36; a packaging substrate 20, electrically connected to the semiconductor element; and a motherboard 10, electrically connected to the packaging substrate 20, and transmitting external electrical signals to the semiconductor elements 32, 34, 36.

[0090] According to an implementation example, the package substrate 20 includes: a core layer 22 , an upper layer 26 and a cavity portion 28 . The upper layer 26 is located on a surface of the core layer 22 , and the cavity element 40 may be located in the cavity portion 28 .

[0091] The semiconductor element portion 30 refers to an element mounted on a semiconductor device, and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, computing elements (first element 32, second element 34) such as a CPU, a GPU, etc., memory elements (third element 36) such as a memory chip, etc., can be applied as the semiconductor element portion 30, but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0092] As the motherboard 10, a motherboard such as a printed circuit board or a printed wiring board can be used.

[0093] The package substrate 20 may further include a lower layer (not shown) that is selectively located below the core layer 22 .

[0094] The core layer 22 may include: a glass substrate 21 including a first region 221 and a second region 222, wherein the first region 221 has a first thickness 211, and the second region 222 is adjacent to the first region 221 and has a second thickness 212, wherein the second thickness 212 is smaller than the first thickness 211; a plurality of core vias 23 penetrating the glass substrate 21 along the thickness direction of the glass substrate 21; a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23, and electrically connecting the first surface 213 and the second surface 214 of the glass substrate 21 through the core vias 23, wherein the second surface 214 faces the first surface 213. That is, the core layer 22 includes the glass substrate 21, the core vias 23, the cavity 28, or all of them, wherein the glass substrate 21 includes the first surface 213 and the second surface 214 facing each other.

[0095] The second region 222 of the core layer 22 may function as a cavity structure.

[0096] In the same region, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, so that the two surfaces are substantially parallel to each other, and thus the glass substrate 21 has a predetermined thickness as a whole.

[0097] The internal space 281 is formed by the difference in thickness between the first region 221 and the second region 222 , and serves to accommodate a part or the entirety of the cavity element 40 .

[0098] The glass substrate 21 may include a core through hole 23, and the core through hole 23 passes through the first surface 213 and the second surface 214. The core through holes 23 may be formed entirely in the first region 221 and the second region 222, and may be formed in a desired pitch and pattern.

[0099] As a packaging substrate for semiconductor devices, the prior art uses a stacked silicon substrate and an organic substrate. In the case of a silicon substrate, due to the semiconductor characteristics, there is a concern about the generation of parasitic elements when applied to high-speed circuits, and there is a disadvantage of relatively large power loss. In addition, in the case of an organic substrate, a larger area is required when forming a more complex distribution pattern, but this does not conform to the manufacturing trend of ultra-miniaturized electronic devices. In order to form a complex distribution pattern within a set size, the pattern actually needs to be refined, but due to the material properties of polymers and other materials used for organic substrates, there are actually limitations in the refinement of the pattern.

[0100] In the implementation example, as a method for solving these problems, the glass substrate 21 is used as a support body for the core layer 22. In addition, by using the core through hole 23 formed by penetrating the glass substrate 21 together with the glass substrate 21, a package substrate 20 having characteristics of further shortening the length of current flow, further miniaturization, faster response and less loss is provided.

[0101] The glass substrate 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but is not limited thereto.

[0102] The core through hole 23 passes through the glass substrate 21. The core through hole 23 may be formed by removing a predetermined region of the glass substrate 21, and specifically, may be formed by etching the plate glass by a physical and / or chemical method.

[0103] Specifically, in the process of forming the core through hole 23, a defect (imperfection) may be formed on the surface of the glass substrate 21 by laser or the like, and then chemical etching, laser etching, etc. may be applied, but the present invention is not limited thereto.

[0104] The number of the core through holes 23 may be 100 to 3,000, 100 to 2,500, or 225 to 1,024 based on the unit area (1 cm x 1 cm) of the glass substrate 21. When such a spacing condition is met, a conductive layer can be formed and the performance of the package substrate can be improved.

[0105] The core distribution layer 24 includes a core distribution pattern 241 as a conductive layer and a core insulation layer 223. The core distribution pattern 241 electrically connects the first surface 213 and the second surface 214 of the glass substrate 21 through a through hole, and the core insulation layer 223 surrounds the core distribution pattern 241. The core layer 22 forms a conductive layer through the core through hole 23 inside, thereby playing the role of an electrical channel across the glass substrate 21, and connecting the upper and lower parts of the glass substrate 21 at a relatively short distance, so as to have the characteristics of faster transmission of electrical signals and low loss. For example, the conductive layer can be applied with a copper plating layer, but is not limited to this.

[0106] The shape of the cavity 28 can be substantially circular, triangular, quadrilateral, hexagonal, octagonal, cross-shaped, etc., and there is no limitation on the shape.

[0107] The shape of the cavity element 40 can be substantially cylindrical, rectangular hexahedral or polygonal.

[0108] The cavity portion 28 may include a cavity allocation pattern as a conductive layer, the cavity allocation pattern electrically connecting the cavity element 40 with the core allocation layer 24 , and an insulating layer surrounding the cavity allocation pattern.

[0109] On the other hand, the cavity portion 28 according to another embodiment may be implemented in a form that penetrates the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion 28 may be formed by the same process as the core through hole 23, and the area and shape of the cavity portion 28 that penetrates the glass substrate 21 may be different from those of the core through hole 23.

[0110] In this embodiment, the insulating layer may be formed after the cavity element 40 is disposed in the cavity portion 28. That is, the insulating layer may also be formed in the cavity portion 28 through the process of forming the core insulating layer 223 described above.

[0111] The core distribution pattern 241 may be formed to be electrically connected to the cavity member 40 .

[0112] The cavity element 40 may include an active element such as a transistor or a power transmission element such as a multi-layer ceramic capacitor (MLCC), that is, a passive element.

[0113] When an element such as a transistor that converts an electrical signal between a motherboard and a semiconductor element portion into an appropriate level is used as the cavity element 40, a transistor or the like is applied to a path of the packaging substrate 20, thereby providing a semiconductor device 100 with greater efficiency and higher speed.

[0114] In addition, power transmission elements such as multilayer ceramic capacitors (MLCC) play an important role in the performance of semiconductor elements. Power transmission elements as passive elements are usually used in semiconductor elements at least 200, and the characteristics of the conductive layer around the element in terms of power transmission are also affected by the performance. In one implementation example, a core through hole of a non-circular shape can be used with such a power transmission element in the part where the conductive layer needs low resistance.

[0115] On the other hand, passive components such as capacitors can be individually inserted and applied in the cavity component 40, and a component group including a plurality of passive components can also be formed in a manner of exposing electrodes and then inserted into the cavity component. In the latter case, the operability of manufacturing the package substrate can be made smoother, and it is more conducive to positioning the insulating layer in the space between the complex components with high reliability.

[0116] The glass substrate 21 plays an intermediate role and a mediating role in connecting the semiconductor element part 30 and the motherboard 10 at its upper and lower parts respectively, and the core through hole 23 plays a role as a channel for transmitting these electrical signals, thereby realizing smooth transmission of signals.

[0117] The upper layer 26 is arranged on the first surface 213 .

[0118] The upper layer 26 includes an upper distribution layer 25 and an upper connection layer 27. The upper connection layer 27 is located on the upper distribution layer 25. The uppermost surface of the upper layer 26 can be protected by a covering layer 60. An opening portion is formed in the covering layer 60, which can directly contact the connection electrode of the semiconductor element part 30.

[0119] The upper distribution layer 25 includes: an upper insulating layer 253 located on the first surface 213 ; an upper distribution pattern 251 , which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24 and is built into the upper insulating layer 253 .

[0120] The upper insulating layer 253 may be any material as long as it is used as an insulating layer in a semiconductor element or a package substrate, for example, epoxy resin containing a filler may be used, but the present invention is not limited thereto.

[0121] The insulator layer may be formed by forming a coating and curing the coating, or by laminating an uncured or semi-cured thin film of the insulator on the core layer 22 and curing the thin film. In this case, if a reduced pressure lamination method is used, the insulator is embedded in the space inside the core through hole 23, and the process can be performed efficiently.

[0122] According to an implementation example, even if multiple insulator layers are stacked and applied, it may be difficult to distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 may use the same insulating material. In this case, the boundary may be substantially indistinguishable. Alternatively, according to another implementation example, the boundary of the insulator layer may be generated by setting the pressure and temperature used to cure the multiple insulator layers to be different.

[0123] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined form, and can be formed, for example, by a build-up layer method. Specifically, an insulating layer is formed, and after removing unnecessary portions of the insulating layer, a conductive layer is formed by copper plating or the like, and after selectively removing unnecessary portions of the conductive layer, an insulating layer is re-formed on the conductive layer, and after re-removing the unnecessary portions, a conductive layer is formed by gold plating, and this method is repeated to form the upper distribution pattern 251 in which the conductive layer is formed in a desired pattern in a vertical or horizontal direction.

[0124] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, in order to smoothly transmit electrical signals with the semiconductor element portion 30 and to fully accommodate the desired complex pattern, at least a portion of the upper distribution pattern 251 includes a fine pattern. In this case, the fine pattern refers to a width and a pitch of less than 4 μm, less than 3.5 μm, less than 3 μm, less than 2.5 μm, or 1 μm to 2.3 μm, respectively (hereinafter, the same description of the fine pattern).

[0125] At least a portion of the upper connection layer 27 is electrically connected to the upper distribution pattern 251. The upper connection layer 27 includes an upper connection pattern 272 and an upper connection electrode 271. The upper connection pattern 272 is located on the upper insulating layer 253. The upper connection electrode 271 electrically connects the semiconductor element portion 30 to the upper connection pattern 272. The upper connection pattern 272 may also be located on a surface of the upper insulating layer 253. At least a portion of the upper connection pattern 272 may also be exposed on the upper insulating layer 253 and embedded in the upper insulating layer 253. For example, in the case where the upper connection pattern 272 is located on a surface of the upper insulating layer 253, the upper insulating layer 253 may be formed by gold plating or the like. In the case where a portion of the upper connection pattern 272 is exposed on the upper insulating layer 253 and embedded in the upper insulating layer 253, a portion of the insulating layer or the conductive layer may be removed by surface grinding, surface etching or the like after forming a copper plating layer or the like.

[0126] At least a portion of the upper connection pattern 272 may include a fine pattern together with the upper distribution pattern 251 described above. In this way, the upper connection pattern 272 including the fine pattern can electrically connect more components even in a narrow area, thereby making it possible to more smoothly connect electrical signals between components or with the outside, thereby achieving a more integrated package.

[0127] The upper surface connection electrode 271 and the semiconductor element portion 30 may be directly connected via a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball.

[0128] The cavity portion 28 is located above and / or below the second region 222. Then, the cavity portion 28 includes a cavity distribution layer 282 and an inner space 281. The cavity distribution layer 282 is electrically connected to the core distribution pattern 241. The cavity element 40 is disposed in the inner space 281.

[0129] Specifically, in the second region 222, the thickness of the glass substrate 21 is smaller than the thickness of the glass substrate 21 in the first region 221, and the cavity element 40 may be located in the inner space 281 formed by the thickness difference. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass substrate 21 function as an electrical connection structure for connecting the cavity element 40 with external elements.

[0130] In addition, a cavity portion penetrating the first surface 213 and the second surface 214 of the glass substrate 1 may be generated in the glass substrate 1 , and the cavity elements 40 may be arranged in the cavity portion 28 .

[0131] The package substrate 20 is also connected to the motherboard 10. The motherboard 10 can be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 through a terminal or the like, and the motherboard 10 can also be electrically connected through a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 in contact with the motherboard 10 can also be connected to the motherboard 10 through a lower layer (not shown) located at the lower part of the core layer 22.

[0132] According to an example, in addition to the glass substrate 21 , other additional substrates may not be substantially used in the packaging substrate 20 located between the semiconductor device portion 30 and the motherboard 10 .

[0133] In the past, an interposer and an organic substrate were stacked together and used to connect the components to the motherboard. It is understood that this multi-level form is used for at least two reasons, one of which is that there is a scale problem when directly bonding the fine pattern of the component to the motherboard, and the other reason is that the wiring may be damaged due to the difference in thermal expansion coefficient during the bonding process or the driving process of the semiconductor device. In the implementation example, a glass substrate with a thermal expansion coefficient similar to that of the semiconductor element is used, and a fine pattern with a small scale sufficient to mount the component is formed on the first surface and the upper layer of the glass substrate to solve these problems.

[0134] Hereinafter, a method for manufacturing a package substrate according to an implementation example of the present invention will be described.

[0135] Figure 4 and Figure 5 This is a flow chart illustrating a manufacturing process of a package substrate according to an implementation example using a cross section.

[0136] First, if Figure 4 As shown in part (a), a glass substrate 21a having a flat first surface and a flat second surface is prepared, and a defect (discontinuity) 21b is formed on the glass surface at a predetermined position in order to form a core through hole. The glass substrate can be a glass substrate suitable for a substrate of an electronic device, for example, an alkali-free glass substrate, but is not limited thereto. As commercial products, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. In the process of forming the defect (discontinuity), mechanical etching, laser irradiation, etc. can be used.

[0137] like Figure 4As shown in part (b), an etching step is performed on the glass substrate 21a formed with the defect 21b to form the core through hole 23 through a physical or chemical etching process. During the etching process, a through hole is formed in the defective portion of the glass substrate 21a, and the surface of the glass substrate 21a may also be etched. In order to prevent such etching of the glass surface, a masking film or the like may also be applied. However, considering the trouble of removing the masking film after applying it, the glass substrate itself with the defect may be etched. In this case, the thickness of the glass substrate with the core through hole may be somewhat smaller than the thickness of the initial glass substrate.

[0138] After this, if Figure 4 As shown in parts (c) and (d) of FIG. 2 , a conductive layer 21d is formed on the glass substrate 21a, and then a core layer manufacturing step can be performed. For the conductive layer, a metal layer containing copper metal can be used, but it is not limited thereto.

[0139] The surface properties of glass (including the surface of the glass substrate and the surface of the core through hole) are different from those of copper metal, so the adhesion is low. In the implementation example, the adhesion between the glass surface and the metal can be improved by two methods, a dry method and a wet method.

[0140] The dry method is a method suitable for sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter surface of the core through hole by sputtering a metal. In the process of forming the seed layer 21c, different types of metals such as titanium, chromium, and nickel can be sputtered together with copper. In this case, the glass-metal adhesion can be improved by the anchoring effect of the interaction between the surface morphology of the glass and the metal particles.

[0141] Wet mode is the mode of primer treatment, is to utilize the compound substance with the functional group of amine etc. to carry out pretreatment, forms the mode of primer coating 21c thus.According to the degree of desired adhesion, utilize silane coupling agent to carry out pretreatment, can utilize compound or particle with amine functional group to carry out primer treatment afterwards.As mentioned above, the support substrate of realization example needs to have the high performance of the degree that can be enough to form fine pattern, and also should keep this high performance after primer treatment.Accordingly, when this primer comprises nanoparticle, preferably be applicable to have the nanoparticle of the size below 150nm with average diameter, for example, the particle with amino group preferably uses nanoparticle.Give an example, the bonding strength improver that the CZ series etc. of described primer coating can be applied MEC company forms.

[0142] For the seed layer / undercoat layer 21c, the conductive layer can selectively form a metal layer to be in a state where the conductive layer is removed or not removed. In addition, for the seed layer / undercoat layer 21c, the part that needs or does not need to form a conductive layer can be selectively processed into an activated or inactivated state in the gold plating, and then the subsequent process can be carried out. For example, the activation or inactivation treatment can be treated with light irradiation treatment of a predetermined wavelength, chemical treatment, etc. The formation of the metal layer can use the copper plating method used in the manufacture of semiconductor elements, but is not limited to this.

[0143] like Figure 4 As shown in part (e), a portion of the core distribution layer can be removed when the portion is not needed, and gold plating is performed after a portion of the seed layer is removed or inactivated, thereby forming a conductive layer in a predetermined pattern, thereby also forming an etching layer 21e of the core distribution layer.

[0144] Figure 5 The manufacturing steps of forming an insulating layer and an upper distribution pattern are described according to an implementation example.

[0145] like Figure 5 As shown in part (a) of the embodiment of the present invention, the core through hole may be subjected to an insulating layer forming step, in which the hollow space is filled with an insulating layer after forming a core distribution layer as the conductive layer. At this time, the applicable insulating layer may be an insulating layer manufactured in the form of a thin film, for example, a method of laminating an insulating layer in the form of a thin film by reduced pressure, etc. If reduced pressure lamination is performed in this way, the insulating layer is fully embedded in the hollow space inside the core through hole, and the core insulating layer can be formed without gaps.

[0146] exist Figure 5 Parts (b) to (e) of FIG. 1 illustrate the upper layer manufacturing steps.

[0147] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming an insulating layer 23a or a laminated insulating film (film), and it is preferable to simply use a laminated insulating film. The lamination of the insulating film can be carried out by laminating the insulating film and curing the insulating film. At this time, if a reduced pressure lamination method is adopted, the insulating resin can also be fully immersed in the layer where the conductive layer is not formed inside the core through hole. The upper insulating layer is also directly in contact with the glass substrate in at least a portion, so it is suitable to have a layer with sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have a characteristic of an adhesion test value of more than 4B according to ASTM D3359 test.

[0148] The upper distribution pattern is formed by repeatedly forming the insulating layer 23a and forming the conductive layer 23c in a predetermined pattern and then etching the unnecessary part to form the etching layer 23d of the conductive layer. In the case of conductive layers formed adjacent to each other with the insulating layer in between, the blind through hole 23b can be formed in the insulating layer and then subjected to a gold plating process. The blind through hole 23b can be formed by dry etching such as laser etching and plasma etching, and wet etching using a mask layer and an etching solution.

[0149] After that, although not shown, an upper connection layer and a cover layer may be formed.

[0150] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the formation of the upper distribution layer. Specifically, the upper connection pattern and the upper connection electrode can be formed by forming an etching layer of the insulating layer on the insulating layer 23e and then forming an etching layer of the conductive layer thereon, but it is also possible not to use the etching method, but to use a method of selectively forming only the conductive layer. The covering layer can be formed to form an opening (not shown) at a position corresponding to the upper connection electrode to expose the upper connection electrode, and can be directly connected to the element connection part or the terminal of the element.

[0151] If the upper layer is generated, the lower connection layer and the covering layer are formed, and the process of forming the lower layer can be performed. The lower distribution layer and / or the lower connection layer can be formed in a similar manner to the upper connection layer and the covering layer formation steps described above, and the covering layer (not shown) can be selectively formed.

[0152] According to the implementation example, when a plurality of components are mounted on the glass substrate 21, the cavities 29a and 29b of different heights may be generated in consideration of the design of the components (ie, the positions where the components are arranged or the areas or heights of the components).

[0153] Figure 6 Parts (a) to (c) of FIG. 1 are diagrams illustrating a portion of a package substrate according to an implementation example using a cross section.

[0154] like Figure 6 As shown in part (a) of FIG. 2 , according to an implementation example, a first cavity portion 29a having a first depth h1 and a second cavity portion 29b having a second depth h2 may be formed on the glass substrate 21. The first cavity portion 29a and the second cavity portion 29b may all be open toward the first surface 213 and recessed.

[0155] The second depth h2 may be greater than the first depth h1. A cavity element portion having a height corresponding to the depth of the first cavity portion 29a may be arranged in the first cavity portion 29a, and a cavity element portion having a height corresponding to the depth of the second cavity portion 29b may be arranged in the second cavity portion 29b. At this time, the height corresponding to A refers to a height substantially the same as or smaller than the height of A, and does not exclude the meaning of a height greater than the height of A at a level that can be covered by an upper layer, etc. (the same applies below). One or more cavity elements 40a, 40b may be arranged in the cavity element portion. Arranged and molded individual cavity elements may be arranged in the cavity element portion. Alternatively, one or more cavity elements molded using insulating materials, etc. may be arranged in the cavity element portion.

[0156] Although the cavity element portion of the first cavity portion 29a and the cavity element portion of the second cavity portion 29b are different in height from each other, the upper insulating layer 61 formed on the first cavity portion 29a and the second cavity portion 29b may be formed substantially flat without being bent.

[0157] Furthermore, although the heights of the first cavity element 40a and the second cavity element 40b are different from each other, the upper insulating layer 61 formed on the first cavity element 40a and the second cavity element 40b may be substantially formed flat without being bent.

[0158] The insulating layer may be formed by laminating an insulating film for semiconductor such as ABF (Ajinomoto Build-up Film) manufactured by Ajinomoto Co., Ltd. under reduced pressure, but the invention is not limited thereto.

[0159] Due to the characteristics of the insulating material manufactured into a predetermined shape (for example, a thin film shape), during the formation of the insulating layer, the deep and wide space where the insulating material is to be configured is the cause of the uneven surface of the insulating layer. In particular, when it is required to immerse the insulating material in a space wider than the usual through hole and form a cavity structure of the insulating layer, severe bending (UNDULATION) may occur.

[0160] According to an implementation example, the depth of the cavity portion is formed to be different to correspond to the depth of the cavity element, thereby solving this problem.

[0161] A portion of the upper insulating layer 61 is embedded in the first cavity 29a and the second cavity 29b, and the surface of the upper insulating layer 61 can be substantially flatly stacked on the first surface 213. Since the depths of the first cavity 29a and the second cavity 29b are different from each other, the first surface 213 of the glass substrate 21 can be formed to be relatively flat.

[0162] A lower insulating layer 63 may also be formed on the second surface 214 of the glass substrate 21 , that is, on the lower portion of the glass substrate 21 .

[0163] On the other hand, one or more connection electrodes 42 may be arranged on the first surface 213 side of the first cavity element 40 a , and one or more connection electrodes 42 may be arranged on the second cavity element 40 b on the first surface 213 side.

[0164] The connection electrode 42 may be arranged or formed in the direction of the opening of the first cavity 29a and the second cavity 29b, for example, arranged or formed on the first surface 213. The connection electrode 42 may be electrically connected to an upper layer (not shown) disposed on the upper part of the glass substrate 21.

[0165] The connection electrode 42 may be formed as a part of the electrodes of the first cavity element 40 a and the second cavity element 40 b , or may be formed or connected to the distribution electrode of the upper layer, or may be configured in a form including both.

[0166] In another implementation example, the first cavity portion 29a and the second cavity portion 29b can be opened and recessed in the direction of the second surface 214 of the glass substrate 21, rather than in the direction of the first surface 213. In this case, the connection electrode can be configured or formed to contact the first cavity portion 29a and the second cavity portion 29b in the direction of the second surface 214. That is, one of the technical features of the present invention is that cavities with different depths are generated in the glass substrate 21, and the cavities can adopt various opening shapes.

[0167] In addition, the first surface 213 and the second surface 214 of the glass substrate 21 refer to two surfaces facing each other, and are not limited to any specific surface. The cavity portion is open to the first surface and recessed, which can be interpreted as opening to any one of the two surfaces facing each other of the glass substrate 21.

[0168] In another implementation example, Figure 6 As shown in part (b) of FIG. 1 , the core layer 22 may include: a second cavity portion 29b that is open and recessed toward the first surface 213 and has a second depth h2; and a third cavity portion 29c that has a third depth h3 that passes through the first surface 213 and the second surface 214 of the glass substrate 21. The third depth h3 is the same as the height of the glass substrate 21 and is greater than the second depth h2 of the second cavity portion 29b that is recessed only toward one side.

[0169] That is, according to the implementation example, a part of the cavity portions having different depths may be opened in one direction of the glass substrate 21 , and another part may penetrate the glass substrate 21 .

[0170] In the third cavity element 40c mounted in the third cavity portion 29c penetrating the glass substrate 21, the connection electrode 42 may be arranged or formed on the upper surface facing the first surface 213 and the bottom surface facing the second surface 214. That is, in the case of the third cavity element 40c penetrating the glass substrate 21, one or more connection electrodes may be arranged in the direction (second surface 214) facing the connection electrode formed on the first surface 213 with the third cavity element 40c interposed therebetween.

[0171] The connection electrode 42 may be electrically connected to the upper layer and supply power to the semiconductor chip, and may be electrically connected to the lower layer and connected to the motherboard.

[0172] According to another implementation example, Figure 6 As shown in part (c), the opening directions of the plurality of half cavities formed by opening in one direction and being recessed in the glass substrate 21 can be different from each other. For example, the first cavity 29a opens to the first surface 213, and the second cavity 29b can open to the second surface 214.

[0173] As shown in the figure, the first depth h1 of the first cavity portion 29a and the second depth h2 of the second cavity portion 29b are different from each other. According to one example, the second depth h2 may be greater than the first depth h1. Of course, the first depth h1 may also be greater than the second depth h2.

[0174] In an implementation example, the connection electrode 42 in contact with the first cavity element 40 a may be electrically connected to the upper layer, and the connection electrode 42 in contact with the second cavity element 40 b may be electrically connected to the lower layer.

[0175] Depending on the design of the semiconductor element or motherboard connected to the upper layer or the lower layer, the role of the cavity element mounted on the package substrate may be different, and the opening direction of the cavity portion may be different according to the role of the cavity element. According to the opening direction of the cavity portion, the arrangement of the connection electrodes may also be different.

[0176] That is, a first cavity portion 29a which is open and recessed in the direction of the first surface 213 or the second surface 214 and has a first depth h1 may be formed in the glass substrate 21, and a second cavity portion 29b which has a second depth h2 different from the first depth h1 may be open and recessed in the direction of the first surface 213 or the second surface 214.

[0177] As described above, the plurality of cavity elements 40a, 40b, and 40c may be independent passive elements such as MLCC or active elements such as diodes. Such various elements may be different in size, area, or height, which may cause undulation when forming RDL (Re-Distribution Layer).

[0178] According to this, according to the implementation example, when a plurality of components are mounted on the glass substrate 21, cavities having different heights can be generated in consideration of the design of the components (ie, the component arrangement position or the area or height of the components).

[0179] Therefore, when forming the cavity, the packaging substrate having the cavity with different heights can be manufactured by repeatedly performing the method of selectively masking and then etching. However, it is necessary to repeatedly perform the process of forming masking on the surface of the glass substrate 21 and removing the masking, so there is a disadvantage of complicated manufacturing process.

[0180] As another method, when forming a cavity portion, defects with different degrees are formed by selectively irradiating lasers with different intensities or adjusting the irradiation time of the laser, and the packaging substrate can be manufactured by etching the glass substrate 21 formed with the cavity portion. After that, the etching of the glass substrate can be performed at one time. That is, depending on the amount of laser irradiation, etc., the degree of substrate defects formed on the substrate may be different. Through this process, multiple half cavities (Half Cavity) or full cavities (Full Cavity) with different heights can be formed. Accordingly, the undulation (UNDULATION) caused by the different heights of each component when installing various types of components can be alleviated or eliminated.

[0181] Figure 7 Parts (a) to (c) of FIG. 1 are cross-sectional views of a portion of a packaging substrate according to another implementation example.

[0182] like Figure 7 As shown in part (a) of FIG. 2 , a first cavity portion 29a having a first depth h1, a second cavity portion 29b having a second depth h2, and a third cavity portion 29c having a third depth h3 may be formed on the glass substrate 21. The first cavity portion 29a and the second cavity portion 29b are open toward the first surface 213 and are recessed, and the third cavity portion 29c may penetrate the glass substrate 21.

[0183] The second depth h2 is greater than the first depth h1, and the third depth h3 is greater than the second depth h2. The cavity element portion can be arranged in the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c, and the cavity element portion has a height corresponding to the depth of each of the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c.

[0184] The cavity element portion of the first cavity portion 29a, the cavity element portion of the second cavity portion 29b, and the cavity element portion of the third cavity portion 29c have respective heights different from each other, but the upper insulating layer 61 arranged on the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c can actually be formed flat without bending.

[0185] Cavity elements 40a, 40b, 40c having heights corresponding to the depths of the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c may be arranged in the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c.

[0186] As shown in the figure, although the heights of the first cavity element 40a, the second cavity element 40b and the third cavity portion 29c are formed to be different from each other, the upper insulating layer 61 formed on the first cavity element 40a, the second cavity element 40b and the third cavity portion 29c can be actually formed flat without bending.

[0187] A portion of the upper insulating layer 61 is sunken (embedded) inside the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c, and the surface of the upper insulating layer 61 can be flatly stacked on the first surface 213. Optionally, the lower insulating layer 63 can also be formed on the second surface 214 of the glass substrate 21, that is, on the lower part of the glass substrate 21.

[0188] according to Figure 7 The core layer of the implementation example of part (a) may include: one or more connecting electrodes 42, which are arranged on the first cavity element 40a on the first surface 213 side; one or more connecting electrodes 42, which are arranged on the second cavity element 40b on the first surface 213 side; and one or more connecting electrodes 42, which are arranged on the third cavity element 40c on the first surface 213 side.

[0189] The connection electrode 42 is arranged or formed on the first surface 213 in the direction of the openings of the first cavity 29 a , the second cavity 29 b , and the third cavity 29 c , and can be electrically connected to an upper layer (not shown) that can be formed on the glass substrate 21 .

[0190] Additionally, in the third cavity element 40c installed in the third cavity portion 29c penetrating the glass substrate 21, the connection electrode 42 may be arranged or formed on the upper surface facing the first surface 213 and the bottom surface facing the second surface 214. That is, in the case of the third cavity element 40c penetrating the glass substrate 21, one or more connection electrodes may be arranged in the direction (second surface 214) facing the connection electrode formed on the first surface 213 across the third cavity element 40c.

[0191] The connection electrode 42 may be formed as a part of the electrode of the first cavity element 40a, the second cavity element 40b, and the third cavity element 40c, or may be formed as a distribution electrode of an upper layer, or may be configured in a form including both.

[0192] according to Figure 7 The core layer of the implementation example of part (b) includes cavities 29a, 29b, and 29c, which are open toward the second surface 214 of the glass substrate 21, that is, the bottom surface of the glass substrate 21 and are formed concavely.

[0193] In this case, the connection electrode 42 may be arranged or formed on the bottom surface of the first cavity element 40a, the second cavity element 40b and the third cavity element 40c. The connection electrode 42 toward the bottom surface may be electrically connected to the motherboard (not shown) through the lower layer formed under the core layer.

[0194] In accordance with Figure 7 In the core layer of the implementation example of part (c), the opening directions of the multiple half cavities formed by opening and recessing the glass substrate 21 in one direction can be different from each other. For example, the first cavity portion 29a can be opened to the first surface 213, and the second cavity portion 29b can be opened to the second surface 214. As shown in the figure, the first depth h1 of the first cavity portion 29a and the second depth h2 of the second cavity portion 29b are different from each other. According to one example, the second depth h2 can be greater than the first depth h1. Of course, the first depth h1 can also be greater than the second depth h2.

[0195] As described above, the connection electrode 42 in contact with the first cavity element 40a may be electrically connected to the upper layer, and the connection electrode in contact with the second cavity element 40b may be electrically connected to the lower layer.

[0196] Depending on the design of the semiconductor element or motherboard connected to the upper layer or the lower layer, the role of the cavity element mounted on the package substrate may be different, and the opening direction of the cavity portion may be different according to the role of the cavity element. According to the opening direction of the cavity portion, the arrangement of the connection electrodes may also be different.

[0197] tidy Figure 7 The shapes of the cavity portions shown in parts (a), (b) and (c) of the present invention may include a first cavity portion 29a which is open and recessed toward the first surface 213 or the second surface 214 and has a first depth h1, and a second cavity portion 29b which has a second depth h2 different from the first depth h1 may be open and recessed toward the first surface 213 or the second surface 214, and a third cavity portion 29c which passes through the first surface 213 and the second surface 214 may be formed on the glass substrate 21.

[0198] Figure 8FIG. 1 is a flow chart illustrating a manufacturing process of a package substrate according to an implementation example using a cross section. Figure 8 The process of installing the cavity element in the package substrate and forming the core layer is described in detail below. As an example, the description is based on the case of manufacturing a package substrate with three cavity parts, but there is no limitation on the number of cavity parts or the direction of the opening part.

[0199] First, if Figure 8 As shown in part (a) of FIG. 2 , a defect (or a defect) is formed on the surface of the glass substrate 21. In the process of forming the defect (or a defect), mechanical etching, laser irradiation, etc. can be used. As shown in the figure, lasers E1, E2, and E3 can be irradiated to generate defects (step S1: defect formation step).

[0200] At this time, the degree of the defect may be different, such as the size, width or depth of the defect, depending on the depth of the cavity. In the case where the formation intensity of the defect is large, the etching speed may be faster, and the smaller the formation range or intensity of the defect, the slower the etching speed may be. By adjusting the etching speed, cavity portions with different depths can be manufactured. Furthermore, if necessary, the etching degree can also be adjusted by partially applying masking.

[0201] The size of the cavity can be determined in accordance with the component to be installed inside the cavity, that is, the degree of defect can be controlled according to the height or area of ​​the cavity component.

[0202] If a defect has occurred, Figure 8 As shown in part (b), an etching step can be performed to form the cavity portions 29a, 29b, and 29c by a physical or chemical etching process. The etching of the cavity portions can be performed by immersing the cavity portions in an etching solution to simultaneously form cavity portions having different depths (step S2: cavity portion forming step).

[0203] As shown in the figure, the depth h1 of the first cavity 29 a is smaller than the depth h2 of the second cavity 29 b . The third cavity 29 c penetrates the glass substrate as a full cavity, and its depth h3 may be the same as the height of the glass substrate 21 .

[0204] In addition, the bottom area or width of the second cavity portion 29b is larger than that of the first cavity portion 29a, and the area or width of the third cavity portion 29c is larger than that of the second cavity portion 29b. The degree of defects and etching can be adjusted according to the number of cavity elements arranged in the cavity portion.

[0205] Through the defect generation and etching process, a core through hole ( Figure 8 The core through hole may be formed by the same process as the cavity portion or by another independent process.

[0206] Although not shown, after the etching process, a conductive layer may be formed on the surface of the glass (including the surface of the glass substrate, the surface of the cavity portion, and the surface of the core through hole). Typically, the conductive layer may use a metal layer containing copper metal, but is not limited thereto. The conductive layer may be formed by a dry method such as sputtering or a wet method such as primer treatment.

[0207] After the above process, if Figure 8 As shown in part (c), the glass substrate 21 is attached to an adhesive film 80 such as a PI tape (Polyimide Tape), and cavity elements 40a, 40b, 40c are selectively arranged in the cavity portions 29a, 29b, 29c (step S3: arrangement step).

[0208] As shown in the figure, the height of the first cavity element 40a arranged in the first cavity portion 29a is lower than the height of the second cavity element 40b or the third cavity element 40c, and the third cavity element 40c may have the highest height. That is, the cavity portion is generated according to the height or size of the cavity element, and the cavity element is arranged according to the height. Therefore, although there is a height difference between the cavity elements, the upper surface of the glass substrate 21 still has a curved shape smaller than the height difference of the cavity elements, and has a substantially flat shape.

[0209] Afterwards, if Figure 8 As shown in part (d) of FIG. 2 , an insulating layer can be formed by performing a lamination process (lamination on top) on the first surface (step S4: insulating layer formation step). An insulating film 61a such as ABF (Ajinomoto Build-up Film) is laminated on the first surface of the glass substrate 21 as a whole and cured, so that the insulator can be embedded in the internal space of the cavity portions 29a, 29b, and 29c. According to this implementation example, as Figure 8 As shown in part (e), the upper insulating layer can be formed in a relatively flat state without substantially any curvature, that is, in a laminated state.

[0210] According to one example, the insulating layer may be formed by a multiple lamination process, that is, the process of laminating and curing the insulating film is performed twice or more instead of only once, thereby improving the bending phenomenon of the glass substrate and preventing the separation or falling of the cavity element.

[0211] The adhesive film can be removed in a subsequent process as required. For example, the adhesive film can be applied with an adhesive film whose adhesive force can be reduced by irradiation with ultraviolet rays. For the adhesive film, the adhesive force of the adhesive film can be reduced by irradiating the adhesive film with ultraviolet rays directly or through the glass core, so that the adhesive film can be easily removed from the glass core.

[0212] After forming an insulating layer on the first surface of the glass substrate 21, Figure 8 As shown in part (e), a lower insulating layer is also formed on the surface of the second surface, and a connecting electrode 42 electrically connected to the cavity elements 40a, 40b, and 40c can be formed (step S5: connecting electrode forming step). The connecting electrode forming step can be performed after the arranging step or after the insulating layer forming step.

[0213] Then, an upper layer (not shown) may be disposed (or formed) on an upper portion of the glass substrate 21 , and a lower layer (not shown) may be disposed (or formed) on a lower portion of the glass substrate 21 .

[0214] The formation process and reference of the upper and lower layers Figure 5 The parts described in parts (a) to (e) are similar, so repeated description is omitted.

[0215] According to the package substrate and the manufacturing method thereof according to the embodiments described above, components of various shapes and sizes can be compactly mounted inside a glass substrate, and undulation that may occur on a core layer can be alleviated or eliminated.

[0216] The present invention as described above is described with reference to the embodiments shown in the accompanying drawings, but this is only exemplary, and anyone with ordinary knowledge in the relevant technical field can understand that various modifications and variations of the embodiments can be made therefrom. That is, the scope of rights of the present invention is not limited to the above-mentioned embodiments, and various modifications and improved forms of practitioners using the basic concepts of the embodiments defined by the claims are also included in the scope of rights of the embodiments. Therefore, the true technical protection scope of the present invention should be defined by the technical ideas of the claims.

Claims

1. A packaging substrate, comprising a core layer, characterized in that: The core layer comprises: A glass substrate including a first surface and a second surface facing each other, and Two or more cavity portions have opening portions, and the opening portions are open in the direction of the first surface or the direction of the second surface; The two or more cavity portions have different depths from each other.

2. The packaging substrate according to claim 1, characterized in that: Also includes: a cavity element arranged in the cavity portion and including two or more individual elements having mutually different heights; as well as The insulating layer is disposed on the surface of the glass substrate where the opening is formed, and is sunken into the cavity.

3. The packaging substrate according to claim 2, characterized in that: The cavity portion comprises: a first cavity portion, which is open and recessed toward the first surface and has a first depth, and A second cavity portion is open and recessed toward the first surface or the second surface and has a second depth; the second depth is greater than the first depth, The cavity element comprises: a first cavity element arranged in the first cavity portion, and The second cavity element is arranged in the second cavity portion.

4. The packaging substrate according to claim 3, characterized in that: Disposing a connecting electrode on the first cavity element; A connecting electrode is arranged on the second cavity element.

5. The packaging substrate according to claim 1, characterized in that: The cavity portion comprises: The first cavity portion is open and recessed toward the first surface and has a first depth. a second cavity portion that is open and recessed toward the first surface or the second surface and has a second depth, and A third cavity portion having a third depth penetrating the first surface and the second surface; The second depth is greater than the first depth.

6. The packaging substrate according to claim 5, characterized in that: The cavity element comprises: A first cavity element is arranged in the first cavity portion, a second cavity element arranged in the second cavity portion, and A third cavity element arranged in the third cavity portion; A connecting electrode is arranged on the first cavity element, A connecting electrode is arranged on the second cavity element, One or more connection electrodes are arranged on the third cavity element in the direction of the first surface or the direction of the second surface.

7. The packaging substrate according to claim 6, characterized in that: A plurality of connection electrodes are arranged on the third cavity element in two directions of the first surface and the second surface.

8. A method for manufacturing a packaging substrate, characterized in that: include: a defect forming step of preparing a glass substrate including a first surface and a second surface facing each other, and forming a plurality of defects of different degrees on the first surface or the second surface; The cavity forming step is to form two or more cavity portions having different depths by etching the glass substrate.

9. The method for manufacturing a packaging substrate according to claim 8, characterized in that: The method for manufacturing the package substrate further comprises an arrangement step and an insulation layer formation step after the cavity forming step. The arranging step is a step of arranging a plurality of cavity elements in the cavity portion, The insulating layer forming step is a step of forming an insulating layer on the surface of the cavity portion where the opening portion is formed. The plurality of cavity elements arranged in the cavity portion have different heights from each other.

10. The method for manufacturing a packaging substrate according to claim 9, wherein: The cavity portion includes a first cavity portion and a second cavity portion, The first cavity portion is open and recessed toward the first surface and has a first depth. The second cavity portion is open and recessed toward the first surface or the second surface, and has a second depth greater than the first depth. The cavity element comprises a first cavity element and a second cavity element, The first cavity element is arranged in the first cavity portion, The second cavity element is arranged in the second cavity portion, The method for manufacturing the package substrate further comprises a connecting electrode forming step. The connection electrode forming step is a step for forming one or more connection electrodes connected to the first cavity element and one or more connection electrodes connected to the second cavity element.

11. The method for manufacturing a packaging substrate according to claim 9, wherein: The cavity portion includes a first cavity portion, a second cavity portion and a third cavity portion, The first cavity portion is open and recessed toward the first surface and has a first depth. The second cavity portion is open and recessed toward the first surface or the second surface, and has a second depth greater than the first depth. The third cavity portion passes through the first surface and the second surface and has a third depth. The cavity element comprises a first cavity element, a second cavity element and a third cavity element, The first cavity element is arranged in the first cavity portion, The second cavity element is arranged in the second cavity portion, The third cavity element is arranged in the third cavity portion, The method for manufacturing the package substrate further comprises a connecting electrode forming step. The connection electrode forming step is a step for forming one or more connection electrodes connected to the first cavity element, one or more connection electrodes connected to the second cavity element, and one or more connection electrodes connected to the third cavity element.

12. The method for manufacturing a packaging substrate according to claim 11, characterized in that: In the connection electrode forming step, connection electrodes are further formed on two or more surfaces of the third cavity element.

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