Integrated circuit including electronic fuse bit cell

Abstract

An integrated circuit including an electronic fuse bit cell includes: a first backside wiring layer disposed on a backside of a substrate; and an electronic fuse bit unit. The electronic fuse position unit comprises an electronic fuse; a transistor disposed on a front side of the substrate; and a first backside contact passing through the substrate in a vertical direction and electrically connecting the electronic fuse to the transistor. The electronic fuse includes: a first terminal electrically connected to a bit line; a second terminal electrically connected to the first back side contact; and a chain body between the first terminal and the second terminal, and the first terminal, the second terminal, and the chain body are included in the first backside wiring layer.

Description

Background Art

[0001] Due to the demand for highly integrated semiconductor devices and the development of semiconductor processes, the width, spacing and / or height of wiring included in an integrated circuit may be reduced, and the parasitic elements of the wiring may increase. Moreover, in order to reduce power consumption and increase operating speed, the power supply voltage of the integrated circuit may be reduced, and therefore, the influence of the parasitic elements of the wiring on the integrated circuit may be further increased. Therefore, the demand for design methods of integrated circuits that effectively route wiring and vias has been increasing. Summary of the invention

[0002] In general, in some aspects, the present disclosure relates to an integrated circuit capable of improving power performance area (PPA) by implementing an electronic fuse (e-fuse) bit cell using front-side wiring layers and back-side wiring layers, and a method of designing the integrated circuit.

[0003] According to some aspects, the present disclosure relates to an integrated circuit, which includes: a first backside wiring layer, which is arranged on the back side of a substrate; and an electronic fuse bit unit, which includes: an electronic fuse; a transistor, which is arranged on the front surface of the substrate; a first backside contact, which passes through the substrate in a vertical direction to electrically connect the electronic fuse to the transistor, wherein the electronic fuse includes: a first terminal, which is electrically connected to a bit line; a second terminal, which is electrically connected to the first backside contact; and a chain body, which is located between the first terminal and the second terminal, and the first terminal, the second terminal and the chain body are included in the first backside wiring layer.

[0004] According to some aspects, the present disclosure relates to an integrated circuit, which includes: a first front-side wiring layer, which is arranged above the front side of a substrate; a back-side wiring layer, which is arranged on the back side of the substrate and includes a first back-side pattern; a first through-via, which is arranged on the first back-side pattern and passes through the substrate in a vertical direction; and an electronic fuse bit unit, which includes an electronic fuse and a transistor arranged on the front side of the substrate, wherein the electronic fuse includes: a first terminal, which is electrically connected to the first through-via and electrically connected to a bit line via the first through-via and the first back-side pattern; a second terminal, which is electrically connected to the transistor; and a chain body, which is located between the first terminal and the second terminal, and the first terminal, the second terminal and the chain body are included in the first front-side wiring layer.

[0005] According to some aspects, the present disclosure relates to an integrated circuit, which includes: a first front-side wiring layer, which is arranged above the front side of a substrate; a second front-side wiring layer, which is arranged above the first front-side wiring layer; a back-side wiring layer, which is arranged on the back side of the substrate and is configured to receive a power supply voltage; and an electronic fuse bit cell, which includes an electronic fuse and a transistor arranged on the front side of the substrate, wherein the electronic fuse includes: a first terminal, which is electrically connected to a bit line; a second terminal, which is electrically connected to a drain of the transistor; and a chain body, which is located between the first terminal and the second terminal, the first terminal, the second terminal and the chain body are included in the second front-side wiring layer, and the source of the transistor is configured to receive the power supply voltage from the back side pattern.

[0006] According to some aspects, the present disclosure relates to an integrated circuit, which includes: a first front-side wiring layer, which is arranged above the front side of a substrate; a back-side wiring layer, which is arranged on the back side of the substrate and includes a first back-side pattern; a first through-via, which is arranged on the first back-side pattern and passes through the substrate in a vertical direction; and an electronic fuse bit unit, which includes an electronic fuse and a transistor arranged on the front side of the substrate, wherein the electronic fuse includes: a first terminal, which is electrically connected to a bit line; a second terminal, which is electrically connected to the transistor via the first back-side pattern and the first through-via; and a chain body, which is located between the first terminal and the second terminal, and the first terminal, the second terminal and the chain body are included in the first front-side wiring layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0008] Figure 1 is an example layout of an integrated circuit according to some implementations.

[0009] Figure 2 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit taken along line X1-X1'.

[0010] Figure 3 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit taken along line X1-X1'.

[0011] Figure 4is a block diagram of an example of a memory device according to some implementations.

[0012] Figure 5 is a circuit diagram of an example of a cell array according to some embodiments.

[0013] Fig. 6A and Figure 6B is a circuit diagram illustrating an example of an electronic fuse bit cell according to some embodiments.

[0014] Figure 7 is an example layout of an integrated circuit according to some implementations.

[0015] Figure 8 According to some embodiments, Figure 7 A cross-sectional view of the integrated circuit taken along line X2-X2'.

[0016] Fig. 9 is an example layout of an integrated circuit according to some implementations.

[0017] Fig.10 According to some embodiments, Fig. 9 A cross-sectional view of the integrated circuit taken along line X3-X3'.

[0018] Fig.11 is an example layout of an integrated circuit according to some implementations.

[0019] Fig.12 According to some embodiments, Fig.11 A cross-sectional view of the integrated circuit taken along line X4-X4'.

[0020] Fig.13 According to some embodiments, Fig.11 A cross-sectional view of the integrated circuit taken along line X5-X5'.

[0021] Fig.14 is an example layout of an integrated circuit according to some implementations.

[0022] Fig.15 According to some embodiments, Fig.15 A cross-sectional view of the integrated circuit taken along line X6-X6'.

[0023] Fig.16 is an example layout of an integrated circuit according to some implementations.

[0024] Fig.17 According to some embodiments, Fig.16 A cross-sectional view of the integrated circuit taken along line X7-X7'.

[0025] Fig.18 is an example layout of an integrated circuit according to some implementations.

[0026] Fig.19 According to some embodiments, Fig.18 A cross-sectional view of the integrated circuit taken along line X8-X8'.

[0027] Fig. 20 is an example layout of an integrated circuit according to some implementations.

[0028] Fig.21 According to some embodiments, Fig. 20 A cross-sectional view of the integrated circuit taken along line X9-X9'.

[0029] Fig. 22 is an example layout of an integrated circuit according to some implementations.

[0030] Fig.23 According to some embodiments, Fig. 22 A cross-sectional view of the integrated circuit taken along line X10-X10'.

[0031] Fig.24 According to some embodiments, Fig. 22 A cross-sectional view of the integrated circuit taken along line X11-X11'.

[0032] Fig.25 is an example layout of an integrated circuit according to some implementations.

[0033] Fig.26 According to some embodiments, Fig.25 A cross-sectional view of the integrated circuit taken along line X12-X12'.

[0034] Fig. 27 is an example layout of an integrated circuit according to some implementations.

[0035] Fig.28 According to some embodiments, Fig. 27 A cross-sectional view of the integrated circuit taken along line X13-X13'.

[0036] Fig.29 is an example layout of an integrated circuit according to some implementations.

[0037] Fig.30 According to some embodiments, Fig.29 A cross-sectional view of the integrated circuit taken along line X14-X14'.

[0038] Fig.31 is an example layout of an integrated circuit according to some implementations.

[0039] Fig.32 According to some embodiments, Fig.31 A cross-sectional view of the integrated circuit taken along line X15-X15'.

[0040] Fig.33 is an example layout of an integrated circuit according to some implementations.

[0041] Fig.34 According to some embodiments, Fig.33 A cross-sectional view of the integrated circuit taken along line X16-X16'.

[0042] Fig.35 is an example layout of an integrated circuit according to some implementations.

[0043] Fig.36 According to some embodiments, Fig.35 A cross-sectional view of the integrated circuit taken along line X17-X17'.

[0044] Fig.37 is an example layout of an integrated circuit according to some implementations.

[0045] Fig.38 According to some embodiments, Fig.37 A cross-sectional view of the integrated circuit taken along line X18-X18'.

[0046] FIG. 39A to FIG. 39D is a diagram illustrating examples of elements according to some embodiments.

[0047] Fig.40 is a flow chart illustrating an example of a method of manufacturing an integrated circuit according to some embodiments.

[0048] Fig.41 is a block diagram of an example of a system on a chip according to some implementations.

[0049] Fig.42 is a block diagram of an example of a computing system including memory for storing programs according to some implementations. DETAILED DESCRIPTION

[0050] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same elements, and detailed descriptions thereof will be omitted.

[0051] In the present disclosure, the X direction may be referred to as a first direction, the Y direction may be referred to as a second direction, and the Z direction may be referred to as a vertical direction. A plane composed / defined by the X-axis and the Y-axis may be referred to as a horizontal plane. Components arranged in the +Z axis direction relative to other components may be referred to as being above the other components, and components arranged in the -Z axis direction relative to the other components may be referred to as being below the other components.

[0052] In some embodiments, an integrated circuit can be designed by placing multiple standard cells. A standard cell is a unit of the layout of an integrated circuit, and may be referred to as a "cell" according to an embodiment. A standard cell may be designed to include multiple transistors in order to implement a predetermined function. A standard cell design method refers to a method of designing a dedicated large-scale integrated circuit (LSI) to meet one or more design constraints specified by a customer or user by preparing standard cells with multiple functions and combining certain standard cells. After design and verification, the standard cell may be registered (or stored for later reference) in a computer, and by using computer-aided design (CAD) techniques and tools, a logic design obtained by combining standard cells, placement, and routing may be obtained. When designing an integrated circuit, the performance of the integrated circuit may be further improved by reducing the length of interconnects and / or through-holes and the complexity of routing.

[0053] Figure 1 is an example layout of an integrated circuit according to some implementations. Figure 2 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit taken along line X1-X1'.

[0054] exist Figure 1 and Figure 2 In the embodiment, the integrated circuit 10 may include an active region RX, a gate line GT, a contact CA, a first via VA, a first front wiring layer M1, a first back wiring layer BM1, and a back contact BCA. Figure 1 The integrated circuit 10 can be used with Figure 5 For example, the electronic fuse eFS included in the electronic fuse bit cell BC may be implemented as a first backside wiring layer BM1, the transistor TR included in the electronic fuse bit cell BC may include a gate line GT and a source / drain region SD, and the wiring for connecting the electronic fuse eFS to the transistor TR may be implemented as a backside contact BCA.

[0055] The integrated circuit 10 may be implemented as a semiconductor device, and the semiconductor device is formed on a substrate SUB, and the substrate SUB may have a first surface FS and a second surface BS. The first surface FS may be, for example, a surface on which circuit elements such as transistors are arranged, and the first surface FS may be referred to as the front side. The second surface BS may be opposite to the first surface FS, and may be referred to as the back side. The integrated circuit 10 may implement a power distribution network (PDN) by using a first front wiring layer M1 and a first back wiring layer BM1. Thus, some of the signals and / or power applied to the integrated circuit 10 may be transmitted through the front wiring layer including the first front wiring layer M1, i.e., the front PDN (FSPDN), while other signals and / or power may be transmitted through the back wiring layer including the first back wiring layer BM1, i.e., the back PDN (BSPDN). Therefore, compared with a structure in which interconnects are arranged only on the front surface FS of the substrate SUB, the routing complexity may be greatly reduced, and the length of each interconnect or via may be reduced, and the performance of the integrated circuit 10 may be improved.

[0056] For example, the substrate SUB may include one of silicon, silicon on insulator, silicon on sapphire, germanium, silicon germanium, and gallium arsenide. The interlayer insulating layer ILD may be arranged on the substrate SUB. The interlayer insulating layer ILD may include an insulating material, for example, the insulating material may include one of an oxide layer, a nitride layer, and an oxynitride layer.

[0057] In some embodiments, the substrate SUB may correspond to a bulkless substrate. During the process of manufacturing the integrated circuit 10, a device wafer may be formed by forming gate lines, source / drain regions, contacts, vias, and / or wiring layers on the front surface of the substrate SUB. Next, the device wafer is temporarily bonded to a carrier wafer, and a back grinding process is performed on the device wafer to remove at least a portion from the substrate. As described above, a wafer whose back side is ground so that the height of the substrate is a reference height or less may be referred to as a "bulkless wafer" or "bulkless substrate".

[0058] The active region RX may extend in a first direction x. For example, the active region RX may be defined by an isolation layer such as shallow trench isolation (STI), or may be referred to as a diffusion region. The diffusion region is a region doped with impurities that change the electrical properties of the substrate material, and may form a source / drain region SD of the transistor. The source / drain region SD may include an epitaxial region of a semiconductor material such as silicon, boron, tin, germanium, carbon, SiGe, and / or SiC. The contacts CA may each extend in a second direction Y above the active region RX, and the first vias VA may be respectively arranged on the contacts CA. For example, the contacts CA may be respectively on the source / drain region SD, and may be referred to as source / drain contacts.

[0059] The nanosheet stack NS extending in the first direction X may be arranged above the front side FS of the substrate SUB. The nanosheet stack NS may include a plurality of nanosheets overlapping in the vertical direction (Z), for example, a first nanosheet NS1 to a third nanosheet NS3. For example, the nanosheet stack NS may be doped with N-type impurities and may form an N-type transistor. In another example, the nanosheet stack NS may be doped with P-type impurities and may form a P-type transistor. In some embodiments, the nanosheet stack NS may include Si, Ge, or SiGe. In an embodiment, the nanosheet stack NS may include InGaAs, InAs, GaSb, InSb, or a combination thereof.

[0060] The gate lines GT may each extend in the second direction Y and may be spaced apart from each other in the first direction X. Each of the gate lines GT may cover the nanosheet stack NS and may surround each of the first to third nanosheets NS1 to NS3. Thus, the first to third nanosheets NS1 to NS3 may each have a gate allaround (GAA) structure. The gate line GT may be defined as a conductive segment including a conductive material such as polysilicon and one or more metals. A gate insulating layer may be provided between each of the gate lines GT and the first to third nanosheets NS1 to NS3.

[0061] The first front wiring layer M1 may include a plurality of front patterns electrically connected to the source / drain region SD via the first vias VA and the contacts CA. For example, the plurality of front patterns may each extend in the second direction Y and may be spaced apart from each other in the first direction X. The extension direction, width, and / or length of the front patterns included in the first front wiring layer M1 may be variously changed according to some embodiments.

[0062] The first backside wiring layer BM1 may include an electronic fuse 11, and the electronic fuse 11 may include a first terminal 11a, a second terminal 11c, and a fuse link or a link 11b between the first terminal 11a and the second terminal 11c. For example, the first terminal 11a, the link 11b, and the second terminal 11c may correspond to Fig. 6A The anode T1, the chain body LK and the cathode T2, and the first terminal 11a, the chain body 11b and the second terminal 11c can form Fig. 6A Electronic fuse eFS.

[0063] The second terminal 11c may extend in the first direction X below the source / drain region SD, and the back contact BCA may be arranged on the second terminal 11c. Like this, the second terminal 11c may be electrically connected to the drain region DR in the source / drain region SD via the back contact BCA. As described above, the back contact BCA may connect the layers and elements on the back surface BS to the elements in the substrate SUB, such as the source / drain region SD. In detail, the back contact BCA may be connected to the drain region DR in the active region RX, respectively. As described above, the structure that connects the contact to the lower portion of the source / drain region SD may be referred to as a direct back contact (DBC). According to some embodiments, the DBC may include a back contact and / or a back via.

[0064] The first terminal 11a, the chain body 11b, and the second terminal 11c may be arranged along the first direction X. For example, the length of the first terminal 11a and the second terminal 11c in the second direction Y, that is, the width may be greater than the length of the chain body 11b in the second direction Y, that is, the width. However, the present disclosure is not limited thereto, and in some embodiments, the first terminal 11a, the chain body 11b, and the second terminal 11c may be arranged along the second direction Y. Here, the length of the first terminal 11a and the second terminal 11c in the first direction X, that is, the width may be greater than the length of the chain body 11b in the first direction X, that is, the width.

[0065] As described above, according to some embodiments, the electronic fuse 11 may be included in the first backside wiring layer BM1 and may be implemented as a BSPDN, and thereby, the routing resources for the electronic fuse 11 may increase. In detail, the parasitic resistance may be reduced by increasing the width of each of the first terminal 11a, the chain body 11b, and the second terminal 11c. Moreover, since the electronic fuse 11 is implemented as a BSPDN, the routing resources of the FSPDN including the first frontside wiring layer M1 may increase. Therefore, the size of the integrated circuit 10 including the electronic fuse bit cell BC may be reduced, and according to the reduction of the parasitic resistance, the performance of the integrated circuit 10 may be improved, and therefore, the power performance area (PPA) of the integrated circuit 10 may be improved.

[0066] Figure 3 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit taken along the line X1-X1'. Figure 3 , the integrated circuit 10' may correspond to Figure 1 and Figure 2 The integrated circuit 10' may include a fin structure FIN instead of a nanosheet stack NS, and thus, the transistor included in the integrated circuit 10' may be implemented as a FinFET. Hereinafter, as an example, the transistor included in the electronic fuse bit cell according to some embodiments may be illustrated as an MBCFET including a nanosheet stack. However, the transistor included in the electronic fuse bit cell according to an embodiment may be implemented as Figure 3 Furthermore, the transistors included in the electronic fuse bit cell according to some embodiments can be adopted by various methods, which will be referred to below. FIG. 39A to FIG. 39D Detailed description.

[0067] Figure 4 is a block diagram of an example of a memory device according to some embodiments. Figure 4 In the embodiment, the memory device 20 may include a cell array 21, a row decoder 22, a control circuit 23, and an input / output (I / O) circuit 24. Here, the row decoder 22, the control circuit 23, and the I / O circuit 24 may be collectively referred to as a peripheral circuit. According to some embodiments, the peripheral circuit may further include a command buffer, an address buffer, and / or a voltage generator. For example, the memory device 20 may be implemented as Figure 1 Integrated circuit 10.

[0068] The memory device 20 may receive a command CMD, an address ADDR, and data DATA. For example, the memory device 20 may receive a command CMD, an address ADDR, and data DATA for instructing a write operation, and may store the data DATA in a region corresponding to the address ADDR of the cell array 21. Also, the memory device 20 may receive a command CMD and an address ADDR for instructing a read operation, and may output the data stored in a region corresponding to the address ADDR of the cell array 21.

[0069] The cell array 21 may include a plurality of bit cells or memory cells accessed through a plurality of word lines WL and a plurality of bit lines BL. In some embodiments, the memory cells included in the cell array 21 may be one-time programmable (OTP) bit cells, such as electronic fuse bit cells. However, the present disclosure is not limited thereto, and in some embodiments, the memory cells included in the cell array 21 may be volatile memory cells, such as static random access memory (SRAM), dynamic random access memory (DRAM), etc. In some embodiments, the memory cells included in the cell array 21 may be non-volatile memory cells, such as flash memory, resistive random access memory (RRAM), etc. Some embodiments are mainly referred to below. Figures 5 to 6B The electronic fuse bit cell is described with reference to the drawings, but one or more embodiments are not limited thereto.

[0070] The control circuit 23 may generate a row address ADDR_R and a control signal CTR based on a command CMD and an address ADDR. The row decoder 22 may be connected to the cell array 21 via a plurality of word lines WL, and may activate one of the plurality of word lines WL according to the row address ADDR_R. The I / O circuit 24 may be connected to the cell array 21 via a plurality of bit lines BL, and may perform a read operation or a write operation according to the control signal CTR. For example, the I / O circuit 24 may include a column driver. At a timing determined based on the control signal CTR, the column driver may sense a current and / or voltage from a plurality of bit lines BL, or may apply a current and / or voltage to a plurality of bit lines BL.

[0071] Figure 5 is a circuit diagram of an example of a cell array according to some embodiments. Figure 5 In the present disclosure, the cell array 21 may include an electronic fuse bit cell BC connected to the word lines WL1 to WL4 or the bit lines BL1 and BL2. For example, the electronic fuse bit cell BC may be connected to the word line WL1 and the bit line BL1, and may include an electronic fuse eFS and a transistor TR. In the present disclosure, Figures 1 to 3 and Figures 7 to 38 The integrated circuits 10, 10', 10a, 30 to 70d shown in FIG. 70 may correspond to various implementations using electronic fuse bit cells BC. As described above, Figures 1 to 3 and Figure 7 to Figure 37Implementation examples of the electronic fuse bit cell BC are shown in FIG. 2 , but these examples may also be applied to other electronic fuse bit cells included in the cell array 21 .

[0072] Fig. 6A is a circuit diagram illustrating an example of an electronic fuse bit cell according to some embodiments. Fig. 6A In the embodiment of the present invention, the electronic fuse bit cell BC may include an electronic fuse eFS and a transistor TR. The electronic fuse eFS may include an anode T1, a cathode T2, and a chain body LK between the anode T1 and the cathode T2. The chain body LK includes a conductive material, and in some embodiments, may be referred to as a metal chain body, a metal strip, or a fuse. In the present disclosure, the anode T1 may be referred to as a first terminal, and the cathode T2 may be referred to as a second terminal. For example, the width of the chain body LK may be less than the width of the anode T1 and the cathode T2. For example, the length of the chain body LK may be greater than the length of the anode T1 and the cathode T2. As described above, the chain body LK may be adopted in a slender and thin metal material compared to the anode T1 and the cathode T2. However, the present disclosure is not limited thereto, and the width and / or length of the anode T1, the cathode T2, and / or the chain body LK may be variously modified according to some embodiments.

[0073] The anode T1 may be electrically connected to the bit line BL and may receive a fuse source voltage Vfs from the bit line BL. The cathode T2 may be electrically connected to the transistor TR. The electronic fuse eFS is an element whose opposite ends are open or in a high resistance state when a high voltage is applied to the opposite ends thereof, and may have a high resistance value, for example, because of electromigration due to the high voltage.

[0074] The transistor TR may include a gate connected to the word line WL, a drain connected to the cathode T2, and a source receiving a power supply voltage, such as a ground voltage VSS. During a programming operation, a driving voltage is applied to the word line WL, and a high voltage fuse source voltage Vfs may be applied to the bit line BL, and thus, the electronic fuse eFS may be disconnected. The electronic fuse eFS may indicate that data is programmed in the case of a high resistance value.

[0075] Figure 6B is a circuit diagram illustrating an example of an electronic fuse bit cell according to some embodiments. Figure 6BIn the embodiment of the present invention, the electronic fuse bit cell BC' may include an electronic fuse eFS, a programming transistor TR2, and a reading transistor TR1. The programming transistor TR2 may include a gate connected to a programming word line WLP, a drain connected to a node ND, and a source, to which a power supply voltage, such as a ground voltage VSS, is applied. The reading transistor TR1 may include a gate connected to a reading word line WLR, a drain connected to a node ND, and a source connected to a bit line BL. The electronic fuse eFS may include an anode T1 receiving a fuse source voltage Vfs, a cathode T2 connected to a node ND, and a chain body LK located between the anode T1 and the cathode T2.

[0076] During the programming operation, a driving voltage is applied to the programming word line WLP, a high voltage fuse source voltage Vfs may be applied to the anode T1 of the electronic fuse eFS, and thus the electronic fuse eFS may be disconnected. The electronic fuse eFS may indicate that data is programmed in the case of a high resistance value. During the reading operation, the read word line WLR is applied with a read voltage, and a ground voltage VSS may be applied to the anode T1 of the electronic fuse eFS. Thus, a current path through the bit line BL, the read transistor TR1, and the electronic fuse eFS may be formed. Here, depending on whether the programmed electronic fuse eFS is disconnected, the voltage level of the bit line BL is output differently, and thus data may be read.

[0077] As the element is developed through the back-end process, the size of the electronic fuse bit cell BC or BC' may be reduced. According to the reduction in the size of the electronic fuse bit cell BC or BC', the routing resources connected to the electronic fuse bit cell BC may be reduced, and the performance of the memory device may be degraded due to the increase in parasitic resistance caused thereby. Therefore, in order to fully perform a programming operation or a reading operation on the electronic fuse bit cell BC or BC', it is important to reduce the parasitic resistance of the electronic fuse bit cell BC or BC' when designing the layout of the IC including the electronic fuse bit cell BC or BC'.

[0078] According to some embodiments, various layouts and design methods are proposed that can reduce the parasitic resistance of the electronic fuse bit cell BC by increasing the width and number of interconnects that connect the electronic fuse eFS to the transistor TR included in the electronic fuse bit cell BC. In addition, according to some embodiments, various layouts and design methods are provided that can reduce the parasitic resistance of the electronic fuse bit cell BC by increasing the width and number of wirings configured to apply a power supply voltage, such as a ground voltage VSS, to the transistor TR included in the electronic fuse bit cell BC. According to some embodiments, the routing resources connected to the electronic fuse bit cell BC can be increased by using a BSPDN, and therefore, the performance of the memory device can be improved due to the reduction of parasitic capacitance.

[0079] Figure 7 is an example layout of an integrated circuit according to some implementations. Figure 8 According to some embodiments, Figure 7 A cross-sectional view of the integrated circuit taken along line X2-X2'.

[0080] exist Figure 7 and Figure 8 In the embodiment, the integrated circuit 10a corresponds to Figure 1 A modified example of the integrated circuit 10 shown in FIG. 1 and referenced above Figures 1 to 6B The description provided may also be applied to some embodiments. Figure 1 Compared with the integrated circuit 10 of FIG. 1 , the integrated circuit 10a may further include a second front side wiring layer M2, a third front side wiring layer M3, second and third vias V1 and V2, a first back side via BV1, and a second back side wiring layer BM2.

[0081] The second backside wiring layer BM2 may be arranged below the first backside wiring layer BM1 and may receive a bit line BL signal. The first backside via BV1 may be arranged on the second backside wiring layer BM2 and may electrically connect the first backside wiring layer BM1 and the second backside wiring layer BM2 to each other. The first terminal 11a included in the first backside wiring layer BM1 may be electrically connected to the bit line BL via the first backside via BV1 and the second backside wiring layer BM2 and may receive a bit line BL signal.

[0082] The second front side wiring layer M2 may be arranged above the first front side wiring layer M1, and may be electrically connected to the first front side wiring layer M1 via the second through hole V1. For example, the second front side wiring layer M2 may include wiring patterns extending in the second direction Y and spaced apart from each other in the first direction X. The third front side wiring layer M3 may be arranged above the second front side wiring layer M2, and may be electrically connected to the second front side wiring layer M2 via the third through hole V2. For example, the third front side wiring layer M3 may extend in the first direction X. The third front side wiring layer M3 may receive a power supply voltage, such as a ground voltage VSS.

[0083] The source region SS of the transistor may receive a ground voltage VSS from the FSPDN including the first to third front wiring layers M1, M2, and M3. For example, the source region SS may receive a ground voltage VSS via the contact CA, the first via VA, the first front wiring layer M1, the second via V1, the second front wiring layer M2, the third via V2, and the third front wiring layer M3. The wiring for connecting the electronic fuse 11 to the drain region DR of the transistor may be implemented as a BSPDN. For example, the drain region DR of the transistor may be electrically connected to the second terminal 11c via the back contact BCA.

[0084] Fig. 9 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.10 According to some embodiments, Fig. 9 A cross-sectional view of the integrated circuit taken along line X3-X3'.

[0085] exist Fig. 9 and Fig.10 , the integrated circuit 30 may include an active region RX, a gate line GT, a contact CA, a first via VA, a first front wiring layer M1, first to third back wiring layers BM1, BM2 and BM3, a back contact BCA, and a first back via BV1 and a second back via BV2. The integrated circuit 30 corresponds to Figure 1 A modified example of the integrated circuit 10 shown in FIG. Figure 1 The electronic fuse 11 is implemented as a first backside wiring layer BM1 , and according to some embodiments, the electronic fuse 31 may be employed as a second backside wiring layer BM2 .

[0086] The second backside wiring layer BM2 may include an electronic fuse 31, and the electronic fuse 31 may include a first terminal 31a, a second terminal 31c, and a chain body 31b between the first terminal 31a and the second terminal 31c. The first terminal 31a may be electrically connected to the bit line BL via the second backside via BV2 and the third backside wiring layer BM3, and may receive a bit line BL signal. The second terminal 31c may be electrically connected to the drain region DR of the transistor via the first backside via BV1, the first backside wiring layer BM1, and the backside contact BCA. The source region SS of the transistor may receive a power supply voltage, such as a ground voltage VSS, via the FSPDN including the first frontside wiring layer M1 and the second frontside wiring layer M2.

[0087] Fig.11 is an example layout of an integrated circuit according to some implementations. Fig.12 According to some embodiments, Fig.11 A cross-sectional view of the integrated circuit taken along line X4-X4'. Fig.13 According to some embodiments, Fig.11 A cross-sectional view of the integrated circuit taken along line X5-X5'.

[0088] exist Figures 11 to 13, the integrated circuit 40 may include an active region RX, a gate line GT, a back contact BCA, a first back wiring layer BM1 and a second back wiring layer BM2, and a first back via BV1. The first back wiring layer BM1 may include a plurality of back patterns each extending in the second direction Y and spaced apart from each other in the first direction x. The second back wiring layer BM2 may be arranged below the first back wiring layer BM1 and may include back patterns 42a, 42b, and 42c. For example, the back pattern 42a may receive a bit line BL signal, the back pattern 42b may be used as a wiring between the electronic fuse 41 and the transistor, and the back pattern 42c may receive a ground voltage VSS.

[0089] According to some embodiments, the electronic fuse 41 may receive a bit line BL signal via the BSPDN. For example, the electronic fuse 41 may be implemented as a first backside wiring layer BM1. The electronic fuse 41 may include a first terminal 41a, a second terminal 41c, and a link body 41b between the first terminal 41a and the second terminal 41c. The first terminal 41a may be electrically connected to the bit line BL via a first backside via BV1 and a backside pattern 42a included in the second backside wiring layer BM2, and may receive a bit line BL signal.

[0090] According to some embodiments, the electronic fuse bit cell may electrically connect the electronic fuse 41 to the drain region DR of the transistor via the BSPDN. For example, the second terminal 41c may be electrically connected to the drain region DR via the first backside via BV1, the backside pattern 42b included in the second backside wiring layer BM2, the first backside wiring layer BM1, and the backside contact BCA. According to some embodiments, the electronic fuse 41 may receive a ground voltage VSS via the BSPDN. For example, the source region SS may receive a ground voltage VSS via the backside contact BCA, the first backside wiring layer BM1, the first backside via BV1, and the backside pattern 42c included in the second backside wiring layer BM2.

[0091] Fig.14 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.15 According to some embodiments, Fig.15 A cross-sectional view of the integrated circuit taken along line X6-X6'.

[0092] exist Fig.14 and Fig.15, the integrated circuit 50 may include an active region RX, a gate line GT, a contact CA, first to third vias VA, V1 and V2, first to third front wiring layers M1, M2 and M3, a through-hole via or through-hole THV, a back contact BCA, and a first back wiring layer BM1. The through-hole THV may include a through-hole THV1. According to some embodiments, the electronic fuse 51 may be arranged in the first front wiring layer M1. The electronic fuse 51 may include a first terminal 51a, a second terminal 51c, and a chain body 51b between the first terminal 51a and the second terminal 51c.

[0093] The first backside wiring layer BM1 may include backside patterns 52a and 52b. For example, the backside pattern 52a may receive a bit line BL signal, and the backside pattern 52b may receive a ground voltage VSS. The second frontside wiring layer M2 may include wiring patterns M2a, M2c, M2e, and M2f, each extending in the second direction Y and spaced apart from each other in the first direction X. For example, the width of the wiring pattern M2f in the first direction X may be greater than the width of each of the wiring patterns M2a, M2c, and M2e in the first direction X, but is not limited thereto. The third frontside wiring layer M3 may include a wiring line M3a extending in the first direction X.

[0094] According to some embodiments, the electronic fuse 51 may receive a bit line BL signal via BSPDN. For example, a through via THV1 may be arranged on the back pattern 52a and may pass through the substrate SUB in the vertical direction Z. The first terminal 51a may be electrically connected to the back pattern 52a via the first through via VA and the through via THV1. Thus, the first terminal 51a may be electrically connected to the bit line BL via the first through via VA, the through via THV1, and the back pattern 52a, and may receive a bit line BL signal. For example, a first through via VA arranged below the first terminal 51a may have a greater width in the first direction X than other first through vias VA, but the present disclosure is not limited thereto.

[0095] For example, during a programming operation of an electronic fuse bit cell, a fuse source voltage Vfs having a high voltage level may be applied to the electronic fuse 51 via the bit line BL. According to some embodiments, the fuse source voltage Vfs having a high voltage level may be applied to the backside pattern 52a via the BSPDN. Here, since the distance between other interconnects, such as the first to third frontside wiring layers M1, M2, and M3 and the backside pattern 52a is relatively large, the parasitic capacitance between the backside pattern 52a and the other wirings may be reduced. Therefore, during a programming operation of the electronic fuse bit cell, the performance of the integrated circuit 50 may be improved.

[0096] According to some embodiments, the integrated circuit 50 can electrically connect the electronic fuse 51 to the drain region DR of the transistor via the FSPDN. For example, the wiring line M3a included in the third front side wiring layer M3 can be used as an interconnect for connecting between the electronic fuse 51 and the drain region DR of the transistor. The second terminal 51c can be electrically connected to the drain region DR of the transistor via the FSPDN including the first to third vias VA, V1 and V2, the first to third front side wiring layers M1, M2 and M3, and the contact CA.

[0097] According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via BSPDN. The backside pattern 52b may be arranged below the source / drain region SD and may extend, for example, in the first direction X. The backside contact BCA may be arranged on the backside pattern 52b and may pass through the substrate SUB along the vertical direction Z. The source region SS of the transistor may be electrically connected to the backside pattern 52b via the backside contact BCA, and thus may receive a ground voltage VSS via the backside contact BCA and the backside pattern 52b.

[0098] Fig.16 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.17 According to some embodiments, Fig.16 A cross-sectional view of the integrated circuit taken along line X7-X7'.

[0099] exist Fig.16 and Fig.17 In the embodiment, the integrated circuit 50a may correspond to Fig.14 and Fig.15 . The third front side wiring layer M3 may include wiring lines M3a and M3b. For example, the wiring lines M3a and M3b may extend in the first direction x, respectively, and may be spaced apart from each other in the second direction y. The second front side wiring layer M2 may include wiring patterns M2a to M2f. The wiring patterns M2a, M2c, and M2e may be electrically connected to the wiring line M3a via the third through hole V2.

[0100] According to some embodiments, the electronic fuse 51 may receive a bit line BL signal via BSPDN, and the integrated circuit 50a may electrically connect the electronic fuse 51 to the drain region DR of the transistor via FSPDN. According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via FSPDN. For example, the wiring line M3b included in the third front side wiring layer M3 may receive a ground voltage VSS and may correspond to a power rail that supplies a power supply voltage to the source region SS. The wiring patterns M2a, M2c, and M2e may be electrically connected to the wiring line M3a via the third through hole V2. The wiring pattern M2f may be electrically connected to the second terminal 51c via the second through hole V1. The wiring patterns M2b and M2d may be electrically connected to the wiring line M3b via the third through hole V2, and may receive the ground voltage VSS from the third through hole V2 and the wiring line M3b.

[0101] Fig.18 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.19 According to some embodiments, Fig.18 A cross-sectional view of the integrated circuit taken along line X8-X8'.

[0102] exist Fig.18 and Fig.19 , the integrated circuit 50b may correspond to Fig.16 and Fig.17 . The through vias THV may include through vias THV1 and THV2. The first front wiring layer M1 may include a front pattern M1a extending in the first direction X. The first back wiring layer BM1 may include back patterns 52a and 52c.

[0103] According to some embodiments, the electronic fuse 51 may receive a bit line BL signal via BSPDN, and the integrated circuit 50b may electrically connect the electronic fuse 51 to the drain region DR of the transistor via FSPDN. According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via FSPDN and BSPDN. The front side pattern M1a may be electrically connected to the back side pattern 52c via the first via VA and the through via THV2. Moreover, the front side pattern M1a may be connected to the wiring patterns M2b and M2d included in the second front side wiring layer M2 via the second via V1. Thus, the source region SS may receive the ground voltage VS via the back side pattern 52c, the through via THV2, the first via VA, the front side pattern M1a, the second via V1, the wiring patterns M2b and M2d, the first via VA, and the contact CA.

[0104] Fig. 20 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.21 According to some embodiments, Fig. 20 A cross-sectional view of the integrated circuit taken along line X9-X9'.

[0105] exist Fig. 20 and Fig.21 , the integrated circuit 50c may correspond to Fig.14 and Fig.15 . The through via THV may include through vias THV1 and THV3. The first backside wiring layer BM1 may include backside patterns 52a and 52d. The second frontside wiring layer M2 may include wiring patterns M2b and M2d, and the third frontside wiring layer M3 may include wiring lines M3c.

[0106] According to some embodiments, the electronic fuse 51 may receive a bit line BL signal via BSPDN. According to some embodiments, the integrated circuit 50c may electrically connect the electronic fuse 51 to the drain region DR of the transistor via BSPDN. For example, the backside pattern 52d may be used as an interconnect for connecting the electronic fuse to the drain region DR of the transistor. The second terminal 51c of the electronic fuse 51 may be electrically connected to the backside pattern 52d via the first via VA and the through via THV3. The backside pattern 52d may be electrically connected to the drain region DR via the backside contact BCA.

[0107] According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via FSPDN. For example, the wiring line M3c included in the third front side wiring layer M3 may extend in the first direction X and may be arranged above the source / drain region SD. The wiring patterns M2b and M2d included in the second front side wiring layer M2 may extend in the second direction Y, respectively, and may be spaced apart from each other in the first direction X. The source region SS may receive a ground voltage VSS via the contact CA, the first to third vias VA, V1 and V2, the first front side wiring layer M1, the wiring patterns M2b and M2d, and the wiring line M3c.

[0108] Fig. 22 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.23 According to some embodiments, Fig. 22 A cross-sectional view of the integrated circuit taken along line X10-X10', and Fig.24 According to some embodiments, Fig. 22 A cross-sectional view of the integrated circuit taken along line X11-X11'.

[0109] exist Figure 22 to Figure 24 , the integrated circuit 50d may correspond to Fig.16 and Fig.17. The through vias THV may include through vias THV1, THV3, and THV4. The first backside wiring layer BM1 may include backside patterns 52a and 52e, and the first frontside wiring layer M1 may include a frontside pattern M1b. The second frontside wiring layer M2 may include wiring patterns M2a to M2e extending in the second direction Y, and the third frontside wiring layer M3 may include a wiring line M3c.

[0110] According to some embodiments, the electronic fuse 51 may receive a bit line BL signal via BSPDN. According to some embodiments, the integrated circuit 50d may electrically connect the electronic fuse 51 to the drain region DR of the transistor via BSPDN and FSPDN. For example, the second terminal 51c of the electronic fuse 51 may be electrically connected to the back pattern 52e via the first via VA and the through via THV3. The back pattern 52e is electrically connected to the front pattern M1b via the through via THV4 and the first through via VA, and the front pattern M1b may be connected to the wiring patterns M2a, M2c, and M2e via the second through via V1. Thus, the drain region DR may be electrically connected to the second terminal 51c via the through vias THV3 and THV4 and the wiring patterns M2a, M2c, and M2e.

[0111] According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via FSPDN. For example, the wiring line M3c included in the third front side wiring layer M3 may extend in the first direction X and may be arranged above the source / drain region SD. The wiring patterns M2b and M2d included in the second front side wiring layer M2 may extend in the second direction Y, respectively, and may be spaced apart from each other in the first direction X. The source region SS may receive a ground voltage VSS via the contact CA, the first to third vias VA, V1 and V2, the first front side wiring layer M1, the wiring patterns M2b and M2d, and the wiring line M3c.

[0112] Fig.25 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.26 According to some embodiments, Fig.25 A cross-sectional view of the integrated circuit taken along line X12-X12'.

[0113] exist Fig.25 and Fig.26, the integrated circuit 60 may include an active region RX, a gate line GT, a contact CA, first to third vias VA, V1 and V2, first to third front wiring layers M1, M2 and M3, a first back wiring layer BM1, and a through-hole THV. The through-hole THV may include a through-hole THV2, and the first back wiring layer BM1 may include a back pattern 62a. The electronic fuse 61 may include a first terminal 61a, a chain body 61b and a second terminal 61c, and may be arranged in the second front wiring layer M2. The first front wiring layer M1 may include a front pattern M1a extending in the first direction X, the second front wiring layer M2 may also include wiring patterns M2a to M2e, and the third front wiring layer M3 may include wiring lines M3a and M3d.

[0114] In some embodiments, the electronic fuse 61 can receive the bit line BL signal via the FSPDN. For example, the first terminal 61a can be connected to the wiring line M3d via the third via V2, and the wiring line M3d can be connected to the bit line BL to receive the bit line BL signal. Thus, the first terminal 61a can be connected to the bit line BL via the third via V2 and the wiring line M3d, and can receive the bit line BL signal.

[0115] In some embodiments, the integrated circuit 60 can electrically connect the electronic fuse 61 to the drain region DR of the transistor via the FSPDN. For example, the wiring line M3a included in the third front wiring layer M3 can be used as an interconnect for connecting the electronic fuse 61 to the drain region DR. The second terminal 61c can be connected to the wiring line M3a via the third via V2, and the wiring line M3a can be connected to the wiring patterns M2a, M2c and M2e via the second via V2. Thus, the drain region DR can be electrically connected to the second terminal 61c via the contact CA, the first via VA, the first front wiring layer M1, the second via V1, the wiring patterns M2a, M2c and M2e, the third via V2, and the wiring line M3a.

[0116] According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via BSPDN. The backside pattern 62a included in the first backside wiring layer BM1 may receive a ground voltage VSS. The through via THV2 may be arranged on the backside pattern 62a and may pass through the substrate SUB in the vertical direction Z. The front side pattern M1a may be electrically connected to the backside pattern 62a via the first via VA and the through via THV2, and may be electrically connected to the wiring patterns M2b and M2d via the second via V1. Thus, the source region SS may receive a ground voltage VSS from the backside pattern 62a via the wiring patterns M2b and M2d, the front side pattern M1a, and the through via THV2.

[0117] Fig. 27 is an example layout of an integrated circuit according to some implementations. Fig.28 According to some embodiments, Fig. 27 A cross-sectional view of the integrated circuit taken along line X13-X13'.

[0118] exist Fig. 27 and Fig.28 In the embodiment, the integrated circuit 60a may correspond to Fig.25 and Fig.26 A modified example of the integrated circuit 60 of . Compared with the integrated circuit 60, the integrated circuit 60a may further include a backside contact BCA, and the first backside wiring layer BM1 may include a backside pattern 62b. According to some embodiments, the electronic fuse 61 may receive a bit line BL signal via FSPDN. According to some embodiments, the integrated circuit 60a may electrically connect the electronic fuse 61 to the drain region DR of the transistor via FSPDN. According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via BSPDN. The backside pattern 62b may receive the ground voltage VSS, and the backside contact BCA may be arranged on the backside pattern 62b and may pass through the substrate SUB in the vertical direction Z. The source region SS may receive the ground voltage VSS from the backside pattern 62b via the backside contact BCA.

[0119] Fig.29 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.30 According to some embodiments, Fig.29 A cross-sectional view of the integrated circuit taken along line X14-X14'.

[0120] exist Fig.29 and Fig.30 , the integrated circuit 70 may include an active area RX, a gate line GT, a contact CA, first to third vias VA, V1 and V2, first to third front wiring layers M1, M2 and M3, a first back wiring layer BM1, a through-hole THV, and a back contact BCA. The through-hole THV may include through-holes THV2 and THV3. The electronic fuse 71 may include a first terminal 71a, a chain body 71b and a second terminal 71c, and may be arranged in the first front wiring layer M1. The first front wiring layer M1 may also include a front pattern M1a extending in the first direction x. The second front wiring layer M2 may include wiring patterns M2b, M2d and M2g each extending in the second direction Y and spaced apart from each other in the first direction X. The third front wiring layer M3 may include a wiring line M3d. The first back wiring layer BM1 may include back patterns 72a and 72b.

[0121] In some embodiments, the electronic fuse 71 can receive the bit line BL signal via the FSPDN. For example, the first terminal 71a can be connected to the wiring line M3d via the second via V1, the wiring pattern M2g, and the third via V2, and the wiring line M3d can be electrically connected to the bit line BL. Thus, the first terminal 71a can be electrically connected to the bit line BL via the wiring line M3d and can receive the bit line BL signal.

[0122] In some embodiments, the integrated circuit 70 can electrically connect the electronic fuse 71 to the drain region DR of the transistor via the BSPDN. For example, the second terminal 71c can be connected to the backside pattern 72a via the first via VA and the through via THV3, and the backside pattern 72a can be connected to the drain region DR of the transistor via the backside contact BCA. As described above, the second terminal 71c can be electrically connected to the drain region DR via the first via VA, the through via THV3, the backside pattern 72a, and the backside contact BCA.

[0123] In some embodiments, the source region SS of the transistor may receive a ground voltage VSS via BSPDN. For example, the backside pattern 72b may receive a ground voltage VSS and may be electrically connected to the frontside pattern M1a via the through via THV2 and the first through via VA. The frontside pattern M1a may be electrically connected to the wiring patterns M2b and M2d via the second through via V1. Thus, the source region SS of the transistor may receive a ground voltage VSS from the backside pattern 72b via the first through via VA and the second through via V1, the first frontside wiring layer M1 and the second frontside wiring layer M2, and the through via THV2.

[0124] Fig.31 is an example layout of an integrated circuit according to some implementations. Fig.32 According to some embodiments, Fig.31 A cross-sectional view of the integrated circuit taken along line X15-X15'.

[0125] exist Fig.31 and Fig.32 , the integrated circuit 70a may correspond to Fig.29 and Fig.30 A modified example of the integrated circuit 70 of FIG. The through via THV may include through vias THV3 and THV4. The first front wiring layer M1 may further include a front pattern M1b extending in the first direction X, the second front wiring layer M2 may include wiring patterns M2a, M2c, M2e, and M2g, and the third front wiring layer M3 may include a wiring line M3d. The first back wiring layer BM1 may include back patterns 72c and 72d.

[0126] According to some embodiments, the electronic fuse 71 can receive the bit line BL signal via FSPDN, and the integrated circuit 70a can electrically connect the electronic fuse 71 to the drain region DR of the transistor via FSPDN and BSPDN. For example, the backside pattern 72c and the front side pattern M1b can be used as an interconnect for connecting the electronic fuse 71 to the transistor. In detail, the second terminal 71c can be connected to the backside pattern 72c via the first via VA and the through via THV3, and the backside pattern 72c can be connected to the front side pattern M1b via the through via THV4 and the first via VA. The front side pattern M1b can be connected to the wiring patterns M2a, M2c and M2e via the second via V2. As described above, the second terminal 71c can be electrically connected to the drain region DR of the transistor via the first via VA and the second via V1, the through vias THV3 and THV4, the backside pattern 72c, the first front side wiring layer M1 and the second front side wiring layer M2, and the contact CA.

[0127] According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via BSPDN. For example, the backside pattern 72d may receive a ground voltage VSS and may be electrically connected to the source region SS of the transistor via a backside contact BCA. Thus, the source region SS may receive a ground voltage VSS from the backside pattern 72d via the backside contact BCA.

[0128] Fig.33 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.34 According to some embodiments, Fig.33 A cross-sectional view of the integrated circuit taken along line X16-X16'.

[0129] exist Fig.33 and Fig.34 In the embodiment, the integrated circuit 70b may correspond to Fig.31 and Fig.32 . The through vias THV may include through vias THV2, THV3, and THV4. The first front wiring layer M1 may also include front patterns M1a and M1b extending in the first direction X, respectively, the second front wiring layer M2 may include wiring patterns M2a to M2e, and M2g, and the third front wiring layer M3 may include wiring lines M3d. The first back wiring layer BM1 may include back patterns 72b and 72c.

[0130] According to some embodiments, the electronic fuse 71 may receive a bit line BL signal via FSPDN, and the integrated circuit 70b may electrically connect the electronic fuse 71 to the drain region DR of the transistor via FSPDN and BSPDN. According to some embodiments, the source region SS of the transistor may receive a ground voltage VSS via FSPDN and BSPDN. For example, the backside pattern 72b may receive a ground voltage VSS and may be electrically connected to the front side pattern M1a via a through via THV2 and a first through via VA. The front side pattern M1a may be electrically connected to the wiring patterns M2b and M2d via a second through via V1. Thus, the source region SS may receive a ground voltage VSS from the backside pattern 72b via the first front side wiring layer M1 and the second front side wiring layer M2, the first through via VA and the second through via V1, and the through via THV2.

[0131] Fig.35 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.36 According to some embodiments, Fig.35 A cross-sectional view of the integrated circuit taken along line X17-X17'.

[0132] exist Fig.35 and Fig.36 , the integrated circuit 70c may correspond to Fig.29 and Fig.30 . The through via THV may include a through via THV3. The second front side wiring layer M2 may include wiring patterns M2b, M2d, and M2g, and the third front side wiring layer M3 may include wiring lines M3c and M3d. The first back side wiring layer BM1 may include a back side pattern 72a.

[0133] According to some embodiments, the electronic fuse 71 may receive the bit line BL signal via FSPDN, and the integrated circuit 70c may electrically connect the electronic fuse 71 to the drain region DR of the transistor via BSPDN. According to some embodiments, the source region SS of the transistor may receive the ground voltage VSS via FSPDN. For example, the wiring line M3c may receive the ground voltage VSS and may be electrically connected to the wiring patterns M2b and M2d via the third via V2. Thus, the source region SS may receive the ground voltage VSS from the wiring line M3c via the first to third front side wiring layers M1, M2 and M3, the first to third vias VA, V1 and V2, and the contact CA.

[0134] Fig.37 is a diagram showing a layout of an example of an integrated circuit according to some embodiments. Fig.38 According to some embodiments, Fig.37 A cross-sectional view of the integrated circuit taken along line X18-X18'.

[0135] exist Fig.37 and Fig.38 , the integrated circuit 70d may correspond to Fig.29 and Fig.30 . The through vias THV may include through vias THV3 and THV4. The second front side wiring layer M2 may include wiring patterns M2b, M2d, and M2g, and the third front side wiring layer M3 may include wiring lines M3c and M3d. The first back side wiring layer BM1 may include a back side pattern 72c.

[0136] According to some embodiments, the electronic fuse 71 may receive a bit line BL signal via FSPDN, and the integrated circuit 70d may electrically connect the electronic fuse 71 to the drain region DR of the transistor via FSPDN and BSPDN. For example, the second terminal 71c may be connected to the backside pattern 72c via the first via VA and the through via THV3, and the backside pattern 72c may be connected to the front side pattern M1b via the through via THV4 and the first via VA. The front side pattern M1b may be connected to the wiring patterns M2a, M2c, and M2e via the second via V2. As described above, the second terminal 71c may be electrically connected to the drain region DR of the transistor via the first via VA and the second via V1, the through vias THV3 and THV4, the backside pattern 72c, the first front side wiring layer M1 and the second front side wiring layer M2, and the contact CA. According to some embodiments, the source region SS of the transistor may receive the ground voltage VSS via FSPDN.

[0137] FIG. 39A to FIG. 39D is a diagram showing examples of elements according to some embodiments. For example, Fig.39A FinFET 80a is shown, Fig.39B A gate-all-around field effect transistor (GAAFET) 80b is shown. Fig.39C A multi-bridge channel field effect transistor (MBCFET) 80c is shown, and Fig.39D A vertical field effect transistor (VFET) 80d is shown. For ease of illustration, FIG. 39A to FIG. 39C shows a state in which one of the two source / drain regions is removed, Fig.39D A cross section of the VFET 80d taken by a plane parallel to the plane in which the second direction Y and the vertical direction Z lie and passing through the channel CH of the VFET 80d is shown.

[0138] exist Fig.39A In some embodiments, the FinFET 80a may be formed of a fin-shaped active pattern extending in the first direction X between a device isolation layer STI and a gate G extending in the second direction Y. Source / drain S / D may be formed on both sides of the gate G, respectively, and thus, the source and the drain may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. In some embodiments, the FinFET 80a may be formed of a plurality of active patterns and the gate G spaced apart from each other in the second direction Y.

[0139] exist Fig.39B In the embodiment, the GAAFET 80b may be formed of active patterns, i.e., nanowires, which are spaced apart from each other in the vertical direction Z and extend in the first direction X, and a gate G which extends in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, respectively, and thus, the source and the drain may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. The number of nanowires included in the GAAFET 80b is not limited. Fig.39B The example limitations shown in .

[0140] exist Fig.39C In the embodiment, the MBCFET 80c may be formed of active patterns, i.e., nanosheets, which are spaced apart from each other in the vertical direction Z and extend in the first direction X, and a gate G which extends in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, respectively, and thus, the source and the drain may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. The number of nanosheets included in the MBCFET 80c is not limited to Fig.39C The example shown in .

[0141] exist Fig.39D , the VFET 80d may include a top source / drain T_S / D and a bottom source / drain B_S / D spaced apart from each other in a vertical direction Z, with a channel CH disposed therebetween. The VFET 80d may include a gate G surrounding the channel CH between the top source / drain T_S / D and the bottom source / drain B_S / D. An insulating layer may be formed between the channel CH and the gate G.

[0142] However, the transistor according to some embodiments is not limited to the above structure. For example, the integrated circuit may include a ForkFET having a structure in which the N-type transistor and the P-type transistor are close to each other by separating the nanosheet for the P-type transistor and the nanosheet for the N-type transistor by means of a dielectric wall. Moreover, the integrated circuit may include a bipolar junction transistor and a FET, such as a complementary FET (CFET), a negative capacitance FET (NCFET), a carbon-nanotube FET (CNT FET), etc.

[0143] Fig.40 is a flow chart illustrating an example of a method of manufacturing an integrated circuit according to some embodiments. Fig.40 In the method of manufacturing an integrated circuit IC, a standard cell may be included and may include a plurality of operations S10, S30, S50, S70, and S90. A cell library (or standard cell library) D12 may include information about the standard cell, such as functions, characteristics, layout, etc. A design rule D14 may include regulations that the layout of the integrated circuit IC must comply with. For example, the design rule D14 may include regulations about the space between patterns in the same layer, the minimum width of the pattern, the routing direction of the wiring layer, etc.

[0144] In operation S10, a logic synthesis operation for generating netlist data D13 from register transfer level (RTL) data D11 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may refer to a cell library D12 from RTL data D11 written in a hardware description language (HDL), such as a Very High Speed ​​Integrated Circuit (VHSIC) hardware description language (VHDL) or Verilog to perform logic synthesis, thereby generating netlist data D13 including a bitstream or a netlist. Netlist data D13 may correspond to inputs for placement and routing described below.

[0145] In operation S30, standard cells may be placed. For example, a semiconductor design tool (e.g., a P&R tool) may place standard cells used in the netlist data D13 with reference to the cell library D12. In some embodiments, the semiconductor design tool may place standard cells on a row extending along the X-axis direction or the Y-axis direction, and the placed standard cells may receive power supply from a power rail extending along a boundary of the row.

[0146] In operation S50, the pins of the standard cell can be routed. For example, the semiconductor design tool can generate an interconnect for electrically connecting the output pin to the input pin of the arranged standard cell, and generate layout data D15 defining the arranged standard cell and the generated interconnect. The interconnect may include a pattern of a through hole in a through hole layer and / or a wiring layer. The wiring layer may include a front side wiring layer arranged on the upper portion of the front surface of the substrate and a back side wiring layer arranged on the rear surface of the substrate. The layout data D15 may have a format such as GDSII, and may include geometric information about the cell and the interconnect. The semiconductor design tool may refer to the design rule D14 during the pin routing of the cell. The layout data D15 may correspond to the output from placement and routing. A separate operation S50 or operations S30 and S50 may be referred to as a method for designing an integrated circuit.

[0147] like Figures 1 to 38 As shown, the integrated circuit can implement the electronic fuse bit cell by using the front wiring line and the back wiring line. In some embodiments, the electronic fuse included in the electronic fuse bit cell can be arranged on the back wiring layer. In some embodiments, the wiring for the connection between the electronic fuse and the transistor included in the electronic fuse bit cell can be implemented by the front wiring layer and / or the back wiring layer. In some embodiments, the power rail for providing the power supply voltage to the transistor included in the electronic fuse bit cell can be implemented by the front wiring layer and / or the back wiring layer. In some embodiments, the bit line connected to the electronic fuse included in the electronic fuse bit cell can be implemented by the front wiring layer and / or the back wiring layer.

[0148] According to some embodiments, the area for implementing an electronic fuse bit cell can be reduced, and the IR drop of a signal applied to the electronic fuse bit cell can be reduced. For example, the electronic fuse bit cell can reduce parasitic resistance and parasitic capacitance by reducing bit line signals, power supply voltages, and / or fuse source voltages from front-side wiring layers and back-side wiring layers, thereby increasing the speed of operation on the electronic fuse bit cell and thereby improving the performance of the integrated circuit.

[0149] Moreover, according to some embodiments, the integrated circuit can reduce the wiring complexity of the front wiring layer by using the back wiring line included in the back wiring layer, and the PPA of the integrated circuit can be improved. Moreover, by increasing the width of the front wiring line included in the front wiring layer arranged above the electronic fuse bit cell, the IR drop of the signal applied to the front wiring can be further reduced. Moreover, the integrated circuit can further improve the PPA of the integrated circuit by having a DBC structure in which the source / drain region of the transistor is directly connected to the back wiring line of the back wiring layer.

[0150] In operation S70, an operation of making a mask may be performed. For example, optical proximity correction (OPC) for correcting distortion in photolithography such as refraction caused by characteristics of light may be applied to the layout data D15. A pattern on the mask may be defined to form a pattern arranged on a plurality of layers based on the data to which the OPC is applied, and at least one mask for forming a pattern in each of the plurality of layers may be made.

[0151] In operation S90, an operation of manufacturing an integrated circuit IC may be performed. For example, multiple layers may be patterned by using at least one mask made in operation S70, and then the integrated circuit IC may be manufactured. The front-end-of-line (FEOL) process may include, for example, operations of planarizing and cleaning the wafer, operations of forming a groove, operations of forming a well, operations of forming a gate line, and operations of forming a source and a drain. Through the FEOL, various components, such as transistors, capacitors, resistors, etc. may be formed on a substrate. In addition, the back-end process (BEOL) may include, for example, silicide of gate, source and drain regions, operations of adding dielectric substances, planarization operations, operations of forming holes, operations of adding a metal layer, operations of forming a through hole, and operations of forming a passivation layer, etc. Through the BEOL, various components, such as transistors, capacitors, resistors, etc. may be connected to each other. In some embodiments, a middle process (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed on various components. Next, the integrated circuit IC may be packaged in a semiconductor package and may be used as a component in various applications.

[0152] Fig.41 is a block diagram of an example of a system on a chip according to some embodiments. Fig.41 In the embodiment of the present invention, a system-on-chip (SoC) 210 may represent an integrated circuit on which components of a computing system or another electronic system are integrated. For example, an application processor (AP) as an example of SoC 210 may include a processor and components for other functions. SoC 210 may include a core 211, a digital signal processor (DSP) 212, a graphic processing unit (GPU) 213, an internal memory 214, a communication interface 215, and a memory interface 216. The components of SoC 210 may communicate with each other via a bus 217.

[0153] The core 211 may process instructions and may control the operation of the elements included in the SoC 210. For example, the core 211 may drive an operating system and may run an application on the operating system by processing a series of instructions. The DSP 212 may generate useful data by processing digital signals, such as digital signals provided from the communication interface 215. The GPU 213 may generate data for an image output by a display device based on image data provided from the internal memory 214 or the memory interface 216, or may encode the image data. In some embodiments, the IC described above with reference to the accompanying drawings may be included in the core 211, the DSP 212, the GPU 213, and / or the internal memory 214.

[0154] The internal memory 214 may store data required for the operation of the core 211, the DSP 212, and the GPU 213. The communication interface 215 may provide a communication network or interface for one-to-one communication. The memory interface 216 may provide an interface with respect to an external memory of the SoC 210, such as a DRAM, a flash memory, and the like.

[0155] Fig.42 is a block diagram of an example of a computing system including a memory for storing programs according to some implementations. Fig.42 According to some embodiments, at least some of the methods for designing an IC, such as the operations in the above flowchart, may be executed in a computing system 220. The computing system 220 may include a processor 221, an I / O device 222, a network interface 223, a random access memory (RAM) 224, a read only memory (ROM) 225, and a storage device 226. The processor 221, the I / O device 222, the network interface 223, the RAM 224, the ROM 225, and the storage device 226 may be connected to a bus 227 and may communicate with each other via the bus 227.

[0156] The processor 221 may be referred to as a processing unit and may include at least one core capable of executing any instruction set, such as a microprocessor, an AP, a DSP, and a GPU. For example, the processor 221 may be configured to access a memory, namely, a RAM 224 or a ROM 225, via a bus 227 and execute instructions stored in the RAM 224 or the ROM 225. The RAM 224 may store a program 224_1 or at least a portion thereof for a method for designing an IC according to some embodiments, and the program 224_1 may allow the processor 221 to execute at least some of the methods for designing an IC, such as reference 224_1. Fig.40 The operations included in the method are shown.

[0157] When the computing system 220 is powered off, the data stored in the storage device 226 is not erased. According to some embodiments, the memory 226 may store the program 224_1, and before the program 224_1 is executed by the processor 221, the program 224_1 or at least a portion thereof may be loaded from the storage device 226 to the RAM 224. Alternatively, the storage device 226 may store a file made using a program language, and the program 224_1 generated from the file by a compiler, etc., or at least a portion of the program 224_1 may be loaded from the file to the RAM 224. Moreover, the memory 226 may store a database (DB) 226_1, and the database 226_1 may include information required for designing an integrated circuit, such as information about Fig.40 The information of the designed blocks, cell library D12 and / or design rules D14 shown in FIG.

[0158] The memory 226 may also store data to be processed by the processor 221 / has been processed by the processor. That is, according to the program 224_1, the processor 221 may generate data by processing the data stored in the storage device 226 and store the generated data in the storage device 226. For example, the storage device 226 may store Fig.40 The RTL data D11, the netlist data D13, or the layout data D15 shown in FIG.

[0159] The I / O device 222 may include input devices such as a keyboard, a pointing device, etc., and may include output devices such as a display device, a printer, etc. For example, by using the I / O device 222, a user may trigger the execution of the program 224_1 by using the processor 221, inputting Fig.40 The RTL data D11 and / or netlist data D13 shown in FIG. Fig.40 The network interface 223 may provide access to a network external to the computing system 220. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other form of links.

[0160] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of the claimed protection. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Moreover, although features may be described above as working in certain combinations, one or more features from a combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variant of a sub-combination.

Claims

1. An integrated circuit, comprising: a first backside wiring layer, the first backside wiring layer being located on the backside of the substrate; An electronic fuse bit cell, the electronic fuse bit cell comprising: an electronic fuse; a transistor, the transistor being located on the front side of the substrate; and a first backside contact, the first backside contact being configured to pass through the substrate in a vertical direction and electrically connect the electronic fuse to the transistor, Wherein, the electronic fuse comprises: a first terminal electrically connected to a bit line; a second terminal electrically connected to the first backside contact; and A chain body is located between the first terminal and the second terminal, and wherein the first terminal, the second terminal, and the chain body are included in the first backside wiring layer.

2. The integrated circuit of claim 1 , further comprising: a second backside wiring layer, the second backside wiring layer being located below the first backside wiring layer; as well as a backside through hole configured to extend between the first backside wiring layer and the second backside wiring layer in the vertical direction, The first terminal is electrically connected to the bit line via the backside via and the second backside wiring layer.

3. The integrated circuit of claim 1 , further comprising: a backside wiring layer, the backside wiring layer being located between the back side of the substrate and the first backside wiring layer; as well as a backside through hole extending along the vertical direction between the backside wiring layer and the first backside wiring layer, Wherein, the second terminal is electrically connected to the first backside contact via the backside through hole and the backside wiring layer.

4. The integrated circuit of claim 1 , further comprising a front side wiring layer located above the front side of the substrate, in, A source of the transistor is configured to receive a power supply voltage via the front-side wiring layer.

5. The integrated circuit according to claim 1, in, The first backside wiring layer further includes a first backside pattern configured to receive a power supply voltage, The integrated circuit further comprises a second back side contact, the second back side contact is located on the first back side pattern and passes through the substrate along the vertical direction, and The source of the transistor is configured to receive the power supply voltage via the second backside contact and the first backside pattern.

6. The integrated circuit according to claim 5, in, The first backside wiring layer further includes a second backside pattern connected to the first backside contact, Wherein, the integrated circuit further comprises: a second backside wiring layer, the second backside wiring layer being located below the first backside wiring layer; a first backside through-hole configured to extend in the vertical direction between the second terminal and the second backside wiring layer; and a second backside through hole configured to extend in the vertical direction between the second backside pattern and the second backside wiring layer, and The second terminal is electrically connected to the first backside contact via the first backside through hole, the second backside wiring layer, the second backside through hole, and the second backside pattern.

7. An integrated circuit, comprising: a first front-side wiring layer, the first front-side wiring layer being located above the front side of the substrate; a backside wiring layer located on the backside of the substrate and including a first backside pattern; a first through-via, the first through-via being located on the first backside pattern and configured to pass through the substrate in a vertical direction; as well as an electronic fuse bit cell comprising an electronic fuse and a transistor on the front side of the substrate, Wherein, the electronic fuse comprises: a first terminal electrically connected to the first through via and electrically connected to a bit line via the first through via and the first backside pattern; a second terminal electrically connected to the transistor; and A chain body is located between the first terminal and the second terminal, and wherein the first terminal, the second terminal, and the chain body are included in the first front-side wiring layer.

8. The integrated circuit according to claim 7, in, The backside wiring layer further includes a second backside pattern configured to receive a power supply voltage, and The integrated circuit further includes a first backside contact, which is configured to pass through the substrate along the vertical direction and electrically connect the second backside pattern to a source of the transistor.

9. The integrated circuit according to claim 7, in, The first front wiring layer further includes a front pattern, the front pattern being located above the source of the transistor, and The source of the transistor is configured to receive a power supply voltage from the front pattern.

10. The integrated circuit according to claim 7, in, The first front side wiring layer further includes: a first front side pattern, the first front side pattern being located above the source of the transistor; and a second front side pattern, The backside wiring layer further includes a third backside pattern, and the third backside pattern is configured to receive a power supply voltage. Wherein, the integrated circuit further comprises: a second through via located on the third backside pattern, the second through via being configured to pass through the substrate in the vertical direction and electrically connect the third backside pattern to the second frontside pattern; and a second front side wiring layer, the second front side wiring layer being above the first front side wiring layer and electrically connecting the first front side pattern to the second front side pattern, and wherein the source of the transistor is configured to receive the power supply voltage via the first front side pattern, the second front side wiring layer, the second front side pattern, the second through-via and the third back side pattern.

11. The integrated circuit according to claim 7, in, The first front wiring layer further includes a front pattern, wherein the front pattern is located above the drain of the transistor. The integrated circuit further comprises a second front-side wiring layer, the second front-side wiring layer is located above the first front-side wiring layer, and The drain of the transistor is electrically connected to the second terminal via the second front wiring layer and the front pattern.

12. The integrated circuit according to claim 7, in, The backside wiring layer further includes a fourth backside pattern, and Wherein, the integrated circuit further comprises: a third through via configured to pass through the substrate in the vertical direction and electrically connect the fourth backside pattern to the second terminal; and A second backside contact is located on the fourth backside pattern and is configured to electrically connect the fourth backside pattern to a drain of the transistor.

13. The integrated circuit according to claim 7, in, The first front wiring layer further includes a front pattern, Wherein, the backside wiring layer further includes a fifth backside pattern, Wherein, the integrated circuit further comprises: a third through via configured to pass through the substrate in the vertical direction and electrically connect the fifth backside pattern to the second terminal; and A fourth through-via is configured to pass through the substrate along the vertical direction and electrically connect the fifth back-side pattern to the front-side pattern, and wherein the drain of the transistor is electrically connected to the second terminal via the front-side pattern, the third through-via, the fifth back-side pattern and the fourth through-via.

14. An integrated circuit, comprising: a first front-side wiring layer, the first front-side wiring layer being located above the front side of the substrate; a backside wiring layer located on the backside of the substrate and including a first backside pattern; a first through via hole, the first through via hole being arranged on the first backside pattern and passing through the substrate in a vertical direction; as well as an electronic fuse bit cell comprising an electronic fuse and a transistor arranged on the front side of the substrate, Wherein, the electronic fuse comprises: a first terminal electrically connected to a bit line; a second terminal electrically connected to the transistor via the first backside pattern and the first through via; and A chain body is located between the first terminal and the second terminal, and wherein the first terminal, the second terminal, and the chain body are included in the first front-side wiring layer.

15. The integrated circuit according to claim 14, in, The backside wiring layer further includes a second backside pattern, Wherein, the integrated circuit further comprises: a second through-via located on the second backside pattern and passing through the substrate in the vertical direction; and a back side contact, the back side contact being located on the first back side pattern, wherein a source of the transistor is configured to receive a power supply voltage via the second backside pattern and the second through via, and The drain of the transistor is electrically connected to the second terminal via the backside contact, the first backside pattern and the first through via.

16. The integrated circuit according to claim 14, in, The backside wiring layer further includes a third backside pattern, and Wherein, the integrated circuit further comprises: a third through via hole located on the first backside pattern and passing through the substrate in the vertical direction; and a back side contact, the back side contact being located on the third back side pattern, wherein a source of the transistor is configured to receive a power supply voltage via the third backside pattern and the backside contact, and The drain of the transistor is electrically connected to the second terminal via the third through via, the first backside pattern, and the first through via.

17. The integrated circuit according to claim 14, in, The backside wiring layer further includes a second backside pattern, Wherein, the integrated circuit further comprises: a second through-via located on the second backside pattern and passing through the substrate in the vertical direction; and a third through-via, the third through-via being located on the first back-side pattern and passing through the substrate along the vertical direction; wherein a source of the transistor is configured to receive a power supply voltage via the second backside pattern and the second through via, and The drain of the transistor is electrically connected to the second terminal via the first through via, the first backside pattern, and the third through via.

18. The integrated circuit of claim 14, further comprising: a second front-side wiring layer, the second front-side wiring layer being located above the first front-side wiring layer; as well as a back side contact, the back side contact being located on the first back side pattern, wherein the source of the transistor is configured to receive a power supply voltage via the second front-side wiring layer, and The drain of the transistor is electrically connected to the second terminal via the backside contact, the first backside pattern and the first through via.

19. The integrated circuit of claim 14, further comprising: a second front-side wiring layer, the second front-side wiring layer being located above the first front-side wiring layer; as well as a third through-hole, the third through-hole being located on the first back-side pattern and passing through the substrate in a vertical direction; wherein the source of the transistor is configured to receive a power supply voltage via the second front-side wiring layer, and The drain of the transistor is electrically connected to the second terminal via the first and third through vias and the first backside pattern.

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