DC bus anti-interference control method and system

Abstract

The invention relates to the technical field of DC bus anti-interference, in particular to an anti-interference control method and system for a DC bus. The DC bus anti-interference control method comprises the following steps: acquiring a first three-phase current actual value, a DC voltage reference value, a DC voltage actual value and a DC current actual value; determining a second three-phase current actual value corresponding to the first three-phase current actual value; determining a target current reference value according to the direct-current voltage reference value and the direct-current voltage actual value; determining a target disturbance parameter according to the DC voltage actual value and the DC current actual value; based on the second three-phase current actual value, the target current reference value, the target disturbance parameter, the target current reference value and the target disturbance parameter, calculating a value function corresponding to each switch state of the active front end; the active front end has eight different switching states; determining the switching state corresponding to the minimum value function as a target switching state; and controlling the switching state of the active front end based on the target switching state. And the anti-interference capability of the direct-current bus is improved.

Description

Technical Field

[0001] The present application relates to the technical field of DC bus anti-interference, and in particular to a DC bus anti-interference control method and system. Background Art

[0002] In the context of the growing energy demand today, efficient and reliable user-side low-voltage DC distribution systems have become a hot topic of research. Low-voltage DC distribution systems have developed rapidly in recent years due to their high efficiency, easy integration of distributed power generation, and intelligent management. The active front end (AFE) is the core component of the low-voltage DC distribution system. It builds a stable DC bus for distributed power sources and loads, and its working state directly affects the efficiency of the system. At present, the active front end faces a severe challenge in practical applications, that is, how to keep the DC bus voltage stable when the load changes transiently. When the load is added or removed, it will cause a temporary imbalance in the input and output power, resulting in significant fluctuations in the DC bus voltage. This fluctuation phenomenon will cause the power devices connected in parallel to the DC bus to exceed the normal operating voltage range, thereby working under abnormal conditions, seriously affecting the system reliability, and even causing the equipment to fail to operate.

[0003] In the related art, a dynamic mathematical model of the inductor-side current is established, the value functions corresponding to various switch states are compared, and the switch state that minimizes the value function is selected to control the on and off of the switch device to accurately track the current reference value.

[0004] However, although the existing technology can accurately track the current reference value, it fails to fully consider the instantaneous change of the load when selecting the switch state according to the value function. Therefore, when the load is connected or removed, the selected switch state cannot adapt to such changes, resulting in a short-term power imbalance in the system and causing significant fluctuations in the bus voltage. Summary of the invention

[0005] The embodiment of the present application provides an anti-interference control method and system for a DC bus, which observes the active front-end load current by designing an adaptive cascade expanded state observer, and integrates the load current into the value function of the model predictive control strategy through power conversion, so that the selected switching state has anti-interference ability, thereby suppressing the significant fluctuation of the DC bus voltage.

[0006] In some embodiments, a disturbance-resistant control method for a DC bus is provided, and the disturbance-resistant control method for a DC bus is applied to an disturbance-resistant control system of a DC bus, and the disturbance-resistant control system of the DC bus includes an active front end and an AC power grid; the disturbance-resistant control of the DC bus includes: obtaining a first three-phase current actual value, a DC voltage reference value, a DC voltage actual value, and a DC current actual value of the AC power grid; the first three-phase current actual value is located in the abc coordinate system; determining a second three-phase current actual value corresponding to the first three-phase current actual value; the second three-phase current actual value is located in the αβ coordinate system; determining a target current reference value according to the DC voltage reference value and the DC voltage actual value; the target current reference value is located in the αβ coordinate system; determining a target disturbance parameter according to the DC voltage actual value and the DC current actual value; the target disturbance parameter is located in the αβ coordinate system; calculating a value function corresponding to each switch state of the active front end based on the second three-phase current actual value, the target current reference value and the target disturbance parameter, the target current reference value and the target disturbance parameter; the active front end has eight different switch states; determining the switch state corresponding to the minimum value function as the target switch state; and controlling the switch state of the active front end based on the target switch state.

[0007] The anti-disturbance control method for the DC bus provided in the embodiment of the present application is adopted, and the actual value of the second three-phase current, the target current reference value and the target disturbance parameter located in the αβ coordinate system are respectively determined to calculate and determine the value function corresponding to each switch state of the active front end. The target switch state corresponding to the minimum value function is the switch state with the least impact on the DC bus when the load is connected or removed. Therefore, after controlling the switch state of the active front end according to the target switch state, the impact of the load on the DC bus can be minimized, and the power imbalance problem of the DC bus can be reduced. In this way, by integrating the target disturbance parameter into the value function, and the target disturbance parameter is obtained by observing the load current change by the observer, so as to realize the value function constructed in combination with the target disturbance parameter, the switch state of the active front end is regulated to cope with the interference caused by the intervening load. Without losing the steady-state power quality, the anti-interference ability of the DC bus voltage in response to load changes is improved.

[0008] Optionally, the anti-disturbance control system of the DC bus also includes a PI controller, which determines a target current reference value based on a DC voltage reference value and an actual DC voltage value, including: calculating the difference between the DC voltage reference value and the actual DC voltage value to determine an error signal; inputting the error signal into the PI controller to determine a first sub-current reference value; the first sub-current reference value is located on the d-axis of a dq coordinate system; determining a first current reference value based on the first sub-current reference value and the second sub-current reference value; the first current reference value is located in the dq coordinate system; the second sub-current reference value is a preset value and is located on the q-axis of the dq coordinate system; determining a target current reference value based on an inverse Park transform and the first current reference value; the target current reference value is located in the αβ coordinate system.

[0009] Optionally, the anti-disturbance control system of the DC bus further includes an adaptive cascade extended state observer, which determines the target disturbance parameter according to the actual value of the DC voltage and the actual value of the DC current, including: inputting the actual value of the DC voltage and the actual value of the DC current into the adaptive cascade extended state observer to determine the total disturbance observation value; based on the total disturbance observation value, the voltage stabilizing capacitor value and the actual value of the DC voltage, calculating and determining the first sub-disturbance parameter d d (k); the first sub-disturbance parameter is located on the d-axis of the dq coordinate system; based on the first disturbance parameter and the second sub-disturbance parameter, the first disturbance parameter is determined; the first disturbance parameter is located in the dq coordinate system; the second sub-disturbance parameter is a preset value and is located on the q-axis of the dq coordinate system; based on the inverse Park transform and the first disturbance parameter, the target disturbance parameter is determined; the target disturbance parameter is located in the αβ coordinate system.

[0010] Optionally, the adaptive cascade expanded state observer includes a first observer, a second observer and a third observer; the actual value of the DC voltage and the actual value of the DC current are input into the adaptive cascade expanded state observer to determine the total disturbance observation value, including: inputting the actual value of the DC voltage and the actual value of the DC current into the first observer to determine the first disturbance observation value; inputting the actual value of the DC voltage, the actual value of the DC current and the first disturbance observation value into the second observer to determine the second disturbance observation value; inputting the actual value of the DC voltage, the actual value of the DC current, the first disturbance observation value and the second disturbance observation value into the third observer to determine the third disturbance observation value; calculating the sum of the first disturbance observation value, the second disturbance observation value and the third disturbance observation value to determine the total disturbance observation value.

[0011] Optionally, the adaptive cascade extended state observer is as shown in (1) to (7):

[0012]

[0013] in, C is the voltage stabilizing capacitor value, u is the actual value of DC current, y is the actual value of DC voltage, is the total disturbance observation value, is the first perturbation observation, is the second perturbation observation, is the third perturbation observation, γ 1j is the first gain parameter, γ 2j is the second gain parameter, j∈(1,2,3), γ 1j and γ 2j is determined based on the error signal.

[0014] Optionally, determining the first gain parameter and the second gain parameter according to the error signal and the first preset formula includes:

[0015] The first preset formula is:

[0016]

[0017] Calculate the DC voltage reference value V ref And the actual value of DC voltage v dc The difference between the two determines the error signal |V ref -v dc |; When the error signal is within the steady-state threshold range, ω 0 =G 1 ; When the error signal is outside the steady-state threshold range, ω 0 =G 2 Among them, G 1 is the first gain setting value, G 2 is the second gain setting value, G 1 <G 2 .

[0018] Optionally, the anti-disturbance control method for the DC bus further includes: 0 When the value of changes, maintain ω 0 The value of is the preset time after the change.

[0019] Optionally, based on the total disturbance observation value, the voltage stabilizing capacitor value and the actual value of the DC voltage, the first sub-disturbance parameter d is calculated and determined. d (k), including: based on the total disturbance observation and the voltage stabilizing capacitor value C, calculate the load current according to the second preset formula; based on the load current i load And the actual value of DC voltage v dc , according to the third preset formula, calculate the first sub-disturbance parameter d d (k);

[0020] The second preset formula is:

[0021]

[0022] The third preset formula is:

[0023]

[0024] Among them, V gd It is the component of the three-phase grid voltage located on the d-axis in the dq coordinate system.

[0025] Optionally, Among them, Cf pro is the value function, is the target current reference value, i α,β (k+1) is the actual value of the second three-phase current, d α,β (k) is the target disturbance parameter.

[0026] In some embodiments, a disturbance-resistant control system for a DC bus is provided, comprising: a low-voltage DC power distribution system and a controller that are communicatively connected to each other; the low-voltage DC power distribution system comprises an AC power grid, an active front end and a DC bus that are electrically connected to each other; the controller is configured to obtain a first three-phase current actual value, a DC voltage reference value, a DC voltage actual value and a DC current actual value of the AC power grid; the first three-phase current actual value is located in the abc coordinate system; a second three-phase current actual value corresponding to the first three-phase current actual value is determined; the second three-phase current actual value is located in the αβ coordinate system; a target current reference value is determined based on the DC voltage reference value and the DC voltage actual value; the target current reference value is located in the αβ coordinate system; a target disturbance parameter is determined based on the DC voltage actual value and the DC current actual value; the target disturbance parameter is located in the αβ coordinate system; based on the second three-phase current actual value, the target current reference value and the target disturbance parameter, a value function corresponding to each switch state of the active front end is calculated; the active front end has eight different switch states; the switch state corresponding to the minimum value function is determined as the target switch state; based on the target switch state, the switch state of the active front end is controlled.

[0027] It can be understood that the beneficial effects that can be achieved by the technical solution provided by the anti-disturbance control system of the DC bus provided above can be referred to the beneficial effects in the anti-disturbance control method of the DC bus and any of its optional implementations, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 A schematic diagram of the structure of a low-voltage DC power distribution system provided in an embodiment of the present application;

[0030] Figure 2 A structural block diagram of the anti-disturbance control system of the DC bus provided in an embodiment of the present application;

[0031] Figure 3 A flow chart of the anti-disturbance control method for a DC bus provided in an embodiment of the present application;

[0032] Figure 4 The active front-end topology diagram provided for the embodiment of the present application;

[0033] Figure 5 For combination Figure 4 A flowchart of an anti-disturbance control method for a DC bus provided by the illustrated embodiment;

[0034] Figure 6 A schematic diagram of the observation process of the adaptive cascade extended state observer provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of gain parameter adjustment provided in an embodiment of the present application;

[0036] Figure 8 A waveform comparison diagram of steady-state operating conditions at rated power provided in an embodiment of the present application;

[0037] Fig. 9 A waveform comparison diagram of the DC bus voltage after load removal provided in an embodiment of the present application;

[0038] Fig.10 A waveform comparison diagram of the DC bus voltage after load connection provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by ordinary technicians in this field without making creative work all belong to the protection scope of the present application.

[0040] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0041] In addition, in the present application, directional terms such as "upper", "lower", "inner" and "outer" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components placed in the drawings.

[0042] To facilitate understanding of the technical solution of the application, some concepts involved in the application are first explained below.

[0043] Low Voltage DC Distribution System (LVDC) is a power system that distributes electricity in the form of DC. It is mainly used in scenarios where the power supply voltage is low and the power-consuming equipment has a high demand for DC. With the popularization of DC load equipment (such as LED lighting, information technology equipment, industrial control equipment, etc.), low voltage DC distribution systems have gradually gained attention due to their high efficiency and energy saving. Low voltage DC distribution systems usually consist of the following key parts: active front end, DC bus, energy storage device, power electronic converter and protection device.

[0044] Active Front End (AFE) is a control unit implemented through power electronic technology. Its functions mainly include the following aspects: rectification, power factor correction, bidirectional energy flow and harmonic suppression.

[0045] The DC bus is the core part of the entire low-voltage DC power distribution system and is used to transmit and distribute DC power.

[0046] In low-voltage DC power distribution systems, the inner and outer loops of the controller usually describe different feedback loops in the control strategy, with the goal of achieving efficient and stable voltage and power control. Generally speaking, in terms of hierarchy, the outer loop provides reference values ​​(such as target voltage or current) to the inner loop; the inner loop quickly adjusts the actual output of the system according to the instructions of the outer loop. In terms of control objectives, the inner loop focuses on local rapid response and maintaining stable electrical parameters; the outer loop focuses on optimizing the overall performance of the system to achieve global goals.

[0047] To facilitate understanding of the technical solution of the application, the relevant technologies involved in this application are explained below.

[0048] Figure 1 A schematic diagram of the structure of a low-voltage DC power distribution system provided in an embodiment of the present application.

[0049] In the context of the growing energy demand today, efficient and reliable user-side low-voltage DC distribution systems have become a hot research topic. Low-voltage DC distribution systems have developed rapidly in recent years due to their high efficiency, ease of distributed generation integration, and intelligent management. The structure of a low-voltage DC distribution system is as follows: Figure 1 As shown in Figure 1, the active front end (AFE) is a core component of the low-voltage DC power distribution system, providing a reliable connection between distributed power sources and loads (such as Figure 1 The active front end (shown in Figure 1) is a device that uses a DC bus to connect a large number of devices (such as small-power DC appliances, high-power DC appliances, electric vehicle charging piles, energy storage systems, and photovoltaic systems) to build a stable DC bus, and its working state directly affects the efficiency of the system. At present, the active front end faces a severe challenge in practical applications, namely how to keep the DC bus voltage stable when the load changes transiently. When the load is turned on or off, it will cause a temporary imbalance in the input and output power, resulting in significant fluctuations in the DC bus voltage. This fluctuation phenomenon will cause the power devices connected in parallel to the DC bus to exceed the normal operating voltage range, and thus work under abnormal conditions, seriously affecting the system reliability and even causing the equipment to fail to operate.

[0050] In the related art, the outer loop adopts proportional-integral (PI) control and the inner loop adopts finite control set model predictive control (FCS-MPC). This method generates the inner loop active component (d-axis) current reference value by comparing the DC bus voltage reference value with the output bus voltage and sending the difference to the PI controller. By synthesizing the reactive component (q-axis) with a value of 0 with the d-axis current reference value, the current value in the two-phase rotating coordinate system (dq coordinate system) is obtained. After the inverse Park transformation, the MPC current reference value in the inner loop αβ coordinate system is obtained. By establishing a dynamic mathematical model of the inductor side current, comparing the value functions corresponding to various switch states, the switch state that minimizes the value function is selected to control the on and off of the switching device to accurately track the current reference value.

[0051] Although the relevant technology can accurately track the current reference value, it fails to fully consider the instantaneous change of the load when selecting the switch state based on the value function. Therefore, when the load is connected or removed, the selected switch state cannot adapt to this change, resulting in a short-term power imbalance in the system and causing significant fluctuations in the bus voltage.

[0052] In order to solve the above technical problems, the embodiment of the present application provides a DC bus anti-disturbance control method and system, which observes the load current change through an adaptive cascade extended state observer and integrates it into the value function of the inner loop model predictive control, so that the switch state selected by the value function can effectively cope with the load mutation. Compared with the anti-disturbance control method in the related art, the anti-disturbance control method improves the anti-disturbance ability of the DC bus voltage when coping with load changes without losing the steady-state power quality.

[0053] Specifically, the disturbance rejection control method for a DC bus provided in an embodiment of the present application is an active front-end DC bus disturbance rejection model predictive control method based on an adaptive cascade extended state observer (DR-MPC).

[0054] Figure 2 This is a structural block diagram of the anti-disturbance control system of the DC bus provided in an embodiment of the present application.

[0055] Combination Figure 2 As shown, an embodiment of the present application provides an anti-disturbance control system for a DC bus, comprising: a low-voltage DC power distribution system and a controller 04 that are communicatively connected to each other; the low-voltage DC power distribution system comprises an AC power grid 01, an active front end 02 and a DC bus 03 that are electrically connected to each other; the controller 04 is configured to obtain a first three-phase current actual value, a DC voltage reference value, a DC voltage actual value and a DC current actual value of the AC power grid 01; determine a target disturbance parameter based on the DC voltage actual value and the DC current actual value; determine a target switching state of the active front end 02 corresponding to the minimum value function based on the first three-phase current actual value, the DC voltage reference value, the DC voltage actual value, the DC current actual value and the target disturbance parameter; and control the switching state of the active front end 02 based on the target switching state.

[0056] The anti-disturbance control system of the DC bus 03 provided in the embodiment of the present application is adopted, and the operating parameters of the DC bus 03 and the target disturbance parameters of the DC bus 03 (i.e., the disturbance of the DC bus when the load is connected) are obtained through the controller 04, and the switch state of the active front end 02 is regulated in combination with the value function constructed by the target disturbance parameters to cope with the interference caused by the intervening load. Without losing the steady-state power quality, the anti-disturbance ability of the DC bus 03 voltage in response to load changes is improved.

[0057] Figure 3 A flow chart of an anti-disturbance control method for a DC bus provided in an embodiment of the present application.

[0058] Combination Figure 2 The anti-disturbance control system of the DC bus shown in the figure, the embodiment of the present application provides an anti-disturbance control method of the DC bus, such as Figure 3 As shown, the anti-disturbance control method of the DC bus includes steps S100 to S700, which are specifically as follows:

[0059] Step S100, obtaining a first three-phase current actual value, a DC voltage reference value, a DC voltage actual value and a DC current actual value of an AC power grid; the first three-phase current actual value is located in an abc coordinate system.

[0060] Optionally, the first three-phase current actual value includes a first current value i a , the second current value i b and the third current value i c ; Obtaining the actual value of the DC current, including step S101 and step S102, specifically as follows:

[0061] Step S101, obtaining the current switch state of the active front end; the current switch state includes the switch state S of the a phase of the active front end. a , b-phase switch status S b and c-phase switch state S c ; where x = a, b, c, S x =1, the upper bridge arm of phase x is turned on and the lower bridge arm is turned off, S x When =0, the upper bridge arm of phase x is turned off and the lower bridge arm is turned on.

[0062] Step S102, based on the actual value of the first three-phase current and the current switch state, calculate the actual value of the DC current i according to the formula shown in (1) below: dc .

[0063] i dc =S a i a +S b i b +S c i c (1).

[0064] In this embodiment, the DC output current of the active front end is calculated according to the switch state of the active front end.

[0065] Figure 4 This is a diagram of the active front-end topology provided in an embodiment of the present application. Figure 4 That is Figure 1 A topological diagram of frame A in the illustrated embodiment.

[0066] Optionally, combined Figure 4As shown, the active front end AEF includes a phase a bridge arm, a phase b bridge arm, a phase c bridge arm and a voltage stabilizing capacitor C. Each bridge arm includes a first switch and a second switch, and the first switch and the second switch operate in a complementary mode, that is, only one of the first switch or the second switch is in a conducting state. x Indicates the switch state of the x-phase bridge arm, x = a, b, c. When the first switch is on and the second switch is off (i.e., the upper bridge arm of the x-phase is on and the lower bridge arm is off), S x =1. When the second switch is turned on (i.e., the lower bridge arm of phase x is turned on and the upper bridge arm is turned off), S x =0.

[0067] Combination Figure 4 As shown, the inductor current is modeled and analyzed, and the current dynamic equation in the three-phase stationary coordinate system (abc coordinate system) is obtained as shown in (2):

[0068]

[0069] Where e a 、e b 、e c are the three-phase grid voltage, i a 、i b 、i c are respectively the first current value i in the first three-phase inductor current a , the second current value i b and the third current value i c , v a 、v b 、v c They are the three-phase AC side voltages of AFE respectively.

[0070] The capacitor voltage on the DC load side of AFE is modeled and analyzed, and the mathematical model of the dynamic load side is obtained as shown in (3):

[0071]

[0072] Where i load is the load current, v dc is the DC output voltage, i dc is the AFE DC output current (calculated by (1) above).

[0073] Step S200, determining the second three-phase current actual value corresponding to the first three-phase current actual value; the second three-phase current actual value is located in the αβ coordinate system.

[0074] In this step, by transforming the coordinates, the actual values ​​of the first three-phase current in the abc coordinate system are transformed into the actual values ​​of the second three-phase current in the αβ coordinate system, so as to calculate the value function of each switch state of the active front end according to the actual values ​​of the second three-phase current.

[0075] Specifically, the first three-phase current actual value in the abc coordinate system is converted into the second three-phase current actual value in the αβ coordinate system according to the following (4). The first three-phase current actual value includes the first current value i a , the second current value i b and the third current value i c , the first three-phase current actual value includes the fourth current value i α and the fifth current value i β .

[0076]

[0077] Step S300, determining a target current reference value according to a DC voltage reference value and an actual DC voltage value; the target current reference value is located in an αβ coordinate system.

[0078] In this step, the DC bus voltage reference value V ref With the output bus voltage v dc The difference is obtained by comparison and sent to the PI controller to generate the first sub-current reference value of the inner loop active component (d axis). The current component in the two-phase rotating coordinate system (dq coordinate system) is obtained by synthesizing the second sub-current reference value of the reactive component (q axis) with a value of 0 with the first sub-current reference value of the d axis. After that, the MPC current reference value in the inner loop αβ coordinate system is obtained through inverse Park transformation.

[0079] Figure 5 For combination Figure 4 The flowchart of the anti-disturbance control method of the DC bus provided by the illustrated embodiment.

[0080] For example, Figure 5 The PI DC bus voltage outer loop block diagram in FIG. 1 is the implementation process of step S300 .

[0081] Optionally, the anti-disturbance control system of the DC bus further includes a PI controller, and step S300 includes steps S301 to S304, which are specifically as follows:

[0082] Step S301, calculating the difference between the DC voltage reference value and the DC voltage actual value to determine an error signal.

[0083] Step S302, input the error signal into the PI controller to determine a first sub-current reference value; the first sub-current reference value is located on the d-axis of the dq coordinate system.

[0084] Step S303, determining a first current reference value based on the first sub-current reference value and the second sub-current reference value; the first current reference value is located in the dq coordinate system; the second sub-current reference value is a preset value and is located on the q axis of the dq coordinate system.

[0085] Step S304, determining a target current reference value based on the inverse Park transformation and the first current reference value; the target current reference value is located in the αβ coordinate system.

[0086] In this embodiment, an error signal between the DC voltage reference value and the DC voltage actual value is first determined to determine the current first sub-current reference value according to the error signal. Thus, in the dq coordinate system, the first sub-current reference value located on the d-axis and the preset second sub-current reference value located on the q-axis are synthesized to determine the first current reference value located in the dq coordinate system. The first current reference value located in the dq coordinate system can then be converted into a target current reference value located in the αβ coordinate system.

[0087] Specifically, (1) is transformed into the αβ coordinate system by Clark transformation to obtain (5):

[0088]

[0089] In the formula, e α 、e β are the grid voltage in the αβ coordinate system, i α 、i β They are the inductor current in the αβ coordinate system, V α 、V β They are the AFE AC side voltages in αβ coordinate system respectively.

[0090] Discretize (4) using the forward Euler method to obtain (6).

[0091]

[0092] Therefore, the synthesis i α (k+1) and i β (k+1), we can get

[0093] Specifically, adding (k) or (k+1) after a parameter is the discretization representation of the parameter. α (k+1) is i α The discretization representation of is not described one by one in this application.

[0094] Step S400, determining a target disturbance parameter according to the actual value of the DC voltage and the actual value of the DC current; the target disturbance parameter is located in the αβ coordinate system.

[0095] For example, Figure 5 The adaptive cascade extended state observer (AC-ESO) block diagram in FIG. 4 is the implementation process of step S400.

[0096] Optionally, the anti-disturbance control system of the DC bus further includes an adaptive cascade extended state observer, and step S400 includes steps S401 to S404, which are specifically as follows:

[0097] Step S401: inputting the actual value of the DC voltage and the actual value of the DC current into an adaptive cascade extended state observer to determine a total disturbance observation value.

[0098] Optionally, the adaptive cascade extended state observer includes a first observer, a second observer and a third observer; step S401 includes steps S4011 to S4014, which are specifically as follows:

[0099] Step S4011, inputting the actual value of the DC voltage and the actual value of the DC current into a first observer to determine a first disturbance observation value.

[0100] Step S4012: inputting the actual value of the DC voltage, the actual value of the DC current and the first disturbance observation value into a second observer to determine a second disturbance observation value.

[0101] Step S4013, inputting the actual value of the DC voltage, the actual value of the DC current, the first disturbance observation value and the second disturbance observation value into a third observer to determine a third disturbance observation value.

[0102] Step S4014, calculating the sum of the first disturbance observation value, the second disturbance observation value and the third disturbance observation value to determine the total disturbance observation value.

[0103] In this embodiment, the first disturbance observation value, the second disturbance observation value and the third disturbance observation value are respectively observed by each observer in the adaptive cascade extended state observer to determine the total disturbance observation value, so as to facilitate the determination of the target disturbance observation value according to the total disturbance observation value, and then facilitate the regulation of the switch state of the active front end to cope with the voltage fluctuation of the DC bus caused by the load connection or removal, thereby improving the anti-interference ability of the DC bus voltage in response to load changes. In addition, the observed disturbance value can be gradually corrected by the multi-stage observer, thereby improving the accuracy of the total disturbance observation value.

[0104] Specifically, by cascading multiple stages of extended state observers and dynamically adjusting the gain parameters of the observer according to the size of the output error, the observer has the ability to quickly observe in transient state and the ability to suppress high-frequency noise in steady state.

[0105] Figure 6 A schematic diagram of the observation process of the adaptive cascade extended state observer provided in an embodiment of the present application.

[0106] Specifically, the adaptive cascade extended state observer is Figure 6 ESO-1 (first observer), ESO-2 (second observer) and ESO-3 (third observer) are extended state observers (ESO) at each level. It is sent to ESO-2 as a known disturbance and observed by ESO-2. The residual between Further As a known disturbance, it is sent to ESO-3 and obtained The residual between The adaptive cascade extended state observer obtains the total disturbance in the form of cascade ESO.

[0107] Specifically, (3) and the unknown disturbance in the system is considered as An adaptive cascade extended state observer is designed, as shown in the following embodiment.

[0108] Optionally, the adaptive cascade extended state observer is as shown in the following equations (1) to (7):

[0109]

[0110] in, C is the voltage stabilizing capacitor value, u is the actual value of DC current, y is the actual value of DC voltage, is the total disturbance observation value, is the first perturbation observation, is the second perturbation observation, is the third perturbation observation, γ 1j is the first gain parameter, γ 2j is the second gain parameter, j∈(1,2,3), γ 1j and γ 2j is determined based on the error signal.

[0111] Optionally, determining the first gain parameter and the second gain parameter according to the error signal and the first preset formula includes steps S1 to S3, which are specifically as follows:

[0112] The first preset formula is:

[0113]

[0114] Step S1, calculate the DC voltage reference value V ref And the actual value of DC voltage v dc The difference between the two determines the error signal |V ref -v dc |.

[0115] Step S2: When the error signal is within the steady-state threshold range, ω 0 =G 1 .

[0116] Step S3: When the error signal is outside the steady-state threshold range, ω 0 =G 2 .

[0117] Among them, G 1 is the first gain setting value, G 2 is the second gain setting value, G 1 <G 2 .

[0118] In this embodiment, the gain value of each ESO of the adaptive cascade extended state observer is changed by dynamically adjusting the first gain parameter and the second gain parameter according to the output error, so that the adaptive cascade extended state observer can select a low gain coefficient when the DC bus is in a steady state (that is, when the error signal is within the steady-state threshold interval) to suppress the influence of high-frequency noise. When a disturbance occurs (when there is a load connected or removed from the DC bus, that is, when the error signal is outside the steady-state threshold interval), the adaptive cascade extended state observer can select a high gain value in time to ensure the rapidity and accuracy of disturbance observation.

[0119] Specifically, when ω 0 For high gain (ω 0 =G 2 ), the adaptive cascade extended state observer exhibits faster dynamic response capability, but is also more susceptible to high-frequency noise. On the contrary, ω 0 Select low gain (ω 0 =G 1 ), but it will also reduce the observer's response speed to dynamic changes. To this end, the embodiment of the present application dynamically adjusts the first gain parameter and the second gain parameter according to the size of the error signal, so that the adaptive cascade expanded state observer has both the anti-noise ability at low gain and the dynamic performance at high gain.

[0120] Figure 7 A schematic diagram of gain parameter adjustment provided in an embodiment of the present application.

[0121] For example, in combination Figure 7 As shown, when the error signal is at |Vref -v dc | In steady state (error signal is within the steady state threshold interval), select ω 0 =G 1 , in order to suppress the influence of high frequency noise. When the error signal is |V ref -v dc | In the case of transient state (error signal is within the steady-state threshold range), select ω 0 =G 2 , by adaptively cascading the expanded state observer's dynamic response capability.

[0122] Optionally, the anti-disturbance control method for the DC bus further includes: 0 When the value of changes, maintain ω 0 The value of is the value after the change. The preset time T d .

[0123] In this embodiment, ω 0 Rapid changes in |V ref -v dc |The steady-state threshold interval ξ is not reached s =[-d s ,d s ], ω 0 Repeated switching occurs, affecting the steady-state performance. To this end, a preset delay time T is introduced during the switching process. d (the delay time is the preset time in the above embodiment), so that ω 0 After the instantaneous switching, it can maintain T d Length of time to avoid 0 After switching, the error signal has not yet entered the steady-state threshold interval ξ s , repeated switching occurs. d The selection of should be the minimum value under the condition of avoiding repeated switching. However, due to different dynamic changes of T d The selection criteria are different, and the maximum value that can cover all dynamic changes should be selected.

[0124] Step S402, based on the total disturbance observation value The voltage stabilizing capacitor value and the actual value of the DC voltage are used to calculate and determine the first sub-disturbance parameter d d (k); The first sub-disturbance parameter is located on the d-axis of the dq coordinate system.

[0125] Optionally, step S402 includes step S4021 and step S4022, which are specifically as follows:

[0126] Step S4021, based on the total disturbance observation value and the voltage stabilizing capacitor value C, and calculate the load current according to the second preset formula.

[0127] Step S4022, based on the load current i load And the actual value of DC voltage v dc , according to the third preset formula, calculate the first sub-disturbance parameter d d (k).

[0128] The second preset formula is:

[0129]

[0130] The third preset formula is:

[0131]

[0132] Among them, V gd It is the component of the three-phase grid voltage located on the d-axis in the dq coordinate system.

[0133] In this embodiment, the load current and the first sub-disturbance parameter are calculated so as to determine the target disturbance parameter according to the first sub-disturbance parameter.

[0134] Specifically, according to the power balance relationship, the current observation value obtained by the adaptive cascade extended state observer is Converted into the corresponding value d of the inner loop of the d-axis current d (k).

[0135] Optionally, calculate V gd , including steps S40221 to S40223, which are as follows:

[0136] Step S40221, calculate the three grid voltages V in the abc coordinate system according to the following fourth preset formula: a 、V b and V c .

[0137] Step S40222: Based on Clark transformation, V a 、V b and V c Transformed into V in αβ coordinate system α 、V β .

[0138] Step S40223, based on Park transformation, V α 、V β Converted to V in dq coordinate system gd .

[0139] The fourth preset formula is:

[0140]

[0141] In this embodiment, the three grid voltages in the abc coordinate system are converted into V in the αβ coordinate system. α 、V β , which can be transformed into V in the dq coordinate system gd .

[0142] Step S403, determining the first disturbance parameter based on the first disturbance parameter and the second sub-disturbance parameter; the first disturbance parameter is located in the dq coordinate system; the second sub-disturbance parameter is a preset value and is located on the q axis of the dq coordinate system.

[0143] Step S404, determining a target disturbance parameter based on the inverse Park transform and the first disturbance parameter; the target disturbance parameter is located in the αβ coordinate system.

[0144] In this embodiment, an adaptive cascade extended state observer is used to observe the disturbance (i.e., the total disturbance observation value) generated by the DC bus connection or removal of the load, so as to determine the target disturbance parameter according to the total disturbance observation value, so as to give a predicted target switching state that can make the system in a steady state when the target disturbance parameter is integrated into the cost function to cope with the disturbance generated by the connection or removal of the load. The anti-interference ability of the DC bus voltage in response to load changes is improved.

[0145] Step S500, based on the second three-phase current actual value, the target current reference value and the target disturbance parameter, calculate the cost function corresponding to each switch state of the active front end; the active front end has eight different switch states.

[0146] For example, Figure 5 The MPC current inner loop block diagram in FIG. 1 is the implementation process of step S500.

[0147] Optionally, Among them, Cf pro is the value function, is the target current reference value, i α,β (k+1) is the actual value of the second three-phase current, d α,β (k) is the target disturbance parameter.

[0148] In this embodiment, the current disturbance generated when the load changes suddenly is added to the value function through power conversion, and the switch state selected by the value function contains the disturbance information of the load change. When the disturbance comes, the best switch state that adapts to the disturbance (that is, the target switch state corresponding to the minimum value function) can be quickly selected, thereby reducing the significant fluctuation of the DC bus voltage and improving the anti-interference ability of the DC bus voltage when responding to load changes.

[0149] For example, the absolute error between the current reference value and the current prediction value is used in the related art to construct a value function, as shown in (7) below. By comparing the value functions corresponding to various switch states, the switch state that minimizes the value function is selected to control the on and off of the switch device to accurately track the current reference value. However, when the load suddenly changes, the switch state selected by this method does not take into account the instantaneous sudden change of the load current, resulting in a temporary input-output power imbalance in the system, causing the bus voltage to fluctuate significantly.

[0150]

[0151] Step S600: determine the switch state corresponding to the minimum value function as the target switch state.

[0152] Step S700, controlling the switch state of the active front end based on the target switch state.

[0153] The anti-disturbance control method for the DC bus provided in the embodiment of the present application is adopted, and the actual value of the second three-phase current, the target current reference value and the target disturbance parameter located in the αβ coordinate system are respectively determined to calculate and determine the value function corresponding to each switch state of the active front end. The target switch state corresponding to the minimum value function is the switch state with the least impact on the DC bus when the load is connected or removed. Therefore, after controlling the switch state of the active front end according to the target switch state, the impact of the load on the DC bus can be minimized, and the power imbalance problem of the DC bus can be reduced. In this way, by integrating the target disturbance parameter into the value function, and the target disturbance parameter is obtained by observing the load current change by the observer, so as to realize the value function constructed in combination with the target disturbance parameter, the switch state of the active front end is regulated to cope with the interference caused by the intervening load. Without losing the steady-state power quality, the anti-interference ability of the DC bus voltage in response to load changes is improved.

[0154] Specifically, the anti-interference control method for the DC bus provided in the embodiment of the present application observes the active front-end load current by designing an adaptive cascade expanded state observer, and integrates the load current into the value function of the model predictive control strategy through power conversion, so that the selected switching state has anti-interference ability, thereby suppressing the significant fluctuation of the DC bus voltage.

[0155] Corresponding to the above-mentioned embodiment of the anti-disturbance control method of the DC bus, the present application also provides an embodiment of the anti-disturbance control system of the DC bus. The anti-disturbance control system of the DC bus includes: a low-voltage DC power distribution system and a controller that are connected to each other in communication; the low-voltage DC power distribution system includes an AC power grid, an active front end and a DC bus that are electrically connected to each other; the controller is configured to obtain a first three-phase current actual value, a DC voltage reference value, a DC voltage actual value and a DC current actual value of the AC power grid; the first three-phase current actual value is located in the abc coordinate system; the second three-phase current actual value corresponding to the first three-phase current actual value is determined; the second three-phase current actual value is located in the αβ coordinate system; according to the DC voltage reference value and the DC voltage actual value, a target current reference value is determined; the target current reference value is located in the αβ coordinate system; according to the DC voltage actual value and the DC current actual value, a target disturbance parameter is determined; the target disturbance parameter is located in the αβ coordinate system; based on the second three-phase current actual value, the target current reference value and the target disturbance parameter, the value function corresponding to each switch state of the active front end is calculated; the active front end has eight different switch states; the switch state corresponding to the minimum value function is determined as the target switch state; based on the target switch state, the switch state of the active front end is controlled.

[0156] The anti-disturbance control method for the DC bus provided in the embodiment of the present application is adopted, and the actual value of the second three-phase current, the target current reference value and the target disturbance parameter located in the αβ coordinate system are determined by the controller respectively, so as to calculate and determine the value function corresponding to each switch state of the active front end. The target switch state corresponding to the minimum value function is the switch state with the least impact on the DC bus when the load is connected or removed. Therefore, after controlling the switch state of the active front end according to the target switch state, the impact of the load on the DC bus can be minimized, and the power imbalance problem of the DC bus can be reduced. In this way, by integrating the target disturbance parameter into the value function, and the target disturbance parameter is obtained by observing the load current change by the observer, so as to realize the value function constructed in combination with the target disturbance parameter, the switch state of the active front end is regulated to cope with the interference caused by the intervening load. Without losing the steady-state power quality, the anti-interference ability of the DC bus voltage in response to load changes is improved.

[0157] In order to verify the effectiveness of the method proposed in this invention, an AFE experimental platform was built. The AFE converter consists of three Imperix SiC power half-bridge modules, and the controller uses an Imperix rapid prototyping controller. The experimental parameters are shown in Table 1.

[0158] Table 1

[0159]

[0160] This application conducts steady-state and transient comparative experiments on the related technology (FCS-MPC) and the method provided in the embodiment of this application (DR-MPC) to verify the effectiveness of the proposed control strategy.

[0161] Figure 8 A waveform comparison diagram of steady-state operating conditions at rated power provided in an embodiment of the present application. Figure 8 (a) is the waveform diagram of the steady-state condition of the related technology (FCS-MPC) at rated power. Figure 8 (b) is a waveform diagram of the DC bus anti-disturbance control method (DR-MPC) provided in an embodiment of the present application under the steady-state condition of rated power.

[0162] The following is a comparative analysis of the steady-state performance of the two control methods. The DC bus voltage reference value is constant at 350V, and the load is 50Ω at rated power. Figure 8 As shown, the analysis shows that the related technology (FCS-MPC) and the method (DR-MPC) provided in the embodiment of the present application both perform well in tracking performance. By comparing the data of the total harmonic distortion (THD) of the current in Table 2, the following conclusions are drawn: At rated power, the current THD of the related technology (FCS-MPC) and the method (DR-MPC) provided in the embodiment of the present application is almost the same, which is 3.58% and 3.61% respectively. It can be seen that the steady-state performance of the two control strategies is consistent.

[0163] Table 2

[0164]

[0165] Fig. 9 A waveform comparison diagram of the DC bus voltage after load removal provided in an embodiment of the present application.

[0166] Compare the performance of the two control strategies when the load changes suddenly. First, the performance of the two control strategies when the load is suddenly removed is compared and analyzed. The DC bus voltage is set to 350V, and the initial load is composed of two 100Ω resistors in parallel (total resistance is 50Ω). When the system is stable, one 100Ω resistor is removed to make the total load resistance become 100Ω. The DC bus voltage waveform after the load is removed is as follows: Fig. 9As shown. The main comparative data are shown in Table 3. The recovery time of the FCS-MPC control strategy after load removal is 46.55ms, and the maximum fluctuation amplitude is 6.13V. In contrast, the recovery time of DR-MPC is reduced by 68.7%, and the maximum fluctuation amplitude is reduced by 60.68%. The results show that compared with FCS-MPC, the DR-MPC control strategy significantly reduces the fluctuation amplitude of the DC bus voltage when the load is suddenly removed, and improves the recovery performance of the DC bus voltage.

[0167] Table 3

[0168]

[0169] Fig.10 A waveform comparison diagram of the DC bus voltage after load connection provided in an embodiment of the present application.

[0170] The performance comparison when the load is suddenly connected is as follows. The DC bus voltage is set to 350V, and the initial load is a 100Ω resistor. When the system is stable, a 100Ω resistor load is connected, and the total load resistance changes from 100Ω to 50Ω (two 100Ω resistors in parallel). The DC bus voltage comparison waveform is as follows Fig.10 The relevant data are shown in Table 4. Fig.10 The data in Table 4 show that compared with FCS-MPC, the maximum voltage fluctuation amplitude of DR-MPC is reduced by 61.44% and the recovery time is shortened by 50.01%. It can be seen that the anti-disturbance control method of the DC bus provided in the embodiment of the present application effectively suppresses the significant fluctuation of the DC bus voltage when the load is connected, and improves the power quality of the DC bus.

[0171] Table 4

[0172]

[0173] To sum up, the anti-interference control method of the DC bus provided in the embodiment of the present application has better anti-interference capability than the anti-interference control method in the related art. When the DC bus is connected to or cut off from the load, it can quickly maintain the voltage of the DC bus to restore to a stable state, thereby improving the anti-interference capability of the DC bus.

[0174] It should be noted that those skilled in the art will easily think of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope of the present application is indicated by the claims.

[0175] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A DC bus anti-disturbance control method, characterized in that: The anti-disturbance control method of the DC bus is applied to the anti-disturbance control system of the DC bus, and the anti-disturbance control system of the DC bus includes an active front end and an AC power grid; the anti-disturbance control method of the DC bus includes: Acquire a first three-phase current actual value, a DC voltage reference value, a DC voltage actual value, and a DC current actual value of the AC power grid; the first three-phase current actual value is located in the abc coordinate system; Determine a second three-phase current actual value corresponding to the first three-phase current actual value; the second three-phase current actual value is located in the αβ coordinate system; Determine a target current reference value according to the DC voltage reference value and the DC voltage actual value; the target current reference value is located in the αβ coordinate system; Determining a target disturbance parameter according to the actual value of the DC voltage and the actual value of the DC current; the target disturbance parameter is located in the αβ coordinate system; Based on the second three-phase current actual value, the target current reference value and the target disturbance parameter, the target current reference value and the target disturbance parameter, calculating the cost function corresponding to each switch state of the active front end; the active front end has eight different switch states; Determine the switch state corresponding to the minimum value function as the target switch state; Based on the target switching state, the switching state of the active front end is controlled.

2. The anti-disturbance control method for a DC bus according to claim 1, characterized in that: The anti-disturbance control system of the DC bus further includes a PI controller, and the determining of the target current reference value according to the DC voltage reference value and the DC voltage actual value includes: Calculating a difference between the DC voltage reference value and the DC voltage actual value to determine an error signal; Inputting the error signal into a PI controller to determine a first sub-current reference value; the first sub-current reference value is located on the d-axis of the dq coordinate system; Based on the first sub-current reference value and the second sub-current reference value, a first current reference value is determined; the first current reference value is located in the dq coordinate system; the second sub-current reference value is a preset value and is located on the q axis of the dq coordinate system; Based on the inverse Park transformation and the first current reference value, the target current reference value is determined; the target current reference value is located in the αβ coordinate system.

3. The anti-disturbance control method for a DC bus according to claim 1, characterized in that: The anti-disturbance control system of the DC bus further includes an adaptive cascade extended state observer, and the target disturbance parameter is determined according to the actual value of the DC voltage and the actual value of the DC current, including: Inputting the actual value of the DC voltage and the actual value of the DC current into the adaptive cascade extended state observer to determine a total disturbance observation value; Based on the total disturbance observation value, the voltage stabilizing capacitor value and the actual value of the DC voltage, the first sub-disturbance parameter d is calculated and determined. d (k); The first sub-disturbance parameter is located on the d-axis of the dq coordinate system; Determine a first disturbance parameter based on the first disturbance parameter and the second sub-disturbance parameter; the first disturbance parameter is located in the dq coordinate system; the second sub-disturbance parameter is a preset value and is located on the q axis of the dq coordinate system; Based on the inverse Park transform and the first disturbance parameter, the target disturbance parameter is determined; the target disturbance parameter is located in the αβ coordinate system.

4. The anti-disturbance control method for a DC bus according to claim 3, characterized in that: The adaptive cascade extended state observer comprises a first observer, a second observer and a third observer; the step of inputting the actual value of the DC voltage and the actual value of the DC current into the adaptive cascade extended state observer to determine the total disturbance observation value comprises: Inputting the actual value of the DC voltage and the actual value of the DC current into the first observer to determine a first disturbance observation value; Inputting the actual value of the DC voltage, the actual value of the DC current and the first disturbance observation value into the second observer to determine a second disturbance observation value; Inputting the DC voltage actual value, the DC current actual value, the first disturbance observation value and the second disturbance observation value into the third observer to determine a third disturbance observation value; The sum of the first disturbance observation value, the second disturbance observation value and the third disturbance observation value is calculated to determine the total disturbance observation value.

5. The anti-disturbance control method for a DC bus according to claim 4, characterized in that: The adaptive cascade extended state observer is shown in (1) to (7) below: Among them, the The C is the voltage stabilizing capacitor value, the u is the actual value of the DC current, the y is the actual value of the DC voltage, is the total disturbance observation value, the is the first disturbance observation value, is the second disturbance observation value, is the third disturbance observation value, the γ 1j is the first gain parameter, the γ 2j is the second gain parameter, j∈(1,2,3), the γ 1j and the γ 2j is determined based on the error signal.

6. The anti-disturbance control method for a DC bus according to claim 5, characterized in that: Determining the first gain parameter and the second gain parameter according to the error signal and a first preset formula includes: The first preset formula is: Calculate the DC voltage reference value V ref and the actual value of the DC voltage v dc The difference between the two determines the error signal |V ref -v dc |; When the error signal is within the steady-state threshold interval, ω0=G1; When the error signal is outside the steady-state threshold interval, ω0=G2; Wherein, G1 is the first gain setting value, G2 is the second gain setting value, G1 <G2。 7. The anti-disturbance control method for a DC bus according to claim 6, characterized in that: Also includes: When the value of ω0 changes, the value of ω0 is maintained at the changed value for a preset time.

8. The anti-disturbance control method for a DC bus according to claim 3, characterized in that: The first sub-disturbance parameter d is calculated based on the total disturbance observation value, the voltage stabilizing capacitor value and the actual value of the DC voltage. d (k) including: Based on the total disturbance observation and the voltage stabilizing capacitor value C, and calculate the load current according to a second preset formula; Based on the load current i load and the actual value of the DC voltage v dc , calculate the first sub-disturbance parameter d according to the third preset formula d (k); The second preset formula is: The third preset formula is: Among them, the V gd is the component of the three-phase grid voltage located on the d-axis in the dq coordinate system.

9. The anti-disturbance control method for a DC bus according to claim 1, characterized in that: Among them, the Cf pro is the value function, is the target current reference value, the i α,β (k+1) is the actual value of the second three-phase current, and the d α,β (k) is the target disturbance parameter.

10. An anti-disturbance control system for a DC bus, characterized in that: include: Low voltage DC power distribution systems and controllers that communicate with each other; The low voltage DC power distribution system comprises an AC power grid, an active front end and a DC busbar which are electrically connected to each other; The controller is configured to obtain a first three-phase current actual value, a DC voltage reference value, a DC voltage actual value, and a DC current actual value of an AC power grid; the first three-phase current actual value is located in an abc coordinate system; determine a second three-phase current actual value corresponding to the first three-phase current actual value; the second three-phase current actual value is located in an αβ coordinate system; determine a target current reference value according to the DC voltage reference value and the DC voltage actual value; The target current reference value is located in the αβ coordinate system; a target disturbance parameter is determined according to the actual value of the DC voltage and the actual value of the DC current; the target disturbance parameter is located in the αβ coordinate system; based on the actual value of the second three-phase current, the target current reference value and the target disturbance parameter, a cost function corresponding to each switch state of the active front end is calculated; the active front end has eight different switch states; Determine the switch state corresponding to the minimum value function as the target switch state; Based on the target switching state, the switching state of the active front end is controlled.

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