Circulating current suppression method and system of parallel converter
By generating zero-sequence voltage components based on the low-frequency zero-sequence circulation value in the parallel converter and introducing low-frequency synchronization signals as the control mechanism, the problem of zero-sequence circulation in the parallel converter is solved, effective control of low-frequency and high-frequency circulation is achieved, and system performance is improved.
Patent Information
- Application Number
- CN202411711855.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-02-28
AI Technical Summary
When running in parallel, the parallel converter can cause zero-sequence circulation, which increases system losses and reduces equipment performance. Existing methods such as increasing inductance or introducing isolation transformers can suppress circulation, but can lead to reduced system response speed, increased volume and weight, and high manufacturing costs.
By generating zero-sequence voltage components based on the low-frequency zero-sequence circulation value, injecting zero-sequence voltage components into the parallel converter, reducing the problem of low-frequency zero-sequence circulation, and introducing low-frequency synchronization signals as a key control mechanism to adjust the carrier signal to reduce high-frequency circulation.
It effectively reduces the low-frequency and high-frequency circulation in the parallel converter, avoids the problems of reduced system response speed, increased volume and weight, and high manufacturing costs, and improves the dynamic performance and overall performance of the system.
Smart Images
Figure CN119543603A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of circulating current suppression of parallel converters, and in particular to a circulating current suppression method and system for parallel converters. Background Art
[0002] With the large-scale access of renewable energy to the grid and the continuous increase in the penetration rate of new energy, the capacity of a single converter, as a key power conversion device in the new energy system, can no longer meet the demand. Therefore, converter parallel technology has become a common and effective solution. However, the parallel operation of converters will cause zero-sequence circulating current in the system, which not only increases system losses but also reduces the overall performance of the equipment.
[0003] In the related art, in order to suppress the circulating current problem caused by parallel converters, the main method is to connect an inductor in series at the output end of the converter or introduce an isolation transformer. The series inductor increases the output impedance of the converter, thereby limiting the circulation of the circulating current and reducing the impact of the circulating current on the system performance. The series inductor can form a high-impedance path at the output end of the converter, effectively suppressing the low-frequency circulating current caused by differences in circuit parameters. At the same time, by increasing the inductance value, the amplitude of the high-frequency component can also be reduced, thereby suppressing the generation of high-frequency circulating current. The isolation transformer introduces magnetic isolation to achieve electrical isolation between converters, further blocking the circulating current path.
[0004] In the practice of relevant technologies, there are at least the following problems:
[0005] First, increasing the inductance value will also reduce the system response speed and affect the dynamic performance of the system. Secondly, introducing an isolation transformer or increasing the inductance value will significantly increase the system volume and weight, which is not conducive to application in space-constrained scenarios. In addition, the high manufacturing cost of adding inductance components or introducing isolation transformers also limits their widespread application in engineering practice. Summary of the invention
[0006] The embodiments of the present application provide a method and system for suppressing circulating current of a parallel converter, so as to generate a zero-sequence voltage component based on a low-frequency zero-sequence circulating current value, inject the zero-sequence voltage component into the parallel converter, reduce the low-frequency zero-sequence circulating current problem in the parallel converter, and introduce a low-frequency synchronization signal as a key control mechanism to reduce the high-frequency circulating current problem caused by carrier asynchrony in the parallel converter system.
[0007] In some embodiments, a circulating current suppression method for a parallel converter is provided, and the circulating current suppression method for a parallel converter is used to suppress low-frequency zero-sequence circulating current and high-frequency zero-sequence circulating current in the parallel converter. The circulating current suppression method for a parallel converter includes: determining an initial reference voltage of the parallel converter; determining a voltage compensation amount based on a low-frequency zero-sequence circulating current value of the parallel converter; adjusting the initial reference voltage based on the voltage compensation amount to determine a target reference voltage; obtaining a low-frequency synchronization signal and a carrier signal in the parallel converter; adjusting the carrier signal based on the low-frequency synchronization signal to determine a target carrier signal; determining a pulse width modulation signal based on the target carrier signal and the target reference voltage; and controlling the parallel converter based on the pulse width modulation signal.
[0008] By adopting the circulating current suppression method of the parallel converter provided in the embodiment of the present application, the initial reference voltage can be adjusted based on the low-frequency zero-sequence circulating current value, and then the parallel converter can be modulated based on the adjusted target reference voltage to reduce the low-frequency zero-sequence circulating current. The low-frequency synchronization signal is introduced as a key control mechanism to solve the high-frequency circulating current problem caused by carrier asynchrony in the parallel converter system.
[0009] Optionally, determining an initial reference voltage of the parallel converter includes: obtaining active components and reactive components in the parallel converter in a dq coordinate system; and determining an initial reference voltage corresponding to the active components and the reactive components, wherein the initial reference voltage is located in an abc coordinate system.
[0010] Optionally, determining the initial reference voltage corresponding to the active component and the reactive component includes: determining the grid phase angle based on the grid voltage of the parallel converter; and determining the initial reference voltage based on the grid phase angle, the active component and the reactive component.
[0011] Optionally, based on the low-frequency zero-sequence circulating current value of the parallel converter, a voltage compensation amount is determined, including: obtaining the low-frequency zero-sequence circulating current value; determining an error signal based on the low-frequency zero-sequence circulating current value and a zero-sequence circulating current reference value; and determining a voltage compensation amount corresponding to the error signal based on the error signal.
[0012] Optionally, determining an error signal based on the low-frequency zero-sequence circulating current value and the zero-sequence circulating current reference value includes: calculating an error difference between the low-frequency zero-sequence circulating current value and the zero-sequence circulating current reference value; and the error signal includes the error difference.
[0013] Optionally, determining a voltage compensation amount corresponding to the error signal according to the error signal includes: inputting the error signal into a PI controller to determine the voltage compensation amount.
[0014] Optionally, the low-frequency synchronization signal includes a square wave signal with a preset period; the parallel converter includes a first converter and a second converter; the carrier signal includes a first carrier signal and a second carrier signal, the first carrier signal corresponds to the first converter, and the second carrier signal corresponds to the second converter; the carrier signal is adjusted based on the low-frequency synchronization signal to determine the target carrier signal, including: when the low-frequency synchronization signal is a rising edge or a falling edge, synchronizing the first carrier signal and the second carrier signal.
[0015] Optionally, synchronizing the first carrier signal and the second carrier signal includes: setting the first carrier signal and the second carrier signal to 0 or 1.
[0016] Optionally, determining a pulse width modulation signal according to a target carrier signal and a target reference voltage includes: comparing the target carrier signal and the target reference voltage; when the target carrier signal is greater than the target reference voltage, the pulse width modulation signal is at a low level; when the target carrier signal is less than the target reference voltage, the pulse width modulation signal is at a high level.
[0017] In some embodiments, a circulating current suppression system for a parallel converter is provided, comprising: a parallel converter and a controller; the parallel converter is communicatively connected to the controller; the controller is configured to determine an initial reference voltage of the parallel converter; based on a low-frequency zero-sequence circulating current value of the parallel converter, a voltage compensation amount is determined; based on the voltage compensation amount, the initial reference voltage is adjusted to determine a target reference voltage; a low-frequency synchronization signal and a carrier signal in the parallel converter are obtained; based on the low-frequency synchronization signal, the carrier signal is adjusted to determine a target carrier signal; based on the target carrier signal and the target reference voltage, a pulse width modulation signal is determined; and the parallel converter is controlled based on the pulse width modulation signal.
[0018] It can be understood that the beneficial effects that can be achieved by the technical solution provided by the above-mentioned circulating current suppression system of the parallel converter can be referred to the beneficial effects of the circulating current suppression method of the parallel converter and any of its optional implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0020] Figure 1 A structural block diagram of a circulating current suppression system for parallel converters provided in an embodiment of the present application;
[0021] Figure 2 A circuit topology diagram of a power converter provided in an embodiment of the present application;
[0022] Figure 3 for Figure 1 The equivalent circuit model of the AC side in the embodiment shown;
[0023] Figure 4 A zero-sequence circuit diagram of a parallel converter provided in an embodiment of the present application;
[0024] Figure 5 A schematic flow chart of a method for suppressing circulating current in parallel converters provided in an embodiment of the present application;
[0025] Figure 6 A flowchart of a method for suppressing circulating current in parallel converters provided in an embodiment of the present application;
[0026] Figure 7 A schematic diagram of carrier synchronization of parallel converters provided in an embodiment of the present application;
[0027] Figure 8 This is a schematic diagram of output current without circulating current suppression;
[0028] Fig. 9 It is a schematic diagram of the circulating current waveform without circulating current suppression;
[0029] Fig.10 A schematic diagram of output current provided in an embodiment of the present application;
[0030] Fig.11 A schematic diagram of a circulating current waveform provided in an embodiment of the present application. DETAILED DESCRIPTION
[0031] The technical solutions in the embodiments of the present application will be described clearly below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by ordinary technicians in this field without making creative work all belong to the protection scope of the present application.
[0032] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0033] In addition, in the present application, directional terms such as "upper", "lower", "inner" and "outer" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components placed in the drawings.
[0034] In order to facilitate the understanding of the technical solution of the application, the relevant technologies involved in this application are first explained below.
[0035] With the large-scale access of renewable energy to the grid and the continuous increase in the penetration rate of new energy, the capacity of a single converter, as a key power conversion device in the new energy system, can no longer meet the demand. Therefore, converter parallel technology has become a common and effective solution. However, the parallel operation of converters will cause zero-sequence circulating current in the system, which not only increases system losses but also reduces the overall performance of the equipment.
[0036] With the acceleration of energy transformation, emerging energy technologies such as energy storage technology, renewable energy power generation systems (such as solar photovoltaic power generation and wind power generation) and smart grids have been widely used. Among them, the converter is a key device for energy conversion in the system. With the continuous growth of the installed capacity of various types of renewable energy, the demand for large-capacity converters is also increasing. In order to meet this demand, in actual projects, the system capacity can be expanded by connecting multiple converters in parallel.
[0037] In the parallel converter system, the zero-sequence circulating current problem becomes a key factor restricting the performance of the parallel converter system. The zero-sequence circulating current is mainly composed of low-frequency components and high-frequency components. First, due to the slight differences in the main circuit parameters of each converter in the parallel system, it is difficult to fully synchronize the output voltages of each converter, resulting in a significant zero-sequence voltage difference between the converters, which becomes the main reason for the low-frequency circulating current. Secondly, when each converter in the parallel system is equipped with an independent control unit, the slight deviation of the system clock between the control units will cause the carrier phase difference to increase significantly, thereby inducing high-frequency circulating current. Therefore, in order to reduce system losses and improve equipment performance, effective measures must be taken to suppress the circulating current between parallel converters to ensure the efficient and stable operation of the entire parallel system.
[0038] At present, in order to suppress the circulating current problem caused by parallel converters, the main methods are to connect inductors in series at the converter output end or to introduce isolation transformers. The series inductor increases the output impedance of the converter, thereby limiting the circulation of the circulating current and reducing the impact of the circulating current on the system performance. The series inductor can form a high-impedance path at the output end of the converter, effectively suppressing the low-frequency circulating current caused by differences in circuit parameters. At the same time, by increasing the inductance value, the amplitude of the high-frequency component can also be reduced, thereby suppressing the generation of high-frequency circulating current. The isolation transformer introduces magnetic isolation to achieve electrical isolation between converters, further blocking the circulating current path.
[0039] In the existing method, by adding an inductor element or introducing an isolation transformer at the output end of each converter, the inductor element is added to increase the total inductance of the circulating current loop, thereby effectively suppressing the scale of the circulating current. The introduction of an isolation transformer to block the circulating current path will cause certain limitations in the above method. First, increasing the inductance value will also reduce the system response speed and affect the dynamic performance of the system. Secondly, introducing an isolation transformer or increasing the inductance value will cause a significant increase in the volume and weight of the system, which is not conducive to application in scenarios with limited space. In addition, the high manufacturing cost of adding inductors or introducing isolation transformers also limits their widespread application in engineering practice.
[0040] To solve the above technical problems, the embodiment of the present application provides a method and system for suppressing circulating current of a parallel converter, combining a method for suppressing zero-sequence circulating current with zero-sequence voltage compensation and a low-frequency synchronization signal. By accurately calculating the error between the reference value and the actual measured value of the zero-sequence circulating current, the error signal is sent to the controller to generate a zero-sequence voltage compensation amount. This compensation amount is then superimposed on the original modulation signal to achieve effective control of the low-frequency circulating current. At the same time, in the pulse width modulation (PWM) signal generation process of the converter, a low-frequency synchronization signal is introduced as a key control mechanism to solve the high-frequency circulating current problem caused by carrier asynchrony in the parallel converter system. The embodiment of the present application not only avoids a significant increase in system volume and weight, but also reduces manufacturing costs and overcomes limitations in industrial applications.
[0041] Figure 1 This is a structural block diagram of a circulating current suppression system for parallel converters provided in an embodiment of the present application.
[0042] Combination Figure 1 As shown, an embodiment of the present application provides a circulating current suppression system for a parallel converter, including: a parallel converter 10 and a controller 20. The parallel converter 10 is communicatively connected to the controller 20. The controller 20 is configured to modulate the parallel converter based on the low-frequency zero-sequence circulating current value and the pulse width modulation signal of the parallel converter 10 to reduce the low-frequency circulating current and high-frequency circulating current of the parallel converter.
[0043] The circulating current suppression system of the parallel converter provided in the embodiment of the present application can generate a zero-sequence voltage component based on the low-frequency zero-sequence circulating current value, inject the zero-sequence voltage component into the parallel converter, reduce the low-frequency zero-sequence circulating current in the parallel converter, and introduce a low-frequency synchronization signal as a key control mechanism to reduce the high-frequency circulating current problem caused by carrier asynchrony in the parallel converter system.
[0044] Figure 2 A circuit topology diagram of a power converter provided in an embodiment of the present application.
[0045] The power converter mainly realizes the function of exchanging electric energy between AC and DC, that is, it can convert AC into DC and vice versa, and energy can flow in both directions. Figure 2 As shown, the power converter includes a first three-phase inductor L1, a second three-phase inductor L2, a first parasitic resistor group R1, a second parasitic resistor group R2, a first converter 101 and a second converter 102. The first converter 101 includes a first three-phase full-bridge power switch tube S a,1 , the second three-phase full-bridge power switch tube S b,1 , the third three-phase full-bridge power switch tube S c,1 , the fourth three-phase full-bridge power switch tube Fifth three-phase full-bridge power switch tube Sixth three-phase full-bridge power switch tube The second converter 102 includes a seventh three-phase full-bridge power switch tube S a,2 , the eighth three-phase full-bridge power switch tube S b,2 , the ninth three-phase full-bridge power switch tube S c,2 , the thirteenth phase full-bridge power switch tube Eleventh three-phase full-bridge power switch tube The twelfth three-phase full-bridge power switch tube The upper and lower switches of the same bridge arm work in a complementary mode. The first converter 101 and the second converter 102 are connected in parallel, the AC sides of the first converter 101 and the second converter 102 are connected to the three-phase AC bus, and the DC sides of the first converter 101 and the second converter 102 are connected to the DC bus. The direction of the current flowing from the grid into the converter is defined as the positive direction (marked on Figure 2 The direction of the arrow is the positive direction), and the current in each current branch is recorded as i a,i 、i b,i 、i c,i , where i∈{1,2}, the grid voltage is e a 、e b 、e c , the DC side voltage is V dc Each power converter is closed-loop controlled by a local controller.
[0046] Definition of zero-sequence current i in a three-phase AC system z As shown in the following formula (1), the zero-sequence voltage v z As shown in formula (2):
[0047] i z =(i a +i b +i c ) Formula (1);
[0048] v z =(va +v b +v c ) Formula (2);
[0049] Among them, the zero-sequence current is the circulating current of the parallel converter. a is the current value of phase A, i b is the current value of phase B, i c is the current value of phase C. a is the voltage value of phase A, v b is the voltage value of phase B, v c is the voltage value of phase C.
[0050] Figure 3 for Figure 1 Equivalent circuit model of the AC side in the illustrated embodiment.
[0051] like Figure 3 As shown, using the volt-second balance principle, Figure 1 The voltage output by each phase bridge arm is divided into differential mode voltage and common mode voltage, that is, (v x,i +v z,i ), where v x,i is the differential mode component, v z,i is the common mode component, x∈{a,b,c}. Through the above analysis, according to the connection relationship of each device in the power converter, the equivalent circuit model of the converter is obtained by replacing the switch model with the average model of each phase bridge arm.
[0052] based on Figure 3 The equivalent circuit model shown in the figure defines the direction of the zero-sequence circulating current as follows: Figure 3 As shown by arrow F in the middle, write Kirchhoff voltage equation on the AC side:
[0053]
[0054] Zero sequence circulating current I Z The definition of is formula (4):
[0055] I Z =I Z,1 =-I Z,2 =i a,1 +i b,1 +i c,1 Formula (4).
[0056] Among them, I Z,1 is the zero-sequence circulating current of the first converter, I Z,2 is the zero-sequence circulating current of the second converter.
[0057] In a three-phase symmetrical system, equation (5) should be satisfied:
[0058] v a,1 +vb,1 +v c,1 =v a,2 +v b,2 +v c,2 =0Formula (5).
[0059] Adding (1), (2), and (3) in formula (3) yields formula (6):
[0060]
[0061] Figure 4 This is a zero-sequence circuit diagram of a parallel converter provided in an embodiment of the present application.
[0062] Based on this expression, the circuit model of the zero-sequence circuit when two converters are connected in parallel can be obtained. Based on the above derivation results, the circuit model of the zero-sequence circuit when two converters are connected in parallel can be obtained by using the Thevenin equivalent simplification. Figure 4 As shown. It includes zero sequence voltage v zi , zero sequence circuit inductance L i and zero sequence circuit resistance R i . Analysis of the zero-sequence circuit model shows that the zero-sequence voltage is the essential reason for the generation of zero-sequence circulating current.
[0063] Specifically, zero-sequence voltage is usually caused by the inconsistency of the output voltages of two parallel converters. When there is a difference in these output voltages, a voltage difference is formed, and this difference drives the zero-sequence current to circulate in the parallel branch. In simple terms, the zero-sequence voltage is equivalent to generating a driving force in the parallel system, which drives the zero-sequence current to circulate in the circuit. Therefore, the zero-sequence voltage is the root cause of the zero-sequence circulating current. Therefore, by controlling the zero-sequence voltage generated by the converter, the circulating current can be effectively eliminated.
[0064] Figure 5 A schematic flow chart of a method for suppressing circulating current in parallel converters provided in an embodiment of the present application.
[0065] Figure 6 A flowchart of a method for suppressing circulating current in parallel converters provided in an embodiment of the present application.
[0066] Combination Figures 1 to 4 The embodiment of the present application further provides a method for suppressing circulating current of a parallel converter. The execution subject of the method may be a controller, such as Figure 5 As shown, the circulating current suppression method of the parallel converter includes steps S100 to S600, which are specifically as follows:
[0067] Step S100, determining an initial reference voltage of the parallel converters.
[0068] Specifically, the initial reference voltage is a component in a natural coordinate system (abc coordinate system). The initial reference voltage includes an A-phase initial reference voltage, a B-phase initial reference voltage, and a C-phase initial reference voltage.
[0069] Specifically, each converter includes an A-phase bridge arm, a B-phase bridge arm and a C-phase bridge arm. The A-phase initial reference voltage is the reference voltage of the converter A-phase bridge arm, the B-phase initial reference voltage is the reference voltage of the converter B-phase bridge arm, and the C-phase initial reference voltage is the reference voltage of the converter C-phase bridge arm.
[0070] Combination Figure 2 As shown, in the first converter, the A-phase bridge arm includes a first three-phase full-bridge power switch tube S a,1 And the fourth three-phase full-bridge power switch tube S a,1 The B-phase bridge arm includes the second three-phase full-bridge power switch tube S b,1 And the fifth three-phase full-bridge power switch tube S b,1 The C phase bridge arm includes the third three-phase full-bridge power switch tube S c,1 and the sixth three-phase full-bridge power switch tube S c,1 In the second converter 102, the A-phase bridge arm includes the seventh three-phase full-bridge power switch tube S a,2 And the thirteenth phase full bridge power switch tube The B-phase bridge arm includes the eighth three-phase full-bridge power switch tube S b,2 And the eleventh three-phase full-bridge power switch tube The C phase bridge arm includes the ninth three-phase full-bridge power switch tube S c,2 And the twelfth three-phase full-bridge power switch tube
[0071] Optionally, step S100 includes step S101 and step S102, which are specifically as follows:
[0072] Step S101, obtaining active components and reactive components in a parallel converter in a dq coordinate system.
[0073] In this step, combine Figure 6 As shown, the active component is V d , the reactive component is V q .
[0074] Optionally, combined Figure 6 As shown, step S101 includes steps S1011 to S1015, which are specifically as follows:
[0075] Step S1011, obtaining the active current component reference value of the parallel converter Active current component measurement value I d , reactive current component reference value and the reactive current component measured value Iq .
[0076] Optionally, obtaining the active current component measurement value and the reactive current component measurement value of the parallel converter includes step S10111 and step S10112, which are specifically as follows:
[0077] Step S10111, obtaining the three-phase current value of the parallel converter in the abc coordinate system; the three-phase current value in the abc coordinate system includes the A phase current value i a , B phase current value i b and C phase current value i c .
[0078] Step S10112: convert the three-phase current value in the abc coordinate system into the active current component measurement value I in the dq coordinate system. d and the reactive current component measured value I q .
[0079] Step S1012, calculating the active current component reference value and the measured value of the active current component I d The first error A between.
[0080] Step S1013, calculating the reactive current component reference value and the reactive current component measured value I q The second error B between.
[0081] Step S1014: Based on the first error A, determine the active component V d .
[0082] Step S1015, based on the second error B, determine the reactive component V q Both the active component and the reactive component are components in the dq coordinate system.
[0083] Specifically, the controller includes a current controller, and the current controller is configured to determine an active component based on a first error; and to determine a reactive component based on a second error.
[0084] For example, in combination Figure 6 As shown, after the first error A is sent to the current controller, the active component V is obtained. d ; After the second error B is sent to the current controller, the reactive component V is obtained q .
[0085] Step S102, determining initial reference voltages corresponding to active components and reactive components, where the initial reference voltages are located in an abc coordinate system.
[0086] Specifically, combined Figure 6 As shown, the initial reference voltage of phase A is V a, the initial reference voltage of phase B is V b , the initial reference voltage of phase C is V c .
[0087] Optionally, step S102 includes step S1021 and step S1022, which are specifically as follows:
[0088] Step S1021, determining a grid phase angle θ based on the grid voltage of the parallel converter.
[0089] Specifically, the grid voltage is phase-locked by a phase-locked loop (PLL) to obtain a grid phase angle.
[0090] Step S1022, determining an initial reference voltage based on the grid phase angle, active component and reactive component.
[0091] Exemplarily, based on the grid phase angle, the active component and the reactive component are converted into an initial reference voltage in the abc coordinate system.
[0092] In this embodiment, the active component and reactive component in the dq coordinate system are converted into the initial reference voltage in the abc coordinate system to determine the reference voltage under the current operation, thereby facilitating the adjustment of the initial reference voltage according to the low-frequency zero-sequence circulating current value to reduce the low-frequency zero-sequence circulating current in the parallel converter.
[0093] Specifically, combined Figure 6 As shown, the controller includes a coordinate transformation module, which is configured to transform components in the abc coordinate system into components in the dq coordinate system, or to transform components in the dq coordinate system into components in the abc coordinate system.
[0094] Step S200, determining a voltage compensation amount based on a low-frequency zero-sequence circulating current value of the parallel converter.
[0095] Optionally, step S200 includes steps S201 to S203, which are specifically as follows:
[0096] Step S201, obtaining a low-frequency zero-sequence circulating current value.
[0097] Step S202, determining an error signal based on the low-frequency zero-sequence circulating current value and the zero-sequence circulating current reference value.
[0098] Optionally, step S202 includes step S2021, which is specifically as follows:
[0099] Step S2021, calculate the low-frequency zero-sequence circulating current value i X and zero sequence circulating current reference value The error signal includes the error difference C between them.
[0100] In this embodiment, combined with Figure 6 As shown, by calculating i Z and The error difference C between them is used to determine the error signal.
[0101] Step S203: determining a voltage compensation amount corresponding to the error signal according to the error signal.
[0102] Specifically, the controller also includes a proportional-integral controller (PI), and the PI controller is configured to determine a voltage compensation amount corresponding to the error signal according to the error signal.
[0103] Optionally, step S203 includes step S2031, which is specifically as follows:
[0104] Step S2031, input the error signal into the PI controller to determine the voltage compensation amount.
[0105] Specifically, combined Figure 6 As shown, after the error difference C is sent to the PI controller, the voltage compensation amount D is obtained, so that it is convenient to modulate the parallel converter according to the voltage compensation amount.
[0106] Exemplarily, the PI controller calculates a control signal through proportional-integral regulation and the error signal. This control signal is used to generate a compensation voltage, and the output of the PI controller is a zero-sequence voltage compensation amount (i.e., the voltage compensation amount mentioned above). The zero-sequence voltage compensation amount is used to adjust the output voltage, correct the voltage imbalance between the parallel converters, and thus suppress the low-frequency zero-sequence circulating current.
[0107] Specifically, the principle of the PI controller is: K p is the proportional gain, which determines the immediate effect of the error signal on the output. e(t) is the error signal, i.e., the low-frequency zero-sequence circulating current value i Z and zero sequence circulating current reference value The difference is K i is the integral gain, which determines the effect of the error signal accumulation on the output and helps to eliminate steady-state errors.
[0108] In this embodiment, an error signal is determined to determine the voltage compensation amount corresponding to the low-frequency zero-sequence circulating current that needs to be eliminated, thereby adjusting the initial reference voltage according to the voltage compensation amount to obtain a target reference voltage, and then adjusting the parallel converter according to the target reference voltage to reduce the low-frequency zero-sequence circulating current.
[0109] Step S300, adjusting the initial reference voltage based on the voltage compensation amount to determine the target reference voltage.
[0110] Optionally, combined Figure 6As shown, the target reference voltage includes a phase A target reference voltage, a phase B target reference voltage and a phase C target reference voltage, and the voltage compensation amount D includes a first sub-compensation amount D1, a second sub-compensation amount D2 and a third sub-compensation amount D3.
[0111] Step S300 includes steps S301 to S303, which are specifically as follows:
[0112] Step S301: Add the first sub-compensation value D1 to the initial reference voltage V of phase A. a , get the A phase target reference voltage V a * .
[0113] Step S302: Add the second sub-compensation value D2 to the initial reference voltage V of the phase B. b , get the B phase target reference voltage V b * .
[0114] Step S303: adding the third sub-compensation value D3 to the initial reference voltage V c , get the C phase target reference voltage V c * .
[0115] Specifically, the method of implementing the superposition from step S301 to step S303 is: addition.
[0116] Exemplarily, through steps S100 to S300, a zero-sequence voltage component is generated based on a low-frequency zero-sequence circulating current value, and the zero-sequence voltage component is injected into the parallel converter to reduce the low-frequency zero-sequence circulating current problem in the parallel converter.
[0117] Step S400, obtaining a low-frequency synchronization signal and a carrier signal in a parallel converter.
[0118] Figure 7 A schematic diagram of carrier synchronization of parallel converters provided in an embodiment of the present application.
[0119] For example, the low-frequency synchronization signal is Figure 7 shown.
[0120] Step S500: adjusting the carrier signal based on the low-frequency synchronization signal to determine the target carrier signal.
[0121] Optionally, the low-frequency synchronization signal includes a square wave signal with a preset period; the parallel converter includes a first converter and a second converter; the carrier signal includes a first carrier signal and a second carrier signal, the first carrier signal corresponds to the first converter, and the second carrier signal corresponds to the second converter. Step S500 includes step S501, which is as follows:
[0122] Step S501: When the low-frequency synchronization signal is a rising edge or a falling edge, synchronize the first carrier signal and the second carrier signal.
[0123] In this embodiment, based on a square wave signal (low-frequency synchronization signal) with a preset period, the first carrier signal and the second carrier signal are synchronized at a fixed time (when the low-frequency synchronization signal is at a rising edge or a falling edge), so that the low-frequency synchronization signal is used as a synchronization mechanism to achieve carrier synchronization to reduce high-frequency circulating currents in parallel converters.
[0124] For example, the falling edge of the low-frequency synchronization signal is Figure 7 As indicated in the markings.
[0125] Specifically, in the process of generating pulse width modulation signals of parallel converters, a low-frequency synchronization signal is introduced as a synchronization mechanism. By configuring the on-chip peripherals of the microprocessor, the rising edge or falling edge of the low-frequency synchronization signal is captured, and the carrier counter is forced to be cleared or set at these edge moments. That is, whenever the rising edge or falling edge of the low-frequency signal is detected, the carrier signal will be forced to be cleared or set to ensure the precise synchronization of the carrier signal to adjust and correct the phase difference between the carriers. This effectively suppresses the high-frequency circulating current between the parallel converters.
[0126] Optionally, step S501 includes step S5011, which is specifically as follows:
[0127] Step S5011, setting the first carrier signal and the second carrier signal to 0 or 1.
[0128] In this embodiment, the first carrier signal and the second carrier signal are set to 0 or 1 to synchronize the first carrier signal and the second carrier signal, thereby ensuring accurate synchronization of the carrier signals, adjusting and correcting the phase difference between the carriers, and effectively suppressing the high-frequency circulating current between the parallel converters.
[0129] Combination Figure 7 As shown, taking phase A as an example, S a1 , S a2 Respectively represent the switching actions of the switch tubes of the A-phase bridge arms of the first converter and the second converter, i a0 Represents the circulating current component in the circulating current path of phase A. Figure 7 It can be observed that the deviation of the carrier signal (between the first carrier signal and the second carrier signal) will significantly affect the synchronous action of the switch tube, resulting in inconsistent output voltages between parallel modules, thereby causing high-frequency circulating current problems in the parallel converter system. To solve this problem, a low-frequency synchronization signal is introduced. When the falling edge of the low-frequency signal is detected, the carrier signal is cleared (such as Figure 7The second carrier signal is cleared when the low-frequency synchronization signal is at a falling edge). This operation is intended to eliminate the phase difference between the first carrier signal and the second carrier signal, ensure the synchronization of the switching action, and thus effectively suppress the high-frequency circulating current in the system. Specifically, combined with S a1 , S a2 As shown, after the second carrier signal is cleared, it is synchronized with the first carrier signal, so that the switching actions of the A-phase bridge arms of the first converter and the second converter are the same, even if S a1 , S a2 synchronous.
[0130] Step S600: determining a pulse width modulation signal according to a target carrier signal and a target reference voltage.
[0131] Optionally, step S600 includes steps S601 to S603, which are specifically as follows:
[0132] Step S601, comparing a target carrier signal and a target reference voltage.
[0133] Step S602: When the target carrier signal is greater than the target reference voltage, the pulse width modulation signal is at a low level.
[0134] Step S603: when the target carrier signal is less than the target reference voltage, the pulse width modulation signal is at a high level.
[0135] In this embodiment, the target carrier signal and the target reference voltage are compared to determine the magnitude relationship between the target carrier signal and the target reference voltage, thereby determining the pulse width modulation signal according to the magnitude relationship. Furthermore, since the target carrier signal is a carrier signal adjusted according to the low-frequency synchronization signal, the first carrier signal and the second carrier signal in the target carrier signal are in a synchronous state, and the switching state of the parallel converter is adjusted by using the pulse width modulation signal generated according to the target carrier signal, the high-frequency zero-sequence circulating current caused by the asynchronism of the first carrier signal and the second carrier signal can be reduced.
[0136] Specifically, the controller further includes a pulse width modulation (PWM) module, and the PWM module is configured to determine a pulse width modulation signal according to a target carrier signal and a target reference voltage.
[0137] Exemplarily, the PWM module outputs the pulse width modulation signal of the first converter and the pulse width modulation signal of the second converter in a time-sharing manner. Taking the pulse width modulation signal of the first converter as an example, the pulse width modulation signal includes a first pulse width modulation signal, a second pulse width modulation signal, a third pulse width modulation signal, a fourth pulse width modulation signal, a fifth pulse width modulation signal and a sixth pulse width modulation signal; the first pulse width modulation signal is used to adjust the first three-phase full-bridge power switch tube S a,1The second pulse width modulation signal is used to adjust the fourth three-phase full-bridge power switch tube S a,1 The third pulse width modulation signal is used to adjust the second three-phase full-bridge power switch tube S b,1 The fourth pulse width modulation signal is used to adjust the fifth three-phase full-bridge power switch tube S b,1 The fifth pulse width modulation signal is used to adjust the third three-phase full-bridge power switch tube S c,1 The sixth pulse width modulation signal is used to adjust the sixth three-phase full-bridge power switch tube
[0138] The first pulse width modulation signal and the second pulse width modulation signal are complementary signals, the third pulse width modulation signal and the fourth pulse width modulation signal are complementary signals, and the fifth pulse width modulation signal and the sixth pulse width modulation signal are complementary signals.
[0139] Optionally, step S602 includes steps S6021 to S6023, which are specifically as follows:
[0140] Step S6021, when the target carrier signal is greater than the A-phase target reference voltage, the first pulse width modulation signal or the second pulse width modulation signal is at a low level.
[0141] Step S6022: when the target carrier signal is greater than the B-phase target reference voltage, the third PWM signal or the fourth PWM signal is at a low level.
[0142] Step S6023: when the target carrier signal is greater than the C-phase target reference voltage, the fifth pulse width modulation signal or the sixth pulse width modulation signal is at a low level.
[0143] Optionally, step S603 includes steps S6031 to S6033, which are specifically as follows:
[0144] Step S6031, when the target carrier signal is less than the A-phase target reference voltage, the first pulse width modulation signal or the second pulse width modulation signal is at a high level.
[0145] Step S6032: when the target carrier signal is less than the target reference voltage of the B phase, the third pulse width modulation signal or the fourth pulse width modulation signal is at a high level.
[0146] Step S6033: when the target carrier signal is less than the C-phase target reference voltage, the fifth pulse width modulation signal or the sixth pulse width modulation signal is at a high level.
[0147] Exemplarily, through steps S400 to S600, a low-frequency synchronization signal is introduced as a key control mechanism to reduce the high-frequency circulating current problem caused by carrier asynchrony in the parallel converter system.
[0148] Step S700, controlling the parallel converter based on the pulse width modulation signal. The circulating current suppression method of the parallel converter provided by the embodiment of the present application can adjust the initial reference voltage based on the low-frequency zero-sequence circulating current value, and then modulate the parallel converter based on the adjusted target reference voltage to reduce the low-frequency zero-sequence circulating current. The low-frequency synchronization signal is introduced as a key control mechanism to solve the high-frequency circulating current problem caused by carrier asynchrony in the parallel converter system.
[0149] Specifically, a zero-sequence voltage component (voltage compensation amount) is generated based on the low-frequency zero-sequence circulating current value, and the zero-sequence voltage component is injected into the parallel converter, that is, the zero-sequence voltage component is superimposed on the initial reference voltage to obtain the target reference voltage.
[0150] Corresponding to the embodiment of the aforementioned method for suppressing circulating current of parallel converters, the present application also provides an embodiment of a control device for parallel converters. The control of the parallel converter includes: a parallel converter and a controller. The parallel converter is communicatively connected to the controller. The controller is configured to determine the initial reference voltage of the parallel converter; determine the voltage compensation amount based on the low-frequency zero-sequence circulating current value of the parallel converter; adjust the initial reference voltage based on the voltage compensation amount to determine the target reference voltage; obtain a low-frequency synchronization signal and a carrier signal in the parallel converter; adjust the carrier signal based on the low-frequency synchronization signal to determine the target carrier signal; determine a pulse width modulation signal based on the target carrier signal and the target reference voltage; and control the parallel converter based on the pulse width modulation signal.
[0151] By adopting the circulating current suppression system of the parallel converter provided by the embodiment of the present application, the controller can adjust the initial reference voltage based on the low-frequency zero-sequence circulating current value, and then modulate the parallel converter based on the adjusted target reference voltage to reduce the low-frequency zero-sequence circulating current. The low-frequency synchronization signal is introduced as a key control mechanism to solve the high-frequency circulating current problem caused by carrier asynchrony in the parallel converter system.
[0152] Figure 8 This is a schematic diagram of the output current without circulating current suppression. Figure 8 Where (a) is the output current of the first converter, Figure 8 (b) is the output current of the second converter.
[0153] Fig. 9 It is a schematic diagram of the circulating current waveform without circulating current suppression. Fig. 9 (a) is the circulating current waveform of the first converter. Fig. 9 (b) is the circulating current waveform of the second converter.
[0154] The first converter and the second converter output three-phase current waveform and the zero-sequence circulating current waveform generated by the system are as follows: Figure 8 and Fig. 9As shown in the figure. In this case, the zero-sequence circulating current in the system includes both the low-frequency circulating current component caused by the zero-sequence voltage and the circulating current component with a low-frequency envelope caused by carrier inconsistency. The output current waveform is distorted, and the average value of the zero-sequence circulating current deviates from 0, with an obvious bias.
[0155] Fig.10 This is a schematic diagram of the output current provided in the embodiment of the present application. Fig.10 Where (a) is the output current of the first converter, Fig.10 (b) is the output current of the second converter.
[0156] Fig.11 A schematic diagram of a circulating current waveform provided in an embodiment of the present application. Fig.11 (a) is the circulating current waveform of the first converter. Fig.11 (b) is the circulating current waveform of the second converter.
[0157] In contrast, Fig.10 and Fig.11 The output current waveform obtained by the circulating current suppression method of the parallel converter proposed in the embodiment of the present application and the zero-sequence circulating current waveform generated by the system are given. It can be clearly seen that the zero-sequence circulating current control method proposed in the present invention effectively controls the low-frequency circulating current and high-frequency circulating current in the system to near 0, and the three-phase current output by the converter is symmetrical and presents a sinusoidal envelope. The simulation results prove the effectiveness and correctness of the proposed scheme.
[0158] It should be noted that those skilled in the art will easily think of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope of the present application is indicated by the claims.
[0159] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.
Claims
1. A method for suppressing circulating current of parallel converters, characterized in that: The circulating current suppression method of the parallel converter is used to suppress low-frequency zero-sequence circulating current and high-frequency zero-sequence circulating current in the parallel converter, and the circulating current suppression method of the parallel converter includes: Determining an initial reference voltage for the parallel converter; Determining a voltage compensation amount based on a low-frequency zero-sequence circulating current value of the parallel converter; Based on the voltage compensation amount, adjusting the initial reference voltage to determine a target reference voltage; Acquiring a low-frequency synchronization signal and a carrier signal in the parallel converter; Adjust the carrier signal based on the low-frequency synchronization signal to determine a target carrier signal; Determining a pulse width modulation signal according to the target carrier signal and the target reference voltage; The parallel converter is controlled based on the pulse width modulation signal.
2. The method for suppressing circulating current of parallel converters according to claim 1, characterized in that: The determining of the initial reference voltage of the parallel converter comprises: Obtaining active components and reactive components in the parallel converter in a dq coordinate system; The initial reference voltage corresponding to the active component and the reactive component is determined, and the initial reference voltage is located in an abc coordinate system.
3. The method for suppressing circulating current of parallel converters according to claim 2, characterized in that: The determining the initial reference voltage corresponding to the active component and the reactive component comprises: Determining a grid phase angle based on a grid voltage of the parallel converter; The initial reference voltage is determined based on the grid phase angle, the active component and the reactive component.
4. The method for suppressing circulating current of parallel converters according to claim 1, characterized in that: The step of determining the voltage compensation amount based on the low-frequency zero-sequence circulating current value of the parallel converter comprises: Obtaining the low-frequency zero-sequence circulating current value; Determining an error signal based on the low-frequency zero-sequence circulating current value and the zero-sequence circulating current reference value; The voltage compensation amount corresponding to the error signal is determined according to the error signal.
5. The method for suppressing circulating current of parallel converters according to claim 4, characterized in that: The step of determining an error signal based on the low-frequency zero-sequence circulating current value and the zero-sequence circulating current reference value comprises: The error difference between the low-frequency zero-sequence circulating current value and the zero-sequence circulating current reference value is calculated; and the error signal includes the error difference.
6. The method for suppressing circulating current of parallel converters according to claim 4, characterized in that: The step of determining the voltage compensation amount corresponding to the error signal according to the error signal includes: The error signal is input into a PI controller to determine the voltage compensation amount.
7. The method for suppressing circulating current of parallel converters according to claim 1, characterized in that: The low-frequency synchronization signal includes a square wave signal with a preset period; the parallel converter includes a first converter and a second converter; the carrier signal includes a first carrier signal and a second carrier signal, the first carrier signal corresponds to the first converter, and the second carrier signal corresponds to the second converter; The adjusting the carrier signal based on the low-frequency synchronization signal to determine the target carrier signal includes: When the low-frequency synchronization signal is a rising edge or a falling edge, the first carrier signal and the second carrier signal are synchronized.
8. The method for suppressing circulating current of parallel converters according to claim 7, characterized in that: The synchronizing the first carrier signal and the second carrier signal comprises: The first carrier signal and the second carrier signal are set to 0 or 1.
9. The method for suppressing circulating current of parallel converters according to claim 1, characterized in that: The step of determining a pulse width modulation signal according to a target carrier signal and a target reference voltage comprises: comparing the target carrier signal and the target reference voltage; When the target carrier signal is greater than the target reference voltage, the pulse width modulation signal is at a low level; When the target carrier signal is less than the target reference voltage, the pulse width modulation signal is at a high level.
10. A circulating current suppression system for parallel converters, characterized in that: include: A parallel converter and a controller; the parallel converter is communicatively connected with the controller; The controller is configured to determine an initial reference voltage of the parallel converter; Based on the low-frequency zero-sequence circulating current value of the parallel converter, determine the voltage compensation amount; based on the voltage compensation amount, adjust the initial reference voltage to determine the target reference voltage; obtain a low-frequency synchronization signal and a carrier signal in the parallel converter; adjust the carrier signal based on the low-frequency synchronization signal to determine the target carrier signal; determine a pulse width modulation signal according to the target carrier signal and the target reference voltage; and control the parallel converter based on the pulse width modulation signal.
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