Transistor driving circuit, half-bridge driving circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of electronics, in particular to a transistor driving circuit, a half-bridge driving circuit, a chip and electronic equipment. The transistor driving circuit comprises a first transistor, a second transistor, a third transistor, a logic control circuit and a charge pump circuit, the charge pump circuit is used for generating a second driving signal; the control signal receiving end is used for receiving the on-off control signal; and the logic control circuit is used for controlling at least one of the first transistor, the second transistor and the third transistor to act according to the on-off control signal, so that the driving signal output end outputs a corresponding transistor driving signal. According to the invention, the transistor driving signals comprise the first driving signal and the second driving signal, the first driving signal is the positive voltage driving signal, the second driving signal is the negative voltage driving signal, and the negative voltage driving signal is adopted, so that the condition that the target transistor is mistakenly triggered when the driving signals are interfered can be avoided; and the working stability of the circuit is ensured.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a transistor drive circuit, a half-bridge drive circuit, a chip and an electronic device. Background Art

[0002] Transistors have multiple functions such as detection, rectification, amplification, switching, voltage regulation, and signal modulation. Therefore, transistors can be used in a variety of circuits. In recent years, gallium nitride (GaN) transistors have been used in many circuit scenarios. Compared with traditional silicon (Si) transistors, gallium nitride transistors have lower on-resistance and can be used in scenarios that require higher operating frequencies; and gallium nitride transistors also have significant advantages over silicon transistors in terms of power density and reliability. At the same time, compared with silicon transistors, gallium nitride transistors are also cheaper. However, the driving voltage of enhancement-mode gallium nitride transistors is small, resulting in a small voltage difference between the high level and the low level used to drive the gallium nitride transistor on and off. Therefore, when the driving voltage signal is disturbed, it is easy to be mis-conducted, thereby affecting the stability of the circuit. Summary of the invention

[0003] The present application provides a transistor driving circuit, a half-bridge driving circuit, a chip and an electronic device to solve the technical problem in the related art that the driving voltage signal of the gallium nitride transistor is easily interfered and mis-conducted.

[0004] In a first aspect, the present application provides a transistor driving circuit, comprising: a first transistor, a second transistor, a third transistor, a logic control circuit, and a charge pump circuit;

[0005] The logic control circuit includes a control signal receiving end, a first control end, a second control end and a third control end;

[0006] The first control terminal is connected to the control terminal of the first transistor, the first terminal of the first transistor is used to receive a first drive signal, and the second terminal of the first transistor is a drive signal output terminal; the second terminal of the first transistor is also connected to the first terminal of the third transistor, the control terminal of the third transistor is connected to the third control terminal, and the second terminal of the third transistor is connected to the output terminal of the charge pump circuit; the first terminal of the second transistor is connected to the drive signal output terminal, the control terminal of the second transistor is connected to the third control terminal, and the second terminal of the second transistor is grounded; the positive terminal of the body diode of the second transistor is also connected to the output terminal of the charge pump circuit;

[0007] The control signal receiving end of the logic control circuit is used to receive an on-off control signal; the logic control circuit is used to control at least one action of the first transistor, the second transistor and the third transistor according to the on-off control signal, so that the drive signal output end outputs a corresponding transistor drive signal;

[0008] The transistor drive signal includes the first drive signal and the second drive signal; the first drive signal is a positive voltage drive signal, and the first drive signal is used to drive the target transistor to turn on; the second drive signal is a negative voltage drive signal, and the charge pump circuit is used to generate the second drive signal, and the second drive signal is used to control the target transistor to turn off.

[0009] In one possible design, the transistor driving circuit further includes a low voltage drop linear regulator and a first potential pin;

[0010] The input end of the low voltage drop linear regulator is used to connect to a power supply, and the output end of the low voltage drop linear regulator is connected to the first potential pin;

[0011] The low voltage difference linear regulator is used to perform voltage stabilization processing on the power supply voltage signal output by the power supply to obtain the first drive signal; the first potential pin is used to output the first drive signal.

[0012] In a possible design, the transistor driving circuit further includes a driving speed control pin and a first resistor; a first end of the first resistor is connected to the first potential pin, and a second end of the first resistor is connected to the driving speed control pin; a first electrode of the first transistor is connected to the driving speed control pin;

[0013] The greater the resistance of the first resistor is, the slower the speed at which the first transistor is driven is.

[0014] In one possible design, the transistor driving circuit also includes a power supply pin, the input end of the power supply pin is used to connect to a power supply, the output end of the power supply pin is connected to the input end of the low voltage dropout linear regulator; the output end of the low voltage dropout linear regulator is connected to the input end of the charge pump circuit.

[0015] In one possible design, the transistor driving circuit also includes an overvoltage / undervoltage protection circuit; the output end of the low voltage difference linear regulator is connected to the power supply end of the logic control circuit through the overvoltage / undervoltage protection circuit; the overvoltage / undervoltage protection circuit is used to protect the circuit from overvoltage and undervoltage.

[0016] In a second aspect, the present application further provides a half-bridge driving circuit for driving a half-bridge circuit, wherein the half-bridge circuit includes a first target transistor and a second target transistor, and the first target transistor and the second target transistor are both gallium nitride transistors; the half-bridge driving circuit includes a first transistor driving circuit and a second transistor driving circuit, and the first transistor driving circuit and the second transistor driving circuit are both transistor driving circuits as described in any one of the above items;

[0017] The half-bridge drive circuit further includes a third logic control circuit, a first drive signal receiving end and a second drive signal receiving end, wherein the first drive signal receiving end and the second drive signal receiving end are both connected to the third logic control circuit, and the third logic control circuit is respectively connected to the control signal receiving ends of the first transistor drive circuit and the second transistor drive circuit; the drive signal output end of the first transistor drive circuit is connected to the control electrode of the first target transistor, and the drive signal output end of the second transistor drive circuit is connected to the control electrode of the second target transistor;

[0018] The first drive signal receiving end is used to receive a first drive signal, and the second drive signal receiving end is used to receive a second drive signal; the third logic control circuit is used to generate a first on-off control signal according to the first drive signal and generate a second on-off control signal according to the second drive signal;

[0019] The first on-off control signal is used to control the first transistor driving circuit to output a first transistor driving signal, and the second on-off control signal is used to control the second transistor driving circuit to output a second transistor driving signal; the first transistor driving signal is used to control the conduction and cutoff of the first target transistor, and the second transistor driving signal is used to control the conduction and cutoff of the second target transistor.

[0020] In a possible design, the half-bridge drive circuit further includes a drive shutdown pin, and the drive shutdown pin is connected to the third logic control circuit;

[0021] The drive shutdown pin is used to receive a drive shutdown signal, and the third logic control circuit is used to output a first shutdown signal and a second shutdown signal according to the drive shutdown signal; the first shutdown signal is used to control the first transistor drive circuit to stop working, and the second shutdown signal is used to control the second transistor drive circuit to stop working.

[0022] In a possible design, the half-bridge driving circuit further includes an over-temperature protection circuit, an under-voltage protection circuit, a fault feedback pin, a tenth transistor, and an OR gate circuit;

[0023] The over-temperature protection circuit and the under-voltage protection circuit are connected to the third logic control circuit, the third logic control circuit includes an over-temperature protection signal output terminal and an under-voltage protection signal output terminal, the over-temperature protection signal output terminal and the under-voltage protection signal output terminal are connected to the input terminal of the OR gate circuit, the output terminal of the OR gate circuit is connected to the control electrode of the tenth transistor, the first electrode of the tenth transistor is connected to the fault feedback pin, and the second electrode of the tenth transistor is grounded;

[0024] The over-temperature protection circuit is used to output an over-temperature protection signal when it is detected that the circuit is in an over-temperature state, and the under-voltage protection circuit is used to output an under-voltage protection signal when it is detected that the circuit is in an under-voltage state; the third logic control circuit is used to output the over-temperature protection signal and the under-voltage protection signal to the OR gate circuit; the OR gate circuit is used to perform OR gate processing on the over-temperature protection signal and the under-voltage protection signal, so that when the over-temperature protection signal and / or the under-voltage protection signal are received, a transistor trigger signal is output; the transistor trigger signal is used to drive the tenth transistor to turn on, so that the fault feedback pin outputs a fault signal.

[0025] In a third aspect, the present application further provides a chip, which includes a transistor driving circuit as described in any one of the above items; or includes a half-bridge driving circuit as described in any one of the above items.

[0026] In a fourth aspect, the present application also provides an electronic device, which includes a transistor driving circuit as described in any one of the above items; or includes a half-bridge driving circuit as described in any one of the above items.

[0027] The transistor driving circuit provided by the first aspect above includes: a first transistor, a second transistor, a third transistor, a logic control circuit and a charge pump circuit; the logic control circuit includes a control signal receiving end, a first control end, a second control end and a third control end; the first control end is connected to the control electrode of the first transistor, the first electrode of the first transistor is used to receive the first driving signal, and the second electrode of the first transistor is a driving signal output end; the second electrode of the first transistor is also connected to the first electrode of the third transistor, the control electrode of the third transistor is connected to the third control end, and the second electrode of the third transistor is connected to the output end of the charge pump circuit; the first electrode of the second transistor is connected to the driving signal output end, the control electrode of the second transistor is connected to the third control end, and the second electrode of the second transistor is grounded; the positive electrode of the body diode of the second transistor is connected to the output end of the charge pump circuit; the control signal receiving end is used to receive an on-off control signal; the logic control circuit is used to control at least one action of the first transistor, the second transistor and the third transistor according to the on-off control signal, so that the driving signal output end outputs the corresponding transistor driving signal. Among them, the transistor driving signal in the present application includes a first driving signal and a second driving signal, the first driving signal is a positive voltage driving signal, and the second driving signal is a negative voltage driving signal. The charge pump circuit is used to generate the second driving signal. The use of a negative voltage driving signal can avoid the situation where the target transistor is falsely triggered when the driving signal is interfered with, thereby ensuring the stability of the circuit during operation.

[0028] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0030] Figure 1 A driving signal waveform diagram for driving a gallium nitride transistor provided in the related art;

[0031] Figure 2 A schematic diagram of the structure of a transistor driving circuit provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the structure of a second transistor provided in an embodiment of the present application;

[0033] Figure 4A schematic diagram of a charge pump circuit structure provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of a current loop of a charge pump circuit in a charging state provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of a current loop of a charge pump circuit in a discharge state provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of the structure of an asymmetric half-bridge flyback converter provided in an embodiment of the present application;

[0037] Figure 8 A schematic diagram of the structure of a half-bridge drive circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0039] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0040] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor.

[0042] The driving voltage of the GaN transistor is relatively small, resulting in a small voltage difference between the high level and the low level used to drive the GaN transistor on and off. Therefore, when the driving voltage signal is disturbed, mis-conduction is prone to occur, thereby affecting the stability of the circuit. Figure 1 For a driving signal waveform diagram for driving a gallium nitride transistor provided in the related art, see Figure 1 As shown, for example, in the related art, high and low level signals are sampled to drive transistors, such as Figure 1 As shown in (a), the high-level signal is 6V and the low-level signal is 0V. The high-level signal is used to drive the transistor to turn on, and the low-level signal is used to drive the transistor to turn off. In this way, when the high-level signal is interfered with, the high-level signal is easy to drop to near 0V; or when the low-level signal is interfered with, the low-level signal is easy to be pulled up to near 6V, which will cause the transistor to be triggered by mistake, thereby causing circuit errors, that is, affecting the stability of the circuit.

[0043] In order to overcome the technical problem that GaN transistors are prone to mis-conduction, the related art proposes to use a voltage-stabilizing diode resistor-capacitor voltage divider circuit to output a negative voltage signal to drive the transistor on and off. The driving signal waveform is as follows: Figure 1 As shown in (b), however, a Zener diode resistor-capacitor voltage divider circuit is used to drive the GaN transistor, which usually requires multiple external capacitors and Zener diodes, which makes the structure of the driving circuit very complicated and the hardware cost is high.

[0044] In order to overcome the technical problem of high hardware cost when using a voltage-stabilizing diode resistor-capacitor voltage divider circuit to drive a gallium nitride transistor, the present application proposes to use a charge pump circuit or a Buck-Boost circuit to generate a negative voltage drive signal to drive the gallium nitride transistor to work. However, after testing, when the Buck-Boost circuit is integrated into the driving circuit to generate a negative voltage drive signal for driving the gallium nitride transistor, it cannot be integrated into the driving chip due to the presence of an inductor in the Buck-Boost circuit. The charge pump circuit is composed of capacitors, and the capacitors in the charge pump circuit can use flying capacitors with smaller capacity, so the charge pump circuit can be integrated in the driving circuit. However, the charge pump circuit has a weaker load capacity when the capacity of the flying capacitor is small, and the driving chip is required to have a higher current pull-in current capability. Therefore, directly using a charge pump circuit to generate a negative voltage drive signal will result in insufficient driving capability of the driving chip, and the negative voltage drive signal output by the charge pump circuit is pulled up to the ground potential, that is, the negative voltage drive signal output by the charge pump circuit is pulled up to 0V, resulting in the gallium nitride transistor being unable to be driven.

[0045] In order to overcome the defects in the above-mentioned related technologies, the present application provides a transistor driving circuit, which includes: a first transistor, a second transistor, a third transistor, a logic control circuit and a charge pump circuit; the logic control circuit is used to receive an on-off control signal, and control at least one action of the first transistor, the second transistor and the third transistor according to the on-off control signal, so that the drive signal output terminal outputs a corresponding transistor driving signal. Among them, the transistor driving signal in the present application includes a first driving signal and a second driving signal, the first driving signal is a positive voltage driving signal, and the second driving signal is a negative voltage driving signal, and the use of a negative voltage driving signal can avoid the situation where the target transistor is falsely triggered when the driving signal is interfered, thereby ensuring the stability of the circuit during operation.

[0046] Figure 2 For a schematic diagram of the transistor driving circuit structure provided in the embodiment of the present application, please refer to Figure 2As shown, the transistor driving circuit includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, a logic control circuit 20 and a charge pump circuit CP. The logic control circuit 20 includes a control signal receiving terminal, a first control terminal, a second control terminal and a third control terminal; the first control terminal is connected to the control electrode of the first transistor Q1, the first electrode of the first transistor Q1 is used to receive the first driving signal, and the second electrode of the first transistor Q1 is a driving signal output terminal G; the second electrode of the first transistor Q1 is also connected to the first electrode of the third transistor Q3, the control electrode of the third transistor Q3 is connected to the third control terminal, and the second electrode of the third transistor Q3 is connected to the output terminal of the charge pump circuit CP; the first electrode of the second transistor Q2 is connected to the driving signal output terminal G, the control electrode of the second transistor Q2 is connected to the third control terminal, and the second electrode of the second transistor Q2 is grounded GND; the positive electrode of the body diode D2 of the second transistor Q2 is connected to the output terminal of the charge pump circuit CP.

[0047] Among them, the control signal receiving end of the logic control circuit 20 is used to receive the on-off control signal PWM; the logic control circuit 20 is used to control at least one action of the first transistor Q1, the second transistor Q2 and the third transistor Q3 according to the on-off control signal PWM, so that the drive signal output end G outputs the corresponding transistor drive signal, and the transistor drive signal includes the first drive signal and the second drive signal.

[0048] The charge pump circuit CP of this embodiment is used to generate a second drive signal, and the first electrode of the first transistor Q1 is used to receive the first drive signal; the transistor drive signal includes the first drive signal and the second drive signal generated by the charge pump circuit CP, the first drive signal is a positive voltage drive signal, that is, a positive high-level signal, and the second drive signal is a negative voltage drive signal. When working, the first drive signal is used to drive the target transistor to turn on, and the second drive signal is used to control the target transistor to turn off.

[0049] It can be seen that according to the transistor driving circuit provided by the present embodiment, the logic control circuit 20 can control the corresponding transistor action according to the received on-off control signal PWM, so that the drive signal output terminal G outputs the corresponding transistor driving signal. Specifically, when the logic control circuit 20 receives the on-off control signal PWM as a high-level signal, the first transistor Q1 is controlled to be turned on, so that the drive signal output terminal G outputs the first drive signal received by the first electrode of the first transistor Q1, thereby driving the target transistor to be turned on. When the logic control circuit 20 receives the on-off control signal PWM as a low-level signal, the second transistor Q2 is first controlled to be turned on. At this time, the potential at the drive signal output terminal G is the same as the ground terminal GND, and the target transistor can be controlled to be turned off; when the potential of the drive signal output terminal G is detected to be 0V, the logic control circuit 20 controls the third transistor Q3 to be turned on. At this time, the potential of the drive signal output terminal G is the negative voltage drive signal output by the charge pump circuit CP, so that the target transistor can be controlled to be reliably turned off, avoiding the target transistor from being triggered by mistake, and ensuring the stability of the circuit. At the same time, in this embodiment, when the driving signal is the first driving signal to 0V, the low level of the driving signal is connected to the ground, and the low level of the driving signal is connected to the negative voltage driving potential only when the driving signal reaches 0V; for example, when the driving signal is 6V to 0V, the low level of the driving signal is connected to the ground, and when the driving signal reaches 0V, the low level of the driving signal is connected to -2V, thereby avoiding the problem that the flying capacitor of the charge pump circuit is integrated inside the chip and cannot carry a large current.

[0050] In some embodiments, Figure 1 As shown in (b), the negative voltage driving signal output by the charge pump circuit CP can be specifically -2V. When the logic control circuit 20 controls the third transistor Q3 to be turned on, the potential of the driving signal output terminal G is -2V output by the charge pump circuit CP, thereby stably controlling the target transistor to be turned off and avoiding the target transistor from being triggered incorrectly.

[0051] It can be understood that if the positive electrode of the body diode D2 of the second transistor Q2 is short-circuited with its second electrode, when the third transistor Q3 is turned on, the body diode D2 of the second transistor Q2 is also turned on, and the potential of the drive signal output terminal G is the negative conduction voltage drop of the body diode D2, for example, -0.3V, rather than the -2V output by the charge pump circuit CP, so that the target transistor cannot be reliably turned off.

[0052] Please continue to see Figure 2 As shown, in some embodiments, the driving circuit further includes a negative voltage signal terminal VDDN, and the output end of the charge pump circuit CP is connected to the negative voltage signal terminal VDDN, that is, the potential on the negative voltage signal terminal VDDN is -2V.

[0053] Figure 3For a schematic diagram of the structure of the second transistor provided in the embodiment of the present application, see Figure 3 As shown, in this embodiment, the second transistor Q2 is taken as an NMOS tube as an example to illustrate its structure. In this embodiment, after the anode B of the body diode of the second transistor is connected to the negative voltage signal terminal VDDN, there is no forward-biased PN in the tube in the isolation area. When the drain D terminal is pulled to a negative voltage, the body diode D2 of the NMOS tube will not be turned on, thereby avoiding false triggering of the circuit. Figure 3 In the figure, WN and NWHT are isolation regions, Psub is the substrate, and WP is the P-well for high-voltage area applications.

[0054] In some embodiments, please see Figure 2 As shown, the transistor driving circuit also includes a low voltage difference linear regulator LDO and a first potential pin VDDP. The input end of the low voltage difference linear regulator LDO is used to connect to the power supply, so as to receive the power supply voltage signal VCC provided by the power supply, and the output end of the low voltage difference linear regulator LDO is connected to the first potential pin VDDP. The low voltage difference linear regulator LDO is used to perform voltage stabilization and voltage conversion processing on the power supply voltage signal VCC output by the power supply to obtain a first drive signal, and then output the first drive signal from the first potential pin VDDP. For example, the input power supply voltage signal VCC is stabilized and voltage converted by the low voltage difference linear regulator LDO to obtain a first drive signal as a 6V voltage signal, and then the first potential pin VDDP outputs a 6V voltage signal.

[0055] The first electrode of the first transistor Q1 is indirectly connected to the first potential pin VDDP, so that when the first transistor Q1 is turned on, the driving signal output terminal G outputs the 6V driving signal received by the first electrode of the first transistor Q1, thereby driving the target transistor to turn on.

[0056] In some embodiments, please see Figure 2 As shown, the transistor driving circuit also includes a driving speed control pin RON and a first resistor (not shown in the figure); the first end of the first resistor is connected to the first potential pin VDDP, and the second end of the first resistor is connected to the driving speed control pin RON; the first electrode of the first transistor Q1 is connected to the driving speed control pin RON.

[0057] It can be understood that the speed at which the first transistor Q1 is driven is inversely proportional to the driving current. The larger the resistance value of the first resistor is, the smaller the current input to the first electrode of the first transistor Q1 is, and the slower the speed at which the first transistor Q1 is driven. Therefore, the speed at which the first transistor Q1 is driven can be changed by adjusting the resistance value of the first resistor.

[0058] Please continue to see Figure 2As shown, in some embodiments, the transistor driving circuit also includes a power supply pin, an input end of the power supply pin is used to connect to a power supply, thereby receiving a power supply voltage signal VCC output by the power supply, and an output end of the power supply pin is connected to an input end of a low voltage difference linear regulator LDO; the output end of the low voltage difference linear regulator LDO is connected to an input end of a charge pump circuit CP to power the charge pump circuit CP.

[0059] Please continue to see Figure 2 As shown, in some embodiments, the transistor driving circuit further includes an overvoltage / undervoltage protection circuit 21; the output end of the low voltage difference linear regulator LDO is connected to the power supply end of the logic control circuit 20 through the overvoltage / undervoltage protection circuit 21; the overvoltage / undervoltage protection circuit 21 is used to protect the circuit from overvoltage and undervoltage. It should be noted that the overvoltage / undervoltage protection circuit 21 of this embodiment can adopt the overvoltage / undervoltage protection circuit commonly used in the circuit field, which will not be described here.

[0060] This embodiment uses a charge pump circuit to generate the above negative voltage drive signal. The charge pump circuit uses a simple circuit to achieve DC / DC boost, buck, negative voltage and other converter functions by using different charging and discharging connection methods of the switch capacitor. Compared with the switch converter containing inductor, the charge pump circuit is smaller in size, does not have the electromagnetic interference (EMI) problem caused by the inductor and transformer, and the capacitor is easier to integrate with the chip, so the charge pump circuit can be applied to the transistor drive circuit.

[0061] Figure 4 For a schematic diagram of a charge pump circuit structure provided in an embodiment of the present application, see Figure 4 As shown, the charge pump circuit includes a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, a flying capacitor C fly , input capacitance C in And the output capacitor C out Among them, the input capacitance C in The first end is connected to the positive electrode of the power supply, and the input capacitor C in The second end is connected to the negative electrode of the power supply, which is used to provide a power supply voltage V in The first electrode of the fourth transistor Q4 is connected to the positive electrode of the power supply, the second electrode of the fourth transistor Q4 is connected to the first electrode of the sixth transistor Q6, the second electrode of the sixth transistor Q6 is connected to the negative electrode of the power supply, and the second electrode of the fourth transistor Q4 is also connected to the flying capacitor C fly The first end of the flying capacitor C flyThe second end of the capacitor C is connected to the second electrode of the fifth transistor Q5, the first electrode of the fifth transistor Q5 is the positive electrode of the voltage output terminal, the second electrode of the fifth transistor Q5 is connected to the first electrode of the seventh transistor Q7, the second electrode of the seventh transistor Q7 is the negative electrode of the voltage output terminal, and the output terminal capacitor C out The first end of the capacitor C is connected to the first electrode of the fifth transistor Q5. out The second end of is connected to the second electrode of the seventh transistor Q7. The positive and negative electrodes of the voltage output terminal are used to output the voltage V out The control terminals of the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 are respectively used to receive driving signals to control the on and off of each transistor.

[0062] Figure 5 For a current loop diagram of the charge pump circuit in the charging state provided in the embodiment of the present application, please refer to Figure 5 As shown, in the charging stage of the charge pump circuit, the fourth transistor Q4 and the seventh transistor Q7 are first controlled to be turned on. At this time, the flow direction of the current loop in the charge pump circuit is as follows: Figure 5 As shown, the supply voltage V in For flying capacitor C fly For charging, there is V fly =V in . Figure 6 For a current loop diagram of the charge pump circuit in the discharge state provided in the embodiment of the present application, please refer to Figure 6 As shown, in the discharge stage, the fifth transistor Q5 and the sixth transistor Q6 are first controlled to be turned on. At this time, the flow direction of the current loop in the charge pump circuit is as follows: Figure 6 As shown, V out =-V fly =-V in , in order to output negative pressure signal.

[0063] The transistor driving circuit provided in the present application is described below by taking the application of the transistor driving circuit in a 700V half-bridge flyback converter as an example.

[0064] Figure 7 For a schematic diagram of the asymmetric half-bridge flyback converter structure provided in the embodiment of the present application, see Figure 7As shown, the half-bridge flyback converter includes a power supply V1, a first capacitor C1, a second capacitor C2, a capacitor Cr, an inductor LK, a first diode D1, a flyback converter T, an eighth transistor Q8 and a ninth transistor Q9. The second capacitor C2 is connected in parallel to both ends of the power supply V1, the first electrode of the eighth transistor Q8 is connected to the positive electrode of the power supply V1, the second electrode of the eighth transistor Q8 is connected to the first electrode of the ninth transistor Q9, and the second electrode of the ninth transistor Q9 is grounded PGND. The first end of the inductor LK is connected to the second electrode of the eighth transistor Q8, the second end of the inductor LK is connected to the first end of the primary winding of the flyback converter T, the first end of the capacitor Cr is connected to the second electrode of the ninth transistor Q9, and the second end of the capacitor Cr is connected to the second end of the primary winding of the flyback converter T. Among them, the first end of the secondary winding of the flyback converter T is connected to the positive electrode of the first diode D1, the negative electrode of the first diode D1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the second end of the secondary winding of the flyback converter T, and at the same time, the second end of the first capacitor C1 is also grounded SGND.

[0065] Figure 8 This is a schematic diagram of the structure of a half-bridge driving circuit provided in an embodiment of the present application. The half-bridge driving circuit is used to drive a half-bridge circuit. Generally, the half-bridge circuit includes a first target transistor and a second target transistor. Both the first target transistor and the second target transistor are gallium nitride transistors. The half-bridge driving circuit is used to output a driving signal to drive the first target transistor and the second target transistor to operate. Figure 8 As shown, the half-bridge drive circuit includes a first transistor drive circuit 21 and a second transistor drive circuit 31. The first transistor drive circuit 21 and the second transistor drive circuit 31 are both transistor drive circuits provided by the above-mentioned embodiments. The first transistor drive circuit 21 and the second transistor drive circuit 31 are respectively used to output corresponding drive signals to drive the first target transistor and the second target transistor to operate.

[0066] Please continue to see Figure 8 As shown, the first transistor driving circuit 21 includes a first low voltage difference linear regulator 22, a first overvoltage / undervoltage protection circuit 23, a first logic control circuit 24, a first charge pump circuit 25, an eleventh transistor Q11, a twelfth transistor Q12 and a thirteenth transistor Q13. Among them, HG is a driving signal output terminal, HRON is a driving speed control pin, HVDDP is a first potential pin, and BST is a power supply pin. Among them, the structure of the first transistor driving circuit 21 is the same as the transistor driving circuit structure provided in the above embodiment, and the working principle of each device is also the same, which will not be repeated here.

[0067] Please continue to see Figure 8As shown, the second transistor driving circuit 31 includes a second low voltage difference linear regulator 32, a second overvoltage / undervoltage protection circuit 33, a second logic control circuit 34, a second charge pump circuit 35, a fourteenth transistor Q14, a fifteenth transistor Q15 and a sixteenth transistor Q16. Among them, LG is a driving signal output terminal, LRON is a driving speed control pin, and LVDDP is a first potential pin. Among them, the structure of the second transistor driving circuit 31 is the same as the transistor driving circuit structure provided in the above embodiment, and the working principle of each device is also the same, which will not be repeated here.

[0068] Among them, the half-bridge drive circuit also includes a first level conversion circuit 26 and a second level conversion circuit 36. The third logic control circuit 41 is connected to the first logic control circuit 24 and the second logic control circuit 34 through the first level conversion circuit 26 and the second level conversion circuit 36 ​​respectively. The first level conversion circuit 26 and the second level conversion circuit 36 ​​are used for level conversion to output corresponding on-off control signals.

[0069] Furthermore, the half-bridge drive circuit of this embodiment also includes a third logic control circuit 31, a first drive signal receiving terminal INL and a second drive signal receiving terminal INH. The first drive signal receiving terminal INL and the second drive signal receiving terminal INH are both connected to the third logic control circuit 31, and the third logic control circuit 31 is respectively connected to the control signal receiving terminals of the first transistor drive circuit 21 and the second transistor drive circuit 31; the drive signal output terminal of the first transistor drive circuit 21 is connected to the control electrode of the first target transistor, and the drive signal output terminal of the second transistor drive circuit 31 is connected to the control electrode of the second target transistor.

[0070] For details, please combine Figure 7 and Figure 8 As shown, Figure 7 Take the half-bridge flyback converter provided as an example. Figure 7 The eighth transistor Q8 and the ninth transistor Q9 are respectively equivalent to the first target transistor and the second target transistor, the driving signal output terminal HG of the first transistor driving circuit 21 is connected to the control electrode of the eighth transistor Q8, and the driving signal output terminal LG of the second transistor driving circuit 31 is connected to the control electrode of the ninth transistor Q9.

[0071] Among them, the first drive signal receiving terminal INL is used to receive the first drive signal, and the second drive signal receiving terminal INH is used to receive the second drive signal; the third logic control circuit 41 is used to generate a first on-off control signal according to the first drive signal and to generate a second on-off control signal according to the second drive signal; the first on-off control signal is used to control the first transistor drive circuit 21 to output the first transistor drive signal, and the second on-off control signal is used to control the second transistor drive circuit 31 to output the second transistor drive signal; the first transistor drive signal is used to control the conduction and cutoff of the first target transistor, and the second transistor drive signal is used to control the conduction and cutoff of the second target transistor.

[0072] Specifically, in this embodiment, the first transistor driving signal is used to control the on and off of the eighth transistor Q8, and the second transistor driving signal is used to control the on and off of the ninth transistor Q9.

[0073] In some embodiments, the half-bridge drive circuit of this embodiment also includes a drive shutdown pin / SD, which is connected to the third logic control circuit 41; the drive shutdown pin / SD is used to receive a drive shutdown signal, and the third logic control circuit 41 is used to output a first shutdown signal and a second shutdown signal according to the drive shutdown signal; the first shutdown signal is used to control the first transistor drive circuit 21 to stop working, and the second shutdown signal is used to control the second transistor drive circuit 31 to stop working.

[0074] It is understandable that when a circuit fault, over-temperature, over-current or over-voltage condition is detected, a shutdown signal can be driven by driving the shutdown pin / SD input to control the corresponding transistor drive circuit to stop working, so as to protect the circuit.

[0075] In some embodiments, the half-bridge drive circuit of this embodiment also includes a first hysteresis comparator 42, a second hysteresis comparator 43 and a third hysteresis comparator 44, the first drive signal receiving terminal INL is connected to the third logic control circuit 41 through the first hysteresis comparator 42, the second drive signal receiving terminal INH is connected to the third logic control circuit 41 through the second hysteresis comparator 43; the drive shutdown pin / SD is connected to the third logic control circuit 41 through the third hysteresis comparator 44.

[0076] In some embodiments, the half-bridge driving circuit of this embodiment further includes a pull-down resistor 47, a pull-down resistor 48, and a pull-down resistor 49. The first end of the pull-down resistor 47 is connected to the first driving signal receiving terminal INL, and the second end thereof is grounded; the first end of the pull-down resistor 48 is connected to the second driving signal receiving terminal INH, and the second end thereof is grounded; the first end of the pull-down resistor 49 is connected to the driving shutdown pin / SD, and the second end thereof is grounded.

[0077] In some embodiments, the half-bridge drive circuit of this embodiment also includes an over-temperature protection circuit, an under-voltage protection circuit 46, a fault feedback pin / FLT, a tenth transistor Q10 and an OR gate circuit 45; the over-temperature protection circuit and the under-voltage protection circuit are connected to the third logic control circuit 41, the third logic control circuit 41 includes an over-temperature protection signal output terminal OTP and an under-voltage protection signal output terminal UVLO, the over-temperature protection signal output terminal OTP and the under-voltage protection signal output terminal UVLO are connected to the input terminal of the OR gate circuit 45, the output terminal of the OR gate circuit 45 is connected to the control electrode of the tenth transistor Q10, the first electrode of the tenth transistor Q10 is connected to the fault feedback pin / FLT, and the second electrode of the tenth transistor Q10 is grounded.

[0078] Among them, the over-temperature protection circuit is used to output an over-temperature protection signal when it is detected that the circuit is in an over-temperature state, and the under-voltage protection circuit 46 is used to output an under-voltage protection signal when it is detected that the circuit is in an under-voltage state; the third logic control circuit 41 is used to output the over-temperature protection signal and the under-voltage protection signal to the OR gate circuit 45; the OR gate circuit 45 is used to perform OR gate processing 45 on the over-temperature protection signal and the under-voltage protection signal, so that when the over-temperature protection signal and / or the under-voltage protection signal are received, a transistor trigger signal is output; the transistor trigger signal is used to drive the tenth transistor Q10 to turn on, so that the fault feedback pin / FLT outputs a fault signal.

[0079] In some embodiments, when it is detected that the fault feedback pin / FLT outputs a fault signal, a shutdown signal can be input through the shutdown pin / SD to control the corresponding transistor drive circuit to stop working, so as to protect the circuit.

[0080] It can be understood that, in this embodiment, the first transistor Q1, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the tenth transistor Q10, the eleventh transistor Q11 and the fourteenth transistor Q14 can all be NMOS (N-Metal-Oxide-Semiconductor) tubes, and in other embodiments, the transistor Q1 can also be a PMOS (P-Metal-Oxide-Semiconductor) tube. For example, when the first transistor Q1, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eleventh transistor Q11 and the fourteenth transistor Q14 are NMOS tubes, the first pole is the source, the second pole is the drain, and the control pole is the gate; or the first pole is the drain, the second pole is the source, and the control pole is the gate. In addition, the second transistor Q2, the third transistor Q3, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the twelfth transistor Q12, the thirteenth transistor Q13, the fifteenth transistor Q15 and the sixteenth transistor Q16 of the present embodiment can adopt PMOS (P-Metal-Oxide-Semiconductor) tubes, whose first pole is the drain, the second pole is the source, and the control pole is the gate.

[0081] An embodiment of the present application also provides a chip, which includes the transistor driving circuit as described above; or includes the half-bridge driving circuit as described above; in other words, the above-mentioned transistor driving circuit or half-bridge driving circuit can be integrated into one circuit.

[0082] An embodiment of the present application further provides an electronic device, which includes the transistor driving circuit as described above; or includes the half-bridge driving circuit as described above.

[0083] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A transistor driving circuit, characterized in that: include: A first transistor, a second transistor, a third transistor, a logic control circuit, and a charge pump circuit; The first electrode of the first transistor is used to receive the first drive signal, and the second electrode is the drive signal output terminal; the second electrode of the first transistor is respectively connected to the first electrode of the second transistor and the first electrode of the third transistor, and the second electrode of the second transistor is grounded; the output terminal of the charge pump circuit is respectively connected to the second electrode of the third transistor and the positive electrode of the positive electrode of the body diode in the second transistor; the control electrodes of the first transistor, the second transistor and the third transistor are all connected to the logic control circuit; The control signal receiving end of the logic control circuit is used to receive an on-off control signal; the logic control circuit is used to control at least one action of the first transistor, the second transistor and the third transistor according to the on-off control signal, so that the drive signal output end outputs a corresponding transistor drive signal; The transistor drive signal includes the first drive signal and the second drive signal; the first drive signal is a positive voltage drive signal, and the first drive signal is used to drive the target transistor to turn on; the second drive signal is a negative voltage drive signal, and the charge pump circuit is used to generate the second drive signal, and the second drive signal is used to control the target transistor to turn off.

2. The transistor driving circuit according to claim 1, characterized in that: Also included is a low voltage dropout linear regulator and a first potential pin; The input end of the low voltage drop linear regulator is used to connect to a power supply, and the output end of the low voltage drop linear regulator is connected to the first potential pin; The low voltage drop linear regulator is used to perform voltage stabilization processing on the power supply voltage signal output by the power supply to obtain the first drive signal; The first potential pin is used to output the first driving signal.

3. The transistor driving circuit according to claim 2, characterized in that: It also includes a driving speed control pin and a first resistor; the first end of the first resistor is connected to the first potential pin, the second end of the first resistor is connected to the driving speed control pin; the first electrode of the first transistor is connected to the driving speed control pin; The greater the resistance of the first resistor is, the slower the speed at which the first transistor is driven is.

4. The transistor driving circuit according to claim 2 or 3, characterized in that: It also includes a power supply pin, the input end of the power supply pin is used to connect to a power supply, the output end of the power supply pin is connected to the input end of the low voltage difference linear regulator; the output end of the low voltage difference linear regulator is connected to the input end of the charge pump circuit.

5. The transistor driving circuit according to claim 2 or 3, characterized in that: It also includes an overvoltage / undervoltage protection circuit; the output end of the low voltage difference linear regulator is connected to the power supply end of the logic control circuit through the overvoltage / undervoltage protection circuit; the overvoltage / undervoltage protection circuit is used to protect the circuit from overvoltage and undervoltage.

6. A half-bridge driving circuit, for driving a half-bridge circuit, wherein the half-bridge circuit comprises a first target transistor and a second target transistor, wherein both the first target transistor and the second target transistor are gallium nitride transistors; characterized in that: The half-bridge driving circuit comprises a first transistor driving circuit and a second transistor driving circuit, wherein the first transistor driving circuit and the second transistor driving circuit are both transistor driving circuits according to any one of claims 1 to 5; The half-bridge drive circuit further includes a third logic control circuit, a first drive signal receiving end and a second drive signal receiving end, wherein the first drive signal receiving end and the second drive signal receiving end are both connected to the third logic control circuit, and the third logic control circuit is respectively connected to the control signal receiving ends of the first transistor drive circuit and the second transistor drive circuit; the drive signal output end of the first transistor drive circuit is connected to the control electrode of the first target transistor, and the drive signal output end of the second transistor drive circuit is connected to the control electrode of the second target transistor; The first drive signal receiving end is used to receive a first drive signal, and the second drive signal receiving end is used to receive a second drive signal; The third logic control circuit is used to generate a first on-off control signal according to the first drive signal and to generate a second on-off control signal according to the second drive signal; The first on-off control signal is used to control the first transistor driving circuit to output a first transistor driving signal, and the second on-off control signal is used to control the second transistor driving circuit to output a second transistor driving signal; the first transistor driving signal is used to control the conduction and cutoff of the first target transistor, and the second transistor driving signal is used to control the conduction and cutoff of the second target transistor.

7. The half-bridge driving circuit according to claim 6, characterized in that: It also includes a drive shutdown pin, wherein the drive shutdown pin is connected to the third logic control circuit; The drive shutdown pin is used to receive a drive shutdown signal, and the third logic control circuit is used to output a first shutdown signal and a second shutdown signal according to the drive shutdown signal; the first shutdown signal is used to control the first transistor drive circuit to stop working, and the second shutdown signal is used to control the second transistor drive circuit to stop working.

8. The half-bridge driving circuit according to claim 6, characterized in that: It also includes an over-temperature protection circuit, an under-voltage protection circuit, a fault feedback pin, a tenth transistor, and an OR gate circuit; The over-temperature protection circuit and the under-voltage protection circuit are connected to the third logic control circuit, the third logic control circuit includes an over-temperature protection signal output terminal and an under-voltage protection signal output terminal, the over-temperature protection signal output terminal and the under-voltage protection signal output terminal are connected to the input terminal of the OR gate circuit, the output terminal of the OR gate circuit is connected to the control electrode of the tenth transistor, the first electrode of the tenth transistor is connected to the fault feedback pin, and the second electrode of the tenth transistor is grounded; The over-temperature protection circuit is used to output an over-temperature protection signal when it is detected that the circuit is in an over-temperature state, and the under-voltage protection circuit is used to output an under-voltage protection signal when it is detected that the circuit is in an under-voltage state; the third logic control circuit is used to output the over-temperature protection signal and the under-voltage protection signal to the OR gate circuit; the OR gate circuit is used to perform OR gate processing on the over-temperature protection signal and the under-voltage protection signal, so that when the over-temperature protection signal and / or the under-voltage protection signal are received, a transistor trigger signal is output; the transistor trigger signal is used to drive the tenth transistor to turn on, so that the fault feedback pin outputs a fault signal.

9. A chip, characterized in that: It comprises the transistor driving circuit as described in any one of claims 1 to 5; or it comprises the half-bridge driving circuit as described in any one of claims 6 to 8.

10. An electronic device, characterized in that: It comprises the transistor driving circuit as described in any one of claims 1 to 5; or it comprises the half-bridge driving circuit as described in any one of claims 6 to 8.

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