Control apparatus and method for switching voltage regulator

Abstract

The embodiment of the invention relates to a control device and method for a switching voltage regulator. The control loop circuit generates a control signal indicative of a difference between an output voltage of the switching circuit and a nominal voltage. A drive signal generator is coupled to the control loop circuit and receives a measurement signal indicative of a current flowing in the switching circuit. The drive signal generator also receives a reference signal associated with the control signal and generates a pulse width modulated switching signal for the switching circuit to maintain the output voltage at a regulated value. The drive signal generator compares the measurement signal with the reference signal at a peak value of the measurement signal in a first measurement mode and compares the measurement signal with the reference signal at a valley value of the measurement signal in a second measurement mode. The offset generator generates an offset signal that is added to the control signal at a transition between the first measurement mode and the second measurement mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority of Italian Application No. 102023000017652, filed on August 28, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to a control device and method for a switching voltage regulator. Background Art

[0004] A switching voltage regulator is a device that converts an input direct current (DC) voltage to an output DC voltage. They can have different topologies, the most widespread of which is the four-switch non-inverting topology.

[0005] Switching voltage regulators can also be operated according to different modes, including a buck control mode (step-down) and a boost control mode (step-up). Regulators are also known (so-called buck-boost regulators) which use the two control modes in different operating steps of the regulator, depending on the value of the input voltage, in particular on the relation of the input voltage to the output voltage (greater or smaller).

[0006] This type of switching voltage regulator is based on regulation of the duty cycle (i.e., the time the switch is on and off) and can be used Figure 1 The block diagram is used to represent it.

[0007] Figure 1 The voltage regulator 1 is shown, which comprises a switching circuit 2 and a control device 3. The switching circuit 2 is formed here by a first half-bridge 4 and a second half-bridge 5.

[0008] The first half bridge 4 is formed by a first high side switch (first HSS11) and a first low side switch (first LSS12), which are coupled in series between an input terminal 6 and a reference potential line (ground) 7. An input voltage Vi is applied between the input terminal 6 and the reference potential line 7.

[0009] The second half bridge 5 is formed by a second high side switch (second HSS 13) and a second low side switch (second LSS 14), which are coupled in series between the output terminal 9 and the reference potential line 7. The output voltage Vo (referred to as ground) is present at the output terminal 9 and is provided to the load 18.

[0010] The switches 11 - 14 are typically formed of MOSFET devices. The low side switches (first LSS 12 and second LSS 14 ) have source terminals coupled to each other at a common node 17 .

[0011] The sense resistor 19 is arranged between the common node 17 and the reference potential line 7 .

[0012] The inductor 20 is coupled between the middle node 15 of the first half-bridge 4 and the middle node 16 of the second half-bridge 5 .

[0013] The input capacitor 21 is coupled to the input terminal 6, and the input voltage Vi is applied to the input capacitor 21. The output capacitor 22 is coupled to the output terminal 9, and the output voltage Vo is applied to the output capacitor 22.

[0014] The control device 3 is coupled to the input terminal 6 and the output terminal 9 and receives a reference voltage V ref Furthermore, the control device 3 is coupled to the control terminals of the switches 11 - 14 and to the sense resistor 19 to operate the current control of the switching circuit 2 .

[0015] A regulator operating in buck-boost control mode operates in buck control mode when the input voltage Vi is greater than the output voltage Vo, and vice versa. In some cases, a transition phase may be envisaged, referred to as a buck-boost transition phase.

[0016] In the step-down control mode, the control device 3 controls the opening and closing of the first HSS 11 and the first LSS 12 in an alternating manner; in addition, it keeps the second HSS 13 always on and keeps the second LSS 14 always off, such as Figure 2A as shown in .

[0017] Specifically, the control device 3 generates a first switching signal TON1 and a second switching signal TOFF1, which are digital and opposite to each other. The signals TON1 and TOFF1 are provided to the first HSS 11 and the first LSS 12, respectively, which switch in opposite ways. As indicated, the second HSS 13 is always on (at Figure 2A It receives a high logic signal "1"), while the second LSS14 is always off (in Figure 2A In the case of a PWM, it receives a low logic signal “0”).

[0018] Therefore, in the switch circuit 2, when the first switch signal TON1 is high (logic signal "1") and the second switch signal TOFF1 is low (logic signal "0"), the first HSS 11 is turned on, the first LSS 12 is turned off, and the current (inductor current I L ) flows into the first HSS 11, the inductor 20 and the second HSS 13, as shown by the dotted line. Since the voltage on the inductor 20 is positive and equal to (Vi-Vo), the inductor current I L It increases linearly with a slope of (Vi-Vo) / L (L is the inductance of the inductor 20).

[0019] When the first switch signal TON1 and the second switch signal TOFF1 are switched, the first HSS 11 is turned off, and the first LSS 12 is turned on, and the inductor current I L Flows into the first LSS 12, the inductor 20 and the second HSS 13, as shown by the dashed line. During this time interval, since the voltage across the inductor 20 is negative (Vi>Vo) and equal to (as a first approximation, ignoring the voltage drop across the sense resistor 19) -Vo, the inductor current I L It decreases linearly with a slope of -Vo / L.

[0020] During this phase, the sensing resistor 19 senses the inductor current I L , which is provided to the control device 3.

[0021] In the boost mode, the control device 3 controls the second HSS 13 and the second LSS 14 to be turned on and off in an alternating manner; in addition, it keeps the first HSS 11 always turned on and keeps the first LSS 12 always turned off, such as Figure 2B as shown in .

[0022] Specifically, the control device 3 generates a third switching signal TOFF2 and a fourth switching signal TON2, which are digital and opposite to each other. The signals TOFF2 and TON2 are provided to the second HSS 13 and the second LSS 14, respectively, so that they switch in opposite ways. As indicated, the first HSS 11 is always on (at Figure 2B , it receives a high logic signal “1”), while the first LSS12 is always turned off (it receives a low logic signal “0”).

[0023] Therefore, in the switch circuit 2, when the fourth switch signal TON2 is high (logic signal "1") and the third switch signal TOFF2 is low (logic signal "0"), the second HSS 13 is turned off, the second LSS 14 is turned on, and the inductor current I L Flows into the first HSS 11, the inductor 20 and the second LSS 14, as shown by the dashed line. Therefore, the voltage across the inductor 20 is positive (equal to Vi in an approximation, ignoring the voltage drop across the sense resistor 19), and the inductor current I L Increases linearly with a slope of Vi / L.

[0024] During this phase, the sensing resistor 19 senses the inductor current I L and provide it to the control device 3.

[0025] When the third switch signal TON2 and the fourth switch signal TOFF2 are switched, the second LSS 14 is turned off, and the second HSS 13 is turned on, and the inductor current I LFlows into the first HSS 11, inductor 20, and second HSS 13, as shown by the dashed lines. During this time interval, since the voltage across the inductor 20 is negative (Vi < Vo) and equal to Vi - Vo, the inductor current I L Decreases linearly with a slope of (Vi - Vo) / L.

[0026] In addition, in a manner known per se and not described in detail, during the transition phase between the buck control mode and the boost control mode, a hybrid control mode, commonly referred to as the "buck-boost" control mode, is typically used, in which the buck mode control cycle and the boost mode control cycle alternate, controlling the selective turning on and off of all switches 11 - 14 of the half-bridge 4, 5.

[0027] As indicated, in both control modes, the control device 3 uses the inductor current I L (the valley value in the buck control mode and the peak value in the boost control mode) sensed by the sense resistor 19 to control the output voltage Vo and keep it close to the reference value V ref .

[0028] For this purpose, the control device 3 typically performs current loop control on the switch circuit 2. An example of the control device 3 operating in this manner is shown in the simplified block diagram of Figure 3 .

[0029] Specifically, in Figure 3 , the control device 3 includes: a control loop circuit 31 that measures the error between the output voltage Vo and the reference voltage V ref and generates a control signal I C (current control signal); a ramp generator 32 that generates a current ramp I s ; an adder node 33 that generates a reference current I R , the reference current I R being the sum of the control signal I C and the current ramp I s (I R = I C + I s ); a PWM modulator 34 that compares the inductor current I L with the reference current I R and generates a modulation signal PWM; and a drive logic 36 that generates switch control signals TON1, TOFF1, TON2, TOFF2 based on the modulation signal PWM.

[0030] In the control device 3, the modulation signal PWM has a fixed period, and the PWM modulator 34, in use, responds to the reference current I C + I s and the inductor current IL The comparison between them is used to modify the duty cycle of each cycle of the modulation signal PWM.

[0031] For this type of regulation, there is a problem that during the transition between the buck control mode and the boost control mode, the control signal I C Due to the slow adaptation of the control node (due to the presence of the capacitor network and the compensation network on the control node), the output voltage Vo may experience undesirable transients.

[0032] In this regard, reference Figure 4 , in the transition step from buck control mode to boost control mode, the inductor current I L And the corresponding output voltage Vo over time.

[0033] Specifically, Figure 4 The inductor current I is shown by a circle when the voltage regulator 1 is operated in the buck mode. L The acquisition point of the value at the valley and the inductor current I when the voltage regulator 1 is operated in the boost mode L The values ​​at the peak are obtained as indicated above.

[0034] Figure 4 Also shown is the expected average output current Io and Figure 3 A graph of a control signal Ic (indicating a transition threshold) for obtaining a desired average output current Io.

[0035] It is worth noting that initially, in buck control mode and regulation, the inductor current I L The valley value is approximately equal to the value of the control signal Ic (using I c(buck) instruct).

[0036] When the voltage regulator 1 enters the boost control mode, the inductor current I L The comparison with the control current Ic occurs when the inductor current I L at the peak of (as indicated in the circle).

[0037] In this phase, in the regulation state, the control current Ic has a higher value (in Figure 4 I c(boost) Indicator), which is related to the inductor current I L therefore, the average output current is equal to the expected value Io.

[0038] However, in the transient between buck control mode and boost control mode, due to Figure 3 There are resistance elements and capacitance elements in the control loop circuit 31, so the value of the control current Ic changes up to the new adjustment value I c(boost)does not occur instantaneously, and the value of the control current Ic increases gradually (as shown in the transient part of the control current Ic, with I c(trans) and dotted line), to achieve the stable value I c(boost) .

[0039] Figure 4 The corresponding graph of the output voltage Vo is also shown; it is noteworthy that in the transition from buck control mode to boost control mode, the output voltage Vo undergoes a significant shift (reduction) ΔVo. However, such a reduction (whose value also depends on the control loop bandwidth) is undesirable in a voltage regulator. Summary of the invention

[0040] The object of the present invention is to provide a solution to overcome the disadvantages of the prior art.

[0041] A first aspect relates to a control device for a switching voltage regulator, the switching voltage regulator comprising a switching circuit. The control device comprises: a control loop circuit, the control loop circuit being configured to generate a control signal, the control signal indicating the difference between the output voltage of the switching circuit and the nominal voltage; a drive signal generator circuit, the drive signal generator circuit being coupled to the control loop circuit and being configured to receive a measurement signal and a reference signal, the reference signal being related to the control signal, the measurement signal indicating the current flowing into the switching circuit, comparing the measurement signal with the reference signal at a peak value of the measurement signal in a first measurement mode, comparing the measurement signal with the reference signal at a valley value of the measurement signal in a second measurement mode, and generating a pulse width modulated switching signal, the pulse width modulated switching signal being used to cause the switching circuit to maintain the output voltage at a regulated value; an offset generator circuit, the offset generator circuit being configured to generate an offset signal at a transition between the first measurement mode and the second measurement mode; and an adder, the adder being arranged between the control loop circuit and the drive signal generator circuit, the adder being configured to add the offset signal to the control signal to generate the reference signal.

[0042] The second aspect relates to a switching voltage regulator. The switching voltage regulator includes a switching circuit, the switching circuit includes a high-side switch and a low-side switch, the high-side switch and the low-side switch are coupled in series to the low-side switch arranged between an input node and a reference potential line; a control device, the control device is configured to control the operation of the high-side switch and the operation of the low-side switch, the control device includes: a control loop circuit, the control loop circuit is configured to generate a control signal, the control signal indicates the difference between the output voltage of the switching circuit and the nominal voltage; a drive signal generator circuit, the drive signal generator circuit is coupled to the control loop circuit and is configured to receive a measurement signal and a reference signal, the reference signal is related to the control signal, and the measurement signal indicates a current flowing into the switching circuit, comparing the measurement signal with a reference signal at a peak value of the measurement signal in a first measurement mode, comparing the measurement signal with a reference signal at a valley value of the measurement signal in a second measurement mode, and generating a pulse width modulated switching signal, the pulse width modulated switching signal being used to cause the switching circuit to maintain the output voltage at a regulated value; an offset generator circuit, the offset generator circuit being configured to generate an offset signal at a transition between the first measurement mode and the second measurement mode; and an adder, the adder being arranged between the control loop circuit and the drive signal generator circuit, the adder being configured to add the offset signal to the control signal to generate a reference signal.

[0043] A third aspect relates to a method for operating a switching voltage regulator, the method comprising: receiving an input voltage of a switching circuit of the switching voltage regulator; receiving an output voltage of the switching circuit; receiving a measurement signal, the measurement signal indicating a current flowing into the switching circuit; generating a control signal, the control signal being related to a difference between the output voltage and a nominal voltage; generating a pulse width modulated switching signal based on a comparison between the measurement signal and a reference signal, the reference signal being related to the control signal, the pulse width modulated switching signal being generated to maintain the output voltage at a regulated value, wherein the comparison between the measurement signal and the reference signal occurs at a peak value of the measurement signal in a first measurement mode and at a valley value of the measurement signal in a second measurement mode; and adding an offset signal to the control signal in a transition between the first measurement mode and the second measurement mode.

[0044] According to the present invention, there is provided a control device and method of a switching voltage regulator as defined in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] For a better understanding of the invention, some embodiments of the invention will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0046] Figure 1 A simplified circuit diagram of a known voltage regulator including a switching circuit and a control device is shown;

[0047] Figure 2A shows the case of buck mode operation Figure 1 The current flows in the switching circuit;

[0048] Figure 2B shows the case of boost mode operation Figure 1 The current flows in the switching circuit;

[0049] Figure 3 A block diagram of a known control device is shown;

[0050] Figure 4 Shows Figure 1 The voltage regulator and Figure 3 Curve diagrams of some electrical quantities in the control device;

[0051] Figure 5 Shows Figure 3 A graph of a control signal in a control device;

[0052] Figure 6 A block diagram showing an embodiment of the control device is shown;

[0053] Figure 7 Another block diagram showing an embodiment of the control device;

[0054] Figure 8 Shows Figure 7 Some electrical quantities in the control device are related to Figure 3 Simulation for comparison of similar electrical quantities in the control device;

[0055] Fig. 9 Shows Figure 7 The output voltage behavior of the control device is Figure 3 The output voltage of the control device is compared with the analog;

[0056] Fig.10 yes Figure 6 or Figure 7 An exemplary circuit diagram of a block of a control device;

[0057] Fig.11 block diagrams showing various embodiments of the present voltage regulator; and

[0058] Fig.12 A block diagram of another embodiment of the voltage regulator is shown. DETAILED DESCRIPTION

[0059] Figure 5 The behavior of the control current Ic during the transient from buck control mode (with valley current measurement) to boost control mode (with peak current measurement) is roughly shown, and the Figure 1 The switch circuit 2 regulates the average current Io and the inductor current I during the transition period (desired) L The output current difference ΔIo between the average value Im (shown by the horizontal dotted line) of .

[0060] It is noteworthy that, immediately after switching to the peak measurement mode, the output current difference ΔIo is very high and gradually decreases to reach the (desired) regulated average current Io in the boost control mode.

[0061] For the sake of completeness, it should be noted that the buck-boost control mode is used during transients between the buck control mode and the boost control mode (and vice versa).

[0062] Applicants have appreciated that this output current difference ΔIo corresponds to the current required to maintain the output voltage Vo at a regulated value, and that by compensating for this output current difference ΔIo, both the offset ΔVo of the voltage output and the duration of the transient when switching between valley and peak measurement modes can be significantly reduced.

[0063] Figure 6 A control device 50 is shown which is able to compensate for the output current difference ΔIo discussed above.

[0064] The control device 50 may be coupled to a switching circuit similar to Figure 1 Therefore, the switch circuit is not in Figure 5 is shown in and can be Figure 1 The switching circuit 2 is formed as shown in FIG.

[0065] The control device 50 has Figure 3 The overall structure of the control device 3 is similar to that of the control device 50. Figure 3 Elements common to the control device 3 have been provided with the same reference numerals and will only be described briefly.

[0066] In an embodiment, the control device 50 comprises: a control loop circuit 31, which generates a control signal I C , control signal I C is related to the output voltage Vo and the reference voltage V ref A current signal related to the difference between the two; a ramp generator 32, which generates a current ramp I s ; Adder node 33, which receives the current ramp I s and control signal I C And generate reference current I R PWM modulator 34, which converts the inductor current I L With reference current I RCompare and generate a pulse width modulation signal PWM; and drive logic 36, which generates switch control signals TON1, TOFF1, TON2, TOFF2 according to the modulation signal PWM, similar to Figure 3 The control device 3.

[0067] The control device 50 further includes an offset generator 51, which generates an offset current I OFFSET , the offset current I OFFSET At the transient between the buck control mode and the boost control mode, in particular at the transient from the buck control mode to the boost control mode, the control signal I is added to the adder node 33. C and the current ramp I s Therefore, in the control device 50, during the transient period, the reference current I R Equal to three currents (i.e., current ramp I s , control signal I C and offset current I OFFSET ), I R =I C +I s +I OFFSET .

[0068] Offset current I OFFSET It may be maintained only during the transient phase or during the entire peak control phase. To this end, the offset generator 51 receives an activation signal M, such as a digital signal, the logic level of which determines the activation or inactivation state of the offset generator 51. Here, the activation signal M also indicates the measurement mode of the current, valley current or peak current, and therefore has a first logic state (e.g., a high logic state) during the valley measurement operation and a second logic level, in this example, a low logic state, in the valley measurement mode. Alternatively, it may indicate a transition of the control mode.

[0069] The activation signal M can be generated in different ways: for example, Figure 7 As shown in , the activation signal M is generated by the mode sensing block 52, which receives the output voltage Vo and the input voltage Vi at its input terminals.

[0070] In this case, the mode sensing block 52 can be a simple comparator that compares the input voltage Vi and the output voltage Vo with each other and generates an activation signal M as a digital signal, which has a first logic value (e.g., a high value) when Vi>Vo, otherwise, the digital signal has a second logic value (a low value in this example).

[0071] Alternatively, hysteresis can be used in the comparison between Vi and Vo (e.g., using a hysteresis threshold comparator) to prevent the voltage regulator from oscillating between high and low values when Vi is exactly equal to Vo.

[0072] The activation signal M can also be sent to the PWM modulator to determine at which valley (buck control mode) or peak (boost control mode) the inductor current I is sampled, or sent to the drive logic 36 to determine the drive sequence of switches 11 - 14. L for sampling the inductor current I, or sent to the drive logic 36 to determine the drive sequence of switches 11 - 14.

[0073] It should be noted that if provided, the activation signal M is also used in the buck - boost control phase, where the valley current for Vi > Vo and the peak current for Vi < Vo are sensed.

[0074] In this way, once the mode sensing block 52 senses a predetermined ratio between the input voltage Vi and the output voltage Vo, it switches the activation signal M, the offset generator 51 is activated and provides an offset current I to the adder node 33. OFFSET which is added to the control signal I OFFSET and the current ramp I C . s

[0075] The value of the offset current I OFFSET can be a fixed value, set at the factory or during the setup phase of the control device 50; or it can be a configurable or variable value.

[0076] For example, the value of the offset current I OFFSET can be calculated by analog or digital circuitry inside or outside the offset generator 51 based on electrical quantities (Vi, Vo, I L ,...) of the voltage regulator.

[0077] Specifically, when the input voltage Vi becomes lower or higher than the output voltage Vo, the value of the offset current I OFFSET can be selected to be equal to the ripple of the inductor current I L , equal to:

[0078]

[0079] where Tr is the time interval between the peak and the consecutive valley of the inductor current I L ( Figure 5 ), L is the inductance of the inductor ( Figure 1 20 in

[0080] ), and Vo is the output voltage of the voltage regulator.

[0081] exist Figure 8 The use of Figure 7 The control device 50 and the control current I obtained according to the current offset calculated by (1) C and the inductor current I L The curve diagram (curve I CA and I LA ) is a graph of the same quantity as that of the control device 3 of FIG. 2 (curve I CB and I LB ) and a graph of the activation signal M when transitioning from buck mode operation to boost mode operation.

[0082] As noted, at time t1 , the input voltage Vi becomes lower than the output voltage Vo, and the activation signal M switches from high to low.

[0083] Figure 8 It shows that although the reference current I can be obtained by using the control device 3 of FIG. 2 RB The curve has a significant decrease (as shown in the above reference Figure 4 discussed), but using Figure 7 The control device 50 can obtain the reference current I RA The curve due to the offset current I OFFSET In addition, although the inductor current I can be obtained by using the control device 3 of FIG2 LB The reduction is significant and can be detected within several operating cycles, but using Figure 7 The control device 50 can obtain the inductor current I LA There is minimal reduction in maximum and minimum values.

[0084] As a result, when the offset current I OFFSET is injected, the output voltage Vo shows a lower reduction relative to the boost regulation value, as Fig. 9 , where the output voltage Vo is indicated by VoA, and the output voltage Vo obtainable by the control device 3 of FIG. 2 is indicated by VoB. As indicated, Fig. 9 In the simulation shown in Figure 7 The control device 50 can obtain an output voltage VoA which has a reduction (relative to the regulated boost value) of approximately 50% below the offset exhibited by the voltage output VoB.

[0085] Fig.10A possible implementation of the control loop circuit 31 and the PWM modulator 34 is shown. For the sake of completeness, these circuits, which are described in detail in the Italian patent application 102022000013240 filed on June 22, 2022 corresponding to the European patent application 23178174.1 filed on June 8, 2023, the US patent application 18330754 filed on June 7, 2023, and the Chinese patent application 202310742484.6 filed on June 23, 2023, are briefly described below.

[0086] refer to Fig.10 The control loop circuit 31 includes: a compensation module 110, which receives the output voltage Vo and the reference voltage V ref And provide control voltage V c and a voltage-current conversion module 111, which provides a control voltage V c Based on the control signal I C .

[0087] The compensation module 110 includes an error amplifier, here an operational transconductance amplifier (OTA) 114, OTA 114 having an output 116, output 116 provides an error signal V E , error signal V E Indicates the output voltage Vo and the reference voltage V ref and a compensation network 118, which is coupled to the output 116 and generates a control voltage V c .

[0088] exist Fig.10 In the embodiment, the compensation module 110 further comprises a voltage divider 120 , which is coupled between the output terminal 9 and the reference potential line 7 and has an intermediate node 121 .

[0089] OTA 114 has a first input coupled to reference node 8 and a second input coupled to intermediate node 121 of voltage divider 120. In practice, OTA 114 converts reference voltage V ref Compare with a small fraction of the output voltage Vo.

[0090] The compensation network 118 is a parallel circuit coupled between the output terminal 6 and the reference potential line 7 , and includes a compensation resistor 124 and compensation capacitors 125 , 126 .

[0091] The voltage-current conversion module 111 is formed by a first mirror branch 130 and a second mirror branch.

[0092] The second mirror branch comprises an output transistor 131 of the PMOS type.

[0093] The first mirror branch 130 is coupled to the reference potential line 7 and is connected to the reference potential line 7 at a power supply voltage V CC The series circuit between the power supply line 133 under the power supply line 133 includes a first transistor 135 (here, an NMOS type), a second transistor 136 (here, a PMOS type) and a resistor R C The control resistor 137.

[0094] The first transistor 135 has a gate terminal coupled to the output 116 of the OTA 114 and thus receives the control voltage V C .

[0095] The second transistor 136 has a source terminal connected to the power supply node 133 and a gate terminal connected to the drain terminal. In addition, the gate terminal of the second transistor 136 is connected to the gate terminal of the output transistor 131.

[0096] The first mirror branch 130 generates an intermediate control current I′ C , intermediate control current I' C The control voltage V C Based on.

[0097] The first mirror branch 130 and the second mirror branch 131 have a current mirror ratio of 1:N, so that the control loop circuit 31 provides a current equal to N·I′ at the output. C The control signal I C .

[0098] The PWM modulator 34 includes a current comparator 140 and a PWM generator 144 . The current comparator 140 provides a comparison signal COMP. The PWM generator 144 generates a modulation signal PWM according to a clock signal CLK and the comparison signal COMP.

[0099] The current comparator 140 comprises a comparator element 143 having a positive input 141 and a negative input 142 , the comparator element 143 providing a comparison signal COMP at an output.

[0100] The current comparator 140 further includes a resistor R A The first resistor 146 is coupled between the positive input 141 of the comparator element 143 and the first terminal of the sensing resistor 19 (connected to Figure 1 The common node 17 of the switch circuit 2; and a resistor R B A second resistor 147 is coupled between the negative input 142 of the comparator element 143 and a second terminal of the sensing resistor 19 (connected to the reference potential line 7).

[0101] The positive input 141 of the comparator element 143 is coupled to the output of the adder node 33, and the negative input 142 of the comparator element 143 is coupled to provide a bias current I b Bias node 149.

[0102] It should be noted that the illustrated configuration of the current comparator 140 refers to a valley control mode. In practice, a pair of switches (not shown) connects the output of the adder node 33 to the two inputs 141 and 142 of the comparator element 143, while another pair of switches (not shown) connects the bias node 149 to the two inputs 141 and 142. These switches (not shown) are controlled so that in the peak control mode, the output of the adder node 33 is coupled to the negative input 142 of the comparator element 143, and the bias node 149 is coupled to the positive input 141 of the comparator element 143.

[0103] The PWM generator 144 provides a modulation signal PWM which is digital, whose period is based on the period T of the clock signal CLK and whose duty cycle is variable in a manner known per se in each cycle (or period) of the modulation signal PWM.

[0104] It should be noted that the mirror circuits 131, 136 may be absent; in this case, the drain terminal of the first transistor 135 may be directly connected to the adder node 33; with this solution, the current flowing into the first transistor 135 already represents the control signal I supplied to the adder node 33. C (Although the sign is different).

[0105] In the above Figure 1 The voltage regulator described in 1 injects an offset current I during the transient between control based on valley current measurement and control based on peak current measurement. OFFSET Also applicable to other types of voltage regulation circuits.

[0106] For example, it is suitable for converters that operate only in buck mode. In these circuits, switching between valley current measurement mode and peak current measurement mode is usually not required. Valley current measurement mode or peak current measurement mode is selected in the design step based on the ratio between input voltage Vi and output voltage Vo and other functions (e.g. current limiting).

[0107] In some cases, especially when the ratio between the input voltage and the output voltage is high and the duty cycle is therefore small, the duration of the on-time of the high-side transistor may be too short to enable the current comparator ( Fig.10In this condition, it may be useful to use a measurement mode based on the valley value of the inductor current, because in this way the current comparator has more time to sense the inductor current during the off phase of the high-side transistor.

[0108] However, if the input voltage drops to become close to the output voltage, the duty cycle increases and the off time becomes very small. In this case, it is more convenient to operate in peak current measurement mode because the on time is long.

[0109] Therefore, in this case, switching between valley current sensing control mode and peak current sensing control mode may be useful.

[0110] Therefore, in this case it is also advantageous to be able to inject an offset current during the transient between these two measurement modes.

[0111] Furthermore, in high frequency converters operating with a high ratio between input voltage and output voltage or with large input voltage or output voltage variations, it may be convenient to operate in valley or peak current measurement mode depending on the voltage difference between the input voltage and the output voltage (e.g., valley measurement mode for duty cycle <50% and peak current measurement mode for duty cycle >50%).

[0112] Switching from peak current sensing mode to valley current sensing mode also introduces an error in the current limit value. This error can also be accounted for by injecting an offset current.

[0113] Fig.11 An embodiment of a voltage converter operating only in buck mode is shown, in which the switch is arranged outside the switching circuit, and the inductor current is measured both at peak and valley values ​​alternately with each other depending on the operating conditions.

[0114] In detail, Fig.11 A voltage converter 70 is shown, which comprises a switching circuit 71 and a control device 72 .

[0115] The switch circuit 71 is formed by a half-bridge circuit 74, which includes a high-side switch (HSS 75) and a low-side switch (LSS 76), which receives corresponding control signals T_HS and T_LS (e.g., similar to Figure 1 , Figure 6 and Figure 7 The first switching signal TON1 and the second switching signal TOFF1 of the input terminal 77 are connected in series between the input terminal 77 and the reference potential line (ground) 78. The input voltage Vi is applied between the input terminal 77 and the reference potential line 78, and the input capacitor 79 is coupled to the input terminal 77, and the input voltage Vi is applied to the input capacitor 79.

[0116] Inductor 80 has a first terminal coupled to an intermediate node 81 of half bridge 74. A sense resistor 82 is coupled between a second terminal of inductor 80 and output terminal 83.

[0117] An output capacitor 84 that receives the output voltage Vo is coupled to the output terminal 83 .

[0118] The control device 72 has Figure 7 The control device 72 has a similar structure to the control device 50; the elements common to the control device 50 therefore have the same reference numerals and will not be described again. In the control device 72, the mode sensing block 52 is replaced by an activation block 87 based on sensing the ratio between the output voltage Vo and the input voltage Vi.

[0119] For example, the activation block 87 verifies whether the ratio between the output voltage Vo and the input voltage Vi is greater than a threshold value D TH , for example a fixed value such as 0.5.

[0120] In particular, when the ratio Vo / Vi exceeds the threshold D TH (plus possible hysteresis), the activation signal M switches and activates the offset generator 51.

[0121] In addition, the voltage converter 70 is Figure 6 and Figure 7 The operation is performed in a similar manner as described.

[0122] Fig.12 An embodiment of a voltage converter operating only in buck mode is shown, wherein switches are arranged inside a switching voltage regulator, and the inductor current is measured both at peak and valley values ​​alternately with each other depending on the operating conditions.

[0123] In detail, Fig.12 A converter 90 is shown, which comprises a switching circuit 91 and a control device 92 .

[0124] The switch circuit 91 has Fig.11 The switch circuit 71 has the same structure as that of the switch circuit 71. Therefore, its components have the same reference numerals.

[0125] Here, no sense resistor is arranged between the second terminal of the inductor 80 and the output terminal 83 .

[0126] The control device 92 has Fig.10 The control device 72 is of a similar structure. Therefore, it is only partially represented as a PWM modulator, indicated here by 134, and common elements have been provided with the same reference numerals.

[0127] The PWM modulator 134 includes two current comparators: a peak current comparator 140-P and a valley current comparator 140-V, both of which are similar to those for Fig.10 The current comparator 140 is formed as shown and described.

[0128] The peak current comparator 140-P is coupled to the HSS 75 and senses the voltage drop between its drain and source terminals. In effect, the resistance RDSon of the HHS 75 replaces Fig.10 The sensing resistor 19 in.

[0129] Valley current comparator 140-V is coupled to LSS 76 and senses the voltage drop between its drain and source terminals. In effect, the resistance RDSon of LHS 76 replaces Fig.10 The sensing resistor 19 in.

[0130] The peak current comparator 140-P and the valley current comparator 140-V also receive a reference current I R and bias current I b , and generate corresponding comparison signals COMP-P, COMP-V, similar to those already referenced Fig.10 Discussion of comparative signals.

[0131] with Fig.11 As in the voltage regulator 70, and in a manner not shown, the reference current I R A single adder node (similar to Fig.11 The adder node 33) generates the control current I C (generated by the control loop circuit 31, not shown here), the offset current I OFFSET (generated by the offset generator 51, not shown here) and the current ramp I s Add.

[0132] It should be noted that due to the offset current I OFFSET Only when the inductor current I L The reference current I is added in one of the measurement cycles (eg, in the peak current measurement phase) and is therefore supplied only to one of the peak current comparator 140-P and the valley current comparator 140-V. R Including offset current I OFFSET .

[0133] Furthermore, since they operate alternately, they can be controlled by specific signals (e.g. Fig.11 The activation signal M) is activated and deactivated.

[0134] The comparison signals COMP-P, COMP-V are provided to the PWM generator 144 which may thus generate control signals T_HS and T_LS similar to the control signals already described previously.

[0135] although Fig.12 The outputs of the peak current comparator 140-P and the valley current comparator 140-V are shown coupled to different inputs of the PWM generator 144, but the comparison signals COMP-P, COMP-V can be provided to the same input of the PWM generator 144 because the corresponding peak current comparator 140-P and valley current comparator 140-V operate alternately, as explained above.

[0136] Therefore, the control device and method described herein allow to reduce any voltage transients in the DC-DC converter during switching between peak current measurement operation and valley current measurement operation by means of injecting an offset current in the transient phase.

[0137] This injection also reduces current limit errors.

[0138] Finally, modifications and variations may be made to the apparatus and methods described and illustrated herein without departing from the scope of the present invention, as defined in the appended claims.

Claims

1. A control device for a switching voltage regulator, the switching voltage regulator comprising a switching circuit, the control device comprising: a control loop circuit configured to generate a control signal indicative of a difference between an output voltage of the switching circuit and a nominal voltage; a drive signal generator circuit coupled to the control loop circuit and configured to: receiving a measurement signal and a reference signal, the reference signal being related to the control signal, the measurement signal being indicative of a current flowing into the switching circuit, In a first measurement mode, the measurement signal is compared with the reference signal at a peak value of the measurement signal, In a second measurement mode, the measurement signal is compared with the reference signal at a valley value of the measurement signal, and generating a pulse width modulated switching signal, the pulse width modulated switching signal being used by the switching circuit to maintain the output voltage at a regulated value; an offset generator circuit configured to generate an offset signal at a transition between the first measurement mode and the second measurement mode; as well as An adder is arranged between the control loop circuit and the drive signal generator circuit, and is configured to add the offset signal and the control signal to generate the reference signal.

2. The control device according to claim 1, further comprising an operating mode detector circuit, wherein the operating mode detector circuit is configured to: receiving an electrical signal corresponding to a current operating condition of the switching circuit; and In response to sensing the predetermined relationship between the electrical signals, an activation signal is generated, the activation signal being used for the offset generator circuit. 3 . The control device of claim 2 , wherein the operating mode detector circuit is configured to interrupt the activation signal in response to sensing that the predetermined relationship is no longer satisfied.

4. The control device according to claim 2, wherein the electrical signal includes an input voltage of the switching circuit and the output voltage of the switching circuit, and the operating mode detector circuit is configured to generate the activation signal in response to sensing a predetermined relationship between the input voltage and the output voltage.

5. The control device according to claim 4, wherein the operating mode detector circuit is configured to: In response to sensing that the output voltage is greater than the input voltage plus hysteresis, generating the activation signal, or The activation signal is generated in response to sensing that the input voltage is greater than the output voltage plus hysteresis.

6. The control device according to claim 4, wherein the operating mode detector circuit is configured to: generating the activation signal in response to sensing that the ratio between the output voltage and the input voltage is greater than a threshold value plus hysteresis, or The activation signal is generated in response to sensing that a ratio between the input voltage and the output voltage is less than a threshold plus hysteresis.

7. The control device according to claim 1, wherein the offset generator circuit is a DC generator circuit.

8. A switching voltage regulator comprising: a switching circuit including a high-side switch and a low-side switch, the high-side switch and the low-side switch being coupled in series to the low-side switch arranged between an input node and a reference potential line; A control device, the control device being configured to control the operation of the high-side switch and the operation of the low-side switch, the control device comprising: a control loop circuit configured to generate a control signal indicative of a difference between an output voltage of the switching circuit and a nominal voltage; a drive signal generator circuit coupled to the control loop circuit and configured to: receiving a measurement signal and a reference signal, the reference signal being related to the control signal, the measurement signal being indicative of a current flowing into the switching circuit, In a first measurement mode, the measurement signal is compared with the reference signal at a peak value of the measurement signal, In a second measurement mode, the measurement signal is compared with the reference signal at a valley value of the measurement signal, and generating a pulse width modulated switching signal, the pulse width modulated switching signal being used by the switching circuit to maintain the output voltage at a regulated value; an offset generator circuit configured to generate an offset signal at a transition between the first measurement mode and the second measurement mode; and An adder is arranged between the control loop circuit and the drive signal generator circuit, and is configured to add the offset signal and the control signal to generate the reference signal.

9. The switching voltage regulator of claim 8, wherein the drive signal generator circuit comprises: a first measurement comparator circuit coupled to the high-side switch, the first measurement comparator circuit configured to compare the measurement signal with the reference signal at a peak value of the measurement signal in the first measurement mode; as well as A second measurement comparator circuit is coupled to the low-side switch, the second measurement comparator circuit being configured to compare the measurement signal with the reference signal at a valley value of the measurement signal in the second measurement mode. 10 . The switching voltage regulator of claim 8 , further comprising a half-bridge circuit including the high-side switch and the low-side switch, the half-bridge circuit being configured to receive the pulse width modulated switching signal.

11. The switching voltage regulator according to claim 8, wherein the control device further comprises an operation mode detector circuit, wherein the operation mode detector circuit is configured to: receiving an electrical signal corresponding to a current operating condition of the switching circuit; and In response to sensing the predetermined relationship between the electrical signals, an activation signal is generated, the activation signal being used for the offset generator circuit. 12 . The switching voltage regulator of claim 11 , wherein the operating mode detector circuit is configured to interrupt the activation signal in response to sensing that the predetermined relationship is no longer satisfied.

13. The switching voltage regulator of claim 11, wherein the electrical signal comprises an input voltage of the switching circuit and the output voltage of the switching circuit, and the operating mode detector circuit is configured to generate the activation signal in response to sensing a predetermined relationship between the input voltage and the output voltage.

14. The switching voltage regulator of claim 13, wherein the operating mode detector circuit is configured to: In response to sensing that the output voltage is greater than the input voltage plus hysteresis, generating the activation signal, or The activation signal is generated in response to sensing that the input voltage is greater than the output voltage plus hysteresis.

15. A method of operating a switching voltage regulator, the method comprising: receiving an input voltage of a switching circuit of the switching voltage regulator; receiving an output voltage of the switch circuit; receiving a measurement signal, the measurement signal indicating a current flowing into the switching circuit; generating a control signal, the control signal being related to a difference between the output voltage and a nominal voltage; generating a pulse width modulated switching signal based on a comparison between the measurement signal and a reference signal, the reference signal being related to the control signal, the pulse width modulated switching signal being generated to maintain the output voltage at a regulated value, wherein the comparison between the measurement signal and the reference signal occurs at a peak value of the measurement signal in a first measurement mode and at a valley value of the measurement signal in a second measurement mode; as well as An offset signal is added to the control signal in a transition between the first measurement mode and the second measurement mode.

16. The method according to claim 15, further comprising: receiving an electrical signal, the electrical signal being related to a current operating condition of the switching voltage regulator; generating an activation signal in response to sensing a predetermined relationship between the electrical signals; as well as In response to the generation of the activation signal, the offset signal is generated. 17 . The method of claim 16 , wherein the activation signal is generated in response to sensing a predetermined relationship between the input voltage and the output voltage.

18. The method of claim 17, wherein sensing a predetermined relationship between the input voltage and the output voltage comprises: sensing that the output voltage is greater than the input voltage plus hysteresis; or sensing that the input voltage is greater than the output voltage plus hysteresis; or A ratio between the output voltage and the input voltage is sensed to be greater than a threshold plus hysteresis.

19. The method of claim 15, wherein the transition is a transition from the second measurement mode to the first measurement mode, and the offset signal is interrupted in response to sensing a transition from the first measurement mode to the second measurement mode after the transition from the second measurement mode to the first measurement mode.

20. The method of claim 15, wherein the offset signal is a DC signal.

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