Current simulation analysis method and system of circuit, electronic equipment and storage medium
By building simulation analysis circuits and establishing a current sampling analysis model, the problems of missing current sampling models and insufficient accuracy analysis in the existing technology are solved, and the current sampling accuracy is improved and the performance of the motor drive system is optimized.
Patent Information
- Application Number
- CN202311100932.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-29
- Publication Date
- 2025-02-28
AI Technical Summary
The lack of establishment of current sampling models and effective analysis of current sampling accuracy in the prior art has resulted in insufficient current control of the motor drive system.
By building a simulation analysis circuit with the same structure as the target circuit, combining theoretical parameters, error initial value and actual delay time, a current sampling analysis model is established, and the error initial value is adjusted through the error setting interface until the difference between the simulation sampling current and the actual sampling current is less than the preset threshold.
Accurate analysis and adjustment of current sampling errors is realized, and the current sampling accuracy is improved, thereby improving the overall performance of the motor drive system.
Smart Images
Figure CN119543734A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of motor control technology, and in particular to a current simulation analysis method, system, electronic device and storage medium for a circuit. Background Art
[0002] The current loop, also known as the current feedback loop, is usually used to achieve precise current control and improve the performance of the motor drive system by improving the stability of the current. Current sampling is an important part of the current loop.
[0003] In the prior art, the accuracy of current sampling is mainly improved by improving the structure of hardware circuits or sampling devices, but there is a lack of establishment of current sampling models and analysis of current sampling accuracy. Summary of the invention
[0004] In order to solve the above technical problems, the present disclosure provides a current simulation analysis method, system, electronic device and storage medium for a circuit.
[0005] The present invention solves the above technical problems through the following technical solutions:
[0006] In a first aspect, the present disclosure provides a current simulation analysis method for a circuit. The current simulation analysis method comprises:
[0007] Building a simulation analysis circuit with the same circuit structure based on the target circuit; wherein the simulation analysis circuit includes a delayed sampling circuit and at least one preset element;
[0008] Acquiring the actual sampling current of the target circuit, the actual delay time of the delayed sampling circuit, and the theoretical parameters of the preset element;
[0009] The simulation analysis circuit combines the theoretical parameters, the initial error values corresponding to the theoretical parameters and the actual delay time to establish a corresponding current sampling analysis model; wherein, for each of the preset elements, the current sampling analysis model includes an error setting interface corresponding to the theoretical parameters, which is used to set and adjust the initial error value;
[0010] The initial error value is adjusted based on the error setting interface until the difference between the simulated sampling current sampled by the simulation analysis circuit and the actual sampling current is smaller than a preset threshold value, so as to obtain an error target value.
[0011] Optionally, the current sampling analysis model sets a delay setting interface for setting the actual delay duration for the delayed sampling circuit.
[0012] Optionally, the simulation analysis circuit further includes an analog-to-digital conversion module;
[0013] The current sampling analysis model sets a jump setting interface, which is used to set a corresponding preset jump value for the analog-to-digital conversion module.
[0014] Optionally, a plurality of preset sampling points are set on the simulation analysis circuit, and the simulation sampling current is an average value of current sampling values obtained by sampling at the plurality of preset sampling points.
[0015] In a second aspect, the present disclosure provides a current simulation analysis system for a circuit. The current simulation analysis system comprises:
[0016] A circuit construction module, used to construct a simulation analysis circuit with the same circuit structure based on the target circuit; wherein the simulation analysis circuit includes a delayed sampling circuit and at least one preset element;
[0017] An acquisition module, used for acquiring the actual sampling current of the target circuit, the actual delay time of the delay sampling circuit and the theoretical parameters of the preset element;
[0018] A model building module, used for the simulation analysis circuit to establish a corresponding current sampling analysis model in combination with the theoretical parameters, the initial error values corresponding to the theoretical parameters and the actual delay time; wherein, for each of the preset elements, the current sampling analysis model includes an error setting interface corresponding to the theoretical parameters, which is used to set and adjust the initial error value;
[0019] The error analysis module is used to adjust the initial error value based on the error setting interface until the difference between the simulated sampling current sampled by the simulation analysis circuit and the actual sampling current is less than a preset threshold value, so as to obtain an error target value.
[0020] Optionally, the current sampling analysis model sets a delay setting interface for setting the actual delay duration for the delayed sampling circuit.
[0021] Optionally, the simulation analysis circuit further includes an analog-to-digital conversion module;
[0022] The current sampling analysis model sets a jump setting interface, which is used to set a corresponding preset jump value for the analog-to-digital conversion module.
[0023] Optionally, a plurality of preset sampling points are set on the simulation analysis circuit, and the simulation sampling current is an average value of current sampling values obtained by sampling at the plurality of preset sampling points.
[0024] In a third aspect, the present disclosure provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, when the processor executes the computer program, the current simulation analysis method described in the first aspect is implemented.
[0025] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the current simulation analysis method described in the first aspect is implemented.
[0026] Based on the common sense in the art, the above-mentioned implementation modes can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.
[0027] The positive and progressive effect of the present disclosure is that the present disclosure relies on the accuracy problem of current sampling to design and build a current sampling analysis model that conforms to the circuit structure and underlying control logic of the target circuit to analyze the errors existing in the actual sampling current of the target circuit. Specifically, for each of the preset elements, the current sampling analysis model sets an error setting interface corresponding to the theoretical parameters, which is used to set and adjust the initial error value. The theoretical parameters of the preset elements and the corresponding initial error values are used to simulate the errors caused by the preset elements when the target circuit is actually sampling current. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 A schematic diagram of a flow chart of a current simulation analysis method provided by the present disclosure;
[0029] Figure 2 A schematic diagram of a circuit structure of a simulation analysis circuit provided by the present disclosure;
[0030] Figure 3 A schematic diagram of a current sampling simulation analysis model provided by the present disclosure;
[0031] Figure 4 A schematic diagram of a delayed sampling strategy provided by the present disclosure;
[0032] Figure 5 A schematic diagram of a module of a current simulation analysis system provided by the present disclosure;
[0033] Figure 6 A schematic diagram of the structure of an electronic device provided by the present invention. DETAILED DESCRIPTION
[0034] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0035] It should be noted that if there are descriptions involving "first", "second", etc. in the embodiments of the present disclosure, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.
[0036] In addition, the technical solutions between the various implementation methods can be combined with each other, but they must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this disclosure.
[0037] The disclosed embodiment provides a current simulation analysis method for a circuit. Relying on the accuracy problem of current sampling, a current sampling analysis model that conforms to the circuit structure and underlying control logic of the target circuit is designed and constructed to analyze the errors existing in the actual sampling current of the target circuit.
[0038] As a feasible implementation method, the current simulation analysis method is as follows Figure 1 As shown, the following steps are included:
[0039] S101. Building a simulation analysis circuit with the same circuit structure based on the target circuit.
[0040] Among them, since the circuit structure of the target circuit includes a delayed sampling circuit and at least one preset element, correspondingly, the simulation analysis circuit also includes a delayed sampling circuit and at least one preset element.
[0041] The preset element may include at least one of a sampling resistor module, an operational amplifier module, a reference voltage source, and a preset electrical appliance.
[0042] S102, obtaining the actual sampling current of the target circuit, the actual delay time of the delay sampling circuit, and the theoretical parameters of the preset components.
[0043] Exemplarily, the theoretical parameter of the sampling resistor module is the calibrated resistance value of the sampling resistor module, the theoretical parameter of the operational amplifier module is the operational amplifier gain of the operational amplifier module, the theoretical parameter of the reference voltage source is the calibrated voltage value of the reference voltage source, and the theoretical parameter of the preset electrical appliance is the calibrated resistance value of the preset electrical appliance.
[0044] S103, the simulation analysis circuit combines the theoretical parameters, the initial error values corresponding to the theoretical parameters and the actual delay time to establish a corresponding current sampling analysis model.
[0045] Among them, for each preset component, the current sampling analysis model sets an error setting interface corresponding to the theoretical parameter, which is used to set and adjust the initial error value.
[0046] In this step, the current sampling analysis model uses the theoretical parameters of the preset components and the corresponding initial error values to simulate the error caused by the preset components when the target circuit actually performs current sampling. In addition, the current sampling analysis model also sets the same actual delay time length as the delay sampling circuit in the target circuit for the delay sampling circuit included in the simulation analysis circuit to fully simulate the current sampling process of the target circuit.
[0047] As a feasible implementation method, a plurality of preset sampling points are set on the simulation analysis circuit, and the simulation sampling current is an average value of current sampling values obtained by sampling at the plurality of preset sampling points.
[0048] Based on the above implementation, the current sampling values can be averaged to improve the accuracy of the simulated sampling current.
[0049] S104 , adjusting the initial error value based on the error setting interface until the difference between the simulated sampling current obtained by sampling the simulation analysis circuit and the actual sampling current is less than a preset threshold value, so as to obtain an error target value.
[0050] In this step, the initial error values of various theoretical parameters can be gradually adjusted through the corresponding error setting interface so that the simulated sampling current is close to the actual sampling current.
[0051] As a feasible implementation, the current sampling analysis model sets a delay setting interface for setting a delay sampling circuit according to an actual delay duration.
[0052] The delayed sampling circuits in different target circuits have different actual delay durations. Based on the above implementation, adjustments can be made according to different actual delay durations, making the current sampling analysis model in the disclosed embodiment more flexible and practical.
[0053] Furthermore, when the target circuit includes an analog-to-digital conversion module, the simulation analysis circuit needs not only to set up the corresponding analog-to-digital conversion module, but also to simulate the error of the value jump during the signal conversion process of the analog-to-digital conversion module.
[0054] As a feasible implementation, the simulation analysis circuit further includes an analog-to-digital conversion module; and a current sampling analysis model setting jump setting interface, which is used to set a corresponding preset jump value for the analog-to-digital conversion module.
[0055] For example, a series of random numbers can be sequentially input into the jump setting interface to change the preset jump value, thereby simulating the random changes in the effective bits of the value during analog-to-digital conversion.
[0056] Based on the above implementation, the change of the effective bits of the numerical value when the analog-to-digital conversion module performs analog-to-digital conversion can be effectively simulated.
[0057] Exemplarily, a simulation analysis circuit is obtained according to the target circuit. Figure 2 As shown, it includes a sampling resistor module 201, an operational amplifier module 202, a reference voltage source 203, a preset electrical appliance 204, a filter circuit 205, and an FPGA (Field Programmable Gate Array) module 206 for current sampling. Among them, the FPGA module 206 includes an ADC (Analog-to-Digital Converter) delay sampling circuit 2061 and an analog-to-digital conversion module 2062.
[0058] The above simulation analysis circuit is combined with the actual delay time of the delay sampling circuit, the theoretical parameters of each preset component in the target circuit and the corresponding initial error value to establish the following Figure 3 The current sampling simulation analysis model is shown.
[0059] In the current sampling simulation analysis model, corresponding error setting interfaces are set for the sampling resistor module 201, the operational amplifier module 202, and the reference voltage source 203, a delay setting interface is set for the ADC delay sampling circuit 2061, and a corresponding jump setting interface is set for the analog-to-digital conversion module. In addition, four preset sampling points are set on the simulation analysis circuit.
[0060] In the simulation analysis circuit, the current passes through the sampling resistor module 201, the operational amplifier module 202, the preset electrical appliance, the filter circuit 205 and the FPGA module 206 in sequence.
[0061] Among them, the current sampling strategy of FPGA module 206 is as follows: Figure 4 As shown, the output times of the current loop PWM comparator are counted. When the output times are greater than the set value, the delay counter of the ADC delay sampling circuit 2061 is triggered to perform delay timing. When the delay timing reaches the set actual delay time, the ADC delay sampling circuit 2061 is used for sampling, and the output times and the delay timing are cleared to continue sampling for the next cycle.
[0062] The analog-to-digital conversion module 2062 converts the analog signal sampled by the ADC delayed sampling circuit 2061 into a digital signal recognizable by the FPGA module 206, and displays it through the FPGA module 206, that is, displays the simulated sampling current. It should be noted that when the analog-to-digital conversion module 2062 converts the analog signal into the corresponding digital signal, since the analog signal is continuous and the FPGA module 206 can only process discrete values, it is necessary to perform rounding during the conversion.
[0063] Compare the simulated sampling current with the actual sampling current of the target circuit. If the difference between the two reaches or exceeds the preset threshold, it is necessary to adjust the initial error values of each theoretical parameter through each error setting interface until the difference is less than the preset threshold, and obtain the error target value set in each error setting interface at this time.
[0064] The current sampling analysis model in the embodiment of the present disclosure can be expressed as:
[0065]
[0066] Among them, I is the simulated sampling current, V is the simulated sampling voltage, V ref is the theoretical voltage value of the reference voltage source, V ref_0 is the voltage error value of the reference voltage source, Gain is the theoretical gain of the operational amplifier module, Gain0 is the gain error of the operational amplifier module, R is the theoretical resistance value of the sampling resistor module, and R0 is the resistance error value of the sampling resistor module.
[0067] Based on the same concept, an embodiment of the present disclosure also provides a current simulation analysis system for a circuit.
[0068] As a feasible implementation method, the current simulation analysis system is as follows: Figure 5 As shown, including:
[0069] A circuit construction module 501 is used to construct a simulation analysis circuit with the same circuit structure based on the target circuit; wherein the simulation analysis circuit includes a delay sampling circuit and at least one preset element;
[0070] An acquisition module 502 is used to acquire the actual sampling current of the target circuit, the actual delay time of the delay sampling circuit, and the theoretical parameters of the preset components;
[0071] The model building module 503 is used to simulate and analyze the circuit in combination with the theoretical parameters, the initial error values corresponding to the theoretical parameters and the actual delay time, and to establish a corresponding current sampling analysis model; wherein, for each preset element, the current sampling analysis model includes an error setting interface corresponding to the theoretical parameters, which is used to set and adjust the initial error value;
[0072] The error analysis module 504 is used to adjust the initial error value based on the error setting interface until the difference between the simulated sampling current obtained by the simulation analysis circuit sampling and the actual sampling current is less than a preset threshold value, so as to obtain the error target value.
[0073] In the circuit building module 501, since the circuit structure of the target circuit includes a delayed sampling circuit and at least one preset element, correspondingly, the simulation analysis circuit also includes a delayed sampling circuit and at least one preset element.
[0074] Among them, the preset element may include at least one of a sampling resistor module, an operational amplifier module, a reference voltage source, and a preset electrical appliance.
[0075] In the acquisition module 502, exemplarily, the theoretical parameter of the sampling resistor module is the calibrated resistance value of the sampling resistor module, the theoretical parameter of the operational amplifier module is the operational amplifier gain of the operational amplifier module, the theoretical parameter of the reference voltage source is the calibrated voltage value of the reference voltage source, and the theoretical parameter of the preset electrical appliance is the calibrated resistance value of the preset electrical appliance.
[0076] In the model building module 503, for each preset element, the current sampling analysis model sets an error setting interface corresponding to the theoretical parameter, which is used to set and adjust the initial error value.
[0077] The current sampling analysis model uses the theoretical parameters of the preset components and the corresponding initial error values to simulate the error caused by the preset components when the target circuit actually performs current sampling. In addition, the current sampling analysis model also sets the actual delay time length of the delay sampling circuit included in the simulation analysis circuit to be the same as that of the delay sampling circuit in the target circuit to fully simulate the current sampling process of the target circuit.
[0078] As a feasible implementation method, a plurality of preset sampling points are set on the simulation analysis circuit, and the simulation sampling current is an average value of current sampling values obtained by sampling at the plurality of preset sampling points.
[0079] Based on the above implementation, the current sampling values can be averaged to improve the accuracy of the simulated sampling current.
[0080] In the error analysis module 504 , the initial error values of the theoretical parameters can be gradually adjusted through the corresponding error setting interface so that the simulated sampling current is close to the actual sampling current.
[0081] As a feasible implementation method, the current sampling analysis model package is provided with a delay setting interface for setting a delay sampling circuit according to an actual delay duration.
[0082] The delayed sampling circuits in different target circuits have different actual delay durations. Based on the above implementation, adjustments can be made according to different actual delay durations, making the current sampling analysis model in the disclosed embodiment more flexible and practical.
[0083] Furthermore, when the target circuit includes an analog-to-digital conversion module, the simulation analysis circuit needs not only to set up the corresponding analog-to-digital conversion module, but also to simulate the error of the value jump during the signal conversion process of the analog-to-digital conversion module.
[0084] As a feasible implementation, the simulation analysis circuit further includes an analog-to-digital conversion module; the current sampling analysis model includes a jump setting interface for setting a corresponding preset jump value for the analog-to-digital conversion module.
[0085] For example, a series of random numbers can be sequentially input into the jump setting interface to change the preset jump value, thereby simulating the random changes in the effective bits of the value during analog-to-digital conversion.
[0086] Based on the above implementation, the change of the effective bits of the numerical value when the analog-to-digital conversion module performs analog-to-digital conversion can be effectively simulated.
[0087] Figure 6 The structure of one electronic device disclosed in the present invention is shown. The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the above current simulation analysis method is implemented. Figure 6 The electronic device 60 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.
[0088] like Figure 6 As shown, the electronic device 60 may also be in the form of a general-purpose computing device, for example, it may be a server device. The components of the electronic device 60 may include, but are not limited to: at least one processor 61, at least one memory 62, and a bus 63 connecting different system components (including the memory 62 and the processor 61).
[0089] The bus 63 includes a data bus, an address bus, and a control bus.
[0090] The memory 62 may include a volatile memory, such as a random access memory (RAM) 621 and / or a cache memory 622 , and may further include a read-only memory (ROM) 623 .
[0091] The memory 62 may also include a program / utility 625 having a set (at least one) of program modules 624, such program modules 624 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.
[0092] The processor 61 executes various functional applications and data processing by running the computer programs stored in the memory 62, such as the current simulation analysis method disclosed above.
[0093] The electronic device 60 may also communicate with one or more external devices 64 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 65. Furthermore, the model generating device 60 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 66. Figure 6 As shown, the network adapter 66 communicates with other modules of the model-generated device 60 via the bus 63. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the model-generated device 60, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.
[0094] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.
[0095] The present disclosure also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the above-mentioned current simulation analysis method is implemented.
[0096] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.
[0097] In a possible implementation manner, the present disclosure may also be implemented in the form of a program product, which includes a program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute and implement the above-mentioned current simulation analysis method.
[0098] Among them, the program code for executing the present disclosure can be written in any combination of one or more programming languages, and the program code can be executed completely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or completely on the remote device.
[0099] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. A circuit current simulation analysis method, characterized in that: The current simulation analysis method comprises: Building a simulation analysis circuit with the same circuit structure based on the target circuit; wherein the simulation analysis circuit includes a delayed sampling circuit and at least one preset element; Acquire the actual sampling current of the target circuit, the actual delay time of the delay sampling circuit, and the theoretical parameters of the preset element; The simulation analysis circuit combines the theoretical parameters, the initial error values corresponding to the theoretical parameters and the actual delay time to establish a corresponding current sampling analysis model; wherein, for each of the preset elements, the current sampling analysis model includes an error setting interface corresponding to the theoretical parameters, which is used to set and adjust the initial error value; The error initial value is adjusted based on the error setting interface until the difference between the simulated sampling current sampled by the simulation analysis circuit and the actual sampling current is smaller than a preset threshold value, so as to obtain an error target value.
2. The current simulation analysis method according to claim 1, characterized in that: The current sampling analysis model sets a delay setting interface, which is used to set the actual delay duration for the delay sampling circuit.
3. The current simulation analysis method according to claim 1, characterized in that: The simulation analysis circuit also includes an analog-to-digital conversion module; The current sampling analysis model sets a jump setting interface, which is used to set a corresponding preset jump value for the analog-to-digital conversion module.
4. The current simulation analysis method according to claim 1, characterized in that: A plurality of preset sampling points are set on the simulation analysis circuit, and the simulation sampling current is an average value of current sampling values obtained by sampling at the plurality of preset sampling points.
5. A circuit current simulation analysis system, characterized in that: The current simulation analysis system comprises: A circuit construction module, used to construct a simulation analysis circuit with the same circuit structure based on the target circuit; wherein the simulation analysis circuit includes a delayed sampling circuit and at least one preset element; An acquisition module, used to acquire the actual sampling current of the target circuit, the actual delay time of the delay sampling circuit and the theoretical parameters of the preset element; A model building module, used for the simulation analysis circuit to establish a corresponding current sampling analysis model in combination with the theoretical parameters, the initial error values corresponding to the theoretical parameters and the actual delay time; wherein, for each of the preset elements, the current sampling analysis model includes an error setting interface corresponding to the theoretical parameters, which is used to set and adjust the initial error value; The error analysis module is used to adjust the initial error value based on the error setting interface until the difference between the simulated sampling current sampled by the simulation analysis circuit and the actual sampling current is less than a preset threshold value, so as to obtain an error target value.
6. The current simulation analysis system according to claim 5, characterized in that: The current sampling analysis model sets a delay setting interface, which is used to set the actual delay duration for the delay sampling circuit.
7. The current simulation analysis system according to claim 5, characterized in that: The simulation analysis circuit also includes an analog-to-digital conversion module; The current sampling analysis model sets a jump setting interface, which is used to set a corresponding preset jump value for the analog-to-digital conversion module.
8. The current simulation analysis system according to claim 5, characterized in that: A plurality of preset sampling points are set on the simulation analysis circuit, and the simulation sampling current is an average value of current sampling values obtained by sampling at the plurality of preset sampling points.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, characterized in that: When the processor executes the computer program, it implements the current simulation analysis method as described in any one of claims 1-4.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the current simulation analysis method as described in any one of claims 1 to 4 is implemented.