Current sampling chip circuit, PCB and current sampling device

Abstract

The invention relates to the technical field of current sampling, and discloses a current sampling chip circuit, a PCB and a current sampling device, and the current sampling chip circuit comprises a sampling input module, an operational amplification module and a sampling output module. The sampling input module is used for sampling current of a main circuit; the operational amplification module is used for amplifying the sampling current; the sampling output module is used for outputting a sampling current signal; the output end of the sampling input module is connected with the input end of the operational amplification module, and the output end of the operational amplification module is connected with the input end of the sampling output module; the sampling input module is used for accurately collecting the current of the main circuit, the operational amplification module is used for amplifying the sampling current, and finally the sampling output module is used for outputting the sampling current. High-precision current sampling is achieved through cooperation of the sampling input module and the operational amplification module, and compared with traditional resistor current sampling, power consumption is lower, and therefore high-precision and low-power-consumption current sampling is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of current sampling, and in particular to a current sampling chip circuit, a PCB board, and a current sampling device. Background Art

[0002] Accurate current sampling is crucial in the electronic circuit field and is widely used in numerous scenarios, including power management, motor drives, and battery monitoring. Traditional current sampling methods, such as resistor sampling, have numerous drawbacks. Firstly, resistor sampling requires multiple resistors, which not only increases circuit complexity and cost, but also takes up significant board space. Secondly, the inherent precision limitations of resistors and the resulting power consumption when current flows through them are particularly prominent. Since achieving extremely high resistor accuracy is difficult, the sampled current data can be biased, failing to meet the requirements for high-precision current monitoring and control.

[0003] With the continuous advancement of technology, the requirements for the accuracy, power consumption, and stability of current sampling chip circuits are becoming increasingly stringent. Existing current sampling technology can no longer meet the stringent requirements of emerging application scenarios. Therefore, developing a current sampling chip circuit that can overcome the shortcomings of traditional sampling methods and achieve high precision and low power consumption has become an urgent problem to be solved in this field. Summary of the Invention

[0004] The present invention aims to improve at least one technical problem in the background technology.

[0005] A first aspect of the present invention provides a current sampling chip circuit, comprising: a sampling input module, an operational amplifier module, a startup control module, and a sampling output module; the sampling input module is used to sample the main circuit current; the operational amplifier module is used to amplify the sampled current; the sampling output module is used to output a sampled current signal; the startup control module is used to ensure smooth startup of the circuit and prevent the startup process from interfering with the operational amplifier module; the output end of the sampling input module is connected to the input end of the operational amplifier module, the output end of the operational amplifier module is connected to the input end of the sampling output module, and the output end of the startup control module is connected to the input end of the operational amplifier module.

[0006] The beneficial effects of the embodiments of the first aspect of the present invention are: the main circuit current is accurately collected using the sampling input module, the sampled current is amplified using the operational amplifier module, and finally the sampled current is output using the sampling output module; the startup control module ensures the smooth startup of the circuit to avoid startup interfering with the normal operation of the operational amplifier module; high-precision current sampling is achieved by cooperating with the sampling input module and the operational amplifier module, and the power consumption is lower than that of traditional resistance current sampling, and the startup control module is used to ensure the stability of the circuit under different working conditions, thereby achieving high-precision, low-power, stable and reliable current sampling.

[0007] As some sub-solutions of the above technical solution, the sampling input module includes a power input terminal VIN, a power switch MH1 and a sampling tube MSENSE1; the operational amplifier module includes an operational amplifier OPA1, and the sampling output module includes a fourth transistor MHP4, a second diode D2 and an output pin ISENSE; the drain of the power switch MH1 and the drain of the sampling tube MSENSE1 are both connected to the power input terminal VIN, the power switch MH1 and the sampling tube MSENSE1 share a gate, the source of the power switch MH1 is connected to the positive input terminal VP of the operational amplifier OPA1, the source of the sampling tube MSENSE1 is connected to the negative input terminal VN of the operational amplifier OPA1, the source of the sampling tube MSENSE1 is also connected to the source of the fourth transistor MHP4, the output terminal VOUT of the operational amplifier OPA1 is connected to the gate of the fourth transistor MHP4, the drain of the fourth transistor MHP4 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the output pin ISENSE.

[0008] As some sub-solutions of the above technical solution, the sampling input module further includes a common gate control terminal GH1 , and the common gate control terminal GH1 is respectively connected to the gate of the power switch MH1 and the gate of the sampling transistor MSENSE1 .

[0009] As some sub-solutions of the above technical solution, the operational amplifier module includes a first transistor B1, a second transistor B2, a third transistor B3, a first transistor MHP1, a second transistor MHP2, a third transistor MHP3 and a capacitor C1; the positive input terminal VP is connected to the emitter of the first transistor B1, the collector of the first transistor B1 is connected to the source of the second transistor MHP2, the emitter of the second transistor B2 is connected to the reverse input terminal VN, and the collector of the second transistor B2 is connected to the source of the third transistor MHP3; the base of the first transistor B1 is connected to the base of the second transistor B2 and the source of the first transistor MHP1. The emitter of the second transistor B2 is also connected to the emitter of the third transistor B3, the base of the third transistor B3 is connected to the source of the first transistor MHP1, and the collector of the third transistor B3 is connected to the source of the fourth transistor MHP4; the gate and drain of the second transistor MHP2 are commonly connected to the gate of the third transistor MHP3 and the output terminal VOUT; one end of the capacitor C1 is connected to the collector of the second transistor B2, and the other end of the capacitor C1 is respectively connected to the base of the first transistor B1, the base of the second transistor B2, the base of the third transistor B3, and the source of the first transistor MHP1.

[0010] As some sub-solutions of the above technical solution, the startup control module includes a bias voltage terminal Vbias, an analog voltage terminal VDDA, a first pmos transistor MP1, a first diode D1, a first nmos transistor MN1, a second nmos transistor MN2, a first resistor R1, a fourth transistor B4, a fifth transistor B5, a sixth transistor B6 and a fifth transistor MHN1; the bias voltage terminal Vbias is connected to the gate of the first pmos transistor MP1, the source of the first pmos transistor MP1 is connected to the analog voltage terminal VDDA, the drain of the first pmos transistor MP1 is connected to the source of the second nmos transistor MN2 and the anode of the first diode D1; the cathode of the first diode D1 is connected to the gate of the first nmos transistor MN1, the gate of the first nmos transistor MN1 is connected to the gate of the second nmos transistor MN2, and the drain of the first nmos transistor MN1 is connected to the analog voltage terminal VDDA; the second nmos transistor MN2 is connected to the gate of the first nmos transistor MN2. The drain of the MOS transistor MN2 is connected to the analog voltage terminal VDDA; the source of the first NMOS transistor MN1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the emitter of the fourth transistor B4, the emitter of the fifth transistor B5, and the emitter of the sixth transistor B6 are all grounded; the base of the fourth transistor B4, the base of the fifth transistor B5, and the base of the sixth transistor B6 are all connected to the source of the first NMOS transistor MN1; the collector of the fourth transistor B4 is connected to the anode of the first diode D1; the collector of the fifth transistor B5 is connected to the source of the fifth transistor MHN1; the collector of the sixth transistor B6 is connected to the gate of the first NMOS transistor MN1 and the drain of the third transistor MHP3; the gate of the fifth transistor MHN1 is connected to the analog voltage terminal VDDA, and the drain of the fifth transistor MHN1 is connected to the drain of the second transistor MHP2.

[0011] As some sub-solutions of the above technical solution, the startup control module also includes a second resistor R2, a third resistor R3 and a fourth resistor R4; the second resistor R2 is connected between the source of the first nmos tube MN1 and the base of the fourth transistor B4; the third resistor R3 is connected between the source of the first nmos tube MN1 and the base of the fifth transistor B5; the fourth resistor R4 is connected between the source of the first nmos tube MN1 and the base of the fifth transistor B5.

[0012] As some sub-solutions of the above technical solution, the current ratio relationship between the first transistor B1, the second transistor B2, and the third transistor B3 is 1:1:2; the current ratio relationship between the second transistor MHP2, the third transistor MHP3, and the fourth transistor MHP4 is 1:1:2.

[0013] As some sub-solutions of the above technical solution, the power switch MH1 and the sampling transistor MSENSE1 have the same channel width-to-length ratio.

[0014] A second aspect of the present invention provides a PCB board, on which any of the above-mentioned current sampling chip circuits is printed.

[0015] The PCB board according to the embodiment of the second aspect of the present invention also has corresponding beneficial effects because it includes the current sampling chip circuit of the above technical solution.

[0016] A third aspect of the present invention provides a current sampling device, which uses any of the above-mentioned current sampling chip circuits to achieve operation control.

[0017] The current sampling device according to the embodiment of the third aspect of the present invention also has corresponding beneficial effects because it includes the current sampling chip circuit of the above technical solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0019] Figure 1 A circuit block diagram of the current sampling chip circuit provided by the present invention;

[0020] Figure 2 An application circuit diagram of the current sampling chip circuit provided by the present invention;

[0021] Figure 3 This is a circuit schematic diagram of the current sampling chip circuit provided by the present invention.

[0022] In the attached figure: 1- sampling input module; 2- operational amplifier module; 3- start control module; 4- sampling output module. DETAILED DESCRIPTION

[0023] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0024] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0025] In the description of the present invention, "several" means an indefinite quantity, "multiple" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, and "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" is solely for the purpose of distinguishing technical features and should not be understood to indicate or imply relative importance, or to implicitly indicate the number or order of the technical features indicated. "And / or" throughout the text represents three parallel solutions. For example, "A and / or B" means a solution where A satisfies, a solution where B satisfies, or a solution where both A and B satisfy.

[0026] In the description of the present invention, if there is a short sentence containing multiple parallel features, the attributive defines the closest feature. For example, "B, C, and E are arranged on A, and are connected to D" means that B is arranged on A and E is connected to D, and does not constitute a limitation on C. However, attributives that express the relationship between features, such as "spaced arrangement" or "circular arrangement", do not fall into this category. If the word "all" is preceded by an attributive, it means that all features in the short sentence are limited. For example, "B, C, and D are all arranged on A" means that B, C, and D are all arranged on A. In a sentence with an omitted subject, the omitted subject is the subject of the previous sentence, that is, "B is arranged on A, including C" means that B is arranged on A and A includes C.

[0027] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0028] The following combination Figures 1 to 3 Embodiments of the present invention are described.

[0029] See Figure 1In this embodiment, a current sampling chip circuit includes: a sampling input module 1, an operational amplifier module 2, a startup control module 3, and a sampling output module 4; the sampling input module 1 is used to sample the main circuit current; the operational amplifier module 2 is used to amplify the sampled current; the sampling output module 4 is used to output the sampled current signal; the startup control module 3 is used to ensure smooth startup of the circuit and prevent the startup process from interfering with the operational amplifier module; the output end of the sampling input module 1 is connected to the input end of the operational amplifier module 2, the output end of the operational amplifier module 2 is connected to the input end of the sampling output module 4, and the output end of the startup control module 3 is connected to the input end of the operational amplifier module 2.

[0030] Specifically, the sampling input module 1 includes a power input terminal VIN, a power switch MH1 and a sampling tube MSENSE1; the operational amplifier module 2 includes an operational amplifier OPA1, and the sampling output module 4 includes a fourth transistor MHP4, a second diode D2 and an output pin ISE NSE; the drain of the power switch MH1 and the drain of the sampling tube MSENSE1 are both connected to the power input terminal VIN, the power switch MH1 and the sampling tube MSENSE1 share a gate, the source of the power switch MH1 is connected to the positive input terminal VP of the operational amplifier OPA1, the source of the sampling tube MSENSE1 is connected to the negative input terminal VN of the operational amplifier OPA1, the source of the sampling tube MSENSE1 is also connected to the source of the fourth transistor MHP4, the output terminal VOUT of the operational amplifier OPA1 is connected to the gate of the fourth transistor MHP4, the drain of the fourth transistor MHP4 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the output pin ISENSE.

[0031] See first Figure 3 , Figure 3 This is the circuit schematic of the current sampling chip circuit; it includes two sets of symmetrically arranged sampling circuits. Taking the left arm as an example, the left arm includes: voltage input VIN, power switch MH1, sampling tube MSENSE1, operational amplifier OPA1, fourth transistor MHP4, second diode D2 and output pin ISENSE; the components and principles contained in the right arm are the same as those of the left arm; since only one side of the high-side power tube in the circuit will carry current, in order to output the sampled current signal, the currents on both sides are connected together to the ISENSE pin of the chip.

[0032] The principle of current sampling chip current is as follows: in MOS tube, when the gate, source and drain voltages of power switch and sampling MOS tube are equal, according to the electrical characteristics of MOS tube, the ratio of their currents is equal to the width-to-length ratio, so that accurate sampling can be achieved; in order to ensure that the gate, source and drain voltages of power switch MH1 and sampling tube MSENSE1 are equal, the circuit uses the virtual short function of high voltage operational amplifier, that is, the voltages of the two input terminals of operational amplifier are equal, thereby ensuring that the gate, source and drain voltages of power switch MH1 and sampling tube MSENSE1 are equal; the drain of power switch MH1 and sampling tube MSENSE1 are both connected to the power input terminal VIN, and the power input terminal VIN provides power to the circuit; because the power switch MH1 and sampling tube MSENSE1 are equal, the circuit is connected to the power supply input terminal VIN, and the circuit is connected to the power supply input terminal VIN. NSE1 shares a common gate and the two have the same channel width-to-length ratio, so their conduction characteristics are related. The source of the power switch MH1 is connected to the positive input of the operational amplifier OPA1, and the source of the sampling tube MSENSE1 is connected to the negative input of the operational amplifier OPA1; the source of the fourth transistor MHP4 is connected to the source of the sampling tube MSENSE1 to receive the sampling current signal, and its gate is controlled by the output signal of the operational amplifier OPA1 to adjust its own conduction state and further process the sampling current; the drain of the fourth transistor MHP4 is connected to the anode of the second diode D2, and the second diode D2 plays a unidirectional conduction and a certain signal regulation role. Finally, the current signal is output from the output pin ISENSE through the second diode D2.

[0033] Traditional resistor sampling is significantly affected by factors such as resistor accuracy and temperature. However, the low-loss characteristics of the MOS transistor in this design reduce these interference factors. This embodiment ensures that the gate, source, and drain voltages of the power switch and the sampling MOS transistor are equal, and utilizes the characteristics of the MOS transistor to make the sampling ratio equal to the width-to-length ratio. Compared with traditional resistor sampling methods, this embodiment improves sampling accuracy.

[0034] See Figure 2 , Figure 2 : This is the application circuit diagram of the current sampling chip circuit. In this embodiment, the working principle and adjustment mechanism of the operational amplifier OPA1 are as follows:

[0035] In the first case, when the voltage at the positive input terminal VP increases and the voltage at the reverse input terminal VN remains unchanged:

[0036] When the voltage at the positive input terminal VP increases, since the emitter of the first transistor B1 is connected to VP, its emitter-base voltage increases accordingly. During this process, the potentials of the ports of the fifth transistor B5 and the fifth transistor MHN1 remain unchanged. Based on this, the current in branch x remains constant. According to Kirchhoff's law, when the current in branch x remains unchanged, the emitter current of the first transistor B1 will not change either. Therefore, in order to suppress the increase in the emitter current of the first transistor B1 due to the increase in VP, the potential at point C is quickly pulled up. Since the current in branch x remains unchanged, the gate voltage of the second transistor MHP2 related to the current in branch x remains unchanged, but the potential of the output terminal VOUT will rise with the potential at point C. After the potential of the output terminal VOUT rises, the gate voltage of the third transistor MHP3 decreases, causing the potential at point B to drop. At this time, the source follower formed by the first NMOS transistor MN1 and the first resistor R1 comes into play, causing the fourth transistor B4, the fifth transistor B5 and the sixth transistor B5 to rise. The base potential of transistor B6 decreases. Because the base potential of the fifth transistor B5 decreases, the potential at point A increases, which in turn causes the gate voltage of the fifth transistor MHN1 to decrease, ultimately reducing the current in branch x and the collector of the first transistor B1. The base potential of the sixth transistor B6 decreases, which in turn reduces the collector current in branch y and the second transistor B2. Because the on-state voltage of the sampling transistor MSENSE1 is related to the collector current of the second transistor B2, the collector current of B2 decreases, and the on-state voltage of the sampling transistor MSENSE1 also decreases, thereby increasing the voltage at the reverse input terminal VN. The increase in the voltage at the reverse input terminal VN, that is, the potential at point D, increases. Through the coupling effect of capacitor C1, the increased potential at point D is transmitted to the first transistor B1, the second transistor B2, and the third transistor B3, causing their base potentials to increase. As these changes continue, the voltage at the reverse input terminal VN equals the voltage at the forward input terminal VP, and the circuit returns to a new equilibrium state.

[0037] In the second case, when the voltage at the positive input terminal VP decreases and the voltage at the reverse input terminal VN remains unchanged:

[0038] When the voltage at the positive input terminal VP decreases, the emitter-base voltage of the first transistor B1 decreases accordingly. Because the potentials at the terminals of the fifth transistor B5 and the fifth transistor MHN1 remain unchanged, the current in branch x remains unchanged. According to Kirchhoff's law, the emitter current of the first transistor B1 also remains unchanged. To prevent the emitter current of the first transistor B1 from decreasing due to the decrease in VP, the potential at point C needs to drop rapidly. As the potential at point C decreases, the gate voltage of the second transistor MHP2, which is related to the potential at point C, also decreases. At this time, the current in branch y remains unchanged, but the gate voltage of the third transistor MHP3 increases, causing the potential at point B to rise. The source follower formed by the first NMOS transistor MN1 and the first resistor R1 converts the potential increase at point B into an increase in the base voltage of the fifth transistor B5 and the sixth transistor B6. Because the base voltages of the fifth transistor B5 and the sixth transistor B6 increase, the potential at point A decreases, and the currents of the fifth transistor B5 and the sixth transistor B6 increase. The current of the sampling tube MSENSE1 is positively correlated with the current of the sixth transistor B6. The on-state current and on-state voltage of the sampling tube MSENSE1 also increase accordingly, causing the potential of the reverse input terminal VN to decrease. The decrease in the potential of the reverse input terminal VN, that is, the potential of point D, decreases. Through the coupling effect of capacitor C1, the potential drop at point D is transmitted to the first transistor B1, the second transistor B2, and the third transistor B3, causing their base potentials to drop. As these changes continue until the voltage at the reverse input terminal VN drops to equal the voltage at the positive input terminal VP, the circuit reaches a balanced state again.

[0039] In the third case, when the voltage at the positive input terminal VP remains unchanged and the voltage at the reverse input terminal VN increases:

[0040] When the voltage at the inverting input terminal VN increases, the current in the sampling transistor MSENSE1 connected to the inverting input terminal VN immediately decreases. However, the emitter-base voltage of the second transistor B2 increases. This conflicting situation causes the potential at point D to rise rapidly, and through the coupling effect of capacitor C1, the base voltage of the second transistor B2 increases. During this process, the current in branch x remains unchanged, so the potential at point C decreases, which in turn causes the potential at the output terminal VOUT to decrease. Because the potential at the output terminal VOUT decreases and the potential at point D increases, the gate voltage of the third transistor MHP3 increases, which in turn conflicts with the decrease in the current in branch y. To resolve this conflict, the potential at point B increases, causing the current in branch y to increase. When the current in branch y increases, the on-resistance of the sampling transistor MSENSE1 increases, causing the voltage at the inverting input terminal VN to decrease again until it drops to equal the voltage at the positive input terminal VP, and the circuit is balanced again.

[0041] The fourth case: When the voltage at the positive input terminal VP remains unchanged and the voltage at the reverse input terminal VN decreases:

[0042] When the voltage at the inverting input terminal VN decreases, the current in the sampling transistor MSENSE1 connected to the inverting input terminal VN immediately increases, while the emitter-base voltage of the second transistor B2 decreases. This conflict causes the potential at point D to drop rapidly, and through the coupling effect of capacitor C1, the base voltage of the second transistor B2 increases. During this process, since the current in branch x remains unchanged, the potential at point C rises rapidly, causing the potential at the output terminal VOUT to also rise. Because the potential at the output terminal VOUT rises and the potential at point D falls, the gate voltage of the third transistor MHP3 decreases, which in turn conflicts with the increase in the current in branch y. To balance this conflict, the voltage at point B decreases, and the base voltage of the sixth transistor B6 also decreases, reducing the emitter current of the sixth transistor B6 and, therefore, the current in branch y. The decrease in branch y current causes the voltage at the inverting input terminal VN to increase until it reaches the voltage equal to the voltage at the positive input terminal VP, restoring the circuit to equilibrium.

[0043] Because the DC operating point of the operational amplifier requires that the positive input terminal VP equal the negative input terminal VN, the currents in branches x and y must be equal. The present invention utilizes the fifth and sixth transistors B5 and B6 to assist in this process. When the emitter, collector, and base voltages of the fifth and sixth transistors B5 and B6 are equal, the currents in branches x and b are equal. Furthermore, because the second transistor MHP2 and the third transistor MHP3 are high-voltage transistors, they have poor matching and exhibit channel length modulation, which can lead to significant voltage deviations between nodes C and D. Therefore, the present invention utilizes the first and second transistors B1 and B2 operating in the linear region to reduce the offset voltage between the positive input terminal VP and the negative input terminal VN. The first and second transistors B1 and B2 have good matching, with equal base voltages, minimal collector voltage deviation, and equal currents. Therefore, the positive input terminal VP can be guaranteed to equal the negative input terminal VN, thereby maintaining stable circuit operation.

[0044] In this embodiment, the bias voltage terminal Vbias, the analog voltage terminal VDDA, the first pmos transistor MP1, the first diode D1, the first nmos transistor MN1, the second nmos transistor MN2, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fourth transistor B4, the fifth transistor B5, the sixth transistor B6 and the fifth transistor MHN1 form a startup circuit of the operational amplifier OPA1. The specific working principle is as follows: after power-on, the bias voltage terminal Vbias turns on the first pmos transistor MP1, and the current flows through the first The diode D1 charges the gate capacitance of the first nmos transistor MN1. When the current of the first nmos transistor MN1 causes the voltage at the upper end of the first resistor R1 to rise to about 0.7V, the first nmos transistor MN1 provides current to the bases of the fourth transistor B4, the fifth transistor B5, and the sixth transistor B6. When the fifth transistor B5 is turned on, the potential of the connection point between it and the source of the fifth transistor MHN1 is pulled down, turning on the fifth transistor MHN1. Since the drain of the fifth transistor MHN1 is connected to the drain of the second transistor MHP2, when the fifth transistor B5 is turned on, the potential of the connection point between it and the source of the fifth transistor MHN1 is pulled down, turning on the fifth transistor MHN1. 5 is turned on and pulled down, the gate potential of the second transistor MHP2 also changes accordingly, and the diode connection characteristics of the second transistor MHP2 will affect the gate of the third transistor MHP3 connected to its gate, pulling down the gate of the third transistor MHP3, turning on the third transistor MHP3, and then causing the gate potential of the first transistor MHP1 to drop until the first transistor MHP1 is turned on; after the first transistor MHP1 is turned on, it provides a current path for the first transistor B1, the second transistor B2 and the third transistor B3, so that the first transistor B1 , the second transistor B2 and the third transistor B3 are turned on, and the current completes the startup and enters the normal working state; after the startup is completed, in order to prevent the startup current from interfering with the operational amplifier, the startup current needs to be disconnected. At this time, the current of the first pmos tube MP1 is discharged to the ground through the fourth transistor B4, and the fourth transistor B4 pulls down to make the anode of the first diode D1 reverse biased, thereby disconnecting the startup circuit, preventing the current and potential fluctuations in the startup circuit from affecting the normal operation of the operational amplifier, and ensuring that the operational amplifier module 2 can stably process the sampling current.

[0045] Specifically, the sampling input module 1 also includes a common-gate control terminal GH1, which is connected to the gate of the power switch MH1 and the gate of the sampling transistor MSENSE1, respectively. The gates of both the power switch MH1 and the sampling transistor MSENSE1 are connected to the common-gate control terminal GH1. Simply controlling the output signal of the common-gate control terminal GH1 can simultaneously control the on and off states of both transistors. Compared to independently controlling the gates of the two transistors, this connection method is more reliable and reduces performance inconsistencies caused by gate voltage differences.

[0046] Specifically, the operational amplifier module 2 includes a first transistor B1, a second transistor B2, a third transistor B3, a first transistor MHP1, a second transistor MHP2, a third transistor MHP3 and a capacitor C1; the positive input terminal VP is connected to the emitter of the first transistor B1, the collector of the first transistor B1 is connected to the source of the second transistor MHP2, the emitter of the second transistor B2 is connected to the reverse input terminal VN, and the collector of the second transistor B2 is connected to the source of the third transistor MHP3; the base of the first transistor B1 is connected to the base of the second transistor B2 and the source of the first transistor MHP1; The emitter of the second transistor B2 is also connected to the emitter of the third transistor B3, the base of the third transistor B3 is connected to the source of the first transistor MHP1, and the collector of the third transistor B3 is connected to the source of the fourth transistor MHP4; the gate and drain of the second transistor MHP2 are commonly connected to the gate of the third transistor MHP3 and the output terminal VOUT; one end of the capacitor C1 is connected to the collector of the second transistor B2, and the other end of the capacitor C1 is respectively connected to the base of the first transistor B1, the base of the second transistor B2, the base of the third transistor B3, and the source of the first transistor MHP1.

[0047] Specifically, the startup control module 3 includes a bias voltage terminal Vbias, an analog voltage terminal VDDA, a first pmos transistor MP1, a first diode D1, a first nmos transistor MN1, a second nmos transistor MN2, a first resistor R1, a fourth transistor B4, a fifth transistor B5, a sixth transistor B6 and a fifth transistor MHN1; the bias voltage terminal Vbias is connected to the gate of the first pmos transistor MP1, the source of the first pmos transistor MP1 is connected to the analog voltage terminal VDDA, the drain of the first pmos transistor MP1 is connected to the source of the second nmos transistor MN2 and the anode of the first diode D1; the cathode of the first diode D1 is connected to the gate of the first nmos transistor MN1, the gate of the first nmos transistor MN1 is connected to the gate of the second nmos transistor MN2, and the drain of the first nmos transistor MN1 is connected to the analog voltage terminal VDDA; the second nmos transistor M The drain of N2 is connected to the analog voltage terminal VDDA; the source of the first NMOS transistor MN1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the emitter of the fourth transistor B4, the emitter of the fifth transistor B5, and the emitter of the sixth transistor B6 are all grounded; the base of the fourth transistor B4, the base of the fifth transistor B5, and the base of the sixth transistor B6 are all connected to the source of the first NMOS transistor MN1; the collector of the fourth transistor B4 is connected to the anode of the first diode D1; the collector of the fifth transistor B5 is connected to the source of the fifth transistor MHN1; the collector of the sixth transistor B6 is connected to the gate of the first NMOS transistor MN1 and the drain of the third transistor MHP3; the gate of the fifth transistor MHN1 is connected to the analog voltage terminal VDDA, and the drain of the fifth transistor MHN1 is connected to the drain of the second transistor MHP2.

[0048] Specifically, the startup control module 3 also includes a second resistor R2, a third resistor R3, and a fourth resistor R4. The second resistor R2 is connected between the source of the first nmos transistor MN1 and the base of the fourth transistor B4; the third resistor R3 is connected between the source of the first nmos transistor MN1 and the base of the fifth transistor B5; and the fourth resistor R4 is connected between the source of the first nmos transistor MN1 and the base of the fifth transistor B5. The second resistor R2, the third resistor R3, and the fourth resistor R4 cooperate with the fourth transistor B4, the fifth transistor B5, and the sixth transistor B6, respectively, to provide appropriate bias currents for them, ensuring that the transistors operate in the appropriate range and maintaining normal circuit operation.

[0049] Specifically, the current ratio relationship among the first transistor B1, the second transistor B2, and the third transistor B3 is 1:1:2; the current ratio relationship among the second transistor MHP2, the third transistor MHP3, and the fourth transistor MHP4 is 1:1:2.

[0050] In this embodiment, the load current I LOAD , the current I in branch x a and the current I of the power switch MH1 MH1 The relationship is:

[0051] I LOAD +I a =I MH1 ;

[0052] Branch z sampling current I SENSE , branch y current I b and the sampling tube MSENSE1 current I MSENSE1 The relationship is:

[0053] I SENSE +I b =I MSENSE1 ;

[0054] Power switch MH1 current I MH1 and the sampling tube MSENSE1 current I MSENSE1 The relationship is:

[0055]

[0056] in is the aspect ratio of the power switch MH1 and the sampling tube MSENSE1;

[0057] Since the current ratio between the first transistor B1, the second transistor B2, and the third transistor B3 is 1:1:2, and the current ratio between the second transistor MHP2, the third transistor MHP3, and the fourth transistor MHP4 is 1:1:2, the current ratio of the branches x, b, and c is 1:1:2. Therefore, it can be obtained that:

[0058] I b =I a ;

[0059] I SENSE =2I a ;

[0060] I MSENSE1 =3I a ;

[0061] Therefore, the load current I LOAD And the sampling current I SENSE The relationship is:

[0062]

[0063] This relationship shows that the load current ILOAD and the sampling current I can be determined by knowing the width-to-length ratio of the power switch MH1 and the sampling tube MSENSE1. SENSE The sampling ratio is approximately equal to 1.5 times the width-to-length ratio of the power switch MH1 and the sampling tube MSENSE1.

[0064] Specifically, the power switch MH1 and the sampling transistor MSENSE1 have the same channel width-to-length ratio.

[0065] The sampling scheme of this embodiment ensures that the gate, source, and drain voltages of the power switch MH1 and the sampling tube MSENSE1 are equal. In this case, the sampling ratio is equal to the width-to-length ratio. When the power switch MH1 and the sampling tube MSENSE1 are the same size, their width-to-length ratios are equal. This ensures that, under the same gate-source voltage, the current characteristics of the two are highly matched. When connected in common gate mode, the voltages at the positive and negative input terminals of the op amp can be more stably maintained, enabling more precise setting of the sampling ratio and ensuring sampling accuracy. Furthermore, during circuit operation, the power switch MH1 carries the main circuit current, while the sampling tube MSENSE1 collects the current signal. When the two are the same size, their electrical parameters, such as on-resistance and transconductance, are similar. This allows the sampling tube MSENSE1 to more accurately reflect the current changes of the power switch MH1, optimizes the current characteristic matching during the sampling process, and ensures that the sampled signal more accurately represents the main circuit current.

[0066] A second aspect of the present invention provides a PCB board, on which any of the above-mentioned current sampling chip circuits is printed.

[0067] A third aspect of the present invention provides a current sampling device, which uses any of the above-mentioned current sampling chip circuits to achieve operation control.

[0068] The above specifically describes the preferred embodiments of the present invention, but the present disclosure is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present disclosure.

Claims

1. A current sampling chip circuit, characterized in that: include: Sampling input module, operational amplifier module, startup control module and sampling output module; The sampling input module is used to sample the main circuit current; the operational amplifier module is used to amplify the sampled current; the sampling output module is used to output the sampled current signal; the startup control module is used to ensure smooth startup of the circuit and avoid interference with the operational amplifier module during the startup process; the output end of the sampling input module is connected to the input end of the operational amplifier module, the output end of the operational amplifier module is connected to the input end of the sampling output module, and the output end of the startup control module is connected to the input end of the operational amplifier module.

2. The current sampling chip circuit according to claim 1, characterized in that: The sampling input module includes a power input terminal VIN, a power switch MH1 and a sampling tube MSENSE1; the operational amplifier module includes an operational amplifier OPA1, and the sampling output module includes a fourth transistor MHP4, a second diode D2 and an output pin ISENSE; the drain of the power switch MH1 and the drain of the sampling tube MSENSE1 are both connected to the power input terminal VIN, the power switch MH1 and the sampling tube MSENSE1 share a gate, the source of the power switch MH1 is connected to the positive input terminal VP of the operational amplifier OPA1, the source of the sampling tube MSENSE1 is connected to the negative input terminal VN of the operational amplifier OPA1, the source of the sampling tube MSENSE1 is also connected to the source of the fourth transistor MHP4, the output terminal VOUT of the operational amplifier OPA1 is connected to the gate of the fourth transistor MHP4, the drain of the fourth transistor MHP4 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the output pin ISENSE.

3. The current sampling chip circuit according to claim 2, characterized in that: The sampling input module further includes a common gate control terminal GH1 , which is connected to the gate of the power switch MH1 and the gate of the sampling transistor MSENSE1 .

4. The current sampling chip circuit according to claim 2, characterized in that: The operational amplifier module includes a first transistor B1, a second transistor B2, a third transistor B3, a first transistor MHP1, a second transistor MHP2, a third transistor MHP3 and a capacitor C1; the positive input terminal VP is connected to the emitter of the first transistor B1, the collector of the first transistor B1 is connected to the source of the second transistor MHP2, the emitter of the second transistor B2 is connected to the negative input terminal VN, and the collector of the second transistor B2 is connected to the source of the third transistor MHP3; The base of the first transistor B1 is connected to the base of the second transistor B2 and the source of the first transistor MHP1; the emitter of the second transistor B2 is also connected to the emitter of the third transistor B3, the base of the third transistor B3 is connected to the source of the first transistor MHP1, and the collector of the third transistor B3 is connected to the source of the fourth transistor MHP4; the gate and drain of the second transistor MHP2 are commonly connected to the gate of the third transistor MHP3 and the output terminal VOUT; one end of the capacitor C1 is connected to the collector of the second transistor B2, and the other end of the capacitor C1 is respectively connected to the base of the first transistor B1, the base of the second transistor B2, the base of the third transistor B3, and the source of the first transistor MHP1.

5. The current sampling chip circuit according to claim 4, characterized in that: The startup control module includes a bias voltage terminal Vbias, an analog voltage terminal VDDA, a first pmos transistor MP1, a first diode D1, a first nmos transistor MN1, a second nmos transistor MN2, a first resistor R1, a fourth transistor B4, a fifth transistor B5, a sixth transistor B6 and a fifth transistor MHN1; the bias voltage terminal Vbias is connected to the gate of the first pmos transistor MP1, the source of the first pmos transistor MP1 is connected to the analog voltage terminal VDDA, the drain of the first pmos transistor MP1 is connected to the source of the second nmos transistor MN2 and the anode of the first diode D1; the cathode of the first diode D1 is connected to the gate of the first nmos transistor MN1, the gate of the first nmos transistor MN1 is connected to the gate of the second nmos transistor MN2, the drain of the first nmos transistor MN1 is connected to the analog voltage terminal VDDA; the second nmos transistor MN2 is connected to the gate of the second nmos transistor MN2. The drain of the first nmos transistor MN1 is connected to the analog voltage terminal VDDA; the source of the first nmos transistor MN1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the emitter of the fourth transistor B4, the emitter of the fifth transistor B5, and the emitter of the sixth transistor B6 are all grounded; the base of the fourth transistor B4, the base of the fifth transistor B5, and the base of the sixth transistor B6 are all connected to the source of the first nmos transistor MN1; the collector of the fourth transistor B4 is connected to the anode of the first diode D1; the collector of the fifth transistor B5 is connected to the source of the fifth transistor MHN1; the collector of the sixth transistor B6 is connected to the gate of the first nmos transistor MN1 and the drain of the third transistor MHP3; the gate of the fifth transistor MHN1 is connected to the analog voltage terminal VDDA, and the drain of the fifth transistor MHN1 is connected to the drain of the second transistor MHP2.

6. The current sampling chip circuit according to claim 5, characterized in that: The startup control module also includes a second resistor R2, a third resistor R3 and a fourth resistor R4; the second resistor R2 is connected between the source of the first NMOS transistor MN1 and the base of the fourth transistor B4; the third resistor R3 is connected between the source of the first NMOS transistor MN1 and the base of the fifth transistor B5; the fourth resistor R4 is connected between the source of the first NMOS transistor MN1 and the base of the fifth transistor B5.

7. The current sampling chip circuit according to claim 4, characterized in that: The current ratio relationship among the first transistor B1 , the second transistor B2 , and the third transistor B3 is 1:1:2; the current ratio relationship among the second transistor MHP2 , the third transistor MHP3 , and the fourth transistor MHP4 is 1:1:

2.

8. The current sampling chip circuit according to claim 3, characterized in that: The power switch MH1 and the sampling transistor MSENSE1 have the same channel width-to-length ratio.

9. A PCB board, characterized in that: The PCB board is printed with the current sampling chip circuit according to any one of claims 1 to 8.

10. A current sampling device, characterized in that: The current sampling device uses the current sampling chip circuit according to any one of claims 1 to 8 to achieve operation control.

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