Frequency regulation oscillator circuit

Abstract

Oscillator circuitry and methods of operation thereof are provided, wherein the oscillator circuitry includes at least a first oscillator, a second oscillator, and a lock detector. The first oscillator is configured to generate a first clock signal. The second oscillator is configured to generate a second clock signal. The lock detector is configured to detect a stable phase lock between the first clock signal and the second clock signal, and switch an output of the oscillator circuitry from the first clock signal to the second clock signal in response to detecting the stable phase lock.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to integrated circuits including frequency regulated oscillator circuits, such as frequency locked loop (FLL) oscillator circuits. Background Art

[0002] Oscillators are widely used in electronic devices as clock generators for generating clock signals, which are in turn used to generate various control signals and timing references. For example, voltage-controlled oscillators (VCOs) are often used in closed-loop synchronization circuits, such as frequency-locked loops (FLLs). Conventional VCO-based FLLs can have high accuracy (once stabilized) and relatively low current consumption, but tend to have extremely inaccurate oscillation frequencies at startup and tend to start up slowly (e.g., up to about 100 μs). The slow startup time of conventional implementations of VCO-based FLLs may make them unsuitable for applications that require oscillatory circuitry with relatively fast startup times. Summary of the invention

[0003] A brief overview of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following overview, which is intended to highlight and introduce some aspects of the various exemplary embodiments without limiting the scope. A detailed description of the exemplary embodiments sufficient to allow a person of ordinary skill in the art to obtain and use these concepts will be presented in subsequent sections.

[0004] In an example embodiment, an oscillator circuit system includes: a first oscillator, which is configured to generate a first clock signal; a second oscillator, which is configured to generate a second clock signal; and a lock detector, which is configured to detect a stable phase lock between the first clock signal and the second clock signal, and switch the output of the oscillator circuit system from the first clock signal to the second clock signal in response to detecting the stable phase lock.

[0005] In one or more embodiments, the oscillator circuit system further includes a phase-locked loop (PLL), which includes: a first oscillator; a second oscillator; a phase frequency detector, which is configured to receive a first clock signal and a second clock signal; detect edges of the first clock signal and the second clock signal; assert the first signal in response to detecting an edge of the first clock signal; assert the second signal in response to detecting an edge of the second clock signal; and reset the first signal and the second signal in response to determining that the first signal and the second signal are simultaneously asserted; and a charge pump, which is configured to modify the control signal received by the second oscillator based on the first signal and the second signal.

[0006] In one or more embodiments, the oscillator circuit system further includes a frequency-locked loop, which includes: a second oscillator; a frequency-to-voltage circuit, which is configured to receive a second clock signal and generate a voltage based on the frequency of the second clock signal; and an operational amplifier, which is configured to receive a voltage and a reference voltage from the frequency-to-voltage circuit; compare the voltage and the reference voltage; and modify the control signal based on the result of comparing the voltage and the reference voltage.

[0007] In one or more embodiments, the lock detector is configured to assert a lock signal in response to detecting a stable phase lock.

[0008] In one or more embodiments, in response to the lock signal being deasserted, the first output of the frequency-to-voltage circuit is shorted to the second output of the frequency-to-voltage circuit.

[0009] In one or more embodiments, the oscillator circuit system further includes a multiplexer configured to receive the first clock signal, the second clock signal, and the lock signal. The multiplexer can be configured to output the first clock signal in response to the lock signal not being asserted, and output the second clock signal in response to the lock signal being asserted.

[0010] In one or more embodiments, the lock detector is configured to receive the first signal and the second signal from the phase frequency detector and detect a stable phase lock based on the first signal and the second signal.

[0011] In one or more embodiments, the lock detector includes: a logic circuit system configured to generate a reset signal based on a first signal and a second signal; and a counter circuit system configured to increment a counter at each cycle of a first clock signal until reset by the reset signal or until the counter reaches a predetermined count value, and asserting a lock signal in response to the counter reaching the predetermined count value.

[0012] In one or more embodiments, assertion of the lock signal deactivates any of the first oscillator, the phase frequency detector, the charge pump, and the lock detector.

[0013] In one or more embodiments, the oscillator circuitry further comprises a compensation capacitor coupled to an input of the second oscillator at which the control signal is received. The voltage at the compensation capacitor may be the control signal.

[0014] In one or more embodiments, the oscillator circuit system may further include: a voltage buffer coupled to the output of the charge pump, wherein the output of the charge pump is coupled to the input of the second oscillator; and another compensation capacitor coupled to the voltage buffer. The voltage at the other compensation capacitor may be a control voltage when the PLL is active.

[0015] In an example embodiment, a method of operating an oscillator circuit system may include: generating a first clock signal by a first oscillator of the oscillator circuit system; generating a second clock signal by a second oscillator of the oscillator circuit system; detecting a stable phase lock between the first clock signal and the second clock signal by a lock detector; and switching an output of the oscillator circuit system from the first clock signal to the second clock signal in response to detecting the stable phase lock.

[0016] In one or more embodiments, the first oscillator has a startup time of less than 1 nanosecond and the second oscillator has a startup time of greater than 5 microseconds.

[0017] In one or more embodiments, the method further includes: receiving the first clock signal and the second clock signal by a phase frequency detector of the oscillator circuit system; detecting edges of the first clock signal and the second clock signal by the phase frequency detector; asserting the first signal by the phase frequency detector in response to detecting the edge of the first clock signal; asserting the second signal by the phase frequency detector in response to detecting the edge of the second clock signal; resetting the first signal and the second signal by the phase frequency detector in response to determining that the first signal and the second signal are asserted at the same time; and modifying the control signal received by the second oscillator based on the first signal and the second signal by a charge pump of the oscillator circuit system.

[0018] In one or more embodiments, the method further includes: receiving a second clock signal by a frequency-to-voltage circuit of the oscillator circuit system; generating a voltage by the frequency-to-voltage circuit based on the frequency of the second clock signal; receiving a voltage and a reference voltage from the frequency-to-voltage circuit by an operational amplifier of the oscillator circuit system; comparing the voltage and the reference voltage by the operational amplifier; and modifying the control signal by the operational amplifier based on the result of comparing the voltage and the reference voltage.

[0019] In one or more embodiments, the method further includes asserting a lock signal by the lock detector in response to detecting a stable phase lock; outputting a first clock signal by the oscillator circuit system in response to the lock signal not being asserted; and outputting a second clock signal by the oscillator circuit system in response to the lock signal being asserted.

[0020] In one or more embodiments, the method additionally includes shorting the first output of the frequency-to-voltage circuit to the second output of the frequency-to-voltage circuit in response to the lock signal not being asserted.

[0021] In one or more embodiments, the method further includes receiving, by the lock detector, the first signal and the second signal from the phase frequency detector; and detecting, by the lock detector, a stable phase lock based on the first signal and the second signal.

[0022] In one or more embodiments, the method further includes periodically changing, by a counter circuitry of the lock detector, a value of a counter in response to a stable phase lock; and asserting, by the lock detector, a lock signal in response to a counter of the counter circuitry reaching a predetermined count value.

[0023] In one or more embodiments, the method further includes deactivating any one of the first oscillator, the phase frequency detector, the charge pump, and the lock detector in response to assertion of the lock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete understanding of the subject matter may be obtained by reference to the detailed description and claims considered in conjunction with the following figures, wherein like reference numerals refer to similar elements throughout the figures. The elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. The drawings, together with the detailed description, are incorporated into and form part of this specification and serve to further illustrate examples, embodiments, etc., and to explain various principles and advantages according to the present disclosure, wherein:

[0025] Figure 1 is a block diagram illustrating an example oscillator circuit system according to one or more embodiments, the oscillator circuit system comprising: a voltage controlled oscillator (VCO); a fast start oscillator; and a lock detector configured to determine whether clock signals of the VCO and the fast start oscillator are substantially in phase and, based on the determination, select one of those clock signals for output by the oscillator circuit system;

[0026] Figure 2 FIG. 2 is a diagram showing a lock detector according to one or more embodiments, for example Figure 1 Block diagram of the lock detector.

[0027] Figure 3 FIG. 2 is a diagram showing a charge pump according to one or more embodiments, for example Figure 1 Block diagram of a charge pump.

[0028] Figure 4 FIG. 2 is a diagram showing a VCO in a phase-locked loop (PLL), such as a VCO in a phase-locked loop (PLL), according to one or more embodiments. Figure 1 A graph of the frequency of a clock signal generated by a VCO over time;

[0029] Figure 5is a set of graphs according to one or more embodiments, the set of graphs including graphs showing that a lock detector, such as Figure 1 and 2 A first graph of the voltage of the lock signal generated by the lock detector over time and Figure 4 The clock signal and the fast start oscillator, such as Figure 1 a second graph of the frequency of a fast-start clock signal generated by a fast-start oscillator over time; and

[0030] Figure 6 is a process flow of a method according to one or more embodiments, an oscillator circuit system, e.g. Figure 1 The oscillator circuit system can selectively output one of the fast start oscillator clock signal and the VCO clock signal based on whether a stable phase lock is detected between these clock signals by the method. DETAILED DESCRIPTION

[0031] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. In addition, it is not intended to be bound by any explicit or implicit theory present in the foregoing technical field, background technology or the following detailed description.

[0032] For simplicity and clarity of illustration, the drawings illustrate general constructions, and descriptions and details of well-known features and techniques may be omitted for brevity. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements or regions in the drawings may be enlarged relative to other elements or regions to help improve understanding of the embodiments described herein.

[0033] The terms "first", "second", "third", "fourth", etc. (if any) in the embodiments and claims can be used to distinguish similar elements, and are not necessarily used to describe a specific sequence or time order. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments described herein can, for example, operate in a sequence different from that shown or otherwise described herein. In addition, the terms "including", "having" and any variations thereof are intended to cover non-exclusive inclusions, so that the process, method, object or device including a series of elements is not necessarily limited to those elements, but may include other elements that are not explicitly listed or inherent to such processes, methods, objects or devices. The term "coupled" as used herein is defined as being connected directly or indirectly in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean sufficient to achieve the stated purpose in a practical manner, and minor defects (if any) are not significant for the stated purpose. As used herein, the words "exemplary" and "example" mean "serving as an example, instance or illustration". Any embodiment described herein as exemplary or example should not necessarily be interpreted as being preferred or advantageous over other embodiments.

[0034] Unless otherwise stated, directional references such as "top", "bottom", "left", "right", "above", "below", etc. are not intended to require any preferred orientation, but are described for illustrative purposes with reference to the orientation of the corresponding figure or figures.

[0035] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference only and are therefore not intended to be limiting. For example, unless the context clearly indicates otherwise, the terms "first," "second," and other such numerical terms referring to structures do not imply a sequence or order.

[0036] Various embodiments described herein relate to an oscillator circuit system, the oscillator circuit system including a fast start oscillator included in a phase-locked loop (PLL) and a voltage controlled oscillator (VCO) included in both the PLL and the frequency-locked loop (FLL). According to various embodiments, either or both of the fast start oscillator and the VCO may be relaxation oscillators. The oscillator circuit system is configured to output an oscillation signal (e.g., a clock signal) generated by the fast start oscillator when the oscillator circuit system is turned on (i.e., when the oscillator circuit system is "started"), and then once it is determined that the oscillation of the PLL has stabilized, the output is switched to another oscillation signal (e.g., a clock signal) generated by the VCO, in response to which the phase-locked loop is deactivated. The VCO may be a frequency regulating oscillator, at least because it may be included in the FLL. In one or more embodiments, the stability of the VCO is determined by the oscillation circuit system in response to the detection of a stable phase lock between the clock signal of the VCO and the fast start oscillator.

[0037] In one or more embodiments, a lock detector may be included in the oscillator circuitry, wherein the lock detector is configured to detect a stable phase lock between a clock signal of the VCO and a fast start oscillator based at least in part on an output of a phase frequency detector (PFD). The PFD may receive and monitor the fast start clock signal and the VCO clock signal, and generate PFD output signals (PFD_UP and PFD_DOWN) in response to detected edges of these clock signals (e.g., rising edges or falling edges according to various embodiments). In one or more embodiments, once the detected edges of the two signals are close enough (e.g., where the detected edges of the two clock signals occur within approximately 4ns of each other), in time, the logic circuitry in the lock detector may deem them to be "in phase" or "phase locked".

[0038] In one or more embodiments, to avoid false positives when attempting to detect a phase lock between the fast start clock signal and the VCO clock signal, the lock detector circuit system may include a counter circuit that is clocked by the fast start clock signal CLK_FAST of the fast start oscillator and is configured to increment its count when the PFD output signal indicates a detected phase lock between the fast start clock signal and the VCO clock signal. Otherwise, the counter is reset. When the counter runs uninterruptedly for a sufficiently long period of time (indicating that the monitored clock signal remains in phase during the period so that the phase lock can be considered "stable"), the counter reaches or exceeds a predetermined count value (causing the counter to overflow in some cases), causing the counter to assert a counter output signal. The lock detector may assert a lock signal LCK (e.g., set high) in response to the assertion of the counter output signal. In one or more embodiments, when the counter asserts the counter output signal, the lock detector may be configured to delay the assertion of the lock signal LCK until a rising or falling edge of the VCO clock signal CLK_VCO is detected. Herein, a signal is referred to as "high" when it is at a high logic level, which may correspond to a signal voltage at or near 1.5V (e.g., within a tolerance of, for example, + / - 10%), and the signal is referred to as "low" when it is at a low logic level, which may correspond to a signal voltage at or near 0V (e.g., within a tolerance of, for example, + / - 0.1V).

[0039] When a stable phase lock is detected, the lock detector provides an asserted lock signal LCK to the control input of the multiplexer and one or more of the fast start oscillator, PFD, charge pump, and logic circuit system of the lock detector. When asserted (indicating a stable phase lock and effectively indicating that the oscillation of the VCO is stable), the lock signal LCK disables the fast start oscillator, PFD, charge pump, and lock detector to reduce or eliminate the power consumption of these components during the subsequent operation of the oscillator circuit system. When asserted, the lock signal LCK further causes the multiplexer 118 to switch its output (which is also the output of the oscillator circuit system) from the fast start clock signal CLK_FAST to the VCO clock signal CLK_VCO. In this article, the assertion of a signal can refer to changing the voltage level of the signal from one logic level to another logic level (e.g., from low to high).

[0040] Figure 1An oscillator circuit system 100 is shown, which is configured to accommodate the relatively slow startup time of a frequency regulating voltage controlled oscillator (VCO) by initially setting the clock signal of a fast start oscillator to its output, and then switching its output to the clock signal generated by the VCO once the VCO clock signal has time to stabilize (e.g., in response to detecting a stable phase lock between the VCO's clock signal and the fast start oscillator). As shown, the oscillator circuit system 100 may include a fast start oscillator 102, a phase frequency detector 104, a charge pump 106, a lock detector 108, a voltage controlled oscillator (VCO) 110, a frequency to voltage (FV) circuit 112, an operational amplifier 114, a compensation capacitor 116, and a multiplexer 118. The oscillator circuit system 100 can be configured to provide an output signal OUT, which is initially set to the clock signal CLK_FAST generated by the fast start oscillator when the oscillator circuit system is started. Once it is determined that the oscillation of the VCO 110 has stabilized (e.g., reached a steady state), the output signal OUT is later switched to the clock signal CLK_VCO generated by the VCO 110. In one or more embodiments, the oscillation stability of the VCO 110 may be determined by the lock detector 108 based on whether the clock signals CLK_VCO and CLK_FAST are consistently in phase for a predetermined length of time (i.e., an example of “stable phase lock”).

[0041] The fast start oscillator 102 may be a relaxation oscillator having at least moderate accuracy and a startup time that is faster than the startup time of the VCO 110. As used herein, a "relaxation oscillator" generally refers to any nonlinear electronic oscillator circuit configured to generate a repetitive non-sinusoidal output signal, such as a repetitive sequence of a square wave, a triangle wave, or other non-sinusoidal signal. As used herein, the "start-up time" of an oscillator refers to the amount of time required for the oscillator to reach a stable, non-transient state from initial activation. As used herein, an oscillator having "moderate accuracy" may generate an oscillating signal in a stable state at a frequency that remains within at least + / -25% of a target frequency. In one or more embodiments, the target frequency may be in the range of 16 MHz to about 24 MHz. The fast start oscillator 102 is configured to generate a fast start clock signal CLK_FAST, which the fast start oscillator 102 provides to the inputs of the PFD 104 and the multiplexer 118.

[0042] When operating as part of FLL 120, VCO 110 can have high accuracy and a slower startup time than fast start oscillator 102. In this context, an oscillator with "high accuracy" can generate an oscillation signal at a frequency within at least + / -3% of a target frequency in a stable state. VCO 110 is configured to generate a VCO clock signal CLK_VCO, which VCO 110 provides to the inputs of PFD 104, FV circuit 112, and multiplexer 118.

[0043] In one or more embodiments, the fast start oscillator 102 can have a startup time between about 1 ns and about 50 ns (e.g., a startup time of about one clock cycle of the target frequency of the fast start oscillator 102), and the FLL 120 can have a startup time between about 5 μs and about 100 μs. In this document, unless otherwise stated, a value is considered to be "about" or "approximately" equal to another value if the value is within + / -50% of the other value.

[0044] The fast start oscillator 102, the PFD 104, the charge pump 106, the compensation capacitor 116, and the VCO 110 may be arranged to form a phase locked loop (PLL) 130. In the PLL 130, the fast start clock CLK_FAST generated by the fast start oscillator 102 may serve as a reference to which the PFD 104 compares the VCO clock signal CLK_VCO. For example, the PFD 104 may receive clock signals CLK_FAST and CLK_VCO from the fast start oscillator 102 and the VCO 110, respectively. The PFD 104 is configured to detect edges (e.g., rising edges or falling edges) of the clock signals CLK_FAST and CLK_VCO, and in response generate PFD signals PFD_UP and PFD_DOWN. As a non-limiting example, the PFD 104 may be configured to set the PFD signal PFD_DOWN high in response to detecting a rising edge or leading edge of the clock signal CLK_VCO, set the PFD signal PFD_UP high in response to detecting a rising edge or leading edge of the clock signal CLK_FAST, and reset both PFDs low in response to determining that the PFD signals PFD_UP and PFD_DOWN are high. The PFD 104 may provide the PFD signals PFD_UP and PFD_DOWN to the inputs of the charge pump 106 and the lock detector 108.

[0045] In one or more embodiments, the PLL 130 can be configured to operate in one of three states based on the corresponding logic levels of the PFD signals PFD_UP and PFD_DOWN received from the PFD 104. In a first state where PFD_UP is low and PFD_DOWN is high, the charge pump 106 is configured to provide a current having a first polarity (e.g., negative) at its output, thereby modifying (e.g., reducing) the voltage amplitude of the control signal CONTROL provided to the bottom input of the VCO 110. In a second state where PFD_UP is high and PFD_DOWN is low, the charge pump 106 is configured to provide a current having a second polarity (e.g., positive) at its output, thereby modifying (e.g., increasing) the voltage amplitude of the control signal CONTROL. In a third state where PFD_UP is low and PFD_DOWN is low, the charge pump 106 is configured to output little or no current, so that the charge pump 106 does not significantly modify the voltage amplitude of the control signal CONTROL. In response to detecting that both signals PFD_UP and PFD_DOWN are high, PFD 104 triggers a reset, thereby resetting both PFD_UP and PFD_DOWN to low and returning charge pump 106 to the third state. In one or more embodiments, VCO 110 may be configured such that an increase in the voltage of control signal CONTROL causes an increase in the frequency of CLK_VCO, and a decrease in the voltage of control signal CONTROL causes a decrease in the frequency of CLK_VCO.

[0046] Continuing with the example, if PFD 104 detects an edge (e.g., falling or rising) of clock signal CLK_FAST before an edge of clock signal CLK_VCO (i.e., CLK_VCO lags CLK_FAST), PFD 104 sets PFD_UP high while PFD_DOWN is low during a time period between detection of the CLK_FAST edge and detection of the corresponding CLK_VCO edge, thereby causing charge pump 106 to modify control signal CONTROL (at least in part by charging or discharging compensation capacitor 116) to cause VCO 110 to increase the frequency of clock signal CLK_VCO. Conversely, if PFD 104 detects an edge (e.g., falling or rising) of clock signal CLK_VCO before an edge of clock signal CLK_FAST (i.e., CLK_FAST lags CLK_VCO), PFD 104 sets PFD_DOWN high while PFD_UP is low during a time period between detection of the CLK_VCO edge and detection of the corresponding CLK_FAST edge, thereby causing charge pump 106 to modify control signal CONTROL (at least in part by charging or discharging compensation capacitor 116) to cause VCO 110 to reduce the frequency of clock signal CLK_VCO. Once clock signals CLK_FAST and CLK_VCO are aligned with respect to both phase and frequency, the detected edges of these signals are substantially aligned, such that PFD 104 always sets PFD_UP high and PFD_DOWN high at or near the same time, such that charge pump 106 does not modify control signal CONTROL, thereby indicating that phase lock between clock signals CLK_FAST and CLK_VCO has been achieved. It should be appreciated that this example is intended to be illustrative and not limiting. In one or more other embodiments, other suitable phase detection (eg, using an XOR phase detector) techniques may be used as a basis for adjusting the control signal CONTROL based on a phase comparison between the clock signals CLK_VCO and CLK_FAST.

[0047] The lock detector 108 may be configured to determine whether a stable phase lock has been achieved between the clock signals CLK_VCO and CLK_FAST by monitoring the PFD output signals PFD_UP and PFD_DOWN. The lock detector 108 may be configured to generate a lock signal LCK, which is configured to assert (e.g., set high) in response to detecting a stable phase lock between the clock signals CLK_VCO and CLK_FAST. In one or more embodiments, the lock detector 108 may be configured to output the lock signal LCK to the control inputs of the fast start oscillator 102, the PFD 104, the charge pump 106, and the multiplexer 118. The assertion of the lock signal LCK by the lock detector 108 may disable the fast start oscillator 102, the PFD 104, the charge pump 106, the lock detector 108 (effectively disabling the PLL 130), either by shutting down these components or by removing inputs from these components that would otherwise cause the components to consume power. Assertion of lock signal CLK by lock detector 108 may further cause multiplexer 118 to switch the output signal output from clock signal CLK_FAST to clock signal CLK_VCO, wherein clock signal CLK_VCO, once stabilized, may have better precision and accuracy than clock signal CLK_FAST.

[0048] Figure 2 2 shows an example embodiment of lock detector 108, where lock detector 108 uses a counter-based approach to detect stable phase lock. For example, lock detector 108 may include logic circuitry 202 and counter circuitry 204. Logic circuitry 202 may receive PFD output signals PFD_UP and PFD_DOWN (e.g., from Figure 1 104 of the counter circuit system 204). The logic circuit system may generate a reset signal RES, and the logic circuit system 202 may provide the reset signal RES to the reset input of the counter circuit system 204. For example, when the reset signal RES is high, the counter circuit system 204 may be reset. In one or more embodiments, the logic circuit system 202 includes at least an OR logic gate that receives the PFD_UP and PFD_DOWN signals, and the generation of the reset signal RES depends on the output of this OR logic gate.

[0049] In one or more embodiments, the logic circuit system 202 is configured to assert the reset signal RES (e.g., set high) when one of the signals PFD_UP and PFD_DOWN is high and the other signal is low for a sufficiently long period of time (e.g., longer than about 1 ns or about 5 ns, according to various embodiments). As the difference between the phase and frequency of the clock signals CLK_VCO and CLK_FAST decreases, the period during which one of the signals PFD_UP and PFD_DOWN is high and the other is low becomes shorter and shorter, eventually causing the logic circuit system 202 to stop asserting the reset signal RES (e.g., when the phase difference is less than about 5 ns), at which time the counter circuit system can be allowed to operate (i.e., count) without resetting. The counter circuit system 204 can increment or decrement its count at each cycle of the clock signal CLK_FAST (according to various embodiments) when not reset until the counter circuit system reaches a predetermined count value. In response to the counter reaching the predetermined count value, the counter circuit system 204 can assert the counter output signal. The counter circuit system 204 may assert the lock signal LCK in response to the assertion of the counter output signal. In one or more embodiments, the counter circuit system 204 may delay asserting the lock signal LCK after asserting the counter output signal until the clock signal CLK_VCO is high at the same time as the counter output signal. As a non-limiting example, the counter circuit system 204 may include a 5-bit counter.

[0050] Using counter circuitry 204 to assert lock signal LCK in this manner can increase the likelihood that the detected phase lock between clock signals CLK_VCO and CLK_FAST has stabilized before asserting lock signal LCK (e.g., to switch the output of oscillator circuitry 100 to CLK_VCO and disable the lock signal). Figure 1 PLL 130).

[0051] Return to Figure 1 , the VCO 110, the FV circuit 112, the operational amplifier 114, and the compensation capacitor 116 may be arranged to form a frequency locked loop (FLL) 120. For example, the FV circuit 112 may receive a clock signal CLK_VCO from the VCO 110 and may be configured to generate a frequency dependent voltage based on the clock signal CLK_VCO. The FV circuit 112 may output such a frequency dependent voltage and a separate reference voltage (corresponding to the target frequency of the VCO 110 and the clock signal CLK_VCO) to the inverting and non-inverting inputs of the operational amplifier 114.

[0052] The operational amplifier 114 may receive and compare the frequency-dependent voltage and the reference voltage from the FV circuit 112. In one or more embodiments, the operational amplifier 114 may be an operational transconductance amplifier. The operational amplifier 114 may generate an output signal based on the result of this comparison, wherein the current of the output signal depends on the voltage level difference between the frequency-dependent voltage and the reference voltage. In one or more embodiments, the value of the frequency-dependent voltage may have an inverse relationship with the frequency of the clock signal CLK_VCO, such a high frequency of CLK_VCO produces a lower frequency-dependent voltage, and vice versa. For example, the operational amplifier 114 may generate an output signal having a current, which modifies the voltage of the control signal CONTROL so that the VCO 110 increases the frequency of the clock signal CLK_VCO in response to the frequency-dependent voltage being greater than the reference voltage. The operational amplifier 114 may generate an output signal having a current, which modifies the voltage of the control signal CONTROL so that the VCO 110 decreases the frequency of the clock signal CLK_VCO in response to the frequency-dependent voltage being less than the reference voltage. In response to the frequency-dependent voltage being at or near the same value as the reference voltage, operational amplifier 114 may make insignificant or no modifications to control signal CONTROL.

[0053] In one or more embodiments, switch 113 may be coupled between the outputs of FV circuit 112. Switch 113 may be coupled to the output of FV circuit 112 by an inverted lock signal (i.e., an inverted version of the lock signal LCK output by the lock detector 108) is controlled so that when the lock signal LCK is not asserted, the switch 113 shorts the output paths of the FV circuit 112 together. Shorting the output paths of the FV circuit 112 together before a stable phase lock is detected in this manner can prevent minor non-idealities (e.g., offset voltage effects) in the operational amplifier 114 from significantly affecting the control signal CONTROL while the PLL 130 still attempts to achieve a stable phase lock between the clock signals CLK_VCO and CLK_FAST. In addition, this arrangement ensures that the FLL 120 is pre-biased similar to a target operating bias level (i.e., where once CLK_VCO is stable at or near its target frequency, the voltage output by the FV circuit 112 based on the clock signal CLK_VCO is similar in magnitude to the reference voltage output by the FV circuit). It should be understood that this arrangement is intended to be illustrative rather than limiting, and other techniques may alternatively be used to mitigate interference between the outputs of the operational amplifier 114 and the charge pump 106 before the lock signal LCK is asserted.

[0054] The compensation capacitor 116 may have a first terminal coupled to a node disposed between the input of the VCO 110 and the output of the operational amplifier 14 and the charge pump 106, and may have a second terminal coupled to a ground or reference node. That is, the first terminal of the compensation capacitor may be connected to each of the charge pump 106, the VCO 110, and the operational amplifier 114. The capacitance of the compensation capacitor 116 may be set to a value that ensures stable slewing of the VCO 110.

[0055] In one or more embodiments, compensation capacitor 116 may provide compensation for each of FLL 120 and PLL 130. In this manner, a smooth phase coherent crossover is ensured when switching the output of oscillator circuitry 100 from fast start clock signal CLK_FAST to VCO clock signal CLK_VCO because the state (voltage) stored on compensation capacitor 116 represents the control voltage level required to make the VCO output frequency equal to the PLL reference (e.g., equal to the frequency of clock signal CLK_FAST) when PLL lock is achieved.

[0056] In one or more other embodiments, compensation capacitor 116 may instead provide compensation only for FLL 120 , and charge pump 106 may include a separate compensation capacitor configured to provide compensation for PLL 130 . Figure 3 An example of this arrangement is shown in which the charge pump 106 includes a compensation capacitor 312 that provides compensation for the PLL 130 (separate from the compensation capacitor 116). Figure 1 Components of the oscillator circuit system 100 are described Figure 3 Example.

[0057] As shown, the charge pump 106 receives PFD signals PFD_UP and PFD_DOWN from the PFD 104, which selectively control switches 304 and 306, respectively, to selectively and independently couple current sources 302 and 308 to a node 305. The node 305 is coupled to the output of the charge pump 106 via a voltage buffer 310. A compensation capacitor 312 is coupled between the node 305 and a ground or reference node. The compensation capacitor 312 can store the state (voltage) of the PLL 130, which can set the control voltage CONTROL provided to the input of the VCO 110 via the voltage buffer 310. The arrangement of the voltage buffer 310 can ensure that the voltage stored at the compensation capacitor 312 exceeds the output of the operational amplifier 114, which can advantageously reduce interference from the FFL 120, which otherwise may prevent the PLL 130 from achieving a stable phase lock.

[0058] Return to Figure 1 , the multiplexer 118 may include: a control input CTRL coupled to receive a lock signal LCK from the lock detector 108; a first selectable signal input IN1 coupled to receive a fast start clock signal CLK_FAST from the fast start oscillator 102; a second selectable signal input IN2 coupled to receive a VCO clock signal CLK_VCO from the VCO 110; and an output. The multiplexer 118 is configured to select one of the clock signals CLK_FAST and CLK_VCO based on the value of the lock signal LCK to output as the output signal OUT. For example, when the lock signal LCK is asserted (e.g., set to high), the multiplexer 118 may be configured to output the VCO clock signal CLK_VCO as the output signal OUT. When the lock signal LCK is deasserted (i.e., set to low), the multiplexer 118 may be configured to output the fast start clock signal CLK_FAST as the output signal OUT.

[0059] Figure 4 A diagram 400 is shown, which shows a diagram showing that Figure 1 402 of an example embodiment of a VCO clock signal CLK_VCO generated by the VCO 110. For ease of illustration, reference is made to Figure 1 Components of the oscillator circuit system 100 are described in detail in diagram 400 .

[0060] In this example, the clock signal CLK_VCO represented by curve 402 may have a target frequency of about 16 MHz. However, at startup, the frequency of the clock signal is not at this target frequency and is considered inaccurate. As shown in curve 402, the clock signal CLK_VCO eventually stabilizes to a frequency of about 16 MHz after about 7 μs. In various applications, including some DC-DC converter applications, a startup delay of 7 μs is considered unacceptable. Therefore, if configured to generate the clock signal CLK_VCO represented by curve 402, the VCO 110 will be unsuitable for use in such applications when provided alone (e.g., without the fast startup oscillator 102 and associated circuitry). However, the oscillator circuitry 100 compensates for the delayed stabilization of the VCO clock signal CLK_VCO by utilizing a less accurate but more quickly stabilized fast startup clock signal CLK_FAST generated by the fast startup oscillator 102 when the oscillator circuitry is started, until it is determined (e.g., by the lock detector 108) that the VCO clock signal CLK_VCO has stabilized.

[0061] Figure 5Graphs 500 and 510 are shown, wherein graph 500 shows a graph representing the Figure 1 5. A graph 502 of an example embodiment of a lock signal LCK generated by the lock detector 108 of FIG. 1 and a graph 510 showing an example embodiment of a VCO clock signal CLK_VCO overlapped with the graph 504. Figure 4 The curve 402, the curve 504 represents the Figure 1 For ease of illustration, refer to Figure 1 Components of the oscillator circuit system 100 are depicted in diagrams 500 and 510. In this example, diagrams 500 and 510 show the same time period and use the same time scale.

[0062] In the present example, the oscillator circuit system 100 can output the fast start clock signal CLK_FAST from 0 μs to about 10.5 μs. At about 10.5 μs, the lock signal LCK is asserted by the lock detector 108 (e.g., in response to the counter output signal being asserted by the counter of the lock detector 108, indicating a stable phase lock between the clock signals CLK_FAST and CLK_VCO), so that the curve 502 rises from a false logic level (e.g., about 0V in one or more embodiments) to a true logic level (e.g., about 1.5V in one or more embodiments). The assertion of the lock signal LCK causes the multiplexer 118 to change the output signal OUT of the oscillator circuit system from the fast start clock signal CLK_FAST to the VCO clock signal CLK_VCO. The assertion of the lock signal LCK additionally disables the fast start oscillator 102 (and other components such as the PFD 104, the charge pump 106, and the lock detector 108), causing the fast start clock signal CLK_FAST, shown by the curve 504, to be switched off at approximately 10.5 μs. In one or more embodiments, the lock signal LCK may be kept high (e.g., using a D flip-flop as a non-limiting example) as long as the oscillator circuitry 100 remains turned on after the initial assertion of the lock signal LCK.

[0063] Figure 6 An illustrative process flow of method 600 is shown by which oscillator circuitry can dynamically switch from outputting a first clock signal generated by a fast start-up oscillator to outputting a second clock signal generated by a relaxation oscillator in response to detecting a stable phase lock between a first frequency signal and a second frequency signal. Figure 1 The method 600 is described with reference to the elements of the oscillator circuit system 100. It should be understood that reference to the oscillator circuit system 100 is intended to be illustrative rather than limiting, such that other suitable oscillator circuit systems may be used to perform the method 600 in one or more other embodiments.

[0064] At block 602, the oscillator circuit system 100 is activated (e.g., by asserting one or more enable signals provided to elements of the oscillator circuit system 100, as a non-limiting example, by a computer processor coupled thereto) such that at least the fast start oscillator 102 and the VCO 110 are turned on. When turned on, the fast start oscillator 102 may generate a fast start clock signal CLK_FAST and the VCO 110 may generate a VCO clock signal CLK_VCO.

[0065] At block 604, the oscillator circuit system 100 may select the fast start clock signal output by the fast start oscillator 102 (e.g., as the output signal OUT) to be output by the oscillator circuit system 100 via the multiplexer 118. For example, the oscillator circuit system 100 may select the fast start clock signal CLK_FAST as the output of the multiplexer 118 based on the voltage level of the lock signal LCK output by the lock detector 108 being low, indicating that a stable phase lock has not been detected between the fast start clock signal CLK_FAST and the VCO clock signal CLK_VCO. In one or more embodiments, the lock detector 108 may be at least partially detected by the lock detector 108 using the logic circuit system of the lock detector 108 (e.g., Figure 2 Logic circuit system 202) and counter circuit system (e.g., Figure 2 The counter circuit system 204 of the PFD 104 performs detection of a stable phase lock between CLK_FAST and CLK_VCO based on the PFD signals PFD_UP and PFD_DOWN generated by the PFD 104, as described above. In one or more embodiments, selecting the output of the multiplexer 118 at block 604 can be performed simultaneously with block 602.

[0066] At block 606, the PFD 104 monitors the phase and frequency of the clock signals CLK_VCO and CLK_FAST by detecting an edge (e.g., a leading edge or a trailing edge) of these clock signals and asserting a corresponding one of the PFD signals PFD_DOWN and PFD_UP in response to detecting the edge of the respective clock signal. The PFD 104 may be configured to reset the PFD signals PFD_UP and PFD_DOWN to low in response to detecting that both of these signals are high. In this manner, as the phase and frequency of the clock signals CLK_VCO and CLK_FAST become increasingly aligned, the length of the continuous period of time that either of the signals PFD_UP or PFD_DOWN remains asserted decreases.

[0067] At block 608, lock detector 108 determines whether a stable phase lock between clock signals CLK_FAST and CLK_VCO is detected. In one or more embodiments, lock detector 108 determines whether a stable phase lock has occurred based at least in part on PFD signals PFD_UP and PFD_DOWN. In one or more embodiments, lock detector 108 may detect whether a stable phase lock has occurred using logic circuitry (e.g., Figure 2 Logic circuit system 202) and counter circuit system (e.g., Figure 2 The counter circuit system 204 of the PFD 104 achieves stable phase lock, as described above. If the lock detector 108 detects a stable phase lock, the lock detector asserts the lock signal LCK and the method 600 proceeds to block 610. Otherwise, the method 600 returns to block 606, where the PFD 104 continues to monitor the phase and frequency of the clock signals CLK_FAST and CLK_VCO.

[0068] At block 610, the lock detector 108 provides the asserted lock signal LCK to the control input of the multiplexer 118, causing the multiplexer 118 to select the VCO clock signal CLK_VCO as the output signal OUT. In this way, the output signal OUT of the oscillator circuit system 100 is the clock signal CLK_FAST before the VCO 110 is stabilized, and once the oscillation of CLK_VCO has had enough time to stabilize (e.g., as determined by the lock detector 108 based on whether a stable phase lock has been detected between CLK_FAST and CLK_VCO), the output signal OUT is changed to the VCO clock signal CLK_VCO.

[0069] At block 612, the lock detector 108 disables the fast start oscillator 102, the PFD 104, the charge pump 106, and / or the lock detector 108. For example, the lock detector 108 may output a lock signal LCK (e.g., set high) to one or more of the logic circuitry of the fast start oscillator 102, the PFD 104, the charge pump 106, and the lock detector 108. The lock signal LCK, when high, may disable any or each of the fast start oscillator 102, the PFD 104, the charge pump 106, and the lock detector 108 by preventing power or input signals from being supplied to these components. For example, the lock signal LCK, when high, may keep the counter circuitry of the lock detector 108 in a reset state. As another example, the asserted lock signal LCK may form an open circuit at the output of the charge pump 106. By disabling one or more of the fast start oscillator 102, the PFD 104, the charge pump 106, and the lock detector 108, current consumption of the disabled components may be reduced or eliminated. In this way, the oscillator circuit system 100 may reduce its overall power consumption after the oscillation of the VCO clock signal CLK_VCO has stabilized.

[0070] In one or more embodiments, selecting the VCO clock signal CLK_VCO at block 610 to be output via the multiplexer 118 and disabling the fast start oscillator 102 , PFD 104 , charge pump 106 , and lock detector 108 at block 612 (eg, in response to assertion of lock signal LCK) may be performed simultaneously.

[0071] The above description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly joined to another element (or directly communicates with another element), and not necessarily mechanically joined. Similarly, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly joined to another element (or directly or indirectly communicates with another element), and not necessarily mechanically joined. Therefore, although the schematic diagrams shown in the figures depict an exemplary arrangement of elements, additional intermediary elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter.

[0072] Although the operation of the method herein is shown and described in a particular order, the order of operation of each method can be changed so that some operations can be performed in reverse order, or so that some operations can be performed at least partially simultaneously with other operations. In another embodiment, instructions or sub-operations of different operations can be implemented in a discontinuous and / or alternating manner.

[0073] It should also be noted that at least some of the operations of the methods described herein can be implemented using software instructions stored on a computer-usable storage medium for computer execution. As an example, an embodiment of a computer program product includes a computer-usable storage medium for storing a computer-readable program. A computer-usable or computer-readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or device or apparatus). Examples of non-temporary computer-usable storage media and computer-readable storage media include semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and optical disk. Current examples of optical disks include high-density disks with read-only memory (CD-ROM), high-density disks with read / write (CD-R / W), and digital video disks (DVD).

[0074] Alternatively, the embodiments described herein may be implemented entirely in hardware or in an implementation scheme containing both hardware elements and software elements. In an embodiment using software, the software may include but is not limited to firmware, resident software, microcode, etc.

[0075] Although at least one exemplary embodiment has been presented in the above detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the above detailed description will provide a convenient guide for implementing the one or more embodiments described to those skilled in the art. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, and the scope defined by the claims includes known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. An oscillator circuit system, characterized in that: include: a first oscillator configured to generate a first clock signal; a second oscillator configured to generate a second clock signal; as well as A lock detector, the lock detector being configured to: detecting a stable phase lock between the first clock signal and the second clock signal; as well as The output of the oscillator circuitry is switched from the first clock signal to the second clock signal in response to detecting the stable phase lock.

2. The oscillator circuit system according to claim 1, characterized in that Also includes: A phase-locked loop (PLL), comprising: the first oscillator; the second oscillator; A phase frequency detector configured to: receiving the first clock signal and the second clock signal; detecting edges of the first clock signal and the second clock signal; asserting a first signal in response to detecting an edge of the first clock signal; asserting a second signal in response to detecting an edge of the second clock signal; and resetting the first signal and the second signal in response to determining that the first signal and the second signal are simultaneously asserted; and A charge pump is configured to modify a control signal received by the second oscillator based on the first signal and the second signal.

3. The oscillator circuit system according to claim 2, characterized in that: Also includes: A frequency-locked loop, the frequency-locked loop comprising: the second oscillator; A frequency-to-voltage circuit, the frequency-to-voltage circuit being configured to: receiving the second clock signal; and generating a voltage based on a frequency of the second clock signal; and An operational amplifier, the operational amplifier being configured to: receiving the voltage and a reference voltage from the frequency-to-voltage circuit; comparing the voltage to the reference voltage; and The control signal is modified based on a result of comparing the voltage to the reference voltage.

4. The oscillator circuit system according to claim 3, characterized in that: The lock detector is configured to assert a lock signal in response to detecting the stable phase lock.

5. The oscillator circuit system according to claim 4, characterized in that: In response to the lock signal being deasserted, the first output of the frequency-to-voltage circuit is shorted to the second output of the frequency-to-voltage circuit.

6. The oscillator circuit system according to claim 4, characterized in that: Also includes: a multiplexer configured to receive the first clock signal, the second clock signal, and the lock signal, wherein the multiplexer is configured to: outputting the first clock signal in response to the lock signal being deasserted; and The second clock signal is output in response to the lock signal being asserted.

7. The oscillator circuit system according to claim 4, characterized in that: The lock detector is configured to: receiving the first signal and the second signal from the phase frequency detector; and The stable phase lock is detected based on the first signal and the second signal.

8. The oscillator circuit system according to claim 7, characterized in that: The lock detector comprises: logic circuitry configured to generate a reset signal based on the first signal and the second signal; and A counter circuit system, the counter circuit system being configured to: incrementing a counter at each cycle of the first clock signal until reset by the reset signal or until the counter reaches a predetermined count value; and The lock signal is asserted in response to the counter reaching the predetermined count value.

9. The oscillator circuit system according to claim 4, characterized in that: Assertion of the lock signal deactivates any one of the first oscillator, the phase frequency detector, the charge pump, and the lock detector.

10. A method of operating an oscillator circuit system, characterized in that, The method comprises: generating a first clock signal by a first oscillator of the oscillator circuit system; generating a second clock signal by a second oscillator of the oscillator circuitry; detecting, by a lock detector, a stable phase lock between the first clock signal and the second clock signal; and The output of the oscillator circuitry is switched from the first clock signal to the second clock signal in response to detecting the stable phase lock.

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