Signal sampling circuit

Abstract

The invention discloses a signal sampling circuit, which generates a power supply voltage and a reference ground of a negative power supply domain through a negative voltage power supply module according to a differential input signal, and then converts an input clock signal into a control signal located in the negative power supply domain through a level conversion module according to the obtained power supply voltage and the reference ground of the negative power supply domain. Therefore, the sampling and gain amplification module can use the control signal of the negative power supply domain to sample the differential input signal in the negative power supply domain, so that the signal sampling circuit provided by the embodiment of the invention can effectively sample in both positive and negative voltage ranges, and the application scene of the signal sampling circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and more specifically, to a signal sampling circuit. Background Art

[0002] Analog-to-Digital Converter (ADC) is a link between the world of analog signals and the world of digital signals. It plays a vital role in various electronic devices and chips. It senses and collects various analog signals in the real world through sensors, and then uses ADC to convert them into digital signals that can be processed by digital circuits, thereby controlling the devices to make various responses. Usually, analog signals are continuous signals in the amplitude domain and time domain. Therefore, in ADC, it is generally necessary to use a signal sampling circuit to sample and amplify the analog signal, and then the ADC converts it into a digital signal. A typical example is a power management chip, where the sampling resistor converts the flowing current into an analog voltage signal, and then the signal sampling circuit samples and amplifies the analog voltage signal, and then provides the amplified analog voltage signal to the ADC to convert it into a digital signal and output it to the DSP for processing. Therefore, the signal sampling circuit plays a vital role in the ADC, and the sampling accuracy of the signal sampling circuit directly determines the highest conversion accuracy of the ADC.

[0003] In the prior art, the signal sampling circuit of the ADC usually relies on positive voltage (e.g., 3V power supply to 0V reference ground) for power supply, which limits the signal range it collects, resulting in it being able to process only positive input voltage signals within the power supply voltage range. This limitation makes it impossible for the signal sampling circuit of the prior art to work effectively when processing negative input voltage signals, resulting in the sampling accuracy and conversion accuracy of the ADC being affected.

[0004] However, in power management chips, ADC needs to process analog voltage signals of various loads, which may include negative input voltage signals. Therefore, it is particularly important to develop a signal sampling circuit that can effectively sample both positive and negative voltage ranges. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide a signal sampling circuit that can effectively sample both positive and negative voltage ranges and can also improve the sampling accuracy and conversion accuracy of an analog-to-digital converter.

[0006] According to one aspect of the present invention, there is provided a signal sampling circuit, comprising: a negative voltage power supply module, for generating a first power supply voltage and a first reference ground in a negative power supply domain according to a differential input signal; a level conversion module, for converting an input clock signal in a positive power supply domain into a first control signal and a second control signal in a negative power supply domain according to the first power supply voltage and the first reference ground; and a sampling and gain amplification module, for sampling and gain amplifying the differential input signal under the control of the first control signal and the second control signal to obtain a differential output signal.

[0007] Optionally, the voltage of the differential input signal is in a positive power domain or a negative power domain.

[0008] Optionally, the negative voltage power supply module includes: a current bias unit for providing a bias current; a mirror copy unit having a first current end for receiving the bias current, and a second current end for providing a copy current of the bias current; a first resistor, a first end of which is connected to the second current end of the mirror copy unit and a second end of which is connected to the first reference ground, for generating the first power supply voltage according to the copy current of the bias current; and a negative voltage reference ground unit, for generating the first reference ground according to the differential input signal.

[0009] Optionally, the negative voltage power supply module further includes: a voltage stabilizing capacitor arranged between the first power supply voltage and the first reference ground; and a reverse diode arranged between the first power supply voltage and the first reference ground.

[0010] Optionally, the current bias unit includes: a current source, a first end of which is connected to a second power supply voltage of a positive power domain; a first transistor, a first end and a control end of which are connected to a second end of the current source, and a second end of which is connected to a second reference ground of the positive power domain; a second transistor, a control end of which is connected to a control end of the first transistor, and a second end of which is connected to the second reference ground, and the first end is used to provide the bias current.

[0011] Optionally, the mirror copy unit includes: a third transistor, a first end of which is connected to the second power supply voltage of the positive power domain, and a second end of which is connected to the bias current as a first current end of the mirror copy unit; and a fourth transistor, a first end of which is connected to the second power supply voltage, a control end of which is connected to the control end of the third transistor, and a second end of which is connected to the second current end of the mirror copy unit to provide the copy current.

[0012] Optionally, the third transistor and the fourth transistor are high-voltage transistors.

[0013] Optionally, the negative voltage reference ground unit includes: a second resistor and a third resistor connected in series between the positive input voltage signal and the negative input voltage signal of the differential input signal, and an intermediate node between the second resistor and the third resistor is used to output the first reference ground.

[0014] Optionally, the level conversion module includes: a fifth transistor, a first end of which is connected to the second power supply voltage of the positive power domain, and a control end of which is connected to the input clock signal; a sixth transistor, a first end of which is connected to the second power supply voltage, and a control end of which is connected to the inverted signal of the input clock signal; a seventh transistor, a first end of which is connected to the second end of the fifth transistor, and a control end of which is connected to the second reference ground of the positive power domain; an eighth transistor, a first end of which is connected to the second end of the sixth transistor, and a control end of which is connected to the second reference ground; a ninth transistor, a first end of which is connected to the second end of the seventh transistor at a first node, a control end of which is connected to the second end of the eighth transistor at a second node, and a second end of which is connected to the first reference ground; a tenth transistor, a first end of which is connected to the second node, a control end of which is connected to the first node, and a second end of which is connected to the first reference ground; a first inverter and a second inverter, which are connected in series between the second node and the output end of the first control signal; and a third inverter and a fourth inverter, which are connected in series between the first node and the output end of the second control signal, wherein the first inverter, the second inverter, the third inverter and the fourth inverter all operate between the first power supply voltage and the first reference ground.

[0015] Optionally, the sampling and gain amplification module includes: an operational amplifier, including a positive input terminal and a negative input terminal, and a positive output terminal and a negative output terminal for providing the differential output signal; a first sampling capacitor, a second end of which is connected to the positive input terminal of the operational amplifier; a second sampling capacitor, a second end of which is connected to the negative input terminal of the operational amplifier; a first sampling switch, used to provide the positive input voltage signal of the differential input signal to the first end of the first sampling capacitor according to the first control signal; a second sampling switch, used to provide the negative input voltage signal of the differential input signal to the first end of the second sampling capacitor according to the first control signal; a first feedback capacitor and a second feedback capacitor, used to be selectively connected to the feedback loop of the operational amplifier according to the first control signal and the second control signal; and a plurality of switching switches, the plurality of switching switches being used to change the connection mode of the first feedback capacitor and the second feedback capacitor according to different phases of the first control signal or the second control signal, so that the sampling and gain amplification module is in different working states.

[0016] Optionally, the first end of the first feedback capacitor is connected to the positive input terminal of the operational amplifier, the first end of the second feedback capacitor is connected to the negative input terminal of the operational amplifier, and the multiple switching switches include: a first switching switch, used to connect the second end of the first feedback capacitor to the common-mode voltage signal according to the first control signal; a second switching switch, used to connect the second end of the first feedback capacitor to the positive output terminal of the operational amplifier according to the second control signal; a third switching switch, used to connect the second end of the second feedback capacitor to the common-mode voltage signal according to the first control signal; and a fourth switching switch, used to connect the second end of the second feedback capacitor to the negative output terminal of the operational amplifier according to the second control signal.

[0017] Optionally, the sampling and gain amplification module also includes: a first short-circuiting switch, used to short-circuit the first ends of the first sampling capacitor and the second sampling capacitor according to the second control signal; a second short-circuiting switch, used to short-circuit the positive input end and the positive output end of the operational amplifier according to the first control signal; and a third short-circuiting switch, used to short-circuit the negative input end and the negative output end of the operational amplifier according to the first control signal.

[0018] Optionally, the sampling and gain amplification module further includes: a calibration switch array, used to provide a calibration voltage signal to the first end of the first sampling capacitor and the second sampling capacitor, respectively, so as to calibrate the offset or gain of the operational amplifier, wherein the calibration switch array is not turned on at the same time as the first sampling switch and the second sampling switch.

[0019] Optionally, the calibration switch array includes: a first calibration switch, used to provide a first calibration voltage to a first end of the first sampling capacitor; a second calibration switch, used to provide a second calibration voltage to the first end of the second sampling capacitor; and a third calibration switch, used to provide at least one third calibration voltage to the first end of the first sampling capacitor, wherein the voltage values ​​of the first calibration voltage and the second calibration voltage are zero, and the voltage value of the at least one third calibration voltage is greater than the second calibration voltage, wherein the calibration switch array is configured to turn on the first calibration switch and the second calibration switch and turn off the third calibration switch in an offset calibration phase, and to turn on the second calibration switch and the third calibration switch and turn off the first calibration switch in a gain calibration phase.

[0020] Optionally, the calibration switch array further includes: a first anti-leakage switch, which is arranged on the signal input path of the first calibration switch; a second anti-leakage switch, which is arranged on the signal input path of the second calibration switch; and at least one third anti-leakage switch, which is arranged on at least one signal input path of the third calibration switch, wherein the first anti-leakage switch, the second anti-leakage switch, and the at least one third anti-leakage switch are turned on and off at the same time as the corresponding calibration switch to reduce leakage of the calibration switch array in a non-calibration stage.

[0021] Optionally, the calibration switch array further includes: a first virtual switch having a second end connected to the first end of the second sampling capacitor; at least one second virtual switch corresponding to the number of the at least one third anti-leakage switch, the first end of the at least one second virtual switch being connected to the second calibration voltage, and the second end of the at least one second virtual switch being connected to the first virtual switch, wherein the first virtual switch is synchronously turned on and off with the third calibration switch, and the at least one second virtual switch is always kept in an off state.

[0022] Optionally, the first sampling switch, the second sampling switch, the first anti-leakage switch, the second anti-leakage switch, the at least one third anti-leakage switch and the at least one second virtual switch are low-voltage transistors, and the first calibration switch, the second calibration switch, the at least one third calibration switch and the first virtual switch are high-voltage transistors.

[0023] Optionally, the first control signal and the second control signal are two-phase non-overlapping clock signals.

[0024] To summarize, the signal sampling circuit proposed in the embodiment of the present invention generates the power supply voltage and reference ground of the negative power supply domain according to the differential input signal through the negative voltage power supply module, and then converts the input clock signal into a control signal located in the negative power supply domain according to the obtained power supply voltage and reference ground of the negative power supply domain through the level conversion module, so that the sampling and gain amplification module can use the control signal of the negative power supply domain to sample the differential input signal located in the negative power supply domain. Therefore, the signal sampling circuit of the embodiment of the present invention can effectively perform sampling within the positive and negative voltage ranges, thereby improving the application scenarios of the signal sampling circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic structural diagram of a signal sampling circuit according to an embodiment of the present invention is shown.

[0027] Figure 2 A schematic circuit diagram of a negative voltage power supply module according to an embodiment of the present invention is shown.

[0028] Figure 3 A schematic circuit diagram of a level conversion module according to an embodiment of the present invention is shown.

[0029] Figure 4 A schematic circuit diagram of a sampling and gain amplification module according to an embodiment of the present invention is shown.

[0030] Figure 5 FIG. 4 shows a schematic circuit diagram of a calibration switch array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0032] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuit, a programmable circuit, a state machine circuit and / or an element that can store instructions executed by a programmable circuit. When an element or circuit is said to be "coupled to" another element or an element / circuit is said to be "coupled between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly coupled to" another element, it means that there is no intermediate element between the two.

[0033] In the description of the present invention, the term "two-phase non-overlapping clock signal" refers to a first clock signal and a second clock signal with the same period, and when the first clock signal is valid, the second clock signal is always invalid, and when the second clock signal is valid, the first clock signal is always invalid. For example, the first phase and the second phase of the first clock signal are respectively the high level phase and the low level phase of the clock signal, and the first phase and the second phase of the second clock signal are respectively the low level phase and the high level phase of the clock signal. The first phase of the first clock signal does not overlap with the second phase of the second clock signal. The rising edge of the second clock signal arrives after the falling edge of the first clock signal, and the rising edge of the second clock signal arrives after the falling edge of the second clock signal.

[0034] In all embodiments of the present invention, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present invention, the controlled middle electrode of the MOS transistor is referred to as the control terminal, and the other two ends of the MOS transistor are referred to as the first terminal and the second terminal, respectively. For the convenience of unified description, in the context, the source, drain and gate of a PMOS transistor are referred to as the first terminal, the second terminal and the control terminal, respectively, and the drain, source and gate of an NMOS transistor are referred to as the first terminal, the second terminal and the control terminal, respectively.

[0035] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0036] Figure 1 FIG. 2 shows a schematic structural diagram of a signal sampling circuit according to an embodiment of the present invention. Figure 1 As shown, the signal sampling circuit 100 of the embodiment of the present invention includes a negative voltage power supply module 110, a level conversion module 120 and a sampling and gain amplification module 130. Among them, the signal sampling circuit 100 is used to sample and gain amplify the differential input signals VIP and VIN at the signal input end, so as to obtain differential output signals OUTP and OUTN, and then convert the obtained differential output signals OUTP and OUTN into digital signals through an analog-to-digital converter (ADC) 200 for processing by a subsequent digital circuit. Furthermore, the differential input signals VIP and VIN of this embodiment can be in a positive power domain (for example, a 3V power supply voltage to a 0V reference ground), or in a negative power domain (for example, a 1.5V power supply voltage to a -1.5V reference ground).

[0037] Furthermore, the negative voltage power supply module 110 is connected to the differential input signals VIN and VIP of the signal sampling circuit 100 , and generates a power supply voltage VDDL and a reference ground VSSL in a negative power domain according to the input differential input signals VIN and VIP.

[0038] The level conversion module 120 is used to convert the input clock signal CLK in the positive power domain into the first control signal PH1 and the second control signal PH2 in the negative power domain according to the power voltage VDDL and the reference ground VSSL.

[0039] The sampling and gain amplification module 130 is used to sample and gain amplify the differential input signals VIP and VIN according to the first control signal PH1 and the second control signal PH2 to obtain differential output signals OUTP and OUTN. For example, the first control signal PH1 and the second control signal PH2 are, for example, "two-phase non-overlapping clock signals". For example, the sampling and gain amplification module 130 can be implemented by a switched capacitor programmable gain amplifier (PGA), and the differential input signals VIP and VIN are sampled through a switched capacitor circuit. Since the first control signal PH1 and the second control signal PH2 are both in the negative power domain, the sampling switch in the switched capacitor circuit can sample the differential input signals VIP and VIN in the negative power domain. Further, the sampling and gain amplification module 130 ignores the common-mode signal in the differential input signals VIP and VIN through the PGA circuit, and only converts the differential mode part of the input signal to the positive power domain, thereby realizing the sampling of the differential input signal in the negative power domain.

[0040] Figure 2 FIG. 1 shows a schematic circuit diagram of a negative voltage power supply module 110 according to an embodiment of the present invention. Figure 2 As shown, the negative voltage power supply module 110 includes a current bias unit 111, a mirror copy unit 112, a resistor R1, a negative voltage reference ground unit 113, a voltage stabilizing capacitor C1 and a reverse diode D1. Among them, the current bias unit 111 is used to generate a bias current Ib1. The mirror copy unit 112 is used to mirror the bias current Ib1 to obtain a copy current Ib2 of the bias current Ib1. The negative voltage reference ground unit 113 is used to generate a negative voltage reference ground VSSL according to the differential input signal VIP and VIN. The resistor R1 is arranged between the output of the mirror copy unit 112 and the negative voltage reference ground VSSL, and the copy current Ib2 flows through the resistor R1 to generate the negative voltage power supply voltage VDDL. The capacitor C1 is, for example, a decoupling capacitor (DecouplingCapacitor), which is used to stabilize the power supply voltage VDDL to prevent the power supply voltage VDDL from being unstable when the instantaneous load changes. The cathode of the reverse diode D1 is connected to the power supply voltage VDDL, and the anode of the reverse diode D1 is connected to the reference ground VSSL. The reverse diode D1 is a protection diode for ensuring that the power supply voltage VDDL does not have an overvoltage condition.

[0041] Further, the current bias unit 111 includes a current source 101, a transistor M1 and a transistor M2. The transistor M1 and the transistor M2 are, for example, NMOS transistors. The first end of the current source 101 is connected to the power supply voltage VDDH of the positive power domain, the second end of the current source 101 is connected to the drain and gate of the transistor M1, the gate of the transistor M2 is connected to the drain and gate of the transistor M1, the drain of the transistor M2 is used to output the bias current Ib1, and the sources of the transistor M1 and the transistor M2 are connected to the reference ground VSSH of the positive power domain.

[0042] Further, the mirror copy unit 112 includes a transistor M3 and a transistor M4. Among them, the transistor M3 and the transistor M4 are, for example, PMOS transistors, the sources of the transistor M3 and the transistor M4 are connected to the power supply voltage VDDH, the gates of the transistor M3 and the transistor M4 are connected to each other, the drain of the transistor M3 serves as the first current end of the mirror copy unit 112 to receive the bias current Ib1, and the drain of the transistor M4 serves as the second current end of the mirror copy unit 112 to provide the copy current Ib2. Further, the transistor M3 and the transistor M4 of this embodiment are implemented by high-voltage transistors. It should be noted that the low-voltage MOS transistor and the high-voltage MOS transistor in this article are generally relative. For example, the transistor can be divided into a high-voltage transistor or a low-voltage transistor according to the Vds (drain-source voltage) withstand voltage capability of the MOS transistor, and the withstand voltage capability of the high-voltage transistor is greater than the withstand voltage capability of the low-voltage transistor.

[0043] Furthermore, the negative voltage reference ground unit 113 can be implemented by a voltage divider circuit, and the reference ground VSSL is generated by providing the differential input signals VIP and VIN to a small voltage divider circuit, so as to ensure that the influence of circuit crosstalk on the differential signal can be the same. For example, the negative voltage reference ground unit 113 includes a resistor R2 and a resistor R3, and the resistor R2 and the resistor R3 are connected in series between the positive input voltage signal VIP and the negative input voltage signal VIN of the differential input signal, and the reference ground VSSL is output at the middle node of the resistor R2 and the resistor R3.

[0044] Figure 3 FIG. 1 shows a schematic circuit diagram of a level conversion module 120 according to an embodiment of the present invention. Figure 3 As shown, the level conversion module 120 of the present invention includes: a pull-up unit composed of transistors M5 to M8, a pull-down unit composed of transistors M9 and M10, and inverters INV1 to INV6.

[0045] Inverter INV1 and inverter INV2 are arranged between the positive power domain VDDH~VSSH. Inverter INV1 is used to obtain an inverted signal of the input clock signal CLK whose level range is between the power supply voltage VDDH and the reference ground VSSH. Inverter INV2 is used to obtain a non-inverted signal of the input clock signal CLK.

[0046] The transistor M5 and the transistor M6 in the pull-up unit are, for example, PMOS transistors, and the transistor M7 and the transistor M8 are, for example, NMOS transistors. The sources of the transistors M5 and M6 are connected to the power supply voltage VDDH, the gate of the transistor M5 is connected to the output of the inverter INV2, the gate of the transistor M6 is connected to the output of the inverter INV1, the drain of the transistor M5 is connected to the drain of the transistor M7, the drain of the transistor M6 is connected to the drain of the transistor M8, the gates of the transistors M7 and M8 are connected to the reference ground VSSH, the source of the transistor M7 is connected to the node P1, and the source of the transistor M8 is connected to the node P2.

[0047] The transistor M9 and the transistor M10 in the pull-down unit are, for example, NMOS transistors, the drain of the transistor M9 and the gate of the transistor M10 are connected to the node P1, the gate of the transistor M9 and the drain of the transistor M10 are connected to the node P2, and the sources of the transistor M9 and the transistor M10 are connected to the reference ground VSSL.

[0048] Inverters INV3 to INV6 are arranged between the negative power domains VDDL~VSSL, inverters INV3 and INV4 are connected in series between node P1 and the output end of the second control signal PH2, and inverters INV5 and INV6 are connected in series between node P2 and the output end of the first control signal PH1.

[0049] In this embodiment, when the input clock signal CLK changes from a low level to a high level, the PMOS transistor M6 is turned on, the PMOS transistor M5 is turned off, and the node P2 is pulled up to VSSH-Vth through the NMOS transistor M8 (the potential of the node P2 cannot be higher, otherwise the NMOS transistor M8 will not be turned on, where Vth is the turn-on threshold of the NMOS transistor), and the potential of the node P2 is flipped to a logic high level after the logic shaping of the inverter INV5 and the inverter INV6, and the potential of the logic high level of the first control signal PH1 is equal to the power supply voltage VDDL of the negative power domain. At the same time, the NMOS transistor M9 is turned on, and the node P1 is pulled down to the reference ground VSSL of the negative power domain, and then after the logic shaping of the inverter INV3 and the inverter INV4, the second control signal PH2 is flipped to a logic low level, and the potential of the logic low level of the second control signal PH2 is equal to the reference ground VSSL of the negative power domain.

[0050] Similarly, when the input clock signal CLK changes from a high level to a low level, the PMOS transistor M5 is turned on, the PMOS transistor M6 is turned off, and the node P1 is pulled up to VSSH-Vth through the NMOS transistor M7 (the potential of the node P1 cannot be higher, otherwise the NMOS transistor M8 will not be turned on), and the potential of the node P1 is flipped to a logic high level after the logic shaping of the inverter INV3 and the inverter INV4, and the potential of the logic high level of the second control signal PH2 is equal to the power supply voltage VDDL. At the same time, the NMOS transistor M10 is turned on, and the potential of the node P2 is pulled down to the reference ground VSSL, and then the potential of the node P2 is flipped to a logic low level after the logic shaping of the inverter INV5 and the inverter INV6, and the potential of the logic low level of the first control signal PH1 is equal to the reference ground VSSL.

[0051] Figure 4 FIG. 4 shows a schematic circuit diagram of a sampling and gain amplification module 130 according to an embodiment of the present invention. Figure 4 As shown, the sampling and gain amplification module 130 includes an operational amplifier 131 , a group of sampling capacitors, a group of feedback capacitors, and a plurality of switches.

[0052] In this embodiment, the operational amplifier 131 includes a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The positive input terminal and the negative input terminal of the operational amplifier 131 are respectively used to receive a positive input voltage signal VIP and a negative input voltage signal VIN of a differential input signal, and the positive output terminal and the negative output terminal are respectively used to provide a positive output voltage signal OUTP and a negative output voltage signal OUTN of a differential output signal.

[0053] In this embodiment, the sampling capacitor includes a sampling capacitor CS1 and a sampling capacitor CS2. The second end of the sampling capacitor CS1 is connected to the positive input end of the operational amplifier 131, and the first end is selectively connected to the positive input voltage signal VIP or the calibration voltage signal. The second end of the sampling capacitor CS2 is connected to the negative input end of the operational amplifier 131, and the first end is selectively connected to the negative input voltage signal VIN or the calibration voltage signal.

[0054] In this embodiment, the feedback capacitor includes a feedback capacitor CF1 and a feedback capacitor CF2. The first end of the feedback capacitor CF1 is connected to the positive input terminal of the operational amplifier 131, and the second end is selectively connected to the common mode voltage signal VCM or the positive output terminal of the operational amplifier 131. The first end of the feedback capacitor CF2 is connected to the negative input terminal of the operational amplifier 131, and the second end is selectively connected to the common mode voltage signal VCM or the negative output terminal of the operational amplifier 131.

[0055] In this embodiment, the plurality of switches include sampling switches S11 and S12 , switching switches S15 to S18 , shorting switches S13 , S19 and S20 , and a calibration switch array 132 .

[0056] The sampling switch S11 is connected between the positive input voltage signal VIP and the first end of the sampling capacitor CS1, and the sampling switch S12 is connected between the negative input voltage signal VIN and the first end of the sampling capacitor CS2. For example, the sampling switches S11 and S12 are implemented by NMOS transistors. For example, the sampling switches S11 and S12 are implemented by low-voltage NMOS transistors.

[0057] The switches S15 to S18 are used to change the connection mode of the feedback capacitors CF1 and CF2 according to different phases of the first control signal PH1 and the second control signal PH2, so that the sampling and gain amplification module is in different working states.

[0058] Specifically, the switching switch S15 is connected between the second end of the feedback capacitor CF1 and the common-mode voltage signal VCM, the switching switch S16 is connected between the second end of the feedback capacitor CF1 and the positive output terminal of the operational amplifier 131, the switching switch S17 is connected between the second end of the feedback capacitor CF2 and the common-mode voltage signal VCM, and the switching switch S18 is connected between the second end of the feedback capacitor CF2 and the negative output terminal of the operational amplifier 131.

[0059] The shorting switch S13 is connected between the first terminals of the sampling capacitors CS1 and CS2, the shorting switch S19 is connected between the positive input terminal and the positive output terminal of the operational amplifier 131, and the shorting switch S20 is connected between the negative input terminal and the negative output terminal of the operational amplifier 131. For example, the shorting switch S13 can be implemented by a PMOS transistor and an NMOS transistor arranged in parallel.

[0060] In this embodiment, the common mode voltage signal VCM is any value between zero and the voltage value of the power supply of the analog-to-digital converter.

[0061] Further, control ends of switches S11, S12, S15, S17, S19 and S20 receive the first control signal PH1, and control ends of switches S13, S16 and S18 are used to receive the second control signal PH2.

[0062] In the first phase of the first control signal PH1, switches S11, S12, S15, S17, S19 and S20 are turned on, and switches S13, S16, S18, S19 and S20 are turned off, and the sampling and gain amplification module 130 operates in the first mode.

[0063] In the second phase of the second control signal PH2, the switches S11, S12, S15, S17, S19 and S20 are turned off, and the switches S13, S16 and S18 are turned on, and the sampling and gain amplification module 130 operates in the second mode.

[0064] In this embodiment, when the sampling and gain amplification module 130 operates in the first mode, the differential input signals VIP and VIN are provided to the first ends of the sampling capacitors CS1 and CS2, respectively, and the second ends of the sampling capacitors CS1 and CS2 are connected to the positive output end and the negative output end of the operational amplifier 131 through the shorting switches S19 and S20, respectively, which is equivalent to grounding the second ends of the sampling capacitors CS1 and CS2. At the same time, the positive input end and the positive output end of the operational amplifier 131 are also shorted together through the shorting switch S19, and the negative input end and the negative output end of the operational amplifier 131 are also shorted together through the shorting switch S20. The second ends of the feedback capacitors CF1 and CF2 are connected to the common mode voltage signal VCM, so that the differential input signals VIP and VIN can be stored on the sampling capacitors CS1 and CS2 in the form of charges.

[0065] When the sampling and gain amplification module 130 operates in the second mode, the first ends of the sampling capacitors CS1 and CS2 are short-circuited together. In the first mode, the charges stored on the sampling capacitors CS1 and CS2 are provided to the positive input terminal and the negative input terminal of the operational amplifier 131, and the feedback capacitors CF1 and CF2 are connected to the feedback loop of the operational amplifier 131. Through the feedback amplification of the operational amplifier 131, the differential output signals OUTP and OUTN are obtained.

[0066] Further, the calibration switch array 132 is used to provide calibration voltage signals to the first ends of the sampling capacitors CS1 and CS2, respectively, to calibrate the offset or gain of the operational amplifier 131. For example, the multiple switches in the calibration switch array 132 and the sampling switches S11 and S12 are not turned on at the same time, that is, at the same time, only one of the calibration switch array 132 and the sampling switches S11 and S12 can be turned on.

[0067] Figure 5 FIG. 1 shows a schematic circuit diagram of a calibration switch array 132 according to an embodiment of the present invention. Figure 5 As shown, the calibration switch array 132 includes a plurality of calibration switches S21 to S23. The calibration switch S21 is used to convert the first calibration voltage (eg, Figure 5 0V in the sample capacitor CS1) is supplied to the first terminal (i.e., Figure 5 The calibration switch S22 is used to switch the second calibration voltage (eg, Figure 5 0V in the sample capacitor CS2) is provided to the first terminal (i.e., Figure 5 The calibration switch S23 is used to switch at least one third calibration voltage (eg, Figure 5 The calibration switch array 132 is configured to turn on the calibration switches S21 and S22 and turn off the calibration switch S23 during the offset calibration phase; and to turn on the calibration switches S22 and S23 and turn off the calibration switch S21 during the gain calibration phase, and then determine the offset voltage or gain error of the circuit according to the conversion result of ADC200, and perform corresponding adjustments on the sampling and gain amplification module 130.

[0068] For example, the calibration switches S21 to S23 may be implemented by NMOS transistors, and the gates of the calibration switches S21 to S23 are used to receive the calibration control signal PH1_cal. For example, the calibration control signal PH1_cal has the same clock cycle and voltage domain as the first control signal PH1 (i.e., the voltage of the calibration control signal PH1_cal is also in the negative power domain), but the calibration control signal PH1_cal and the first control signal PH1 do not appear at the same time. Further, since there may be a negative voltage at the VOP terminal or the VON terminal, the calibration switches S21 to S23 may be implemented by high-voltage NMOS transistors.

[0069] Furthermore, in practical applications, when the positive input voltage signal VIP is a positive voltage, there may be a leakage path in the calibration switches S21 to S23, so the calibration switch array 132 of this embodiment also includes a plurality of anti-leakage switches S31 to S34. Among them, the anti-leakage switch S31 is arranged on the signal input path of the calibration switch S21, the anti-leakage switch S32 is arranged on the signal input path of the calibration switch S22, and the anti-leakage switches S33 and S34 are arranged on the signal input path of the calibration switch S23. Among them, the anti-leakage switches S31 to S34 are turned on and off at the same time as the corresponding calibration switches to reduce the leakage of the calibration switch array 132 in the non-calibration stage. For example, the anti-leakage switches S31 to S34 can be implemented by low-voltage NMOS transistors.

[0070] Further, the control end of the anti-leakage switch S31 is used to receive the first enable control signal EN_cal, and the control end of the anti-leakage switch S32 is used to receive the second enable control signal EN_os_cal, wherein when the sampling and gain amplification module 130 is in the offset calibration stage, the first enable control signal EN_cal and the second enable control signal EN_os_cal are valid to turn on the anti-leakage switches S31 and S32. The control ends of the anti-leakage switches S33 and S34 are used to receive the gain control signals SEL1_cal and SEL2_cal respectively, and when the sampling and gain amplification module 130 is in the gain calibration stage, the first enable control signal EN_cal is firstly enabled, and then the gain control signal SEL1_cal or SEL2_cal is enabled according to the required gain calibration gear, so as to turn on the anti-leakage switch S33 or S34 and the anti-leakage switch S31.

[0071] Furthermore, due to the different numbers of high-voltage switches connected to the VOP terminal and the VON terminal, in actual applications, the crosstalk between the VOP terminal and the VON terminal may be different, which in turn affects the sampling accuracy of the sampling and gain amplification module 130. In order to avoid this problem, the calibration switch array 132 of the present embodiment further includes dummy switches S41 to S43. Among them, one end of the dummy switch S41 is connected to the first end (i.e., the VON end) of the sampling capacitor CS2, the other end of the dummy switch S41 is connected to one end of the dummy switches S42 and S43, and the other ends of the dummy switches S42 and S43 are connected to the second calibration voltage (e.g., Figure 5 0V in the circuit). For example, the virtual switches S41 to S43 can be implemented by NMOS transistors. Further, the virtual switch S41 can be implemented by a high-voltage NMOS transistor, and the virtual switches S42 and S43 can be implemented by low-voltage NMOS transistors. Furthermore, the control end of the virtual switch S41 is used to receive the calibration control signal PH1_cal, and the control ends of the virtual switches S42 and S43 are used to be grounded, so the virtual switches S42 and S43 are always kept in the off state.

[0072] To summarize, the signal sampling circuit proposed in the embodiment of the present invention generates the power supply voltage and reference ground of the negative power supply domain according to the differential input signal through the negative voltage power supply module, and then converts the input clock signal into a control signal located in the negative power supply domain according to the obtained power supply voltage and reference ground of the negative power supply domain through the level conversion module, so that the sampling and gain amplification module can use the control signal of the negative power supply domain to sample the differential input signal located in the negative power supply domain. Therefore, the signal sampling circuit of the embodiment of the present invention can effectively perform sampling within the positive and negative voltage ranges, thereby improving the application scenarios of the signal sampling circuit.

[0073] Furthermore, the sampling and gain amplification module of the embodiment of the present invention is implemented by a switched capacitor PGA, and the offset and gain of the PGA are calibrated by a calibration switch array, which is beneficial to improving the sampling accuracy and conversion accuracy of the circuit and can be applied to ADC front-end amplifier circuits for high-precision detection.

[0074] It will be understood by those skilled in the art that the words "during", "when" and "when..." used in this article in connection with the operation of the circuit are not strict terms indicating an action that occurs immediately when the start-up action begins, but that there may be some small but reasonable delay or delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this article mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (for semiconductor doping concentrations, at least twenty percent (20%)) is a reasonable deviation from the accurate ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0075] In addition, it is also necessary to explain that the relational terms such as first and second, etc. in this article are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0076] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A signal sampling circuit, comprising: A negative voltage power supply module, used for generating a first power supply voltage and a first reference ground of a negative power supply domain according to a differential input signal; a level conversion module, configured to convert an input clock signal in a positive power domain into a first control signal and a second control signal in a negative power domain according to the first power voltage and the first reference ground; as well as The sampling and gain amplification module is used to sample and gain amplify the differential input signal under the control of the first control signal and the second control signal to obtain a differential output signal.

2. The signal sampling circuit according to claim 1, wherein: The voltage of the differential input signal is in a positive power domain or a negative power domain.

3. The signal sampling circuit according to claim 1, wherein: The negative pressure power supply module comprises: A current bias unit, used for providing a bias current; A mirror copy unit having a first current terminal for receiving the bias current and a second current terminal for providing a copy current of the bias current; a first resistor, a first end of which is connected to the second current end of the mirror copy unit, and a second end of which is connected to the first reference ground, and is used to generate the first power supply voltage according to the copy current of the bias current; and A negative voltage reference ground unit is used to generate the first reference ground according to the differential input signal.

4. The signal sampling circuit according to claim 3, wherein: The negative pressure power supply module also includes: A voltage stabilizing capacitor disposed between the first power supply voltage and the first reference ground; and A reverse-connected diode is arranged between the first power supply voltage and the first reference ground.

5. The signal sampling circuit according to claim 3, wherein: The current bias unit comprises: a current source having a first terminal connected to a second power supply voltage of the positive power domain; A first transistor, a first terminal and a control terminal connected to the second terminal of the current source, and a second terminal connected to a second reference ground of the positive power domain; A second transistor has a control end connected to the control end of the first transistor, a second end connected to the second reference ground, and a first end used to provide the bias current.

6. The signal sampling circuit according to claim 3, wherein: The mirror copy unit comprises: A third transistor, a first terminal of which is connected to the second power supply voltage of the positive power domain, and a second terminal of which is connected to the bias current as a first current terminal of the mirror copy unit; and A fourth transistor has a first terminal connected to the second power supply voltage, a control terminal connected to the control terminal of the third transistor, and a second terminal serving as a second current terminal of the mirror copy unit to provide the copy current.

7. The signal sampling circuit according to claim 6, wherein: The third transistor and the fourth transistor are high voltage transistors.

8. The signal sampling circuit according to claim 3, wherein: The negative pressure reference ground unit comprises: A second resistor and a third resistor are connected in series between the positive input voltage signal and the negative input voltage signal of the differential input signal, and an intermediate node between the second resistor and the third resistor is used to output the first reference ground.

9. The signal sampling circuit according to claim 1, wherein: The level conversion module comprises: a fifth transistor, a first terminal connected to the second power supply voltage of the positive power domain, and a control terminal connected to the input clock signal; a sixth transistor, a first terminal connected to the second power supply voltage, and a control terminal connected to an inverted signal of the input clock signal; a seventh transistor, a first terminal connected to the second terminal of the fifth transistor, and a control terminal connected to the second reference ground of the positive power domain; an eighth transistor, a first terminal connected to the second terminal of the sixth transistor, and a control terminal connected to the second reference ground; a ninth transistor, a first end of which is connected to the second end of the seventh transistor at a first node, a control end of which is connected to the second end of the eighth transistor at a second node, and a second end of which is connected to the first reference ground; a tenth transistor, having a first terminal connected to the second node, a control terminal connected to the first node, and a second terminal connected to the first reference ground; A first inverter and a second inverter are connected in series between the second node and an output end of the first control signal; and A third inverter and a fourth inverter are connected in series between the first node and the output end of the second control signal. The first inverter, the second inverter, the third inverter and the fourth inverter all operate between the first power supply voltage and the first reference ground.

10. The signal sampling circuit according to claim 1, wherein: The sampling and gain amplification module comprises: An operational amplifier, comprising a positive input terminal and a negative input terminal, and a positive output terminal and a negative output terminal for providing the differential output signal; A first sampling capacitor, a second end of which is connected to the positive input end of the operational amplifier; A second sampling capacitor, a second end of which is connected to the negative input end of the operational amplifier; a first sampling switch, configured to provide a positive input voltage signal of the differential input signal to a first end of the first sampling capacitor according to the first control signal; a second sampling switch, configured to provide a negative input voltage signal of the differential input signal to a first end of the second sampling capacitor according to the first control signal; a first feedback capacitor and a second feedback capacitor, configured to be selectively connected in a feedback loop of the operational amplifier according to the first control signal and the second control signal; and A plurality of switching switches, wherein the plurality of switching switches are used to change the connection mode of the first feedback capacitor and the second feedback capacitor according to different phases of the first control signal or the second control signal, so that the sampling and gain amplification module is in different working states.

11. The signal sampling circuit according to claim 10, wherein: The first end of the first feedback capacitor is connected to the positive input end of the operational amplifier, the first end of the second feedback capacitor is connected to the negative input end of the operational amplifier, and the plurality of switching switches include: a first switching switch, configured to connect the second end of the first feedback capacitor to a common mode voltage signal according to the first control signal; a second switch, configured to connect the second end of the first feedback capacitor to the positive output end of the operational amplifier according to the second control signal; a third switch, configured to connect the second end of the second feedback capacitor to the common mode voltage signal according to the first control signal; and A fourth switch is used to connect the second end of the second feedback capacitor to the negative output end of the operational amplifier according to the second control signal.

12. The signal sampling circuit according to claim 11, wherein: The sampling and gain amplification module also includes: a first shorting switch, configured to short-circuit the first end of the first sampling capacitor and the first end of the second sampling capacitor according to the second control signal; a second shorting switch, configured to short-circuit the positive input terminal and the positive output terminal of the operational amplifier according to the first control signal; and The third short-circuit switch is used to short-circuit the negative input terminal and the negative output terminal of the operational amplifier according to the first control signal.

13. The signal sampling circuit according to claim 10, wherein: The sampling and gain amplification module also includes: a calibration switch array, configured to provide calibration voltage signals to the first terminals of the first sampling capacitor and the second sampling capacitor, respectively, to calibrate the offset or gain of the operational amplifier; The calibration switch array, the first sampling switch, and the second sampling switch are not turned on simultaneously.

14. The signal sampling circuit according to claim 13, wherein: The calibration switch array comprises: A first calibration switch, configured to provide a first calibration voltage to a first end of the first sampling capacitor; A second calibration switch, configured to provide a second calibration voltage to a first end of the second sampling capacitor; and a third calibration switch, configured to provide at least one third calibration voltage to the first end of the first sampling capacitor, The voltage values ​​of the first calibration voltage and the second calibration voltage are zero, and the voltage value of the at least one third calibration voltage is greater than the second calibration voltage. The calibration switch array is configured to turn on the first calibration switch and the second calibration switch and turn off the third calibration switch in an offset calibration phase, and to turn on the second calibration switch and the third calibration switch and turn off the first calibration switch in a gain calibration phase.

15. The signal sampling circuit according to claim 14, wherein: The calibration switch array further comprises: A first anti-leakage switch is arranged on a signal input path of the first calibration switch; A second anti-leakage switch is arranged on a signal input path of the second calibration switch; at least one third anti-leakage switch, arranged on at least one signal input path of the third calibration switch, The first anti-leakage switch, the second anti-leakage switch, the at least one third anti-leakage switch and the corresponding calibration switch are turned on and off simultaneously to reduce leakage of the calibration switch array in a non-calibration stage.

16. The signal sampling circuit according to claim 15, wherein: The calibration switch array further comprises: A first virtual switch having a second end connected to the first end of the second sampling capacitor; at least one second virtual switch corresponding to the number of the at least one third leakage protection switch, wherein a first end of the at least one second virtual switch is connected to the second calibration voltage, and a second end of the at least one second virtual switch is connected to the first virtual switch, The first virtual switch is turned on and off synchronously with the third calibration switch, and the at least one second virtual switch is always kept in an off state.

17. The signal sampling circuit according to claim 16, wherein: The first sampling switch, the second sampling switch, the first anti-leakage switch, the second anti-leakage switch, the at least one third anti-leakage switch and the at least one second virtual switch are low-voltage transistors, and the first calibration switch, the second calibration switch, the at least one third calibration switch and the first virtual switch are high-voltage transistors.

18. The signal sampling circuit according to claim 1, wherein: The first control signal and the second control signal are two-phase non-overlapping clock signals.

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