A cyclic successive approximation analog-to-digital converter with multiple-input comparators and a quantization method

Abstract

The application discloses a cyclic successive approximation analog-to-digital converter of a multi-input comparator and a quantization method. The converter comprises a sampling circuit, a multi-input comparator, a residual amplifier, a load capacitor and a decoder. The method comprises: performing first sampling and conversion processing according to a reference voltage signal to generate a first-sampled residual voltage signal output code; performing amplification processing on the first-sampled residual voltage signal output code based on the residual amplifier to obtain an amplified residual voltage signal output code; performing successive sampling and conversion processing on the amplified residual voltage signal output code to obtain a successively-sampled residual voltage signal output code; and decoding the successively-sampled residual voltage signal output code to obtain an effective residual voltage signal output code. The application can reduce the complexity of the residual amplifier, thereby reducing the power consumption of the converter and improving the performance of the converter. The application can be widely applied to the technical field of mixed signal circuits.

Description

Technical Field

[0001] This application relates to the field of mixed-signal circuit technology, and in particular to a cyclic successive approximation analog-to-digital converter with a multi-input comparator and a quantization method. Background Technology

[0002] In modern electronic systems, analog-to-digital converters (ADCs) are used as the core components to convert continuous analog signals into discrete digital signals. For high-precision ADC implementations, common architecture types mainly include oversampling-based Delta-Sigma ADCs and Noise-Shaping SAR ADCs, as well as Nyquist bandwidth SAR ADCs and pipelined ADCs. Oversampling ADCs improve resolution through noise shaping functions and digital filtering techniques. Although this helps reduce noise, their dependence on oversampling limits their system-level applications. In contrast, high-precision ADC architectures without oversampling or Nyquist bandwidth offer greater flexibility.

[0003] One existing technical architecture for non-oversampling high-precision ADCs is the SAR ADC. A typical SAR ADC structure includes a CDAC, a comparator, a sampling circuit, and SAR logic. For high-precision SAR ADCs, the comparator is one of the most critical components. The comparator's role is to determine the difference between the input signal voltage and the internally generated signal voltage and output the corresponding digital bits. It is the core of analog-to-digital conversion, therefore, the noise characteristics of the comparator directly determine the accuracy of the quantization process. Comparator noise typically includes thermal noise, flicker noise (also known as 1 / f noise), and kick-back noise. These noises can lead to uncertainty in the comparison results, thus affecting the accuracy and reliability of the ADC. Currently, reducing comparator noise is mainly achieved by optimizing the comparator design and adding several stages of preamplifiers, but this also limits the comparator's speed. Another non-oversampling high-precision ADC technical architecture is the pipelined ADC, however, it comes with higher power consumption and more complex circuit design requirements, and relies on high-precision comparators or high-performance amplifiers.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose a cyclic successive approximation analog-to-digital converter with a multi-input comparator and a quantization method, which can reduce the complexity of the residual amplifier, thereby reducing the power consumption of the converter and improving its performance.

[0006] To achieve the above objectives, one aspect of this application proposes a cyclic successive approximation analog-to-digital converter with a multi-input comparator. The converter includes a sampling circuit, a multi-input comparator, a residual amplifier, a load capacitor, and a decoder. The output of the sampling circuit is connected to a first input of the multi-input comparator, the first output of the multi-input comparator is connected to an input of the residual amplifier, the output of the residual amplifier is connected to an input of the load capacitor, the output of the load capacitor is connected to a second input of the multi-input comparator, and the second output of the multi-input comparator is connected to an input of the decoder. Wherein:

[0007] The sampling circuit is used to generate a reference voltage signal;

[0008] The multi-input comparator is used to perform a first sampling and conversion process based on the reference voltage signal to generate a residual voltage signal output code after the first sampling. The amplified residual voltage signal output code is then subjected to successive sampling and conversion processes to obtain a residual voltage signal output code after successive sampling.

[0009] The residual amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

[0010] The load capacitor is used to store the amplified residual voltage signal output code and transmit it to the multi-input comparator;

[0011] The decoder is used to decode the residual voltage signal output code after successive sampling to obtain an effective residual voltage signal output code.

[0012] In some embodiments, the multi-input comparator includes a high-order capacitor array, a middle-order capacitor array, and a low-order capacitor array, wherein the low-order capacitor array, the middle-order capacitor array, and the high-order capacitor array are connected in sequence, wherein:

[0013] The low-position capacitor array is used to perform the quantization process of the reference voltage signal;

[0014] The mid-position capacitor array is used to absorb the amplified comparator offset voltage.

[0015] The high-order capacitor array is used to generate the dummy reference bit.

[0016] In some embodiments, the low-position capacitor array, the middle-position capacitor array, and the high-position capacitor array all participate in the first sampling and conversion process, and the low-position capacitor array and the middle-position capacitor array participate in the successive sampling and conversion process.

[0017] In some embodiments, the residual amplifier includes a trimming network, a switched energy storage capacitor, and an inverter amplifier. The trimming network is electrically connected to the switched energy storage capacitor, and the switched energy storage capacitor is electrically connected to the inverter amplifier, wherein:

[0018] The tuning network is used to adjust the capacitance value of the switched energy storage capacitor;

[0019] The switched energy storage capacitor is used to provide a current signal to the inverter amplifier;

[0020] The inverter amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

[0021] In some embodiments, the tuning network includes a capacitor array and a switch array. The capacitor array includes a plurality of capacitors, and the switch array includes a plurality of switch pairs. Each of the switch pairs includes a first switch and a second switch, wherein:

[0022] The upper plates of the plurality of capacitors are selectively connected to the second terminal of the first switch, and the lower plates of the plurality of capacitors are selectively connected to the first terminal of the second switch.

[0023] The first terminal of the first switch is selectively connected to the upper stage board of the switch energy storage capacitor, and the second terminal of the second switch is selectively connected to the lower stage board of the switch energy storage capacitor.

[0024] In some embodiments, the inverter amplifier includes a first branch switch, a second branch switch, a third branch switch, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first branch switch includes a first branch first branch switch and a first branch second branch switch. The second branch switch includes a second branch first branch switch and a second branch second branch switch. The third branch switch includes a third branch first branch switch and a third branch second branch switch. The first terminal of the first branch first branch switch is connected to a high level. The second terminal of the first branch first branch switch, the upper stage board of the switching energy storage capacitor, and the first terminal of the second branch first branch switch are connected. The first terminal of the first branch second branch switch, the lower stage board of the switching energy storage capacitor, and the first terminal of the second branch second branch switch are connected. The connection is as follows: the second terminal of the second branch switch of the first branch is grounded; the second terminal of the first branch switch of the second branch, the source of the first transistor, and the source of the second transistor are connected; the second terminal of the second branch switch of the second branch, the source of the third transistor, and the source of the fourth transistor are connected; the drains of the first transistor and the third transistor are connected to the first terminal of the first branch switch of the third branch; the drains of the second transistor and the fourth transistor are connected to the second terminal of the second branch switch of the third branch; the second terminal of the first branch switch of the third branch is connected to the first terminal of the second branch switch of the third branch and connected to an enable clock signal; the gate of the first transistor is connected to the gate of the third transistor; and the gate of the second transistor is connected to the gate of the fourth transistor.

[0025] To achieve the above objectives, another aspect of this application proposes a quantization method for a cyclic successive approximation analog-to-digital converter using a multi-input comparator, the quantization method comprising the following steps:

[0026] The first sampling and conversion process is performed based on the reference voltage signal to generate the residual voltage signal output code after the first sampling.

[0027] Based on the residual amplifier, the residual voltage signal output code after the first sampling is amplified to obtain the amplified residual voltage signal output code.

[0028] The amplified residual voltage signal output code is sampled and converted successively to obtain the sampled residual voltage signal output code.

[0029] The residual voltage signal output code after successive sampling is decoded to obtain an effective residual voltage signal output code.

[0030] In some embodiments, the residual amplifier includes a charging phase and an amplification phase.

[0031] In some embodiments, during the charging phase of the residual amplifier, the first branch switch is set to the closed state, the second branch switch is set to the open state, the third branch switch is set to the closed state, the upper stage board of the switching energy storage capacitor is connected to the power supply, the lower stage board of the switching energy storage capacitor is grounded, and the switching energy storage capacitor is charged.

[0032] In some embodiments, during the amplification stage of the residual amplifier, the first branch switch is set to the open state, the second branch switch is set to the closed state, and the third branch switch is set to the open state. The switch energy storage capacitor is used to provide a current signal to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

[0033] The embodiments of this application include at least the following beneficial effects: This application provides a cyclic successive approximation analog-to-digital converter and quantization method with a multi-input comparator. After the first SAR conversion, the residual voltage on the CDAC is amplified by a residual amplifier, and the output result is stored on a capacitor and connected to the second pair of inputs of the comparator. This is used as the input signal in the second SAR conversion. By increasing the number of input pairs of the comparator, it can continue to be repeated to successive SAR conversion. The minimum quantization voltage brought by the segmented SAR conversion and the use of the first SAR conversion result as the input data for successive SAR conversion reduce the complexity of the residual amplifier, thereby reducing the power consumption of the converter and improving the performance of the converter. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a cyclic successive approximation analog-to-digital converter with a multi-input comparator provided in an embodiment of this application;

[0035] Figure 2 This is a flowchart illustrating a quantization method for a multi-input comparator cyclic successive approximation analog-to-digital converter provided in an embodiment of this application.

[0036] Figure 3 This is a schematic diagram of the residual amplifier provided in the embodiments of this application;

[0037] Figure 4 This is a schematic diagram of the FFT spectrum output by the converter at a sampling rate of 10MHz, provided in an embodiment of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0039] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0040] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0042] First, it's important to note that in modern electronic systems, analog-to-digital converters (ADCs) are the core components used to convert continuous analog signals into discrete digital signals. Their wide range of applications includes wireless communication, scientific measurement instruments, medical diagnostic equipment, and industrial automation, all of which place increasingly higher demands on signal processing accuracy and speed. ADC performance is often defined by key metrics such as resolution, sampling rate, linearity, power consumption, and signal-to-noise ratio (SNR), which largely determine the overall system performance and efficiency. For high-precision ADC implementations, common architecture types include oversampling-based Delta-Sigma ADCs and Noise-Shaping SAR ADCs, as well as Nyquist bandwidth SAR ADCs and pipelined ADCs. Oversampling ADCs improve resolution through noise shaping functions and digital filtering techniques; while this helps reduce noise, their dependence on oversampling limits their system-level applications. In contrast, high-precision ADC architectures without oversampling or Nyquist bandwidth offer greater flexibility.

[0043] One of the existing technical architectures for non-oversampling high-precision ADCs is the SAR ADC. Traditional SAR ADCs are widely used due to their simple and efficient architecture, low power consumption, and moderate speed characteristics. A typical SAR ADC structure includes a CDAC, a comparator, a sampling circuit, and SAR logic. SAR ADCs approximate the input signal value bit by bit using a successive approximation algorithm, and their performance is highly dependent on the accuracy of the internal comparator and capacitor array DAC. For high-precision SAR ADCs, the comparator is one of the most critical components. The comparator's role is to determine the difference between the input signal voltage and the internally generated signal voltage and output the corresponding digital bits; it is the core of the analog-to-digital domain conversion. Therefore, the noise characteristics of the comparator directly determine the accuracy of the quantization process. Comparator noise typically includes thermal noise, flicker noise (also known as 1 / f noise), and kick-back noise, which can lead to uncertainty in the comparison results, thus affecting the accuracy and reliability of the ADC. When subtle changes in the input signal need to be measured accurately, comparator noise may mask or distort these subtle signal changes, causing the ADC to output incorrect digital values. This error is particularly significant for high-precision ADCs. For high-precision SAR ADCs, the comparator noise level is typically required to be within half the minimum effective number of bits (LSB). For example, for a 16-bit high-precision ADC with a 0.9V reference voltage, the differential LSB is only 27.5μV. Conventional single-stage dynamic comparators struggle to achieve such stringent noise performance. To improve comparator accuracy, engineers have implemented measures to reduce the impact of comparator noise. A common approach is to optimize the comparator design by adding several preamplifier stages. However, multi-stage preamplifiers not only consume significant power but also limit the comparator speed, thus slowing down the overall system bandwidth. In recent years, some advanced dynamic amplifier architectures have been introduced as preamplifiers for comparators. While they have shown potential in terms of power consumption and speed, the stability and PVT robustness of the dynamic amplifier itself remain significant challenges.

[0044] Another widely adopted non-oversampling high-precision ADC architecture is the pipelined ADC. In a pipelined ADC architecture, the multiplicative digital-to-analog converter (MDAC) is the core module, and its function is crucial. The MDAC is responsible for partially quantizing the signal at each pipeline stage and generating residual signals for use in the next stage. This process enables the pipelined ADC to achieve high throughput and high-precision analog-to-digital conversion; therefore, the performance of the MDAC directly affects the overall performance of the ADC.

[0045] MDACs typically consist of two main parts: a quantizer and a residual amplifier. The quantizer performs a coarse analog-to-digital conversion at each stage, determining a coarse digital approximation of the signal at that stage. In this process, the accuracy and speed of the quantizer are critical to the overall performance of the ADC, especially in applications requiring high sampling rates and high accuracy. In recent years, quantizer architectures have become increasingly diverse and hybrid. Among them, the SAR architecture, due to its simplicity and scalability, has gained particular favor, and pipelined SAR ADCs have become increasingly popular. For high-precision SAR ADCs, a significant advantage of introducing a pipelined structure is that it can greatly relax the limitations on comparator accuracy. For example, for the same 16-bit accuracy requirement, if an 8-8 two-stage pipeline architecture is used, only one comparator meeting 8-bit accuracy is needed, which can bring a significant improvement in comparator power consumption and speed. However, everything has two sides; high-precision pipelined SAR ADCs face equally challenging problems, especially the design of the residual amplifier.

[0046] The residual amplifier is responsible for amplifying the residual analog signal difference (i.e., quantization error) and passing it to the next stage for further refinement. Its design faces numerous challenges. For example, it must achieve high gain to ensure the residual signal is amplified to a level usable for the next stage of processing, while maintaining low distortion and low noise, which lays the foundation for achieving high resolution in pipelined ADCs. However, high amplification gain often comes with high power consumption and complex circuit design requirements; therefore, a balance must be struck between performance and power consumption when designing a residual amplifier. Furthermore, the linearity, bandwidth, and static offset of the residual amplifier must be carefully optimized to minimize the impact of error accumulation on the overall linearity of the ADC. For high-precision applications, the design difficulty and power consumption cost of a residual amplifier are comparable to those of a high-precision comparator.

[0047] In summary, existing Nyquist bandwidth high-precision ADCs typically rely heavily on high-precision comparators or high-performance amplifiers, and the implementation of these two types of modules often comes at a high cost in terms of circuitry and power consumption.

[0048] In view of this, this application provides a cyclic successive approximation analog-to-digital converter with a multi-input comparator. After the first SAR conversion (called α-SAR conversion) is completed, the residual voltage on the CDAC is amplified using a residual amplifier, and the output result is stored on a capacitor and connected to the second pair of inputs of the comparator, serving as the input signal in the second SAR conversion (called β-SAR conversion). By increasing the number of input pairs of the comparator, the above process can be repeated to extend to more SAR conversions. In the additional conversions, the top plate of the CDAC, originally connected to the first pair of inputs, no longer simultaneously performs sampling and binary reference functions, but only provides binary reference functions. The CDAC is reset after the residual amplification is completed. During other SAR conversions besides α-SAR conversion, the bit capacitors in the CDAC will perform different functions: the high-order array will not participate in the SAR conversion directly, but will serve as a dummy bit for generating the reference; the middle-order array and the low-order array will participate in the SAR conversion, where the middle-order array mainly plays a role similar to the high-order redundancy in a pipelined SAR ADC, used to absorb the amplified comparator offset voltage, while the low-order array, like all the bit capacitors in the α-SAR conversion, performs the complete quantization function. For high-precision quantization implemented with this architecture, the power consumption and design complexity of the high-precision comparator are significantly reduced due to the increased minimum quantization voltage resulting from segmented SAR conversion. Simultaneously, due to the common-mode nature of multi-input comparators in transconductance addition, the number of bits in the first quantization can be significantly larger than subsequent quantizations, greatly relaxing the requirements for the residual amplifier. Therefore, through this cyclic multi-step SAR ADC architecture based on multi-input comparators, the cost of high-bit-count SAR quantization is significantly reduced.

[0049] Additionally, it should be noted that this embodiment of the invention introduces a residual amplifier with a gain of 16, adds an extra input pair to the comparator, and transforms the original single-transformation SAR conversion logic into a multi-transformation SAR conversion logic. Since the third and subsequent SAR conversion operations are completely identical to the second SAR conversion, the following explanation uses two SAR conversions (α-SAR conversion and β-SAR conversion) as an example.

[0050] Reference Figure 1 , Figure 1 This is a structural diagram of a cyclic successive approximation analog-to-digital converter with a multi-input comparator provided in an embodiment of the present invention, with reference to... Figure 1The converter includes a sampling circuit, a multi-input comparator, a residual amplifier, a load capacitor, and a decoder. The output of the sampling circuit is connected to the first input of the multi-input comparator. The first output of the multi-input comparator is connected to the input of the residual amplifier. The output of the residual amplifier is connected to the input of the load capacitor. The output of the load capacitor is connected to the second input of the multi-input comparator. The second output of the multi-input comparator is connected to the input of the decoder.

[0051] The sampling circuit is used to generate a reference voltage signal;

[0052] The multi-input comparator is used to perform the first sampling and conversion processing based on the reference voltage signal to generate the residual voltage signal output code after the first sampling. The amplified residual voltage signal output code is then subjected to successive sampling and conversion processing to obtain the residual voltage signal output code after successive sampling.

[0053] Specifically, the multi-input comparator includes a high-order capacitor array, a middle-order capacitor array, and a low-order capacitor array, which are connected in sequence. The low-order capacitor array is used to perform the quantization process of the reference voltage signal; the middle-order capacitor array is used to absorb the amplified comparator offset voltage; and the high-order capacitor array is used to generate the reference dummy bit.

[0054] Additionally, it should be noted that in this embodiment, the low-position capacitor array, the middle-position capacitor array, and the high-position capacitor array all participate in the first sampling and conversion process, while the low-position capacitor array and the middle-position capacitor array participate in the successive sampling and conversion process.

[0055] In this embodiment, a multi-input comparator is introduced to support cyclic multi-step successive approximation (SAR) conversion. The multi-input comparator is the core of this architecture and is typically used to implement addition in the current domain or transconductance domain. For α-SAR conversion (i.e., conventional SAR conversion), the signal on the CDAC can be represented as the input V. in With code word D out The summation is achieved through the two ends of a capacitor, as the capacitor can be considered a natural adder. During the β-SAR conversion stage, the amplified α-SAR conversion residual becomes the input to the β-SAR conversion. At this point, the addition does not need to be achieved through the sampling circuit across the two ends of the capacitor, but rather as an additional input pair at the comparator input.

[0056] In β-SAR conversion, the top plate of the CDAC no longer simultaneously performs sampling and binary reference functions, but is only used to provide the binary reference codeword Dout. After residual amplification, the CDAC is reset. In the β-SAR stage, each bit capacitor plays a different role: the high-bit capacitor array does not participate in β-SAR conversion, but is used as a dummy bit to generate the reference; the middle-bit array participates in β-SAR conversion, playing a role similar to high-bit redundancy in a pipelined SAR ADC, to absorb the amplified comparator offset voltage. The low-bit array, like all bit capacitors in α-SAR, performs the complete quantization function.

[0057] This architecture improves the minimum quantization voltage through segmented SAR conversion, thereby significantly reducing the power consumption and design complexity of high-precision comparators. Furthermore, due to the common-mode nature of multi-input comparators in transconductance domain addition, the number of bits in the first quantization can significantly exceed that of the second quantization. This also correspondingly reduces the requirements for the residual amplifier. Through this cyclic multi-step SAR ADC architecture based on multi-input comparators, high-bit-count accurate quantization can be achieved at a lower cost.

[0058] The schematic diagram of this structure is as follows: Figure 1 As shown, the differential half-circuit has been omitted from the diagram, and a two-step SAR conversion is used as an example. The architecture proposed in this invention is implemented using a 40nm process, with both the supply voltage and reference voltage at 0.9V. The CDAC used is a segmented bridge configuration, with a total of 15-bit binary capacitors, numbered C from high to low bits. 14 C 13 C 12 The sequence C0 includes 3 redundant bits, so a complete SAR conversion can output 12 valid bits. For a two-step SAR conversion, α-SAR performs 15 comparisons and provides 12 valid output bits, while β-SAR conversion starts from the 6th bit, performs 9 SAR conversions, and provides 4 valid output bits.

[0059] The residual amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

[0060] Specifically, such as Figure 3 As shown, the residual amplifier includes a trimming network, a switched energy storage capacitor, and an inverter amplifier. The trimming network is electrically connected to the switched energy storage capacitor, and the switched energy storage capacitor is electrically connected to the inverter amplifier. The trimming network is used to adjust the capacitance value of the switched energy storage capacitor; the switched energy storage capacitor is used to provide a current signal to the inverter amplifier; and the inverter amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

[0061] It should be noted that the adjustment network includes a capacitor array and a switch array. The capacitor array includes several capacitors, and the switch array includes several switch pairs. Each switch pair includes a first switch and a second switch. The upper-level board of the capacitors is selectively connected to the second terminal of the first switch, and the lower-level board of the capacitors is selectively connected to the first terminal of the second switch. The first terminal of the first switch is selectively connected to the upper-level board of the switching energy storage capacitor, and the second terminal of the second switch is selectively connected to the lower-level board of the switching energy storage capacitor.

[0062] Furthermore, it should be noted that the inverter amplifier includes a first branch switch, a second branch switch, a third branch switch, and a first transistor M. P1 Second transistor M P2 Third transistor M N1 With the fourth transistor M N2 The first branch switch includes the first branch switch S of the first branch. 1,p With the first branch and second branch switch S 1,n The second branch switch includes the second branch first branch switch S. 2,p With the second branch switch S of the second branch circuit 2,n The third branch switch includes the third branch first branch switch S. 3,a With the second branch switch of the third branch S 3,b In this circuit, the first terminal of the first branch switch of the first branch is connected to a high level; the second terminal of the first branch switch of the first branch and the upper stage board of the switching energy storage capacitor are connected to the first terminal of the first branch switch of the second branch; the first terminal of the second branch switch of the first branch and the lower stage board of the switching energy storage capacitor are connected to the first terminal of the second branch switch of the second branch; the second terminal of the second branch switch of the first branch is grounded; the second terminal of the first branch switch of the second branch and the source of the first transistor are connected to the source of the second transistor; the second terminal of the second branch switch of the second branch and the source of the third transistor are connected to the source of the fourth transistor; the drains of the first transistor and the third transistor are connected to the first terminal of the first branch switch of the third branch; the drains of the second transistor and the fourth transistor are connected to the second terminal of the second branch switch of the third branch; the second terminal of the first branch switch of the third branch is connected to the first terminal of the second branch switch of the third branch and connected to an enable clock signal; the gate of the first transistor is connected to the gate of the third transistor; and the gate of the second transistor is connected to the gate of the fourth transistor.

[0063] In this embodiment, since the reference level for the β-SAR conversion remains unchanged, the required amplification factor for the residual amplifier is 16x. Due to the advantages of the proposed architecture, the residual amplifier has very low linearity requirements and does not need to drive a large CDAC load. The embodiments of this invention select... Figure 3The floating inverter amplifier (FIA) structure shown serves as a residual amplifier, consisting of an inverter amplifier and a switched energy storage capacitor C. R Composition. As a dynamic amplifier, its operation can be divided into a charging stage and an amplification stage. When the amplifier's enable clock Φ... AMP When the voltage level is low, FIA is in the charging phase. At this time, switch S... 1,p S 1,n Close, switch S 2,p S 2,n Disconnect, S 3,a S 3,b Closed, energy storage capacitor C R The top and bottom plates are connected to the power supply and ground, respectively, and the two differential output nodes are set to V. CM During the amplification stage, switch S... 1,p S 1,n Disconnect, switch S 2,p S 2,n Closed, S 3,a S 3,b Disconnect, C R Like a battery, it powers the circuit, resulting in a continuous but gradually decaying source-drain current. According to the fundamental current law, the current through the two capacitor plates must be equal, making the output node a symmetrical virtual ground, thus stabilizing the common-mode output voltage. Due to the common-mode performance requirements of multi-input comparators as transconductance adders, the excellent common-mode output characteristics of the FIA ​​are a perfect fit for this structure, eliminating the need for an additional common-mode feedback (CMFB) circuit. It also features N+1 trimming capacitors C t,N ,…,C t,1 C t,0 and the corresponding switch pair S t,N<a&b> ,…,S t,1<a&b> ,S t,0<a&b> The trimming bank adjusts the FIA ​​equivalent energy storage capacitor C. R The gain is adjusted by adjusting the size of the open-loop FIA gain, which ensures the PVT robustness of the open-loop FIA gain.

[0064] The load capacitor is used to store the amplified residual voltage signal output code and transmit it to the multi-input comparator;

[0065] The decoder is used to decode the residual voltage signal output code after successive sampling to obtain an effective residual voltage signal output code.

[0066] In summary, traditional 16-bit high-precision SAR ADCs require capacitance mismatch calibration of the 16-bit CDAC, while high-precision pipelined SAR ADCs, due to the different CDACs sampled at each stage, have even more complex mismatch calibration processes. The architecture proposed in this invention, while similar to the pipelined approach in its two SAR conversions, uses only one CDAC, ensuring complete consistency of the binary reference level code value generated by the CDAC between the two conversions. Furthermore, by decomposing the 16 bits into 12+4 bits, the effective number of bits in the CDAC is only 12, allowing for a larger unit capacitance value than that used in traditional 16-bit high-precision SAR ADCs, thus significantly reducing calibration difficulty.

[0067] Please see Figure 2 This application also provides a quantization method for a cyclic successive approximation analog-to-digital converter (ADC) using a multi-input comparator, which can realize the above-mentioned cyclic successive approximation ADC using a multi-input comparator. The system includes:

[0068] S100: Perform the first sampling and conversion processing based on the reference voltage signal to generate the residual voltage signal output code after the first sampling;

[0069] S200: Based on the residual amplifier, the residual voltage signal output code after the first sampling is amplified to obtain the amplified residual voltage signal output code.

[0070] It should be noted that in some embodiments, step S200 may include: S210, for the charging stage of the residual amplifier, setting the first branch switch to the closed state, setting the second branch switch to the open state, setting the third branch switch to the closed state, connecting the upper stage board of the switching energy storage capacitor to the power supply, and grounding the lower stage board of the switching energy storage capacitor to charge the switching energy storage capacitor; S220, for the amplification stage of the residual amplifier, setting the first branch switch to the open state, setting the second branch switch to the closed state, setting the third branch switch to the open state, using the switching energy storage capacitor to provide a current signal, amplifying the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

[0071] S300: The amplified residual voltage signal output code is sampled and converted successively to obtain the sampled residual voltage signal output code.

[0072] S400: Decode the residual voltage signal output code after successive sampling to obtain an effective residual voltage signal output code;

[0073] In some specific embodiments, sampling is performed first, followed by the α-SAR conversion phase (Φ). alphaAfter 15 comparisons, a 15-bit output code is generated. During this stage, the gates of the second pair of input transistors of the comparator are grounded, which is considered to be off. After the α-SAR conversion is completed, the FIA ​​amplification stage begins (Φ... AMP The FIA ​​amplifies the residual voltage from the α-SAR conversion by a factor of 16 and stores it in the load capacitor C. L After the amplification phase ends, the CDAC is briefly reset, after which the load capacitor C... L Connect the gates of the second pair of input transistors to the comparator to begin the β-SAR stage (Φ beta The process involves nine comparisons to generate a 9-bit output code. After the β-SAR conversion is complete, a total of 26 bits of output code are obtained in a single sampling period, which can be decoded to obtain 16 valid output bits.

[0074] Furthermore, such as Figure 4 The diagram shows the output spectrum of the invented cyclic multi-step successive approximation analog-to-digital converter architecture based on a multi-input comparator. The ADC sampling frequency is 10MHz, and the input frequency is a sine wave with a peak-to-peak value of 1.6V at 0.547MHz. The output code value is imported into MATLAB for FFT testing. The FFT results show that the ADC has an output SNDR of 88.7dB, an effective number of bits (ENOB) of 14.44 bits, and a core power consumption of 0.675mW within a 5MHz Nyquist bandwidth. The calculated quality factor FoMs is 187.4dB.

[0075] In comparison, in the industry, Analog Devices (ADI)'s AD7626 chip is an example. This ADC chip is a 16-bit 10MHz sampling rate SAR ADC, and it also boasts the highest bandwidth among the company's 16-bit single-channel precision ADC products. According to the datasheet, the AD7626 has an SNR of 91.5dB and a total power consumption of 136mW. Although industrial products often incur considerable power consumption in reference buffers and other stability components, the power consumption of the ADC architecture proposed in this invention remains highly attractive.

[0076] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0077] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A cyclic successive approximation analog-to-digital converter with a multi-input comparator, characterized in that, The converter includes a sampling circuit, a multi-input comparator, a residual amplifier, a load capacitor, and a decoder. The output of the sampling circuit is connected to the first input of the multi-input comparator. The first output of the multi-input comparator is connected to the input of the residual amplifier. The output of the residual amplifier is connected to the input of the load capacitor. The output of the load capacitor is connected to the second input of the multi-input comparator. The second output of the multi-input comparator is connected to the input of the decoder. Wherein: The sampling circuit is used to generate a reference voltage signal; The multi-input comparator is used to perform a first sampling and conversion process based on the reference voltage signal to generate a residual voltage signal output code after the first sampling. The amplified residual voltage signal output code is then subjected to successive sampling and conversion processes to obtain a residual voltage signal output code after successive sampling. The residual amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code. The load capacitor is used to store the amplified residual voltage signal output code and transmit it to the multi-input comparator; The decoder is used to decode the residual voltage signal output code after successive sampling to obtain an effective residual voltage signal output code; The multi-input comparator includes a high-order capacitor array, a middle-order capacitor array, and a low-order capacitor array, wherein the low-order capacitor array, the middle-order capacitor array, and the high-order capacitor array are connected in sequence, wherein: The low-position capacitor array is used to perform the quantization process of the reference voltage signal; The mid-position capacitor array is used to absorb the amplified comparator offset voltage. The high-order capacitor array is used to generate the reference dummy bit; The low-position capacitor array, the middle-position capacitor array, and the high-position capacitor array all participate in the first sampling and conversion process, and the low-position capacitor array and the middle-position capacitor array participate in the successive sampling and conversion process.

2. The converter according to claim 1, characterized in that, The residual amplifier includes a trimming network, a switched energy storage capacitor, and an inverter amplifier. The trimming network is electrically connected to the switched energy storage capacitor, and the switched energy storage capacitor is electrically connected to the inverter amplifier, wherein: The tuning network is used to adjust the capacitance value of the switched energy storage capacitor; The switched energy storage capacitor is used to provide a current signal to the inverter amplifier; The inverter amplifier is used to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

3. The converter according to claim 2, characterized in that, The tuning network includes a capacitor array and a switch array. The capacitor array includes a plurality of capacitors, and the switch array includes a plurality of switch pairs. Each switch pair includes a first switch and a second switch, wherein: The upper plates of the plurality of capacitors are selectively connected to the second terminal of the first switch, and the lower plates of the plurality of capacitors are selectively connected to the first terminal of the second switch. The first terminal of the first switch is selectively connected to the upper stage board of the switch energy storage capacitor, and the second terminal of the second switch is selectively connected to the lower stage board of the switch energy storage capacitor.

4. The converter according to claim 2, characterized in that, The inverter amplifier includes a first branch switch, a second branch switch, a third branch switch, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first branch switch includes a first branch first sub-switch and a first branch second sub-switch; the second branch switch includes a second branch first sub-switch and a second branch second sub-switch; and the third branch switch includes a third branch first sub-switch and a third branch second sub-switch. The first terminal of the first branch first sub-switch is connected to a high level. The second terminal of the first branch first sub-switch, the upper stage board of the switch energy storage capacitor, and the first terminal of the second branch first sub-switch are connected. The first terminal of the first branch second sub-switch, the lower stage board of the switch energy storage capacitor, and the first terminal of the second branch second sub-switch are connected. The second terminal of the second branch switch of the first branch is grounded. The second terminal of the first branch switch of the second branch, the source of the first transistor, and the source of the second transistor are connected. The second terminal of the second branch switch of the second branch, the source of the third transistor, and the source of the fourth transistor are connected. The drains of the first transistor and the third transistor are connected to the first terminal of the first branch switch of the third branch. The drains of the second transistor and the fourth transistor are connected to the second terminal of the second branch switch of the third branch. The second terminal of the first branch switch of the third branch is connected to the first terminal of the second branch switch of the third branch and connected to an enable clock signal. The gate of the first transistor is connected to the gate of the third transistor. The gate of the second transistor is connected to the gate of the fourth transistor.

5. A quantization method for a cyclic successive approximation analog-to-digital converter applied to a multi-input comparator according to any one of claims 1-4, characterized in that, The quantification method includes the following steps: The first sampling and conversion process is performed based on the reference voltage signal to generate the residual voltage signal output code after the first sampling. Based on the residual amplifier, the residual voltage signal output code after the first sampling is amplified to obtain the amplified residual voltage signal output code. The amplified residual voltage signal output code is sampled and converted successively to obtain the sampled residual voltage signal output code. The residual voltage signal output code after successive sampling is decoded to obtain an effective residual voltage signal output code.

6. The method according to claim 5, characterized in that, The residual amplifier includes a charging stage and an amplification stage.

7. The method according to claim 6, characterized in that, During the charging phase of the residual amplifier, the first branch switch is set to the closed state, the second branch switch is set to the open state, the third branch switch is set to the closed state, the upper stage board of the switching energy storage capacitor is connected to the power supply, the lower stage board of the switching energy storage capacitor is grounded, and the switching energy storage capacitor is charged.

8. The method according to claim 7, characterized in that, During the amplification stage of the residual amplifier, the first branch switch is set to the open state, the second branch switch is set to the closed state, and the third branch switch is set to the open state. The switch energy storage capacitor is used to provide a current signal to amplify the residual voltage signal output code after the first sampling to obtain the amplified residual voltage signal output code.

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