Analog-to-digital conversion circuit and analog-to-digital conversion method
By designing an analog-to-digital conversion circuit in a successive approximation analog-to-digital converter SAR ADC, adjusting the driving capability of the buffer and providing multiple clock cycles for conversion, the problem of the impact of the reference voltage VREF kickback is solved, and the conversion is completed in a timely manner and power consumption is reduced.
Patent Information
- Application Number
- CN202411658002.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-02-28
AI Technical Summary
In the successive approximation analog-to-digital converter SAR ADC, since the buffer output end does not have an external load capacitor, the up and down swing of the reference voltage VREF becomes larger, and the kickback is larger, which affects the conversion of the most significant bit MSB and subsequent effective bit conversion, causing output confusion.
An analog-to-digital conversion circuit is designed, including a buffer, a conversion control unit and an analog-to-digital converter. By adjusting the driving capability of the buffer during each effective bit conversion period, it provides multiple clock cycles for conversion, reduces the kickback effect on the reference voltage VREF, and ensures that the conversion is completed.
It effectively reduces the impact of kickback on the reference voltage VREF, ensures timely completion of conversion, reduces power consumption, and improves the overall performance of the analog-to-digital converter.
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Figure CN119543950A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an analog-to-digital conversion circuit and an analog-to-digital conversion method. Background Art
[0002] Common circuit structures with successive approximation analog-to-digital converters SAR ADC are as follows: Figure 1 As shown, since the driving capability of the bandgap reference circuit BG is insufficient, a buffer needs to be added to increase the driving capability of the reference voltage VREF.
[0003] The problem with this structure is that due to some scenario requirements (such as saving cost and area), the output end of the buffer buffer is not connected to an external load capacitor. This will cause the up and down swings of the reference voltage VREF output by the buffer buffer to become larger, and especially during the conversion period corresponding to the most significant bit MSB of the successive approximation analog-to-digital converter SAR ADC, when the switch of the capacitor unit corresponding to the most significant bit MSB is switched, the kick back to the reference voltage VREF is large (and if there is a load capacitor, the larger the load capacitor, the larger the kick back). At this time, the reference voltage VREF needs to be re-established, which may cause the most significant bit MSB of the successive approximation analog-to-digital converter SAR ADC to fail to complete the conversion in time, and will also affect the subsequent valid bit conversion, causing confusion in the output of the entire successive approximation analog-to-digital converter SAR ADC.
[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention
[0005] The object of the present invention is to provide an analog-to-digital conversion circuit and an analog-to-digital conversion method, which can reduce the influence caused by the kick-back on the reference voltage VREF during each conversion period, ensure the completion of the conversion, and reduce power consumption.
[0006] In order to achieve the above objective, a specific embodiment of the present invention provides an analog-to-digital conversion circuit, including: a buffer, a conversion control unit and an analog-to-digital converter.
[0007] The buffer is used to provide a reference voltage; the conversion control unit is used to generate multiple conversion control signals based on a clock signal, and the conversion control signals are used to form each conversion time period; the analog-to-digital converter is used to perform conversion from the most significant bit to the least significant bit based on the reference voltage in the corresponding conversion time period, wherein the conversion time periods corresponding to all significant bits are not exactly the same, and the conversion time period corresponding to the most significant bit is greater than or equal to the conversion time periods corresponding to other significant bits.
[0008] In one or more embodiments of the present invention, the conversion periods corresponding to the effective bits decrease in sequence from the most effective bit to the least effective bit.
[0009] In one or more embodiments of the present invention, the buffer includes an operational amplifier unit, an output unit and an output control unit, the output end of the operational amplifier unit is connected to the input end of the output unit, the output unit outputs a reference voltage based on the output signal of the operational amplifier unit, one or more output control units are provided, the output end of the output unit is connected to the output end of the output control unit, and the output control unit is used to adjust the driving capability of the buffer based on the connection between itself and the output end of the operational amplifier unit within the corresponding conversion period.
[0010] In one or more embodiments of the present invention, the output unit includes a first transistor and a second transistor, the first end of the first transistor is connected to the power supply voltage, the second end of the first transistor is connected to the second end of the second transistor to form the output end of the output unit, the first end of the second transistor is connected to the ground voltage, the control end of the first transistor is connected to the first output end of the operational amplifier unit, and the control end of the second transistor is connected to the second output end of the operational amplifier unit.
[0011] In one or more embodiments of the present invention, the output control unit includes a third transistor, a fourth transistor and a switch unit, the first end of the third transistor is connected to the power supply voltage, the second end of the third transistor is connected to the second end of the fourth transistor to form the output end of the output control unit, the first end of the fourth transistor is connected to the ground voltage, the control end of the third transistor and the control end of the fourth transistor are connected to the first output end and the second output end of the operational amplifier unit through the switch unit, and the switch unit is closed during the corresponding conversion period.
[0012] In one or more embodiments of the present invention, the output unit includes a first transistor and a first load unit, the first end of the first transistor is connected to the power supply voltage, the second end of the first transistor is connected to the first end of the first load unit to form the output end of the output unit, the second end of the first load unit is connected to the ground voltage, and the control end of the first transistor is connected to the output end of the operational amplifier unit; or
[0013] The first end of the first transistor is connected to the ground voltage, the second end of the first transistor is connected to the first end of the first load unit to form the output end of the output unit, the second end of the first load unit is connected to the power supply voltage, and the control end of the first transistor is connected to the output end of the operational amplifier unit.
[0014] In one or more embodiments of the present invention, the output control unit includes a second transistor, a second load unit and a switch unit, the first end of the second transistor is connected to the power supply voltage, the second end of the second transistor is connected to the first end of the second load unit to form the output end of the output control unit, the second end of the second load unit is connected to the ground voltage, the control end of the second transistor is connected to the first end of the switch unit, the second end of the switch unit is used to receive the output voltage of the operational amplifier unit, and the switch unit is closed in the corresponding conversion period; or
[0015] The first end of the second transistor is connected to the ground voltage, the second end of the second transistor is connected to the first end of the second load unit to form the output end of the output control unit, the second end of the second load unit is connected to the power supply voltage, the control end of the second transistor is connected to the first end of the switch unit, the second end of the switch unit is used to receive the output voltage of the operational amplifier unit, and the switch unit is closed during the corresponding conversion period.
[0016] In one or more embodiments of the present invention, the conversion control unit includes a plurality of triggers connected in series, each of the triggers is used to generate a corresponding conversion control signal based on a clock signal during the conversion phase, and the phase difference between two adjacent conversion control signals is one clock cycle.
[0017] The present invention also discloses an analog-to-digital conversion method. Based on the analog-to-digital conversion circuit, the analog-to-digital conversion method includes:
[0018] Provide reference voltage through buffer;
[0019] In the conversion phase, a conversion control unit generates a plurality of conversion control signals based on the clock signal, and each conversion period is formed by the conversion control signals;
[0020] The conversion from the most significant bit to the least significant bit is performed by an analog-to-digital converter based on a reference voltage in a corresponding conversion period, wherein the conversion periods corresponding to all significant bits are not exactly the same, and the conversion period corresponding to the most significant bit is set to be greater than or equal to the conversion periods corresponding to other significant bits.
[0021] In one or more embodiments of the present invention, providing a reference voltage through a buffer includes:
[0022] outputting a reference voltage based on an output signal of the operational amplifier unit of the buffer through an output unit of the buffer;
[0023] In the conversion stage, based on the conversion period corresponding to each valid bit, the number of output control units connected to the output end of the operational amplifier unit in the buffer is controlled to adjust the driving capability of the buffer, wherein, in the conversion period corresponding to the most significant bit, the number of output control units connected to the output end of the operational amplifier unit is set to be greater than the number of output control units connected to the output end of the operational amplifier unit in the conversion period corresponding to other valid bits.
[0024] Compared with the prior art, the analog-to-digital conversion circuit and analog-to-digital conversion method of the present invention provide multiple clock cycles for conversion when each valid bit is converted (especially the most significant bit conversion), thereby reducing the impact of the reference voltage kick-back during conversion, providing sufficient time for the reference voltage to be re-established, and ensuring the completion of the conversion, and the same is true for the conversion of each valid bit that will produce a kick-back. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0026] Figure 1 The schematic diagram of the analog-to-digital conversion circuit in the prior art.
[0027] Figure 2 4 is a circuit schematic diagram of the analog-to-digital conversion circuit in Example 1.
[0028] Figure 3 This is a circuit schematic diagram of the buffer in the first embodiment.
[0029] Figure 4 This is a circuit diagram of the conversion control unit in the first embodiment.
[0030] Figure 5 This is a first signal waveform diagram of the analog-to-digital conversion circuit in the first embodiment.
[0031] Figure 6 This is a second signal waveform diagram of the analog-to-digital conversion circuit in Example 1.
[0032] Figure 7 This is a circuit schematic diagram of the buffer in the second embodiment. DETAILED DESCRIPTION
[0033] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0034] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.
[0035] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.
[0036] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.
[0037] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0038] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.
[0039] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.
[0040] like Figure 2 As shown, an analog-to-digital conversion circuit in an embodiment of the present invention includes: a buffer, a conversion control unit 20 and an analog-to-digital converter ADC.
[0041] The buffer buffer is used to provide a reference voltage VREF. In one embodiment, the input end of the buffer buffer is connected to the output end of the bandgap reference voltage BG, and the buffer buffer is used to improve the driving capability of the output voltage of the bandgap reference voltage BG.
[0042] The conversion control unit 20 is used to generate a plurality of conversion control signals based on the clock signal CLK, and the conversion control signals are used to form each conversion period. In one embodiment, the conversion control unit 20 receives an input signal VIN, and when the input signal VIN is at an effective level, it indicates that a conversion phase has been entered. In the conversion phase, the conversion control unit 20 generates a plurality of conversion control signals based on the clock signal CLK. In one embodiment, the edges of any two conversion control signals can constitute a conversion period. Specifically, the length of the period from the rising edge of one conversion control signal to the rising edge of another conversion control signal can be considered as a conversion period, that is, the rising edge of each conversion period corresponds to the rising edge of the first conversion control signal, and the falling edge of the conversion period corresponds to the rising edge of the last conversion control signal.
[0043] The analog-to-digital converter ADC is used to convert from the most significant bit MSB to the least significant bit LSB based on the reference voltage VREF in the corresponding conversion period, wherein the conversion periods corresponding to all the significant bits are not exactly the same, and the conversion period corresponding to the most significant bit is greater than or equal to the conversion periods corresponding to the other significant bits. In one embodiment, at least one conversion period is greater than the clock cycle of the clock signal CLK, and the analog-to-digital converter ADC is a successive approximation analog-to-digital converter SAR ADC.
[0044] In one embodiment, the conversion period TM corresponding to the most significant bit MSB is the largest and is greater than the conversion periods TM-1 to TL corresponding to other significant bits, while the conversion periods TM-1 to TL corresponding to other significant bits are equal. In other embodiments, the conversion periods corresponding to each significant bit obtained by the analog-to-digital converter ADC based on the conversion control signal decrease in sequence from the most significant bit MSB to the least significant bit LSB, that is, the conversion periods TM, TM-1 to TL gradually decrease, and the decreasing difference between the conversion periods can be adjusted as needed.
[0045] like Figure 3 As shown, the buffer includes an operational amplifier unit 11, an output unit 12 and an output control unit 13. The operational amplifier unit 11 is a front-stage circuit, the output end of the operational amplifier unit 11 is connected to the input end of the output unit 12, and the output unit 12 outputs a reference voltage VREF based on the output signal of the operational amplifier unit 11.
[0046] There are multiple output control units 13, and the output end of the output unit 12 is connected to the output end of the output control unit 13. The output control unit 13 is used to adjust the driving capability of the buffer buffer based on the connection between itself and the output end of the operational amplifier unit 11 during the corresponding conversion period. In other embodiments, only one output control unit 13 may be provided.
[0047] like Figure 3 As shown, the output unit 12 includes a first transistor M1 and a second transistor M2, the first end of the first transistor M1 is connected to the power supply voltage, the second end of the first transistor M1 is connected to the second end of the second transistor M2 to form the output end of the output unit 12, the first end of the second transistor M2 is connected to the ground voltage, the control end of the first transistor M1 is connected to the first output end of the operational amplifier unit 11, and the control end of the second transistor M2 is connected to the second output end of the operational amplifier unit 11.
[0048] The output control unit 13 includes a third transistor M3, a fourth transistor M4 and a switch unit. The first end of the third transistor M3 is connected to the power supply voltage, the second end of the third transistor M3 is connected to the second end of the fourth transistor M4 to form the output end of the output control unit 13, the first end of the fourth transistor M4 is connected to the ground voltage, the control end of the third transistor M3 and the control end of the fourth transistor M4 are connected to the first output end and the second output end of the operational amplifier unit 11 through the switch unit. The switch unit is closed in the corresponding conversion period, that is, in the conversion period of the most significant bit MSB, and the number of output control units 13 connected to the first output end and the second output end of the operational amplifier unit 11 can be controlled by controlling the number of closed switch units. When the switch unit is closed, it is equivalent to connecting the first transistor M1 and the third transistor M3 in parallel, and connecting the second transistor M2 and the fourth transistor M4 in parallel, thereby improving the overall current carrying capacity and driving capability.
[0049] The switch unit includes a first switch K1 and a second switch K2, wherein a first end of the first switch K1 is connected to a control end of the third transistor M3, a second end of the first switch K1 is connected to a first output end of the operational amplifier unit 11, a first end of the second switch K2 is connected to a control end of the fourth transistor M4, and a second end of the second switch K2 is connected to a second output end of the operational amplifier unit 11.
[0050] In other embodiments, the first end of the first switch K1 of the downstream output control unit 13 remains connected unchanged, but the second end of the first switch K1 can be connected to the control end of the third transistor M3 of the upstream output control unit 13, and the same applies to the fourth transistor M4. At this time, each first switch K1 and the second switch K2 no longer independently controls the connection between the current output control unit 13 and the output unit 12, and the downstream output control unit 13 can only be connected after the first switch K1 and the second switch K2 of the upstream output control unit 13 are closed.
[0051] like Figure 4 As shown, the conversion control unit 20 includes a plurality of triggers D1, D2, D3 to Dn connected in series, the D input terminal of the first trigger D1 is used to receive the input signal VIN, the Q output terminal of the first trigger D1 is connected to the D input terminal of the next trigger D2, and they are connected in series in sequence, and the CK clock terminals of all triggers D1, D2, D3 to Dn are used to receive the clock signal CLK. Each trigger D1, D2, D3 to Dn is used to generate a corresponding conversion control signal netp based on the clock signal CLK during the conversion phase. <1> 、netp <2> 、netp <3> ~netp <n>.
[0052] like Figure 5 As shown in FIG. 1 , when the input signal VIN is at a high level, it indicates that the analog-to-digital converter ADC has entered the conversion phase. The first trigger D1 generates a high-level conversion control signal netp at the beginning of the first clock cycle after the input signal VIN jumps to a high level. <1> The second flip-flop D2 generates a high-level conversion control signal netp at the beginning of the corresponding second clock cycle. <2> The third flip-flop D3 generates a high-level conversion control signal netp at the beginning of the corresponding third clock cycle. <3> , and so on, until the last trigger Dn generates a high-level conversion control signal netp <n>, so the phase difference between two adjacent conversion control signals is one clock cycle.
[0053] In one embodiment, the first conversion control signal netp <1> The rising edge of the third conversion control signal netp <3> The time between the rising edges of is used as the conversion period TM of the most significant bit MSB of the analog-to-digital converter ADC. The third conversion control signal netp <3> The rising edge of the fourth conversion control signal netp <4> The time between the rising edges of the analog-to-digital converter ADC and the next significant bit MSB-1 is used as the conversion period TM-1, and the fourth conversion control signal netp <4> The rising edge of the fifth conversion control signal netp <5> The time between the rising edges of is used as the conversion period TM-2 of the next significant bit MSB-2 of the analog-to-digital converter ADC, and so on, until the conversion period TL of the least significant bit TL is obtained. It can be seen that the conversion period TM of the most significant bit MSB is equal to two clock cycles of the clock signal CLK, and the conversion periods of other significant bits are equal to one clock cycle of the clock signal CLK. In other embodiments, the conversion period of each significant bit (including the most significant bit MSB) can be set as needed, and the corresponding clock period can be gradually reduced from the conversion period TM of the most significant bit MSB to the conversion period TL of the least significant bit LSB.
[0054] In the analog-to-digital converter ADC, each effective bit corresponds to one or a group of capacitors, and one or a group of capacitors are switched between the ground voltage and the reference voltage VREF through a switch, and the capacitance between each effective bit is different. The capacitance corresponding to the most effective bit is larger than the capacitance corresponding to other effective bits and decreases in sequence. When the most effective bit is converted, a conversion period TM greater than one clock cycle is provided to ensure the conversion time. Even if a kickback (noise) is generated on the reference voltage VREF, enough time can be given to the reference voltage VREF to establish a normal state for subsequent conversion. If a kickback (noise) is generated on the reference voltage VREF at other effective bits, the corresponding conversion period can also be increased.
[0055] In addition, during the conversion phase, the driving capability of the entire buffer can be changed by adjusting the number of connections between the output control unit 13 and the operational amplifier unit 11. Figure 6 and Figure 3 As shown, in the conversion period TM of the most significant bit MSB, the control signals S1, S2~Sn are all high level, indicating that the first switch K1 and the second switch K2 of the switch units of all the output control units 13 are all closed (each control signal can be considered to control the first switch K1 and the second switch K2 of a switch unit), and the driving ability of the buffer is the strongest at this time; in the conversion period TM-1 of the next significant bit MSB-1, the control signals S1, S2~Sn-1 are high level, and the control signal Sn is low level. At this time, the first switch K1 and the second switch K2 of the switch unit of one output control unit 13 are disconnected, and the driving ability of the buffer is correspondingly reduced, and the power consumption is also reduced accordingly, and so on, until the least significant bit LSB is converted, the first switch K1 and the second switch K2 of the switch units of all the output control units 13 are disconnected, the driving ability of the buffer is the weakest, and the power consumption is also the smallest. In other embodiments, all output control units 13 may be connected to the operational amplifier unit 11 only when the most significant bit MSB is converted, while when other significant bits are converted, the number of output control units 13 connected to the operational amplifier unit 11 is fixed (it may be one or a specified number, or there may be no output control unit 13).
[0056] By improving the driving capability of the buffer and providing multiple clock cycles for conversion when each valid bit is converted (especially the most significant bit MSB conversion), the kickback (noise) to the reference voltage VREF and the impact caused by the kickback to the reference voltage VREF during conversion can be reduced, giving enough time for the reference voltage VREF to be re-established to ensure the completion of the conversion, and the same is true for the conversion of each valid bit that will generate a kickback. Based on the improvement of the driving capability of the buffer, the size of the switch used for switching in the analog-to-digital converter ADC can be reduced at the same time. When the conversion is carried out towards the least significant bit LSB, the kickback generated will become smaller and smaller or even disappear. At this time, the driving capability of the buffer is correspondingly reduced, thereby greatly reducing power consumption.
[0057] In one embodiment, the corresponding conversion period can be provided by directly switching the switch used for conversion in the analog-to-digital converter ADC through a conversion control signal, or by controlling the switching of the conversion switch based on the conversion control signal through a controller in conjunction with a software program.
[0058] This embodiment also discloses an analog-to-digital conversion method. Based on the above analog-to-digital conversion circuit, the analog-to-digital conversion method includes:
[0059] The reference voltage VREF is provided through the buffer.
[0060] Specifically, the reference voltage VREF is outputted through the output unit 12 of the buffer buffer based on the output signal of the operational amplifier unit 11 of the buffer buffer.
[0061] In addition, during the conversion stage, based on the conversion period corresponding to each valid bit, the number of output control units 13 in the buffer buffer connected to the output end of the operational amplifier unit 11 is controlled to adjust the driving capability of the buffer buffer, wherein, in the conversion period corresponding to the most significant bit MSB, the number of output control units 13 connected to the output end of the operational amplifier unit 11 is set to be greater than the number of output control units 13 connected to the output end of the operational amplifier unit 11 in the conversion period corresponding to other valid bits.
[0062] In the conversion phase (the input signal VIN is at a high level), the conversion control unit 20 generates a plurality of conversion control signals based on the clock signal CLK, and each conversion period is formed by the conversion control signals.
[0063] The conversion from the most significant bit MSB to the least significant bit LSB is performed based on the reference voltage VREF by the analog-to-digital converter ADC in the corresponding conversion period, wherein the conversions corresponding to all significant bits are not exactly the same, and the conversion period corresponding to the most significant bit MSB is set to be greater than the conversion periods corresponding to other significant bits. In one embodiment, the conversion period corresponding to the most significant bit MSB is set to be greater than one clock cycle of the clock signal CLK.
[0064] Example 2
[0065] like Figure 7 As shown, the difference between this embodiment and embodiment 1 lies in the output unit 12 and the output control unit 13 in the buffer. The output unit 12 includes a first transistor M1 and a first load unit R1, and the first load unit R1 is preferably a resistor. The first end of the first transistor M1 is connected to the power supply voltage, the second end of the first transistor M1 is connected to the first end of the first load unit R1 to form the output end of the output unit 12, the second end of the first load unit R1 is connected to the ground voltage, and the control end of the first transistor M1 is connected to the output end of the operational amplifier unit 11. The first transistor M1 is a P-channel MOS tube, the first end of the first transistor M1 is a source, the second end of the first transistor M1 is a drain, and the control end of the first transistor M1 is a gate.
[0066] In other embodiments, the first end of the first transistor M1 is connected to the ground voltage, the second end of the first transistor M1 is connected to the first end of the first load unit R1 to form the output end of the output unit 12, the second end of the first load unit R1 is connected to the power supply voltage, and the control end of the first transistor M1 is connected to the output end of the operational amplifier unit 11. The first transistor M1 is an N-channel MOS transistor, the first end of the first transistor M1 is a source, the second end of the first transistor M1 is a drain, and the control end of the first transistor M1 is a gate.
[0067] like Figure 7 As shown, the output control unit 13 includes a second transistor M2, a second load unit R2 and a switch unit K1, the second load unit R2 is preferably a resistor, the first end of the second transistor M2 is connected to the power supply voltage, the second end of the second transistor M2 is connected to the first end of the second load unit R2 to form the output end of the output control unit 13, the second end of the second load unit R2 is connected to the ground voltage, the control end of the second transistor M2 is connected to the first end of the switch unit K1, the second end of the switch unit K1 is used to receive the output voltage of the operational amplifier unit 11, and the switch unit K1 is closed in the corresponding conversion period. The second transistor M2 is a P-channel MOS tube, the first end of the second transistor M2 is the source, the second end of the second transistor M2 is the drain, and the control end of the second transistor M2 is the gate.
[0068] In other embodiments, the first end of the second transistor M2 is connected to the ground voltage, the second end of the second transistor M2 is connected to the first end of the second load unit R2 to form the output end of the output control unit 13, the second end of the second load unit R2 is connected to the power supply voltage, the control end of the second transistor M2 is connected to the first end of the switch unit K1, the second end of the switch unit K1 is used to receive the output voltage of the operational amplifier unit 11, and the switch unit K1 is closed in the corresponding conversion period. The second transistor M2 is an N-channel MOS transistor, the first end of the second transistor M2 is the source, the second end of the second transistor M2 is the drain, and the control end of the second transistor M2 is the gate.
[0069] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
[0070] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.< / n> < / n>
Claims
1. An analog-to-digital conversion circuit, characterized in that: include: A buffer for providing a reference voltage; A conversion control unit, used for generating a plurality of conversion control signals based on a clock signal, wherein the conversion control signals are used for forming each conversion period; as well as An analog-to-digital converter is used to convert from the most significant bit to the least significant bit based on a reference voltage in a corresponding conversion period, wherein the conversion periods corresponding to all significant bits are not exactly the same, and the conversion period corresponding to the most significant bit is greater than or equal to the conversion periods corresponding to other significant bits.
2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The conversion time periods corresponding to the effective bits decrease in sequence from the most effective bit to the least effective bit.
3. The analog-to-digital conversion circuit according to claim 1, characterized in that: The buffer includes an operational amplifier unit, an output unit and an output control unit. The output end of the operational amplifier unit is connected to the input end of the output unit. The output unit outputs a reference voltage based on the output signal of the operational amplifier unit. One or more output control units are provided. The output end of the output unit is connected to the output end of the output control unit. The output control unit is used to adjust the driving capability of the buffer based on the connection between itself and the output end of the operational amplifier unit within the corresponding conversion period.
4. The analog-to-digital conversion circuit according to claim 3, characterized in that: The output unit includes a first transistor and a second transistor, the first end of the first transistor is connected to the power supply voltage, the second end of the first transistor is connected to the second end of the second transistor to form the output end of the output unit, the first end of the second transistor is connected to the ground voltage, the control end of the first transistor is connected to the first output end of the operational amplifier unit, and the control end of the second transistor is connected to the second output end of the operational amplifier unit.
5. The analog-to-digital conversion circuit according to claim 3, characterized in that: The output control unit includes a third transistor, a fourth transistor and a switch unit, the first end of the third transistor is connected to the power supply voltage, the second end of the third transistor is connected to the second end of the fourth transistor to form the output end of the output control unit, the first end of the fourth transistor is connected to the ground voltage, the control end of the third transistor and the control end of the fourth transistor are connected to the first output end and the second output end of the operational amplifier unit through the switch unit, and the switch unit is closed in the corresponding conversion period.
6. The analog-to-digital conversion circuit according to claim 3, characterized in that: The output unit comprises a first transistor and a first load unit, the first end of the first transistor is connected to the power supply voltage, the second end of the first transistor is connected to the first end of the first load unit to form the output end of the output unit, the second end of the first load unit is connected to the ground voltage, and the control end of the first transistor is connected to the output end of the operational amplifier unit; or The first end of the first transistor is connected to the ground voltage, the second end of the first transistor is connected to the first end of the first load unit to form the output end of the output unit, the second end of the first load unit is connected to the power supply voltage, and the control end of the first transistor is connected to the output end of the operational amplifier unit.
7. The analog-to-digital conversion circuit according to claim 3, characterized in that: The output control unit comprises a second transistor, a second load unit and a switch unit, wherein a first end of the second transistor is connected to a power supply voltage, a second end of the second transistor is connected to a first end of the second load unit to form an output end of the output control unit, a second end of the second load unit is connected to a ground voltage, a control end of the second transistor is connected to a first end of the switch unit, a second end of the switch unit is used to receive an output voltage of the operational amplifier unit, and the switch unit is closed in a corresponding conversion period; or The first end of the second transistor is connected to the ground voltage, the second end of the second transistor is connected to the first end of the second load unit to form the output end of the output control unit, the second end of the second load unit is connected to the power supply voltage, the control end of the second transistor is connected to the first end of the switch unit, the second end of the switch unit is used to receive the output voltage of the operational amplifier unit, and the switch unit is closed during the corresponding conversion period.
8. The analog-to-digital conversion circuit according to claim 1, characterized in that: The conversion control unit includes a plurality of triggers connected in series, each of which is used to generate a corresponding conversion control signal based on a clock signal during a conversion phase, and the phase difference between two adjacent conversion control signals is one clock cycle.
9. An analog-to-digital conversion method, characterized in that: Based on the analog-to-digital conversion circuit according to any one of claims 1 to 8, the analog-to-digital conversion method comprises: Provide reference voltage through buffer; In the conversion phase, a conversion control unit generates a plurality of conversion control signals based on the clock signal, and each conversion period is formed by the conversion control signals; The conversion from the most significant bit to the least significant bit is performed by an analog-to-digital converter based on a reference voltage in a corresponding conversion period, wherein the conversion periods corresponding to all significant bits are not exactly the same, and the conversion period corresponding to the most significant bit is set to be greater than or equal to the conversion periods corresponding to other significant bits.
10. The analog-to-digital conversion method according to claim 9, characterized in that: Providing a reference voltage through a buffer includes: outputting a reference voltage based on an output signal of the operational amplifier unit of the buffer through an output unit of the buffer; In the conversion stage, based on the conversion period corresponding to each valid bit, the number of output control units connected to the output end of the operational amplifier unit in the buffer is controlled to adjust the driving capability of the buffer, wherein, in the conversion period corresponding to the most significant bit, the number of output control units connected to the output end of the operational amplifier unit is set to be greater than the number of output control units connected to the output end of the operational amplifier unit in the conversion period corresponding to other valid bits.