Method, apparatus, device, system and readable storage medium for data transmission

Abstract

The present application discloses a method, apparatus, device, system and readable storage medium for data transmission. The method for data transmission includes: a first module obtains at least one path of first data encoded by a first FEC; performs conversion processing on the at least one path of first data to obtain at least one path of second data, and the sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data; transmits the obtained at least one path of second data. By performing conversion processing on at least one path of first data to obtain at least one path of second data whose sum of rates is not less than the sum of the rates of at least one path of first data, the method can further perform data transmission at a relatively high rate.

Description

[0001] This application is a divisional application. The application number of the original application is 202111278595.3, and the original application date is October 30, 2021. The entire content of the original application is incorporated herein by reference. Technical Field

[0002] Embodiments of this application relate to the field of communication technologies, and in particular, to a method, apparatus, device, system, and readable storage medium for data transmission. Background Art

[0003] With the continuous increase in the demand for data transmission, the requirement for transmission rate is also constantly rising. For example, in scenarios such as data centers that require low-latency transmission, data needs to be transmitted at a relatively high transmission rate. Therefore, there is an urgent need for a data transmission method to achieve a high transmission rate. Summary of the Invention

[0004] This application provides a method, apparatus, device, system, and readable storage medium for data transmission to improve the data transmission rate.

[0005] In a first aspect, a method for data transmission is provided. The method includes: a first module obtains at least one path of first data encoded with a first forward error correction (FEC) code; performs conversion processing on the at least one path of first data to obtain at least one path of second data, where the sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data; and transmits the obtained at least one path of second data.

[0006] By performing conversion processing on at least one path of first data to obtain at least one path of second data whose sum of rates is not less than the sum of the rates of the at least one path of first data, this method can then transmit data at a relatively high rate.

[0007] In a possible implementation, the first module performs conversion processing on at least one path of first data to obtain at least one path of second data, including: the first module aligns the at least one path of first data and obtains a plurality of first codewords according to the alignment result; decodes the plurality of first codewords and obtains at least one path of second data according to the decoding result.

[0008] In a possible implementation, obtaining at least one path of second data according to the decoding result includes: encoding the decoding result according to a second FEC code type to obtain a plurality of second codewords; and obtaining at least one path of second data according to the plurality of second codewords. For decoding results obtained from different first data, the first module can use the same or different second FEC code types to encode the decoding results to flexibly adapt to transmission scenarios and requirements.

[0009] In a possible implementation manner, obtaining at least one path of second data according to a plurality of second codewords includes: interleaving the plurality of second codewords, and obtaining at least one path of second data according to the interleaving result.

[0010] In a possible implementation manner, the first data includes an alignment flag AM, and the AM is used to align at least one path of first data; encoding the decoding result according to a second FEC code type to obtain a plurality of second codewords, including: deleting the AM in the decoding result, and encoding the decoding result after deleting the AM according to the second FEC code type to obtain a plurality of second codewords.

[0011] In a possible implementation manner, encoding the decoding result after deleting the AM according to the second FEC code type to obtain a plurality of second codewords includes: combining the decoding result after deleting the AM into one path of third data in a sequential sending manner, and encoding the one path of third data to obtain a plurality of second codewords; or converting the decoding result after deleting the AM into at least two paths of third data, and encoding the at least two paths of third data to obtain a plurality of second codewords.

[0012] In a possible implementation manner, converting the decoding result after deleting the AM into at least two paths of third data includes: combining the decoding result after deleting the AM into one path of fourth data, and converting the one path of fourth data into at least two paths of third data.

[0013] In a possible implementation manner, encoding one path of third data to obtain a plurality of second codewords includes: encoding the one path of third data as a whole according to the second FEC code type to obtain a plurality of second codewords; or converting the one path of third data into at least two paths of fifth data, and encoding the at least two paths of fifth data respectively according to the second FEC code type to obtain a plurality of second codewords, where the rate of the fifth data is less than the rate of the third data. This method can encode the third data in different ways to obtain a plurality of second codewords, so that the applicable transmission scenarios and transmission requirements of this method are relatively flexible. In addition, when the number of paths of the third data is multiple, the number of paths of the third data and the second FEC code type used for encoding the third data can be flexibly set to be applicable to different transmission scenarios and transmission requirements.

[0014] In a possible implementation manner, encoding at least two paths of third data to obtain a plurality of second codewords includes: encoding the at least two paths of third data as a whole according to the second FEC code type to obtain a plurality of second codewords; or encoding the at least two paths of third data respectively according to the second FEC code type to obtain a plurality of second codewords.

[0015] In a possible implementation, at least two paths of third data are respectively encoded according to a second FEC code type to obtain a plurality of second codewords, including: encoding at least two paths of third data respectively as a whole according to the second FEC code type to obtain a plurality of second codewords; or, converting at least two paths of third data into at least two paths of sixth data respectively, and encoding at least two paths of sixth data according to the second FEC code type to obtain a plurality of second codewords, where the rate of the sixth data is less than the rate of the third data.

[0016] In a possible implementation, at least one path of second data is obtained according to a decoding result, including: marking error code blocks among a plurality of code blocks included in the decoding result, and obtaining at least one path of second data according to the marked decoding result. Since the first module can mark the error code blocks in the decoding result, when a subsequent receiving-side module receives the second data obtained based on the decoding result, it can effectively correct the data based on the marked error code blocks, so as to improve the error correction performance and the quality of data transmission.

[0017] In a possible implementation, a first module performs conversion processing on at least one path of first data to obtain at least one path of second data, including: the first module aligns at least one path of first data, and obtains a plurality of first codewords according to the alignment result; and obtains at least one path of second data according to the plurality of first codewords.

[0018] In a possible implementation, obtaining at least one path of second data according to a plurality of first codewords includes: combining the plurality of first codewords, and obtaining at least one path of second data according to the combination result.

[0019] In a possible implementation, combining the plurality of first codewords and obtaining at least one path of second data according to the combination result includes: combining the plurality of first codewords into one path of second data in a sequentially transmitted manner; or, combining the plurality of first codewords into at least two paths of second data.

[0020] In a possible implementation, at least one path of first data is data obtained through interleaving, and obtaining a plurality of first codewords according to the alignment result includes: deinterleaving the alignment result, and obtaining a plurality of first codewords according to the deinterleaving result.

[0021] In a possible implementation, a first module processes at least one path of first data to obtain at least one path of second data, including: the first module encodes at least one path of first data according to a second FEC code type to obtain a plurality of third codewords; the first module obtains at least one path of second data based on the plurality of third codewords. Since the first module can re-encode the obtained first data encoded with the first FEC code type through the second FEC code type, the second data has a higher coding gain, and when transmitted in a channel prone to bit errors, it can effectively correct the bit-error data, thereby improving the quality of data transmission.

[0022] In a possible implementation, obtaining at least one path of second data based on the plurality of third codewords includes: interleaving the plurality of third codewords and obtaining at least one path of second data according to the interleaving result.

[0023] In a possible implementation, the first module encodes at least one path of first data according to a second FEC code type to obtain a plurality of third codewords, including: combining at least one path of first data into one path of seventh data in a sequential transmission manner and encoding the one path of seventh data to obtain a plurality of third codewords; or converting at least one path of first data into at least two paths of seventh data and encoding the at least two paths of seventh data to obtain a plurality of third codewords. This method can encode the seventh data in different ways to obtain a plurality of third codewords, so the applicable transmission scenarios and transmission requirements of this method are relatively flexible. In addition, when the number of paths of the seventh data is multiple, the number of paths of the seventh data and the second FEC code type used for encoding the seventh data can be flexibly set to suit different transmission scenarios and transmission requirements.

[0024] In a possible implementation, converting at least one path of first data into at least two paths of seventh data includes: combining at least one path of first data into one path of eighth data and converting the one path of eighth data into at least two paths of seventh data.

[0025] In a possible implementation, encoding one path of seventh data to obtain a plurality of third codewords includes: globally encoding one path of seventh data according to a second FEC code type to obtain a plurality of third codewords; or converting one path of seventh data into at least two paths of ninth data and encoding the at least two paths of ninth data separately according to a second FEC code type to obtain a plurality of third codewords, where the rate of the ninth data is less than the rate of the seventh data.

[0026] In a possible implementation, encoding at least two paths of seventh data to obtain a plurality of third codewords includes: globally encoding the at least two paths of seventh data according to a second FEC code type to obtain a plurality of third codewords; or encoding the at least two paths of seventh data separately according to a second FEC code type to obtain a plurality of third codewords.

[0027] In a possible implementation, at least two seventh data are respectively encoded according to a second FEC code type to obtain a plurality of third codewords, including: encoding at least two seventh data respectively according to the second FEC code type as a whole to obtain a plurality of third codewords; or, converting at least two seventh data into at least two tenth data respectively, and encoding at least two tenth data according to the second FEC code type to obtain a plurality of third codewords, where the rate of the tenth data is less than the rate of the seventh data.

[0028] In a possible implementation, the first module transmits at least one second data, including: the first module inserts synchronization data into at least one second data and transmits the data after the synchronization data is inserted.

[0029] In a possible implementation, the first module inserts synchronization data into at least one second data, including: determining the AM corresponding to each second data in at least one second data; inserting the AM corresponding to each second data into each second data as synchronization data.

[0030] In a possible implementation, the AM corresponding to each second data is obtained by adjusting the AM included in the corresponding first data; or, the AM corresponding to each second data is all the content of the AM included in the corresponding first data; or, the AM corresponding to each second data is part of the content of the AM included in the corresponding first data.

[0031] In a second aspect, a data transmission method is provided, the method including: the third module obtains at least one second data, the at least one second data is data obtained by performing a conversion process on at least one first data, the sum of the rates of the at least one second data is not less than the sum of the rates of the at least one first data, and the first data is data encoded using a first forward error correction code (FEC) code type; the third module performs a conversion process on the at least one second data to obtain at least one first data.

[0032] In a third aspect, a data transmission device is provided, the device is applied to the first module, and the device includes:

[0033] An obtaining unit, configured to obtain at least one first data, where the first data is data encoded using a first forward error correction code (FEC) code type;

[0034] A conversion unit, configured to perform a conversion process on the at least one first data to obtain at least one second data, where the sum of the rates of the at least one second data is not less than the sum of the rates of the at least one first data;

[0035] A transmission unit, configured to transmit at least one second data.

[0036] In a possible implementation, a conversion unit is configured to align at least one path of first data, and obtain a plurality of first codewords according to the alignment result; decode the plurality of first codewords, and obtain at least one path of second data according to the decoding result.

[0037] In a possible implementation, the conversion unit is configured to encode the decoding result according to a second FEC code type to obtain a plurality of second codewords; and obtain at least one path of second data according to the plurality of second codewords.

[0038] In a possible implementation, the conversion unit is configured to interleave the plurality of second codewords, and obtain at least one path of second data according to the interleaving result.

[0039] In a possible implementation, the first data includes an alignment flag AM, and the AM is used to align at least one path of first data; the conversion unit is configured to delete the AM in the decoding result, and encode the decoding result after deleting the AM according to a second FEC code type to obtain a plurality of second codewords.

[0040] In a possible implementation, the conversion unit is configured to merge the decoding result after deleting the AM into one path of third data in a sequential transmission manner, and encode the one path of third data to obtain a plurality of second codewords; or convert the decoding result after deleting the AM into at least two paths of third data, and encode the at least two paths of third data to obtain a plurality of second codewords.

[0041] In a possible implementation, the conversion unit is configured to merge the decoding result after deleting the AM into one path of fourth data, and convert the one path of fourth data into at least two paths of third data.

[0042] In a possible implementation, the conversion unit is configured to perform overall encoding on one path of third data according to a second FEC code type to obtain a plurality of second codewords; or convert the one path of third data into at least two paths of fifth data, and perform encoding on the at least two paths of fifth data respectively according to a second FEC code type to obtain a plurality of second codewords, where the rate of the fifth data is less than the rate of the third data.

[0043] In a possible implementation, the conversion unit is configured to perform overall encoding on at least two paths of third data according to a second FEC code type to obtain a plurality of second codewords; or perform encoding on the at least two paths of third data respectively according to a second FEC code type to obtain a plurality of second codewords.

[0044] In a possible implementation, a conversion unit is configured to perform overall encoding on at least two paths of third data respectively according to a second FEC code type to obtain a plurality of second codewords; or, convert at least two paths of third data into at least two paths of sixth data respectively, and perform encoding on at least two paths of sixth data according to the second FEC code type to obtain a plurality of second codewords, where the rate of the sixth data is less than the rate of the third data.

[0045] In a possible implementation, a conversion unit is configured to mark error code blocks among a plurality of code blocks included in a decoding result, and obtain at least one path of second data according to the marked decoding result.

[0046] In a possible implementation, a conversion unit is configured to align at least one path of first data, and obtain a plurality of first codewords according to the alignment result; and obtain at least one path of second data according to the plurality of first codewords.

[0047] In a possible implementation, a conversion unit is configured to merge a plurality of first codewords, and obtain at least one path of second data according to the merging result.

[0048] In a possible implementation, a conversion unit is configured to merge a plurality of first codewords into one path of second data in a sequential transmission manner; or merge a plurality of first codewords into at least two paths of second data.

[0049] In a possible implementation, a conversion unit is configured to deinterleave an alignment result, and obtain a plurality of first codewords according to the deinterleaving result.

[0050] In a possible implementation, a conversion unit is configured to encode at least one path of first data according to a second FEC code type to obtain a plurality of third codewords; and obtain at least one path of second data according to the plurality of third codewords.

[0051] In a possible implementation, a conversion unit is configured to interleave a plurality of third codewords, and obtain at least one path of second data according to the interleaving result.

[0052] In a possible implementation, a conversion unit is configured to merge at least one path of first data into one path of seventh data in a sequential transmission manner, and encode the one path of seventh data to obtain a plurality of third codewords; or convert at least one path of first data into at least two paths of seventh data, and encode at least two paths of seventh data to obtain a plurality of third codewords.

[0053] In a possible implementation, a conversion unit is configured to merge at least one path of first data into one path of eighth data, and convert the one path of eighth data into at least two paths of seventh data.

[0054] In a possible implementation, a conversion unit is configured to perform overall encoding on one path of seventh data according to a second FEC code type to obtain a plurality of third codewords; or, convert one path of seventh data into at least two paths of ninth data, and perform encoding on the at least two paths of ninth data respectively according to the second FEC code type to obtain a plurality of third codewords, where the rate of the ninth data is less than the rate of the seventh data.

[0055] In a possible implementation, a conversion unit is configured to perform overall encoding on at least two paths of seventh data according to a second FEC code type to obtain a plurality of third codewords; or perform encoding on the at least two paths of seventh data respectively according to the second FEC code type to obtain a plurality of third codewords.

[0056] In a possible implementation, a conversion unit is configured to perform overall encoding on at least two paths of seventh data respectively according to a second FEC code type to obtain a plurality of third codewords; or, convert each of the at least two paths of seventh data into at least two paths of tenth data, and perform encoding on the at least two paths of tenth data respectively according to the second FEC code type to obtain a plurality of third codewords, where the rate of the tenth data is less than the rate of the seventh data.

[0057] In a possible implementation, a transmission unit is configured to insert synchronization data into at least one path of second data and transmit the data after the synchronization data is inserted.

[0058] In a possible implementation, a transmission unit is configured to determine the AM corresponding to each path of second data in at least one path of second data; and insert the AM corresponding to each path of second data into each path of second data as synchronization data.

[0059] In a possible implementation, the AM corresponding to each path of second data is obtained by adjusting the AM included in the corresponding first data; or, the AM corresponding to each path of second data is all the content of the AM included in the corresponding first data; or, the AM corresponding to each path of second data is part of the content of the AM included in the corresponding first data.

[0060] Fourthly, a data transmission device is provided. The device is applied to a third module and includes:

[0061] An acquisition unit is configured to acquire at least one path of second data, where the at least one path of second data is data obtained by performing conversion processing on at least one path of first data, the sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data, and the first data is data encoded using a first forward error correction code (FEC) code type;

[0062] A conversion unit is configured to perform conversion processing on the at least one path of second data to obtain at least one path of first data.

[0063] In a fifth aspect, a device for data transmission is provided. The device includes a processor coupled to a memory. At least one program instruction or code is stored in the memory and is loaded and executed by the processor to enable the device to implement the data transmission method according to any one of the first aspect or the second aspect.

[0064] In a sixth aspect, a data transmission system is provided. The system includes: a first data transmission device for performing the method according to any one of the first aspect or the first aspect, and a second data transmission device for performing the method according to any one of the second aspect or the second aspect.

[0065] In a seventh aspect, a computer-readable storage medium is provided. At least one program instruction or code is stored in the computer-readable storage medium. When the program instruction or code is loaded and executed by a processor, the computer is enabled to implement the data transmission method according to any one of the first aspect or the second aspect.

[0066] Another communication device is provided. The device includes a communication interface, a memory, and a processor. The memory and the processor communicate with each other through an internal connection path. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the communication interface to receive data and control the communication interface to send data. When the processor executes the instructions stored in the memory, the processor is enabled to execute the method according to any one of the first aspect or any possible implementation manner of the first aspect, or execute the method according to any one of the second aspect or any possible implementation manner of the second aspect.

[0067] Exemplarily, the processor is one or more, and the memory is one or more.

[0068] Exemplarily, the memory may be integrated with the processor, or the memory and the processor are separately arranged.

[0069] In a specific implementation process, the memory may be a non-transitory memory, such as a read only memory (ROM). It may be integrated with the processor on the same chip or separately arranged on different chips. The present application does not limit the type of the memory and the arrangement manner of the memory and the processor.

[0070] A computer program (product) is provided. The computer program (product) includes computer program code. When the computer program code is run by a computer, the computer is enabled to execute the methods in the above aspects.

[0071] A chip is provided, which includes a processor for calling and running instructions stored in the memory, so that a device installed with the chip executes the methods in the above aspects.

[0072] Another chip is provided, including: an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The processor is configured to execute code in the memory, and when the code is executed, the processor is configured to execute the methods in the above aspects.

[0073] A device is provided, including the chip according to any one of the above solutions.

[0074] A device is provided, including any one of the first modules in the above solutions, and / or any one of the third modules in the above solutions. Description of the Drawings

[0075] Figure 1 It is a schematic diagram of an implementation scenario of a data transmission method provided by an embodiment of the present application;

[0076] Figure 2 It is a flowchart of a data transmission method provided by an embodiment of the present application;

[0077] Figure 3 It is a schematic diagram of a first data and a second data provided by an embodiment of the present application;

[0078] Figure 4 It is a schematic diagram of another first data and a second data provided by an embodiment of the present application;

[0079] Figure 5 It is a schematic diagram of a process of obtaining at least one path of second data provided by an embodiment of the present application;

[0080] Figure 6 It is a schematic diagram of another process of obtaining at least one path of second data provided by an embodiment of the present application;

[0081] Figure 7 It is a schematic diagram of a process of marking an error code block provided by an embodiment of the present application;

[0082] Figure 8 It is a schematic diagram of another process of marking an error code block provided by an embodiment of the present application;

[0083] Figure 9 It is a schematic diagram of another process of marking an error code block provided by an embodiment of the present application;

[0084] Figure 10 It is a schematic diagram of another process of marking an error code block provided by an embodiment of the present application;

[0085] Figure 11 It is a schematic diagram of a process for merging into the third data provided by an embodiment of the present application;

[0086] Figure 12 It is another schematic diagram of the first data and the second data provided by an embodiment of the present application;

[0087] Figure 13 It is another schematic diagram of the first data and the second data provided by an embodiment of the present application;

[0088] Figure 14 It is a schematic diagram of the implementation environment of an application scenario provided by an embodiment of the present application;

[0089] Figure 15 It is another schematic diagram of the implementation environment of an application scenario provided by an embodiment of the present application;

[0090] Figure 16 It is another schematic diagram of the implementation environment of an application scenario provided by an embodiment of the present application;

[0091] Figure 17 It is another schematic diagram of the implementation environment of an application scenario provided by an embodiment of the present application;

[0092] Figure 18 It is another flowchart of a data transmission method provided by an embodiment of the present application;

[0093] Figure 19 It is a schematic diagram of the structure of a data transmission device provided by an embodiment of the present application;

[0094] Figure 20 It is another schematic diagram of the structure of a data transmission device provided by an embodiment of the present application;

[0095] Figure 21 It is another schematic diagram of the structure of a data transmission device provided by an embodiment of the present application. Detailed implementation manners

[0096] The terms used in the implementation manner part of the present application are only used to explain the embodiments of the present application, rather than intended to limit the present application. The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0097] In the field of communication technology, with the increasing demand for data transmission and the continuous improvement of the requirement for transmission rate, the current transmission rate is gradually difficult to meet the requirement. For example, in scenarios such as data centers that require low-latency transmission, 200 Gigabit Ethernet (GE) / 400GE is gradually difficult to meet the latency requirement, and a higher transmission rate is needed for data transmission, such as 800GE / 1.6T Terabit Ethernet (TE).

[0098] In response to this, an embodiment of the present application provides a data transmission method. This method performs conversion processing on at least one path of first data to obtain at least one path of second data, and the sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data, so as to be able to transmit data at a higher rate. The method provided by the embodiment of the present application is applicable to any one of the end-to-end forward error correction (FEC) architecture, segment-by-segment architecture, and concatenated FEC architecture. Moreover, for the segment-by-segment FEC architecture and the concatenated FEC architecture, the method of the embodiment of the present application can reuse the current modules to save optical fiber, module, and device overhead.

[0099] Figure 1 FIG. shows an implementation scenario of a data transmission method provided by an embodiment of the present application. This implementation scenario includes multiple modules, and information can be exchanged between each module to achieve data transmission. As Figure 1 shown, data can be transmitted between the first module 101 and the second module 102, and between the first module 101 and the third module 103. It should be noted that the implementation scenario as Figure 1 shown can include N modules, where N is a positive integer greater than or equal to 2, Figure 1 and only the case of 3 modules is taken as an example for illustration. In addition, each module can be located within the same chip or in different chips.

[0100] Combined with Figure 1 the implementation scenario shown, the data transmission method provided by the embodiment of the present application is as Figure 2 shown, including but not limited to S201 to S203.

[0101] S201, the first module obtains at least one path of first data, and the first data is data encoded using the first FEC code type.

[0102] The embodiments of the present application do not limit the rate of the first data. In some embodiments, the rate of the first data is any one of 50 gigabits per second (Gb / s), 100 Gb / s, 200 Gb / s, 400 Gb / s, 800 Gb / s, 1.6 terabits per second (Tb / s), 3.2 Tb / s, 6.4 Tb / s, or other non-standard rates. Exemplarily, when the first data is multiplexed, the rates of the multiplexed first data may be the same or different. For example, as Figure 3 shown, the first module obtains four-way first data, and the rates of the four-way first data are all 200 GE. Another example, as Figure 4 shown, the first module obtains four-way first data, and the rates of the four-way first data are 100 GE, 100 GE, 200 GE, and 400 GE respectively.

[0103] In addition, at least one-way first data is data encoded with the same or different first FEC code types. The embodiments of the present application do not limit the first FEC code type. Exemplarily, the first FEC code type is any one of Reed-Solomon (RS) code, Bose-Chaudhuri-Hocquenghem (BCH) code, Fire code, Turbo code, Turbo product code (TPC), Staircase code, and Low-density parity-check (LDPC) code.

[0104] The embodiments of the present application do not limit the manner in which the first module obtains at least one-way first data. Exemplarily, the first module and the second module can perform data transmission, and the first module receives at least one-way first data sent by the second module. For example, the first module is located on the first chip, and the second module is located on the second chip. The first module receives at least one-way first data sent by the second module, including but not limited to the first module receiving the first data sent by the second module through the channel of the attachment unit interface (AUI).

[0105] In addition to being encoded with the first FEC code type, the first data may also undergo other processing. The embodiments of the present application do not limit the processing manner of other processing of the first data other than the first FEC code type encoding. For example, the first data is data encoded with the first FEC code type and distributed through the physical medium attachment sublayer (PMA), or the first data is data encoded with the first FEC code type and subjected to interleaving processing and PMA distribution, etc.

[0106] S202, the first module processes at least one path of first data to obtain at least one path of second data, and the sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data.

[0107] In the embodiments of the present application, the rate of the second data is not limited. In order to achieve data transmission at a higher rate, the sum of the rates of the converted second data is not less than the sum of the rates of the first data before conversion, that is, the sum of the rates of all the first data before conversion is not greater than the sum of the rates of all the second data after conversion. In some embodiments, the rate of the second data is any one of 400 Gb / s, 800 Gb / s, 1.6 Tb / s, 3.2 Tb / s, 6.4 Tb / s, or other non-standard rates. Exemplarily, when the second data is multiplexed, the rates of the multiplexed second data may be the same or different.

[0108] Exemplarily, the first module processes at least one path of first data to obtain at least one path of second data, including but not limited to the following three cases.

[0109] Case 1, for the Segment-by-Segment FEC architecture, the first module processes at least one path of first data to obtain at least one path of second data, including: the first module aligns at least one path of first data, and obtains a plurality of first codewords according to the alignment result; decodes the plurality of first codewords, and obtains at least one path of second data according to the decoding result.

[0110] Exemplarily, the first module aligns at least one path of first data, including but not limited to aligning at least one path of first data separately. For example, the first module converts at least one path of first data into at least one path of first sub-data, and aligns the at least one path of first sub-data belonging to the same path of first data.

[0111] In some embodiments, the first data includes an alignment marker (AM), and the AM is used to align at least one path of first data. For example, for the case where the first data includes an AM, aligning at least one path of first data includes but not limited to AM locking and de-skewing. Among them, AM locking is used to find the codeword boundary, that is, to align at least one path of first data. After finding the codeword boundary, de-skewing can be performed according to the standards, such as the various versions or future versions of IEEE802.3, and then a plurality of first codewords can be obtained. In some embodiments, the first module aligns at least one path of first data, including: the first module converts at least one path of first data into at least one path of first sub-data, and performs AM locking and de-skewing on the at least one path of first sub-data. Exemplarily, aligning at least one path of first data can refer to Figure 5 andFigure 6 The AM locking / de-skewing steps shown.

[0112] Exemplarily, the alignment result of aligning at least one path of first data includes at least one first codeword sequence, and one first codeword sequence corresponds to one path of first data. Exemplarily, when at least one path of first data is non-interleaved data, obtaining a plurality of first codewords according to the alignment result includes, but is not limited to, for each first codeword sequence in at least one first codeword sequence, obtaining a plurality of first codewords according to the code length interval. Exemplarily, when at least one path of first data is interleaved data, obtaining a plurality of first codewords according to the alignment result includes, but is not limited to, de-interleaving the alignment result, and obtaining a plurality of first codewords according to the de-interleaving result. For example, de-interleaving each first codeword sequence in at least one first codeword sequence, and obtaining a plurality of first codewords according to the de-interleaving result. Regarding the interleaving manner of at least one path of first data, the present application does not limit this. For example, the interleaving manner of at least one path of first data includes, but is not limited to, at least one of codeword interleaving or lane interleaving. When de-interleaving the alignment result, corresponding de-interleaving is performed according to the interleaving manner of at least one path of first data. Exemplarily, the step of obtaining a plurality of first codewords may refer to Figure 5 and Figure 6 The steps shown for obtaining FEC1 (first FEC code type) codewords.

[0113] After obtaining a plurality of first codewords, the first module decodes the plurality of first codewords to obtain a decoding result. For example, as Figure 5 and Figure 6 The FEC1 decoding steps shown. In some embodiments, decoding the plurality of first codewords to obtain a decoding result includes, but is not limited to, decoding the plurality of first codewords and discarding the check bits of the plurality of first codewords to obtain a decoding result. That is to say, the decoding result may include the information bits of the plurality of first codewords and does not include the check bits of the plurality of first codewords. Exemplarily, when the first module decodes the plurality of first codewords, the plurality of first codewords are decoded according to the first FEC code type.

[0114] In some embodiments, obtaining at least one path of second data according to the decoding result includes, but is not limited to, S1-1 and S1-2.

[0115] S1-1, encoding the decoding result according to the second FEC code type to obtain a plurality of second codewords.

[0116] The embodiments of the present application do not limit the second FEC code type. Exemplarily, the second FEC code type is any one of RS code, BCH code, Fire code, turbo code, turbo product code, staircase code, and LDPC code. Exemplarily, the decoding result includes decoding results respectively obtained based on each path of first data. When encoding the decoding result according to the second FEC code type, for the decoding results obtained based on different first data, the same or different second FEC code types can be used for encoding, and the embodiments of the present application do not limit this.

[0117] In some embodiments, when the first data includes AM, encoding the decoding result according to the second FEC code type to obtain multiple second codewords includes: deleting the AM in the decoding result, and encoding the decoding result after deleting the AM according to the second FEC code type to obtain multiple second codewords. Regarding the manner of deleting the AM in the decoding result, the embodiments of the present application do not limit this. For example, when obtaining the codeword boundary through AM locking, the position of the AM is obtained, and thus the AM can be deleted according to the position of the AM.

[0118] In some embodiments, obtaining at least one path of second data according to the decoding result includes: marking the error code blocks in the multiple code blocks included in the decoding result, and obtaining at least one path of second data according to the marked decoding result. In a possible implementation manner, performing reverse coding on the multiple code blocks included in the decoding result, marking the error code blocks in the multiple code blocks obtained by reverse coding, and obtaining at least one path of second data according to the multiple code blocks marked with error code blocks. For example, as Figure 7 and Figure 8 shown, the decoding result includes n 257-bit (bit) code block streams. Performing reverse coding on the multiple 257-bit (bit) code block streams to obtain n 66-bit code block streams, marking the error code blocks in the n 66-bit code block streams, and obtaining at least one path of second data according to the n 66-bit code block streams marked with error code blocks.

[0119] In another possible implementation manner, performing reverse coding on the multiple code blocks included in the decoding result, marking the error code blocks in the multiple code blocks obtained by reverse coding, performing transcoding on the multiple code blocks marked with error code blocks, and obtaining at least one path of second data according to the multiple code blocks obtained by transcoding. For example, as Figure 9 and Figure 10 shown, the decoding result includes n 257-bit (bit) code block streams. Performing reverse coding on the n 257-bit (bit) code block streams to obtain n 66-bit code block streams, marking the error code blocks in the n 66-bit code block streams, performing transcoding on the n 66-bit code block streams marked with error code blocks to obtain n 257-bit code block streams, and obtaining at least one path of second data according to the n 257-bit code block streams.

[0120] Optionally, the operation of marking the error code blocks may be performed based on the decoding result after deleting the AM. That is, after deleting the AM in the decoding result, the error code blocks in the decoding result after the deleted AM are marked, and at least one second data is obtained according to the decoding result after deleting the AM and marking the error code blocks. By marking the error code blocks, the error codes introduced by AUI transmission, system noise, etc. are dealt with.

[0121] Exemplarily, encoding the decoding result after deleting the AM according to the second FEC code type to obtain a plurality of second codewords, including but not limited to the following two methods.

[0122] Method 1 for obtaining a plurality of second codewords: The decoding result after deleting the AM is merged into one third data in a sequentially transmitted manner, and the one third data is encoded to obtain a plurality of second codewords.

[0123] Since the decoding result after deleting the AM is merged into one third data in a sequentially transmitted manner, the decoding results after deleting the AM based on each first data included in the third data may appear periodically. For example, the decoding result after deleting the AM includes n 257-bit code block streams, and the n 257-bit code block streams are sequentially transmitted, so that the data belonging to the n 257-bit code block streams in the merged one third data appears periodically. In the embodiments of the present application, the granularity of sequential transmission is not limited, including but not limited to 5440-bit, 5140-bit, 257-bit, 66-bit, 10-bit, 2-bit or 1-bit.

[0124] Exemplarily, for the case where the decoding result after deleting the AM includes the decoding results after deleting the AM corresponding to multiple first data, the decoding results after deleting the AM corresponding to each first data are sequentially transmitted and merged into one third data. For example, the decoding result after deleting the AM includes four code block streams, namely code block stream A, code block stream B, code block stream C, and code block stream D, where code block stream A includes code blocks A.1, A.2, A.3, A.4, A.5, A.6, A.7, etc., code block stream B includes code blocks B.1, B.2, B.3, B.4, B.5, B.6, B.7, etc., code block stream C includes code blocks C.1, C.2, C.3, C.4, C.5, C.6, C.7, etc., and code block stream D includes code blocks D.1, D.2, D.3, D.4, D.5, D.6, D.7, etc. Then, in some embodiments, when the decoding result after deleting the AM is merged into one third data in a sequentially transmitted manner, the code block conditions of each code block stream included in this third data are as Figure 11As shown in (a) of , the order of the code blocks included in the third data is A.1, B.1, C.1, D.1, A.2, B.2, C.2, D.2, A.3, and so on.

[0125] In some embodiments, the decoding results after deleting AM are merged into one path of third data in a sequential transmission manner, including but not limited to: merging the decoding results after deleting AM into one path of third data at a reference rate in a sequential transmission manner. For example, in response to the sum of the rates of the acquired first data being less than the reference rate, the decoding results after deleting AM are merged with the first reference data into one path of third data at the reference rate. If the sum of the rates of the acquired first data is 400GE and the reference rate is 800GE, then the decoding results after deleting AM are merged with the first reference data of 400GE into one path of third data of 800GE. The first reference data can be idle data, which can be set based on the application scenario. The embodiments of the present application do not limit the content of the first reference data. Among them, the reference rate can be set according to experience or actual requirements, and the embodiments of the present application do not limit this. Regarding the method of merging the decoding results after deleting AM with the first reference data into one path of third data at the reference rate, the embodiments of the present application also do not limit this. For example, the decoding results after deleting AM and the first reference data are merged into one path of third data at the reference rate in a sequential transmission manner, or the decoding results after deleting AM are merged, and the merged data is merged with the first reference data into one path of third data at the reference rate in a sequential transmission manner.

[0126] In some embodiments, for the case where the decoding results after deleting AM include the decoding results after deleting AM corresponding to multiple paths of first data, the decoding results after deleting AM are merged into one path of third data at a reference rate in a sequential transmission manner, including: sequentially transmitting the decoding results after deleting AM corresponding to each path of first data and the padding data blocks, and merging them into one path of third data. For example, still taking the decoding results after deleting AM including code block stream A, code block stream B, code block stream C, and code block stream D as an example, the padding data block can be meaningless data, such as pseudo-random binary sequence (PRBS) data, or meaningful overhead. The embodiments of the present application do not limit the content of the padding data block and can be flexibly set based on the application scenario. In some embodiments, when the decoding results after deleting AM and the padding data blocks are merged into one path of third data in a sequential transmission manner, the code block situations of each code block stream included in this path of third data are as Figure 11 shown in (b) of , the order of the code blocks included in the third data is A.1, B.1, C.1, D.1, A.2, padding data block, B.2, C.2, D.2, A.3, and so on.

[0127] In some embodiments, the decoding results after deleting AM are combined into a single third data in a sequential transmission manner, including but not limited to interleaving the decoding results after deleting AM, and combining the interleaved decoding results after deleting AM into a single third data in a sequential transmission manner. The present application does not limit the interleaving method of the decoding results after deleting AM. Exemplarily, the method of combining the decoding results after deleting AM into a single third data can refer to Figure 5 the steps of data interleaving and distribution shown.

[0128] Exemplarily, encoding a single third data to obtain multiple second codewords includes but is not limited to: globally encoding a single third data according to a second FEC code type to obtain multiple second codewords; or, converting a single third data into at least two fifth data, and encoding the at least two fifth data separately according to the second FEC code type to obtain multiple second codewords, where the rate of the fifth data is less than the rate of the third data. For example, the third data is a single 800GE data, and globally encoding the third data according to the second FEC code type to obtain multiple second codewords; or, converting the third data into two 400GE fifth data, and encoding the two fifth data separately according to the second FEC code type to obtain multiple second codewords. Exemplarily, global encoding is used to encode the data to be encoded as a single data. The present application does not limit the method of converting a single third data into at least two fifth data. For example, converting a single third data into at least two fifth data in a sequential transmission manner. The step of encoding a single third data to obtain multiple second codewords can refer to Figure 5 the FEC2 (second FEC code type) encoding and processing steps shown.

[0129] Among them, global encoding means combining multiple data into a single data for encoding, or in other words, global encoding is used to encode the data to be encoded as a single data. Therefore, globally encoding a single third data according to the second FEC code type means encoding a single third data as a single data.

[0130] The second way to obtain multiple second codewords: convert the decoding results after deleting AM into at least two third data, and encode the at least two third data to obtain multiple second codewords.

[0131] Exemplarily, the rate of the third data may be the reference rate. The number of channels of the third data and the reference rate may be set according to experience or actual requirements, and the embodiments of the present application do not limit them. In some embodiments, the decoding result after deleting AM is converted into at least two channels of third data in a sequential sending manner. Exemplarily, converting the decoding result after deleting AM into at least two channels of third data includes, but is not limited to, interleaving the decoding result after deleting AM, and converting the interleaved decoding result after deleting AM into at least two channels of third data. The present application does not limit the interleaving method of the decoding result after deleting AM. Exemplarily, the method of converting the decoding result after deleting AM into at least two channels of third data may refer to Figure 6 the steps of data interleaving and distribution shown.

[0132] Exemplarily, in the case where the sum of the rates of at least one channel of first data is less than the sum of the rates of at least two channels of third data, the decoding result after deleting AM and the second reference data are jointly converted into at least two channels of third data with the reference rate. For example, the rates of the four channels of first data obtained are 400GE, 400GE, 400GE, and 200GE, and the reference rate is 800GE. The decoding result after deleting AM and the second reference data of 200GE are jointly converted into two channels of third data with a rate of 800GE. Another example, the rate of one channel of first data obtained is 1.6TE, and the reference rate is 800GE. The decoding result after deleting AM and the second reference data of 1.6TE are jointly converted into four channels of third data with a rate of 800GE. The second reference data may be idle data, which can be set based on the application scenario. The embodiments of the present application do not limit the content of the second reference data. Exemplarily, the second reference data may include multiple padding data blocks, and the embodiments of the present application do not limit the situation of the padding data blocks included in each channel of the at least two channels of third data.

[0133] Exemplarily, in the case where the sum of the rates of at least one channel of first data is equal to the sum of the rates of at least two channels of third data, the decoding result after deleting AM is converted into at least two channels of third data. For example, as Figure 12 shown, the rates of the four channels of first data obtained are all 400GE, and the decoding result after deleting AM is converted into two channels of third data with a rate of 800GE. Another example, as Figure 13 shown, the rate of one channel of first data obtained is 1.6TE, and the decoding result after deleting AM is converted into two channels of third data with a rate of 800GE.

[0134] In some embodiments, for the case where the number of paths of the first data is multiple, for any one of at least two paths of the third data, this one path of the third data may only include the decoding result after deleting AM of some of the first data, or include the decoding result after deleting AM of each path of the first data. For example, still taking the decoding result after deleting AM including code block streams A, B, C, and D as an example. In some embodiments, when merging the decoding results after deleting AM into two paths of third data in a sequential sending manner, the code block situations of each code block stream included in the two paths of third data are as shown in Figure 11 shown in (c) of. The order of the code blocks included in one path of the third data is A.1, C.1, A.2, C.2, A.3, C.3, A.4, C.4, A.5, etc., and the order of the code blocks included in the other path of the third data is B.1, D.1, B.2, D.2, B.3, D.3, B.4, D.4, B.5, etc. It should be noted that Figure 11 only takes (c) of as an example to merge code block stream A and code block stream C into one path of the third data, and code block stream B and code block stream D are merged into one path of the third data for illustration, but it does not limit the implementation manner. Each path of the third data can be formed by arbitrarily converging two code block streams.

[0135] In other embodiments, when merging the decoding results after deleting AM into two paths of third data in a sequential sending manner, the code block situations of each code block stream included in the two paths of third data are as shown in Figure 11 shown in (d) of. The order of the code blocks included in one path of the third data is A.1, B.1, C.1, D.1, A.3, B.3, C.3, D.3, A.5, etc., and the order of the code blocks included in the other path of the third data is A.2, B.2, C.2, D.2, A.4, B.4, C.4, D.4, A.6, etc.

[0136] In addition, in the process of merging to obtain the third data in the manners shown in (a), (c), and (d) of the above Figure 11 , it may also include sequentially sending the padding data blocks and the data to be merged. The specific process can refer to the manner shown in (b) of Figure 11 , which will not be elaborated here one by one. Optionally, the padding data blocks are not necessarily sent periodically, and can also be sent at different intervals. For example, one padding data block is sent after a certain number of data, or multiple padding data blocks are inserted after a certain number of data.

[0137] Exemplarily, the decoding result after deleting AM is converted into at least two paths of third data, including: merging the decoding result after deleting AM into one path of fourth data, and converting one path of fourth data into at least two paths of third data. For example, if the four paths of first data obtained are all 400GE data, the decoding result after deleting AM is merged into one path of 1.6TE fourth data, and this one path of 1.6TE fourth data is converted into two paths of 800GE third data.

[0138] When encoding at least two paths of third data, either overall encoding or separate encoding can be used. Exemplarily, encoding at least two paths of third data to obtain multiple second codewords includes: overall encoding at least two paths of third data according to the second FEC code type to obtain multiple second codewords; or separately encoding at least two paths of third data according to the second FEC code type to obtain multiple second codewords. The step of encoding at least two paths of third data to obtain multiple second codewords can refer to Figure 6 the FEC2 (second FEC code type) encoding and processing steps shown.

[0139] In some embodiments, separately encoding at least two paths of third data according to the second FEC code type to obtain multiple second codewords includes: overall encoding at least two paths of third data separately according to the second FEC code type to obtain multiple second codewords; or converting each of at least two paths of third data into at least two paths of sixth data, and separately encoding at least two paths of sixth data according to the second FEC code type to obtain multiple second codewords, where the rate of the sixth data is less than the rate of the third data. Regarding the process of converting each of at least two paths of third data into at least two paths of sixth data and separately encoding at least two paths of sixth data according to the second FEC code type, it has the same principle as the related process in Method 1 of obtaining multiple second codewords where one path of third data is converted into at least two paths of fifth data and separately encoded according to the second FEC code type, which will not be elaborated here. Among them, overall encoding means merging multiple paths of data into one path of data for encoding, or in other words, overall encoding is used to encode the data to be encoded as one path of data. Therefore, overall encoding at least two paths of third data according to the second FEC code type means encoding all the third data in at least two paths of third data as one path of data.

[0140] The method provided in the embodiments of the present application can encode the third data in different ways to obtain multiple second codewords, so that the applicable transmission scenarios and transmission requirements of the method are relatively flexible. In addition, when the number of paths of the third data is multiple, the number of paths of the third data and the second FEC code type used for encoding the third data can be flexibly set to be applicable to different transmission scenarios and transmission requirements.

[0141] S1-2. Obtain at least one path of second data according to multiple second codewords.

[0142] Exemplarily, obtaining at least one path of second data according to multiple second codewords includes, but is not limited to, interleaving the multiple second codewords and obtaining at least one path of second data according to the interleaving result. Regarding the manner of interleaving the multiple second codewords, embodiments of the present application do not impose limitations. For example, at least one of codeword interleaving or lane interleaving is performed on the multiple second codewords.

[0143] Case 2. The first module aligns at least one path of first data, and obtains multiple first codewords according to the alignment result; obtains at least one path of second data according to the multiple first codewords.

[0144] Among them, the manner in which the first module aligns at least one path of first data and obtains multiple first codewords according to the alignment result is the same as the relevant process principle in the above-mentioned Mode 1, and will not be elaborated here.

[0145] Exemplarily, obtaining at least one path of second data according to multiple first codewords includes: combining the multiple first codewords and obtaining at least one path of second data according to the combination result. For example, combining the multiple first codewords and obtaining at least one path of second data according to the combination result includes, but is not limited to, the following two manners.

[0146] Combination Mode 1. Combine the multiple first codewords into one path of second data in a sequential transmission manner.

[0147] Since the multiple first codewords are combined into one path of second data in a sequential transmission manner, the multiple first codewords obtained based on each path of first data included in this second data can appear periodically. Among them, the manner of combining the multiple first codewords into one path of second data in a sequential transmission manner is the same as the relevant process principle of combining the decoding results after deleting AM into one path of third data in a sequential transmission manner, and will not be elaborated here.

[0148] Combination Mode 2. Combine the multiple first codewords into at least two paths of second data.

[0149] Exemplarily, the manner of combining the multiple first codewords into at least two paths of second data is the same as the relevant process principle of converting the decoding results after deleting AM into at least two paths of third data, and will not be elaborated here.

[0150] It should be noted that regardless of which of the above combination manners, this second data can be interleaved data, and embodiments of the present application do not impose limitations on the interleaving manner.

[0151] In Case 3, the first module encodes at least one path of first data according to the second FEC code type to obtain multiple third codewords; the first module obtains at least one path of second data based on the multiple third codewords.

[0152] Exemplarily, the first module encodes at least one path of first data according to the second FEC code type to obtain multiple third codewords, including but not limited to the following two methods.

[0153] Method 1 for obtaining multiple third codewords: Combine at least one path of first data into one path of seventh data in a sequential transmission manner, and encode the one path of seventh data to obtain multiple third codewords.

[0154] In some embodiments, combining at least one path of first data into one path of seventh data in a sequential transmission manner includes but is not limited to: the first module aligns at least one path of first data, obtains multiple first codewords according to the alignment result, and combines the multiple first codewords into one path of seventh data in a sequential transmission manner. The embodiment of the present application does not limit the granularity of sequential transmission, including but not limited to 5440-bit, 5140-bit, 257-bit, 66-bit, 10-bit, 2-bit or 1-bit. Regarding the method of the first module aligning at least one path of first data and obtaining multiple first codewords according to the alignment result, the relevant process principle is the same as that in Method 1 above, and will not be elaborated here.

[0155] In some embodiments, combining at least one path of first data into one path of seventh data in a sequential transmission manner includes but is not limited to: combining at least one path of first data into one path of seventh data at a reference rate in a sequential transmission manner. For example, in response to the sum of the rates of the acquired first data being less than the reference rate, combine at least one path of first data with third reference data into one path of seventh data at the reference rate. If the sum of the acquired first data rates is 400GE and the reference rate is 800GE, then combine at least one path of first data with 400GE of third reference data into one path of 800GE of seventh data. The third reference data may be idle data. The embodiment of the present application does not limit the content of the third reference data. For example, determine the third reference data based on the application scenario. It should be noted that the reference rate can be set according to experience or actual needs, and the embodiment of the present application does not limit this. Regarding the method of combining at least one path of first data with third reference data into one path of seventh data at the reference rate, the embodiment of the present application also does not limit it. For example, combine at least one path of first data and third reference data into one path of seventh data at the reference rate in a sequential transmission manner, or combine at least one path of first data, and then combine the combined data with third reference data into one path of seventh data at the reference rate in a sequential transmission manner.

[0156] Exemplarily, encoding a path of seventh data to obtain multiple third codewords, including but not limited to: overall encoding a path of seventh data according to a second FEC code type to obtain multiple third codewords; or, converting a path of seventh data into at least two paths of ninth data, and encoding the at least two paths of ninth data respectively according to the second FEC code type to obtain multiple third codewords, wherein the rate of the ninth data is less than the rate of the seventh data. For example, the seventh data is a path of 800GE data, overall encoding the seventh data according to the second FEC code type to obtain multiple third codewords; or, converting the seventh data into two paths of 400GE ninth data, and encoding the two paths of ninth data respectively according to the second FEC code type to obtain multiple third codewords. Exemplarily, overall encoding is used to encode the data to be encoded as a single path of data. The present application does not limit the manner of converting a path of seventh data into at least two paths of ninth data. For example, converting a path of first data into at least two paths of ninth data in a sequential transmission manner.

[0157] The second way to obtain multiple third codewords is to convert at least one path of first data into at least two paths of seventh data, and encode the at least two paths of seventh data to obtain multiple third codewords.

[0158] Exemplarily, the rate of the seventh data can be a reference rate, and the number of paths and the reference rate of the seventh data can be set according to experience or actual requirements, which are not limited in the embodiments of the present application. In some embodiments, at least one path of first data is converted into at least two paths of seventh data in a sequential transmission manner.

[0159] Exemplarily, when the sum of the rates of at least one path of first data is less than the sum of the rates of at least two paths of seventh data, at least one path of first data and fourth reference data are jointly converted into at least two paths of seventh data with the reference rate. For example, the rates of the four paths of first data obtained are 400GE, 400GE, 400GE, and 200GE, and the reference rate is 800GE. At least one path of first data and 200GE of fourth reference data are jointly converted into two paths of 800GE of seventh data. Another example, the rate of one path of first data obtained is 1.6TE, and the reference rate is 800GE. At least one path of first data and 1.6TE of fourth reference data are jointly converted into four paths of 800GE of seventh data.

[0160] Exemplarily, when the sum of the rates of at least one path of first data is equal to the sum of the rates of at least two paths of seventh data, at least one path of first data is converted into at least two paths of seventh data.

[0161] In some embodiments, for the case where the number of paths of the first data is multiple, for any one path of the at least two paths of seventh data, the any one path of seventh data may only include data of part of the first data or include data of each path of the first data.

[0162] Exemplarily, converting at least one path of first data into at least two paths of seventh data includes: combining at least one path of first data into one path of eighth data, and converting one path of eighth data into at least two paths of seventh data. For example, the four paths of first data obtained are all 400GE data, combining the four paths of first data into one path of 1.6TE eighth data, and converting the one path of 1.6TE eighth data into two paths of 800GE seventh data.

[0163] When encoding at least two paths of seventh data, either overall encoding or separate encoding can also be used. Exemplarily, encoding at least two paths of seventh data to obtain a plurality of third codewords includes: overall encoding at least two paths of seventh data according to the second FEC code type to obtain a plurality of third codewords; or separately encoding at least two paths of seventh data according to the second FEC code type to obtain a plurality of third codewords.

[0164] In some embodiments, separately encoding at least two paths of seventh data according to the second FEC code type to obtain a plurality of third codewords includes: overall encoding at least two paths of seventh data according to the second FEC code type to obtain a plurality of third codewords; or converting each of at least two paths of third data into at least two paths of tenth data, and separately encoding at least two paths of tenth data according to the second FEC code type to obtain a plurality of third codewords, where the rate of the tenth data is less than the rate of the seventh data. Regarding the process of converting each of at least two paths of seventh data into at least two paths of tenth data and separately encoding at least two paths of tenth data according to the second FEC code type, the relevant process principle is the same as that of converting one path of seventh data into at least two paths of ninth data and separately encoding at least two paths of ninth data according to the second FEC code type in the first method of obtaining a plurality of third codewords above, and will not be elaborated here.

[0165] Exemplarily, obtaining at least one path of second data according to a plurality of third codewords includes but is not limited to interleaving the plurality of third codewords, and obtaining at least one path of second data according to the interleaving result. Regarding the method of interleaving the plurality of third codewords, the embodiments of the present application do not limit it. For example, at least one of codeword interleaving or lane - to - lane interleaving of the plurality of third codewords.

[0166] The method provided by the embodiments of the present application can encode the seventh data in different ways to obtain a plurality of third codewords, so that the applicable transmission scenarios and transmission requirements of the method are relatively flexible. In addition, when the number of paths of the seventh data is multiple, the number of paths of the seventh data and the second FEC code type used for encoding the seventh data can be flexibly set to be applicable to different transmission scenarios and transmission requirements.

[0167] S203. The first module transmits at least one path of second data.

[0168] Exemplarily, the first module transmits at least one path of second data, including: the first module inserts synchronization data into at least one path of second data and transmits the data after the synchronization data is inserted. The synchronization data includes, but is not limited to, at least one of AM, coherent digital signal processing (DSP) frame header, training symbol, or pilot symbol.

[0169] In some embodiments, the first module inserts synchronization data into at least one path of second data, including: determining the AM corresponding to each path of second data in at least one path of second data; using the AM corresponding to each path of second data as the synchronization data to insert into each path of second data. Exemplarily, the AM corresponding to each path of second data is obtained by adjusting the AM included in the corresponding first data; or, the AM corresponding to each path of second data is all the content of the AM included in the corresponding first data; or, the AM corresponding to each path of second data is part of the content of the AM included in the corresponding first data. Among them, adjusting the AM included in the corresponding first data includes, but is not limited to, adjusting the AM content or length according to different granularities.

[0170] In some embodiments, when the acquired first data is multiple paths of first data, the AM included in any one path of first data among the multiple paths of first data can be used as the AM corresponding to any one path of second data. It should be noted that the AMs corresponding to each path of second data can be the same or different. For example, the AMs of each path of second data can be determined respectively according to actual requirements.

[0171] Exemplarily, when the first module transmits at least one path of second data, other processing can also be performed, such as multiplexing (mux) the at least one path of second data, inserting a training sequence (TS) / pilot symbol, adjusting the frequency point, optical modulation, etc., and transmitting the at least one path of second data after the processing. Whether the data transmitted by the first module is the data after the synchronization data is inserted or the data after other processing, the multiplexing granularity adopted by the first module when transmitting data includes, but is not limited to, FEC codeword, 257-bit, 66-bit, 10-bit, or 1-bit, and the embodiments of the present application do not limit this.

[0172] The method provided by the embodiment of the present application can obtain at least one path of second data whose rate sum is not less than the rate sum of at least one path of first data by performing conversion processing on at least one path of first data, and thus can perform data transmission at a relatively high rate. In addition, since the first module can re-encode the obtained first data encoded with the first FEC code type through the second FEC code type, the second data has a higher coding gain, and can effectively correct the data with errors when transmitted in a channel prone to errors, thereby improving the quality of data transmission.

[0173] Next, in combination with the Figure 2 method flow shown above, taking the first module being located on the first chip and the second module being located on the second chip as examples for the following several scenarios, the data transmission method provided by the embodiment of the present application will be illustrated.

[0174] Scenario 1: The first chip and the second chip are applied to a segmented FEC architecture.

[0175] Exemplarily, Scenario 1 corresponds to Figure 2 Case 1 in the shown embodiment. The implementation environment of this scenario can be as Figure 14 shown, and the process of data transmission is as follows.

[0176] The second chip transmits eight paths of first data to the first chip via AUI. The media access control (MAC) rate of the first data is 100 Gb / s, and the first data are all encoded with the RS(544, 514) FEC code pattern. The second chip transmits one path of first data via one AUI, and the transmission rate is 106.25 Gb / s. The first chip includes eight processing units, and each processing unit is used to process one path of first data. After receiving the eight paths of first data, the first chip performs AM locking on each path of first data respectively to align the first data and obtain multiple first codewords. Since the first data are encoded with the RS(544, 514) FEC code pattern, the multiple first codewords are codewords encoded with the RS(544, 514) FEC code pattern. Exemplarily, when the first data are data obtained through interleaving, the first chip performs AM locking on the first data, and after obtaining the alignment result, performs de-interleaving on the alignment result to obtain multiple first codewords according to the de-interleaving. After the first chip obtains multiple first codewords, it decodes the multiple first codewords. In a possible implementation manner, the first chip performs interleaving on the decoding result and obtains at least one path of second data according to the interleaved decoding result. After the first chip obtains the decoding result, it deletes the AM in the decoding result, where the AM can be used to determine the AM corresponding to each path of second data in at least one path of second data. It should be noted that the first chip can process each path of first data simultaneously or first process one path of first data and then process other paths of first data. The embodiments of the present application do not limit this.

[0177] Further, the first chip merges the decoding result after deleting the AM. For example, the decoding result after deleting the AM is merged into one path of 800GE third data in a sequential sending manner, or the decoding result after deleting the AM is converted into at least two paths of 800GE third data. The first chip performs data processing on the third data. For example, it encodes the third data to obtain multiple second codewords and obtains at least one path of second data according to the multiple second codewords.

[0178] Finally, the first chip inserts the AM as synchronization data into at least one path of second data; performs transmitter (TX) DSP on the data after inserting the synchronization data to obtain 800G coherent light.

[0179] In another possible implementation manner, the implementation environment of this scenario is as Figure 15 shown, and the data transmission process is as follows.

[0180] The second chip transmits a first data to the first chip via AUI. The MAC rate of the first data is 1.6 Tb / s, and the first data is data encoded and interleaved in the 2xRS(544, 514) FEC code pattern. The second chip transmits the first data via 16 AUIs. Among them, one AUI is used for one first sub-data, and the transmission rate is 106.25 Gb / s. After receiving the first data, the first chip performs AM locking / de-skewing on the first data to align the first data, obtaining multiple first codewords. Since the first data is data encoded in the RS(544, 514) FEC code pattern, the multiple first codewords are codewords encoded in the RS(544, 514) FEC code pattern. Exemplarily, in the case where the first data is data obtained through interleaving, the first chip performs AM locking on the first data. After obtaining the alignment result, the first chip performs de-interleaving on the alignment result, and obtains multiple first codewords according to the de-interleaving. After the first chip obtains multiple first codewords, the first chip decodes the multiple first codewords. In a possible implementation manner, the first chip interleaves the decoding result, and obtains at least one second data according to the interleaved decoding result. After the first chip obtains the decoding result, the first chip deletes the AM in the decoding result, where the AM can be used to determine the AM corresponding to each second data in at least one second data.

[0181] Further, the first chip distributes the decoded result after deleting the AM. For example, the decoded result after deleting the AM is converted into two 800GE third data. The first chip processes the two third data. For example, the first chip encodes the two third data to obtain multiple second codewords, and obtains two second data according to the multiple second codewords. It should be noted that the processing of the two third data can be the same or different.

[0182] After that, the first chip inserts the AM as synchronization data into the two second data; performs TX DSP on the data after inserting the synchronization data, and obtains two 800G coherent lights. Among them, the processing of the two second data can be the same or different, so that the wavelengths of the two 800G coherent lights obtained can be the same or different.

[0183] Scenario 2: The first chip and the second chip are applied to an end-to-end FEC architecture.

[0184] Exemplarily, this Scenario 2 corresponds to Figure 2 Case 2 in the shown embodiment. The implementation environment of this scenario is as Figure 16 shown, and the process of data transmission is as follows.

[0185] The second chip transmits eight paths of first data to the first chip via AUI. The MAC rate of all the first data is 100 Gb / s, and all the first data are data encoded with the RS(544, 514) FEC code type. The second chip transmits one path of first data via one AUI, and the transmission rate is 106.25 Gb / s. The first chip includes eight processing units, and each processing unit is used to process one path of first data. After receiving the eight paths of first data, the first chip performs AM locking on each path of first data respectively to align the first data and obtain multiple first codewords. Since the first data are data encoded with the RS(544, 514) FEC code type, the multiple first codewords are codewords encoded with the RS(544, 514) FEC code type. Exemplarily, in the case where the first data are data obtained through interleaving, after the first chip performs AM locking on the first data to obtain an alignment result, the first chip performs deinterleaving on the alignment result to obtain multiple first codewords according to the deinterleaving. The processing of each path of first data by the first chip can be executed simultaneously or first execute the processing of one path of first data and then execute the processing of other paths of first data, which is not limited in the embodiments of the present application.

[0186] Further, the first chip merges the multiple first codewords. For example, the multiple first codewords are merged into one path of 800GE second data in a sequential transmission manner, or the multiple first codewords are converted into at least two paths of 800GE second data. Finally, the first chip performs TX DSP on at least one path of second data to obtain 800G coherent light.

[0187] Scenario three: The first chip and the second chip are applied to a cascaded FEC architecture.

[0188] Exemplarily, this scenario three corresponds to Figure 2 Case three in the shown embodiment. The implementation environment of this scenario is as Figure 17 shown, and the data transmission process is as follows.

[0189] The second chip transmits eight paths of first data to the first chip through AUI. The MAC rate of the first data is 100 Gb / s, and the first data are all data encoded with the RS(544, 514) FEC code pattern. The second chip transmits one path of first data through one AUI, and the transmission rate is 106.25 Gb / s. The first chip includes eight processing units, and each processing unit is used to process one path of first data. After receiving the eight paths of first data, the first chip performs AM locking on each path of first data respectively to align the first data and obtain multiple first codewords. Since the first data are data encoded with the RS(544, 514) FEC code pattern, the multiple first codewords are codewords encoded with the RS(544, 514) FEC code pattern. Exemplarily, when the first data are data obtained through interleaving, the first chip performs AM locking on the first data, and after obtaining the alignment result, performs deinterleaving on the alignment result, and obtains multiple first codewords according to the deinterleaving. The processing of each path of first data by the first chip can be executed simultaneously or first execute the processing of one path of first data and then execute the processing of other paths of first data, which is not limited in the embodiments of the present application.

[0190] Further, the first chip combines the multiple first codewords obtained based on each path of first data. For example, combines the multiple first codewords into one path of 800GE seventh data, or converts the multiple first codewords into at least two paths of 800GE seventh data. The first chip performs data processing on the seventh data. For example, encodes the seventh data to obtain multiple third codewords, and obtains at least one path of second data according to the multiple third codewords.

[0191] After that, the first chip performs TX DSP on at least one path of second data to obtain 800G coherent light.

[0192] The above uses the first module as an example to illustrate the data transmission method. Next, after the first module transmits at least one path of second data, the data transmission process of the third module is described. As Figure 18 shown, the data transmission method includes the following steps.

[0193] S1801, the third module obtains at least one path of second data. The at least one path of second data is data obtained by performing conversion processing on at least one path of first data. The sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data. The first data are data encoded with the first FEC code pattern.

[0194] Combined with Figure 1 the implementation environment shown, the third module obtains at least one path of second data sent by the first module. Combined with Figure 2In the embodiments shown, there are multiple ways for the first module to obtain at least one path of second data. The embodiments of the present application will not elaborate on them one by one here. Please refer to the content of the above Figure 2 shown embodiments.

[0195] S1802. The third module performs conversion processing on at least one path of second data to obtain at least one path of first data.

[0196] Since there are multiple ways for the first module to obtain at least one path of second data, there are also multiple situations for the second data. For different situations of the second data, the third module can adopt different processing methods. For example, for the situation where the second data is data encoded using the second FEC code type, the third module decodes the second data according to the second FEC code type to obtain the decoded data.

[0197] After that, the third module can further process the decoded data. The embodiments of the present application do not limit the processing method of the third module for the second data. For example, the decoded data is continuously sent to other modules. In addition, the third module can be located in the third chip, and the first module is located in the first chip. The third module receives at least one path of second data sent by the first module through AUI.

[0198] The method provided by the embodiments of the present application obtains at least one path of first data with a sum of rates not greater than the sum of the rates of at least one path of second data by performing conversion processing on at least one path of second data, thereby enabling data transmission at a higher rate. In addition, since the second data can be data encoded using the first FEC code type and the second FEC code type, effective error correction can be performed on the data with errors when transmitting in a channel prone to errors by decoding using the second FEC code type, thereby improving the quality of data transmission.

[0199] The embodiments of the present application also provide a data transmission device. Figure 19 is a schematic structural diagram of a data transmission device provided by the embodiments of the present application. Based on Figure 19 the following multiple units shown, Figure 19 the data transmission device shown can perform all or part of the operations performed by the first module. It should be understood that the device may include more additional units than the units shown or omit some of the units shown. The embodiments of the present application do not limit this. As Figure 19 shown, the device includes:

[0200] An acquisition unit 1901, configured to acquire at least one path of first data, where the first data is data encoded using the first forward error correction code (FEC) code type;

[0201] A conversion unit 1902, configured to perform conversion processing on at least one path of first data to obtain at least one path of second data, and the sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data;

[0202] A transmission unit 1903, configured to transmit at least one path of second data.

[0203] In a possible implementation manner, the conversion unit 1902 is configured to align at least one path of first data, and obtain a plurality of first codewords according to the alignment result; decode the plurality of first codewords, and obtain at least one path of second data according to the decoding result.

[0204] In a possible implementation manner, the conversion unit 1902 is configured to encode the decoding result according to a second FEC code type to obtain a plurality of second codewords; and obtain at least one path of second data according to the plurality of second codewords.

[0205] In a possible implementation manner, the conversion unit 1902 is configured to perform interleaving on the plurality of second codewords, and obtain at least one path of second data according to the interleaving result.

[0206] In a possible implementation manner, the first data includes an alignment flag AM, and AM is used to align at least one path of first data; the conversion unit 1902 is configured to delete AM in the decoding result, and encode the decoding result after deleting AM according to a second FEC code type to obtain a plurality of second codewords.

[0207] In a possible implementation manner, the conversion unit 1902 is configured to merge the decoding result after deleting AM into one path of third data in a sequential sending manner, and encode the one path of third data to obtain a plurality of second codewords; or, convert the decoding result after deleting AM into at least two paths of third data, and encode the at least two paths of third data to obtain a plurality of second codewords.

[0208] In a possible implementation manner, the conversion unit 1902 is configured to merge the decoding result after deleting AM into one path of fourth data, and convert the one path of fourth data into at least two paths of third data.

[0209] In a possible implementation manner, the conversion unit 1902 is configured to perform overall encoding on one path of third data according to a second FEC code type to obtain a plurality of second codewords; or, convert one path of third data into at least two paths of fifth data, and encode the at least two paths of fifth data respectively according to a second FEC code type to obtain a plurality of second codewords, where the rate of the fifth data is less than the rate of the third data.

[0210] In a possible implementation, the conversion unit 1902 is configured to perform overall encoding on at least two paths of third data according to a second FEC code type to obtain a plurality of second codewords; or perform encoding on at least two paths of third data separately according to the second FEC code type to obtain a plurality of second codewords.

[0211] In a possible implementation, the conversion unit 1902 is configured to perform overall encoding on at least two paths of third data separately according to a second FEC code type to obtain a plurality of second codewords; or convert each of at least two paths of third data into at least two paths of sixth data, and perform encoding on at least two paths of sixth data separately according to the second FEC code type to obtain a plurality of second codewords, where the rate of the sixth data is less than the rate of the third data.

[0212] In a possible implementation, the conversion unit 1902 is configured to mark error code blocks among a plurality of code blocks included in a decoding result, and obtain at least one path of second data according to the marked decoding result.

[0213] In a possible implementation, the conversion unit 1902 is configured to align at least one path of first data, obtain a plurality of first codewords according to the alignment result; and obtain at least one path of second data according to the plurality of first codewords.

[0214] In a possible implementation, the conversion unit 1902 is configured to merge a plurality of first codewords, and obtain at least one path of second data according to the merging result.

[0215] In a possible implementation, the conversion unit 1902 is configured to merge a plurality of first codewords into one path of second data in a sequential transmission manner; or merge a plurality of first codewords into at least two paths of second data.

[0216] In a possible implementation, the conversion unit 1902 is configured to perform deinterleaving on the alignment result, and obtain a plurality of first codewords according to the deinterleaving result.

[0217] In a possible implementation, the conversion unit 1902 is configured to encode at least one path of first data according to a second FEC code type to obtain a plurality of third codewords; and obtain at least one path of second data according to the plurality of third codewords.

[0218] In a possible implementation, the conversion unit 1902 is configured to perform interleaving on a plurality of third codewords, and obtain at least one path of second data according to the interleaving result.

[0219] In a possible implementation, the conversion unit 1902 is configured to combine at least one path of first data into one path of seventh data in a sequential transmission manner, and encode the one path of seventh data to obtain a plurality of third codewords; or, convert at least one path of first data into at least two paths of seventh data, and encode the at least two paths of seventh data to obtain a plurality of third codewords.

[0220] In a possible implementation, the conversion unit 1902 is configured to combine at least one path of first data into one path of eighth data, and convert the one path of eighth data into at least two paths of seventh data.

[0221] In a possible implementation, the conversion unit 1902 is configured to perform overall encoding on one path of seventh data according to the second FEC code type to obtain a plurality of third codewords; or, convert the one path of seventh data into at least two paths of ninth data, and perform encoding on the at least two paths of ninth data respectively according to the second FEC code type to obtain a plurality of third codewords, where the rate of the ninth data is less than the rate of the seventh data.

[0222] In a possible implementation, the conversion unit 1902 is configured to perform overall encoding on at least two paths of seventh data according to the second FEC code type to obtain a plurality of third codewords; or perform encoding on at least two paths of seventh data respectively according to the second FEC code type to obtain a plurality of third codewords.

[0223] In a possible implementation, the conversion unit 1902 is configured to perform overall encoding on at least two paths of seventh data respectively according to the second FEC code type to obtain a plurality of third codewords; or, convert each of the at least two paths of seventh data into at least two paths of tenth data, and perform encoding on the at least two paths of tenth data respectively according to the second FEC code type to obtain a plurality of third codewords, where the rate of the tenth data is less than the rate of the seventh data.

[0224] In a possible implementation, the transmission unit 1903 is configured to insert synchronization data into at least one path of second data and transmit the data after the synchronization data is inserted.

[0225] In a possible implementation, the transmission unit 1903 is configured to determine the AM corresponding to each path of second data in at least one path of second data; and insert the AM corresponding to each path of second data into each path of second data as synchronization data.

[0226] In a possible implementation, the AM corresponding to each path of second data is obtained by adjusting the AM included in the corresponding first data; or, the AM corresponding to each path of second data is all the content of the AM included in the corresponding first data; or, the AM corresponding to each path of second data is part of the content of the AM included in the corresponding first data.

[0227] Figure 20The following is a schematic structural diagram of a data transmission device provided by an embodiment of the present application. Based on Figure 20 the following multiple units shown, the Figure 20 data transmission device shown can perform all or part of the operations performed by the third module. It should be understood that the device may include more additional units than the units shown or omit some of the units shown, and the embodiments of the present application do not limit this. As Figure 20 shown, the device includes:

[0228] An acquisition unit 2001, configured to acquire at least one path of second data, where the at least one path of second data is data obtained by performing conversion processing on at least one path of first data, and the sum of the rates of the at least one path of second data is not less than the sum of the rates of the at least one path of first data, and the first data is data encoded using a first forward error correction (FEC) code type;

[0229] A conversion unit 2002, configured to perform conversion processing on at least one path of second data to obtain at least one path of first data.

[0230] It should be understood that when the above Figure 19 、 Figure 20 provided device implements its functions, only the above division of each functional module is used for illustration. In practical applications, the above functions can be allocated to different functional units according to needs, that is, the internal structure of the device is divided into different functional units to complete all or part of the functions described above. In addition, the device provided in the above embodiment and the method embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0231] An embodiment of the present application provides a data transmission device, the device includes: a processor, the processor is coupled to a memory, and at least one program instruction or code is stored in the memory, and the at least one program instruction or code is loaded and executed by the processor so that the data transmission device implements the method in the above method embodiment.

[0232] Refer to Figure 21 , Figure 21 which shows a schematic structural diagram of a data transmission device 1100 provided by an exemplary embodiment of the present application. The data transmission device 1100 is a transmitting side / receiving side device. Figure 21 The data transmission device 1100 shown is used to execute the above Figure 2Operations involved in the data transmission method shown. The data transmission device 1100 is, for example, a network device such as a switch or a router, and other devices including this chip cascading mode (such as a server, a PC, etc.). The hardware structure of the data transmission device 1100 includes a communication interface 1101 and a processor 1102. Optionally, the communication interface 1101 and the processor 1102 are connected through a bus 1104. Among them, the communication interface 1101 is used to obtain the first data and transmit the second data. The processor may store instructions or program codes, and execute the functions performed by the first module or the third module by calling the instructions or program codes. Optionally, the network device further includes a memory 1103, and the instructions or program codes are stored in the memory 1103. The processor 1102 is used to call the instructions or program codes in the memory 1103 to enable the network device to execute the relevant processing steps of the first module in the above method embodiment. In a specific embodiment, the data transmission device 1100 in the embodiment of the present application may include the first module in each of the above method embodiments. The processor 1102 in the data transmission device 1100 reads the instructions or program codes in the memory 1103, so that Figure 21 the data transmission device 1100 shown is capable of performing all or part of the operations performed by the first module.

[0233] In a specific embodiment, the data transmission device 1100 in the embodiment of the present application includes the third module in each of the above method embodiments. The processor 1102 in the data transmission device 1100 reads the instructions or program codes in the memory 1103, so that Figure 21 the data transmission device 1100 shown is capable of performing all or part of the operations performed by the third module.

[0234] Exemplarily, the processor 1102 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of this application. For example, the processor 1102 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in connection with the disclosed content of the embodiments of the present invention. The processor can also be a combination for implementing computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.

[0235] Optionally, the data transmission device 1100 further includes a bus. The bus is used to transfer information between the components of the data transmission device 1100. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 21 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus. Figure 21 In the figure, in addition to being connected by a bus, the components of the data transmission device 1100 can also be connected in other ways. The embodiments of the present invention do not limit the connection manner of each component.

[0236] The memory 1103 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, such as a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, such as an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1103 exists independently, for example, and is connected to the processor 1102 through a bus. The memory 1103 can also be integrated with the processor 1102.

[0237] The communication interface 1101 uses any device such as a transceiver to communicate with other devices or communication networks, and the communication network can be an Ethernet, a radio access network (RAN) or a wireless local area network (WLAN), etc. The communication interface 1101 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 1101 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. In the embodiment of the present application, the communication interface 1101 can be used for the device 1100 for data transmission to communicate with other devices.

[0238] In a specific implementation, as an embodiment, the processor 1102 can include one or more CPUs. Each of these processors can be a single-CPU processor or a multi-CPU processor. Here, the processor can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0239] In a specific implementation, as an embodiment, the data transmission device 1100 may include multiple processors. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0240] In a specific implementation, as an embodiment, the data transmission device 1100 may further include an output device and an input device. The output device communicates with the processor 1102 and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with the processor 1102 and can receive user input in various ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensing device, etc.

[0241] In some embodiments, the memory 1103 is used to store the program code for executing the solution of this application, and the processor 1102 can execute the program code stored in the memory 1103. That is, the data transmission device 1100 can implement the data transmission method provided in the method embodiment through the program code in the processor 1102 and the memory 1103. The program code may include one or more software modules. Optionally, the processor 1102 itself may also store the program code or instructions for executing the solution of this application.

[0242] In a specific embodiment, the data transmission device 1100 of the embodiment of this application may include the first chip in each of the above method embodiments. The processor 1102 in the data transmission device 1100 reads the program code stored in the memory 1103 or the program code or instructions stored by the processor 1102 itself, so that Figure 21 the data transmission device 1100 shown can perform all or part of the operations performed by the first module.

[0243] In a specific embodiment, the data transmission device 1100 of the embodiment of this application may include the third module in each of the above method embodiments. The processor 1102 in the data transmission device 1100 reads the program code stored in the memory 1103 or the program code or instructions stored by the processor 1102 itself, so that Figure 21 the data transmission device 1100 shown can perform all or part of the operations performed by the third module.

[0244] The device 1100 for data transmission may also correspond to the above-mentioned Figure 19 , 20 shown device, Figure 19 , 20 and each functional unit in the shown device is implemented by software of the device 1100 for data transmission. In other words, Figure 19 , 20 the functional units included in the shown device are generated after the processor 1102 of the device 1100 for data transmission reads the program code stored in the memory 1103.

[0245] Among them, Figure 2-18 each step of the data transmission method shown is completed by an integrated logic circuit in hardware in the processor of the device 1100 for data transmission or instructions in software form. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by a hardware processor, or executed and completed by a combination of hardware and software modules in the processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0246] The embodiments of the present application also provide a data transmission system, which includes: a first device for data transmission and a second device for data transmission; the first device for data transmission is used to execute Figure 2 the method executed by the first module shown, and the second device for data transmission is used to execute Figure 18 the method executed by the third module shown.

[0247] The respective functions of the first device for data transmission and the second device for data transmission of this system can refer to the relevant descriptions shown in the above Figure 2 and Figure 18 , and will not be elaborated here one by one.

[0248] It should be understood that the above-mentioned processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. It is worth noting that the processor can be a processor that supports the advanced RISC machines (ARM) architecture.

[0249] Further, in an alternative embodiment, the above-mentioned memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0250] The memory can be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus random access memory (DR RAM).

[0251] A computer-readable storage medium is further provided, in which at least one program instruction or code is stored. When the program instruction or code is loaded and executed by a processor, the computer is enabled to implement the data transmission method as described above. Figure 2-18 shown.

[0252] This application provides a computer program. When the computer program is executed by a computer, the processor or the computer can be enabled to execute the corresponding steps and / or processes in the above method embodiments.

[0253] A chip is provided, including a processor, configured to call and run instructions stored in a memory, so that a device installed with the chip executes the method in the above aspects.

[0254] Another chip is provided, including: an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The processor is configured to execute the code in the memory. When the code is executed, the processor is configured to execute the method in the above aspects.

[0255] A device is provided, including the chip in any of the above solutions.

[0256] A device is provided, including the first chip in any of the above solutions, and / or the third chip in any of the above solutions.

[0257] In some embodiments, Figure 14-17 In, the second chip may be a transmitting-side device, such as a physical layer (PHY) chip in a router, a switch, or a server. The first chip may be an interface of a receiving-side device, such as a chip in an optical module or a CDR / retimer chip. In some embodiments, the first chip may be a transmitting-side device, such as a PHY chip in a router, a switch, or a server. The third chip may be an interface of a receiving-side device, such as a chip in an optical module or a CDR / retimer chip. The PHY chip may be a chip located on a single board of a computing device, and the chip may be one or any combination of a CPU, a network processor (NP), a neural network processing unit (NPU), a field programmable gate array (FPGA), a programmable logic controller (PLC), etc.

[0258] In some embodiments, communication between the first chip and the second chip is via AUI; in some embodiments, communication between the third chip and the first chip is via AUI.

[0259] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk).

[0260] The above specific embodiments further elaborate on the purpose, technical solution, and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not used to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solution of the present application should be included in the protection scope of the present application.

[0261] Those of ordinary skill in the art can realize that, in combination with the method steps and modules described in the embodiments disclosed herein, they can be implemented by software, hardware, firmware, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0262] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disc, etc.

[0263] When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiments of the present application can be described in the context of machine-executable instructions, such as in program modules executed in devices included in a target real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., which perform specific tasks or implement specific abstract data structures. In various embodiments, the functions of the program modules can be combined or split among the described program modules. The machine-executable instructions for the program modules can be executed within a local or distributed device. In a distributed device, the program modules can be located in both local and remote storage media.

[0264] The computer program code for implementing the method of the embodiments of the present application can be written in one or more programming languages. These computer program codes can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing devices, such that when the program codes are executed by the computer or other programmable data processing devices, the functions / operations specified in the flowchart and / or block diagram are implemented. The program codes can be executed entirely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0265] In the context of the embodiments of the present application, the computer program code or related data can be carried by any suitable carrier, so that the device, apparatus, or processor can perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like.

[0266] Examples of signals can include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0267] A machine-readable medium can be any tangible medium that contains or stores a program for use in or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. More specific examples of a machine-readable storage medium include an electrical connection with one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0268] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0269] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the module is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed couplings, direct couplings, or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or modules, and can also be electrical, mechanical, or other forms of connection.

[0270] The module described as a separate component may or may not be physically separated, and the component displayed as a module may or may not be a physical module, that is, it may be located in one place, or may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.

[0271] In addition, the functional modules in each embodiment of the present application can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0272] When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of this application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0273] In this application, the meaning of the term "at least one" refers to one or more, and the meaning of the term "a plurality" refers to two or more. For example, a plurality of second messages refers to two or more second messages. In this article, the terms "system" and "network" are often used interchangeably.

[0274] It should be understood that the terms used in the description of various examples herein are only for describing specific examples and are not intended to be restrictive. As used in the description of various examples and the appended claims, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0275] It should also be understood that the term "comprises" (also referred to as "includes", "including", "comprises", and / or "comprising") when used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups.

[0276] It should also be understood that the terms "if" and "when" can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined..." or "if [the stated condition or event] is detected" can be interpreted to mean "when it is determined..." or "in response to determining..." or "when [the stated condition or event] is detected" or "in response to detecting [the stated condition or event]".

[0277] It should be understood that determining B based on A does not mean determining B solely based on A. B can also be determined based on A and / or other information.

[0278] It should also be understood that the "one embodiment", "an embodiment", and "a possible implementation" mentioned throughout the specification mean that the specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment", "a possible implementation" that appear throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in one or more embodiments in any suitable manner.

Claims

1. A method for data transmission, characterized in that, The method includes: Obtaining at least two paths of first data, where the at least two paths of first data are respectively data encoded using a first forward error correction (FEC) code type; Aligning the at least two paths of first data respectively to obtain a plurality of first codewords corresponding to the at least two paths of first data; Decoding the plurality of first codewords corresponding to the at least two paths of first data respectively; Performing data merging on the at least two paths of decoded first data to obtain third data; Encoding the third data according to a second FEC code type to obtain a plurality of second codewords; Obtaining at least one path of second data according to the plurality of second codewords; Transmitting the at least one path of second data.

2. The method according to claim 1, characterized in that, The first FEC code type is Reed - Solomon (RS) code, and the second FEC code type is Turbo Product Code (TPC).

3. The method according to claim 1, characterized in that, The obtaining of the at least two paths of first data includes: a first module receiving the at least two paths of first data sent by a second module through an Attachment Unit Interface (AUI).

4. The method according to claim 3, wherein The first module is located on a first chip, and the second module is located on a second chip.

5. The method according to any one of claims 1 to 4, characterized in that, The aligning of the at least two paths of first data respectively includes: Respectively obtaining at least one path of sub - data corresponding to each first data, and aligning the at least one path of sub - data belonging to the same path of first data.

6. The method according to any one of claims 1 to 4, characterized in that The aligning of the at least two paths of first data respectively includes: Performing AM locking and de - skewing on the at least two paths of first data respectively.

7. The method according to any one of claims 1 to 4, characterized in that The aligning of the at least two paths of first data respectively to obtain a plurality of first codewords corresponding to the at least two paths of first data includes: Aligning the at least two paths of first data respectively, and performing de - interleaving on the alignment result; Respectively obtaining a plurality of first codewords corresponding to the at least two paths of first data according to the de - interleaving result.

8. The method according to any one of claims 1 to 4, characterized in that The transmitting of the at least one path of second data includes: Inserting a training sequence and / or pilot symbols into the at least one path of second data, and transmitting the at least one path of second data inserted with the training sequence and / or pilot symbols.

9. The method according to any one of claims 1 to 4, characterized in that The first data includes an alignment flag AM, which is used to align at least one path of first data. Before performing data merging on the at least two paths of decoded first data to obtain third data, the method further includes: Deleting the AM in the decoded data.

10. The method according to any one of claims 1 to 4, characterized in that, The obtaining of at least one path of second data according to the plurality of second codewords includes: Performing interleaving on the second codewords to obtain the at least one path of second data.

11. The method according to claim 10, wherein Performing interleaving on the second codewords to obtain the at least one path of second data includes: Performing codeword interleaving or interleaving between channel lanes on the second codewords to obtain the at least one path of second data.

12. The method according to any one of claims 1-4 and 11, characterized in that, The rate of the first data is 400 gigabits per second (Gb / s) or 200 gigabits per second (Gb / s) or 100 gigabits per second (Gb / s), and the rate of the second data is 800 Gb / s or 1.6 terabits per second (Tb / s).

13. The method according to any one of claims 1-4, 11, characterized in that, The at least two paths of first data include 8 paths of 100 gigabits per second (Gb / s) data.

14. A method for data transmission, characterized in that, The method includes: Obtain at least one path of second data, where the at least one path of second data is data obtained by performing transformation processing on at least two paths of first data, and the first data is data encoded using a first forward error correction (FEC) code type; Perform transformation processing on the at least one path of second data to obtain the at least one path of first data; The at least one path of second data being data obtained by performing transformation processing on at least two paths of first data includes: Align the at least two paths of first data respectively to obtain a plurality of first codewords corresponding to the at least two paths of first data; Decode the plurality of first codewords corresponding to the at least two paths of first data respectively; Perform data merging on the at least two paths of decoded first data to obtain third data; Encode the decoded third data according to a second FEC code type to obtain a plurality of second codewords; Obtain at least one path of second data according to the plurality of second codewords.

15. The method according to claim 14, wherein The obtaining at least one path of second data according to the plurality of second codewords includes: Perform interleaving on the second codewords to obtain the at least one path of second data.

16. A device for data transmission, characterized in that, The apparatus is configured to execute the method according to any one of claims 1 to 13.

17. A data transmission device, characterized in that, The apparatus is configured to execute the method according to claim 14 or 15.

18. An optical module, characterized in that, The optical module is configured to execute the method according to any one of claims 1 to 15.

19. A data transmission system, characterized in that, The data transmission system includes a first data transmission device and a second data transmission device. The first data transmission device is configured to execute the method according to any one of claims 1 - 13, and the second data transmission device is configured to execute the method according to claim 14 or 15.

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