Bit synchronization device and method for K-band missile-borne networking data link

Abstract

The invention provides a bit synchronization device and method for a K-band missile-borne networking data chain, and the method specifically comprises the steps: determining four reference sampling points through a bit synchronization error compensation controller according to a received sampling offset estimation value and a received sampling frequency offset estimation value; the bit synchronization error compensation controller estimates a fractional interval u according to the sampling offset estimation value and the sampling frequency offset estimation value; and the bit synchronization error compensation controller controls the interpolation filter to complete baseband signal interpolation according to the reference sampling point and the fractional interval and outputs the interpolated baseband signal as the baseband signal after bit synchronization. According to the invention, bit synchronization errors caused by clock drift caused by Doppler and inconsistent sampling clock frequencies at the transmitting end and the receiving end can be eliminated.

Description

Technical Field

[0001] The present invention relates to the field of data link communication technology, and in particular to the field of bit synchronization methods in missile-borne networking data link communication technology. Background Art

[0002] Prior art 1: "Design and FPGA implementation of bit synchronization loop for UAV measurement and control link Communication Technology Vol. 52 No. 10" designed a bit synchronization loop based on Gardner algorithm plus Farrow structure. The algorithm mainly includes an interpolation filter module, a timing error detector module, a loop filter module and an NCO controller module, such as Figure 1 The figure shows a block diagram of a bit synchronization loop design based on the Gardner algorithm, which can track a certain degree of bit timing clock drift caused by the clock inconsistency between the transmitting and receiving ends and the Doppler frequency shift.

[0003] Prior art 2 "Design of time-frequency synchronization scheme for short-time burst system based on GMSK modulation Information Communication No. 210" points out that the commonly used closed-loop synchronization algorithm requires feedback and iteration, and the synchronization time is relatively long, which is not suitable for short burst communication systems, so it adopts an open-loop bit synchronization scheme. This scheme uses 10 groups of 128-bit PN codes as synchronization headers. When 8 peak values ​​are detected to be greater than the synchronization threshold, the synchronization is determined to be successful, and the sampling channel with the most peak values ​​is determined to be the best sampling channel.

[0004] Prior art three "Research on Bit Synchronization of All-Digital Single-Carrier Receiver Communication Technology Vol. 54 No. 4" points out that the negative feedback loop bit synchronization algorithm has a long convergence time and is not suitable for short-time burst transmission, and proposes a feedforward all-digital bit synchronization algorithm. The algorithm uses the pseudo-random sequence information of the physical frame header to directly estimate the optimal sampling time, and restores the sampling value of the optimal sampling time through an interpolation algorithm, thereby achieving rapid convergence of the bit synchronization algorithm without adding other redundant information.

[0005] The first existing technology adopts a bit synchronization loop based on the Gardner algorithm plus the Farrow structure. This technology can track a certain degree of bit timing clock drift caused by the inconsistency of the clocks at the transmitting and receiving ends and the Doppler frequency shift. However, the algorithm adopted by this technology is a closed-loop synchronization algorithm, and it takes time to lock the bit synchronization loop. Therefore, this technology is generally used in communication systems that adopt a continuous wave communication system, and is not suitable for networking communication applications with high dynamic and burst communication characteristics.

[0006] The second existing technology adopts an open-loop bit synchronization scheme based on oversampling and time domain correlation. This technology does not require loop locking time and can be used in networking communication systems with high dynamic and burst communication characteristics. Since this scheme does not contain an interpolator, the sampling rate it uses is an integer multiple of the symbol rate. This condition cannot be met in some applications, thus limiting the application of this technology; considering that this technology uses a high oversampling rate to improve the bit synchronization accuracy, the high-precision bit synchronization in the broadband communication application scenario brings challenges to the bit synchronization of the communication system. In this application scenario, a multi-channel correlator is required to calculate for each sampling point, thereby increasing the complexity of bit synchronization; this technology only synchronizes the arrival time of the burst frame, and does not take into account the bit synchronization error caused by the inconsistent sampling clock frequency at the transmitting and receiving ends and the clock drift caused by Doppler.

[0007] Prior art 3 adopts a feedforward all-digital bit synchronization algorithm, which directly estimates the optimal sampling time using the pseudo-random sequence information of the physical frame header, and restores the sampling value of the optimal sampling time through the interpolation algorithm, thereby achieving rapid convergence of the bit synchronization algorithm without adding other redundant information. Although this technology is greatly improved over prior art 1 and prior art 2, this technology also does not take into account the bit synchronization error caused by the inconsistent sampling clock frequency at both ends of the transmitter and receiver and the clock drift caused by Doppler, so it will cause bit synchronization offset in a high dynamic environment. Summary of the invention

[0008] In view of this, the present invention provides a bit synchronization device and method that can be used for K-band missile-borne networking data link, which is suitable for networking communication systems with high dynamic and burst communication characteristics. The specific technical solution is as follows:

[0009] A bit synchronization device for a K-band missile-borne networking data link comprises a frame synchronization module, a bit synchronization error estimation module and a bit synchronization error compensation module, wherein the frame synchronization module is used to complete the frame synchronization function, the bit synchronization error estimation module is used to complete the sampling offset estimation and the sampling frequency offset estimation, and the bit synchronization error compensation module is used to complete the sampling offset and the sampling frequency offset compensation according to the sampling offset estimation value and the sampling frequency offset estimation value.

[0010] Furthermore, the bit synchronization error compensation module includes a compensation controller and an interpolation filter; wherein the interpolation filter completes the interpolation of the baseband signal after frame synchronization under the control of the compensation controller.

[0011] Furthermore, the interpolation filter adopts a cubic Lagrange interpolation filter.

[0012] Furthermore, the interpolation filter performs interpolation based on the four previous and next reference sampling points, and the cubic Lagrange interpolation filter coefficients corresponding to the reference sampling points are as shown in the following formula (1):

[0013]

[0014] Where u is the fractional interval.

[0015] Furthermore, the carrier Doppler frequency shift is used to complete the sampling frequency offset estimation.

[0016] A bit synchronization method for a K-band missile-borne networking data link is implemented based on the above-mentioned bit synchronization device, and includes the following steps: a bit synchronization error compensation controller receives a sampling offset estimation value and a sampling frequency deviation estimation value output by a bit synchronization error estimation module; first, the bit synchronization error compensation controller determines four reference sampling points for each symbol according to the sampling offset estimation value and the sampling frequency deviation estimation value, wherein each symbol refers to a group of sampling data to be synchronized input to the system; then, the bit synchronization error compensation controller estimates the fractional interval u of each symbol according to the sampling offset estimation value and the sampling frequency deviation estimation value; finally, the bit synchronization error compensation controller controls an interpolation filter to complete baseband signal interpolation according to the reference sampling points and fractional intervals selected for each symbol, and outputs the interpolated baseband signal as the baseband signal after bit synchronization.

[0017] The following beneficial effects can be achieved by adopting the present invention:

[0018] 1. The present invention can eliminate the bit synchronization error caused by the inconsistent sampling clock frequency at both ends of the transmitter and receiver and the clock drift caused by Doppler.

[0019] 2. The present invention uses carrier Doppler frequency shift to complete sampling frequency offset estimation, and completes whole frame data bit synchronization based on sampling frequency offset estimation and frame synchronization information, which is particularly suitable for networking communication applications with high dynamic and burst communication characteristics.

[0020] 3. The present invention can work in the communication systems of the two physical layer frame structures shown in FIG. 4 (a) and (b), and the bit synchronization algorithm proposed in the present invention has universal applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Design a block diagram for a bit synchronization loop based on the Gardner algorithm;

[0022] Figure 2 This is a block diagram of the bit synchronization implementation of the present invention;

[0023] Figure 3 This is a processing block diagram of the bit synchronization compensation module of the present invention;

[0024] FIG4(a) is a common frame structure diagram in burst communication;

[0025] FIG4( b ) is another common frame structure diagram in burst communication. DETAILED DESCRIPTION

[0026] Combination Figure 1 , Figure 2 , Figure 3 4(a) and 4(b) further illustrate the present invention.

[0027] The present invention provides a bit synchronization method that can be used for K-band missile-borne networking data links. The bit synchronization block diagram is as follows: Figure 2 As shown, the synchronization method includes a frame synchronization module, a bit synchronization error estimation module and a bit synchronization error compensation module, wherein the frame synchronization module completes the frame synchronization function, the bit synchronization error estimation module completes the sampling offset estimation and the sampling frequency offset estimation, and the bit synchronization error compensation completes the sampling offset and the sampling frequency offset compensation according to the sampling offset estimation value and the sampling frequency offset estimation value.

[0028] As shown in Figure 4, it is a processing block diagram of the bit synchronization error compensation module. The bit synchronization error compensation module mainly includes a compensation controller and an interpolation filter. The interpolation filter is the core of the bit synchronization error compensation module. The interpolation filter completes the interpolation of the baseband signal after frame synchronization under the control of the bit synchronization error compensation controller. The interpolation filter used in the scheme uses a cubic Lagrange interpolation filter. The filter is interpolated based on the four reference sampling points before and after. The cubic Lagrange interpolation filter coefficient corresponding to the reference sampling point is

[0029]

[0030] The bit synchronization error compensation controller receives the sampling offset estimation value and the sampling frequency offset estimation value output by the bit synchronization error estimation module. First, the bit synchronization error compensation controller determines four reference sampling points for each symbol according to the sampling offset estimation value and the sampling frequency offset estimation value. Then, the bit synchronization error compensation controller estimates the fractional interval u of each symbol according to the sampling offset estimation value and the sampling frequency offset estimation value. Finally, the bit synchronization error compensation controller controls the interpolation filter to complete the baseband signal interpolation according to the reference sampling points and fractional intervals selected for each symbol and outputs the interpolated baseband signal as the baseband signal after bit synchronization.

[0031] As shown in 4(a), a physical layer frame structure commonly used in burst communication mainly includes pilot and data, wherein the pilot and data lengths should be reasonably designed according to different application scenarios. As shown in 4(b), another physical layer frame structure commonly used in burst communication mainly includes multi-segment pilot and multi-segment data, wherein the number and length of segments of the pilot and data should be reasonably designed according to different application scenarios. The present invention can work in communication systems adopting the above two physical layer frame structures. The bit synchronization technology is suitable for networking communication applications with high dynamic and burst communication characteristics. The bit synchronization algorithm proposed in the present invention has universal applicability.

Claims

1. A bit synchronization device for K-band missile-borne networking data link, characterized in that: It includes a frame synchronization module, a bit synchronization error estimation module and a bit synchronization error compensation module, wherein the frame synchronization module is used to complete the frame synchronization function, the bit synchronization error estimation module is used to complete the sampling offset estimation and the sampling frequency offset estimation, and the bit synchronization error compensation module is used to complete the sampling offset and the sampling frequency offset compensation according to the sampling offset estimation value and the sampling frequency offset estimation value.

2. A bit synchronization device for a K-band missile-borne networking data link according to claim 1, characterized in that: The bit synchronization error compensation module comprises a compensation controller and an interpolation filter; wherein the interpolation filter completes the interpolation of the baseband signal after frame synchronization under the control of the compensation controller.

3. A bit synchronization device for K-band missile-borne networking data link according to claim 2, characterized in that: The interpolation filter adopts a cubic Lagrange interpolation filter.

4. The bit synchronization device for K-band missile-borne networking data link according to any one of claim 3, characterized in that: The interpolation filter performs interpolation based on the four previous and next reference sampling points.

5. The bit synchronization device for K-band missile-borne networking data link according to any one of claims 1 to 4, characterized in that: The sampling frequency offset estimation is done using the carrier Doppler shift.

6. A bit synchronization method for K-band missile-borne networking data link, based on the above-mentioned bit synchronization device, characterized in that: The bit synchronization error compensation controller determines four reference sampling points according to the received sampling offset estimation value and sampling frequency deviation estimation value; The bit synchronization error compensation controller estimates the fractional interval u according to the sampling offset estimation value and the sampling frequency deviation estimation value; The bit synchronization error compensation controller controls the interpolation filter to complete the baseband signal interpolation according to the reference sampling point and the fractional interval and outputs the interpolated baseband signal as the bit synchronized baseband signal.

Images