A method for deterministic transmission of test data delay in TTE integrated Ethernet

Abstract

The present invention discloses a method for deterministically transmitting test data with time delay in the integration of TTE and Ethernet, including: using an FPGA to follow the design of the time synchronization core module in the TTE protocol, which can process the received protocol control frame (PCF) to achieve high-precision time synchronization of multiple nodes, and using the command-condition interaction method to control the status and other core signals; generating a scheduling table by combining the deadline-first maximum matching algorithm, including eight steps of scheduling parameter input, period calculation, shortest path calculation, deadline-first preprocessing, maximum matching sorting, message allocation, conflict detection, and scheduling table loading; using the FPGA to load the scheduling table into the scheduling configuration module, integrating Ethernet transmission, and performing periodic time slot allocation for the link to ensure the stability of time synchronization and the time delay determinacy of test data transmission. The present invention can balance the link load on the premise of reducing the real-time data packet loss rate.

Description

Technical Field

[0001] The present invention belongs to the fields of electronic engineering and computer science, and particularly relates to a method for deterministically transmitting test data delay in TTE integrated Ethernet. Background Art

[0002] In the current era of big data with information explosion, the reasonable collection, screening, processing and analysis of data are very important. The current transmission and processing of real-time data are pain points in typical test scenarios, specifically including services such as high-precision spatio-temporal services, interconnection and real-time fusion perception of data. The premise for the smooth progress of upper-layer real-time decision-making is to ensure that key data is delivered to the decision-making center in real time. In scenarios where high-speed and deterministic transmission of test data is required in test and measurement, there are extremely strict time requirements for the deterministic transmission of real-time data. If the delay deterministic transmission of real-time data cannot be guaranteed, it may cause major problems such as poor real-time decision-making or test results not conforming to the actual situation. How to achieve the delay deterministic transmission of test data is one of the key issues to support upper-layer decision-making.

[0003] With the development of information technology, many data transmission protocol standards have emerged, including commonly used industrial Ethernet, Modbus, and Zigbee, etc. However, in terms of the delay determinism of data transmission, the best method is to achieve time synchronization between the two communication parties through a time synchronization protocol. On the basis of maintaining a common time standard between the two, the method of triggering transmission according to a schedule is adopted to achieve the delay deterministic transmission of data.

[0004] Time-Triggered Ethernet (TTE) is a network protocol designed specifically to meet real-time and high-reliability requirements. It manages data transmission through a time-triggered mechanism to ensure the predictability and determinism of communication. This protocol supports two communication modes: time-triggered and event-triggered, can efficiently manage bandwidth, give priority to transmitting real-time data streams, and avoid data conflicts and network congestion. Selecting this method can achieve high-precision time synchronization. As a programmable hardware logic device, FPGA has the characteristics of high parallel processing and hardware acceleration, which is conducive to the implementation of TTE integrated Ethernet.

[0005] However, there is little research on how to use FPGA to implement a TTE protocol with high time synchronization accuracy, generate a schedule through an efficient algorithm, and integrate it into traditional Ethernet. Summary of the Invention

[0006] To solve the above technical problems, the present invention provides a method for deterministically transmitting test data delay in TTE integrated Ethernet. An FPGA is used to design a time synchronization core module in the TTE protocol. This module can process the received protocol control frame (PCF), achieve high-precision time synchronization of multiple nodes through transparent clock update, solidification, and compression algorithms, and at the same time use the command-condition interaction method to control the status and other core signals; use the maximum matching algorithm combined with deadline priority to generate a scheduling table, including five steps: scheduling parameter input, shortest path calculation, deadline priority preprocessing, maximum matching sorting, and message allocation, to reduce the packet loss rate of real-time data and balance the link load; use the FPGA to load the scheduling table into the scheduling configuration module, integrate Ethernet transmission, and perform periodic time slot allocation for the link, successively for protocol control frames, real-time data, and non-real-time data, to ensure the stability of time synchronization and the delay determinacy of TT flow transmission.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A method for deterministically transmitting test data delay in TTE integrated Ethernet includes the following steps:

[0009] Step 1: Design a time synchronization core module in accordance with the TTE protocol, process the received protocol control frame (PCF), achieve high-precision time synchronization of multiple nodes through transparent clock update, solidification, and compression algorithms, and use the command-condition interaction method to control the status and other core signals. The specific implementation is as follows:

[0010] Design a PCF receiving module to parse the UDP data packet obtained from the network layer, and extract and integrate the cycle, member group, synchronization priority, synchronization domain, PCF frame type, and transparent clock field; design a PCF sending module, after triggering the sending condition, obtain the cycle, member group, synchronization priority, synchronization domain, PCF frame type, and transparent clock field according to the core signal parameters of the current system, frame them into a UDP data packet and send it to the network layer;

[0011] Design transparent clock update, solidification, and compression algorithms. The transparent clock update is used to record the cumulative transmission delay update in the entire link transmission, including dynamic and static delays; the solidification algorithm is used to reorder the receiving time points and transparent clock values of PCF frames on each link to ensure that the receiving and sending orders of each PCF frame are the same and the sending and receiving intervals are equal; the compression algorithm is used to integrate the PCF frames received by the CM device from multiple SM devices, obtain the local clock differences of each SM based on the solidification time points in each PCF frame, and execute the compression algorithm to obtain a weighted unified compression time point, and use this as a standard to correct the local clocks of each device;

[0012] Design the time synchronization core module, execute the corresponding algorithm and complete the management of local state and other core signals according to the command-condition interaction method. The solidification processing module and the compression processing module execute the corresponding solidification and compression algorithms. The state control module manages the local state jump and maintains the state core signal. The timeout module detects whether the time in the current state exceeds the threshold limit and maintains the time_out core signal. The clustering detection module detects whether the number of local member groups exceeds the threshold limit and maintains the local_member core signal. The local time control module controls the local time count and jump, maintains the local_clk core signal, and the local cycle control module controls the local cycle count and jump, maintains the local_cycle core signal. The synchronous calculation module calculates the correction value of the local time according to the input parameters and maintains the clk_correct core signal.

[0013] Step 2: Generate a scheduling table using the maximum matching algorithm combined with cutoff priority, including eight steps: scheduling parameter input, cycle calculation, shortest path calculation, cutoff priority preprocessing, maximum matching sorting, message allocation, conflict detection and scheduling table loading, to reduce the packet loss rate of real-time data and balance the link load. The specific implementation is as follows:

[0014] Input message model parameters, including terminal node information, switch information, transmission link information, and parameters of all TT message information;

[0015] Cycle calculation, based on the idea of ​​TDMA time division multiple access, the TT message is allocated periodic time slots, and the matrix cycle MC and the basic cycle BC are defined. A TT message is sent at least once in an MC, and a TT message is sent at most once in a BC;

[0016] For the shortest path calculation, the Dijkstra algorithm is used to generate a shortest path tree for each message source node and determine the shortest path for each TT message;

[0017] Deadline priority preprocessing, pre-prioritizes all TT messages in order of deadline from small to large;

[0018] Maximum matching sorting, re-sorting all TT messages based on the in-and-out degrees of all nodes, defining the node with the largest out-degree as the sending node and the node with the smallest in-degree as the receiving node, and assigning priority to the TT messages of the source node and the target node consisting of the sending node and the receiving node;

[0019] Message allocation, assigning each TT message to a matrix cycle according to the pre-sorted priority;

[0020] Conflict detection: Examine whether each TT message exceeds the deadline. If there is a conflict, it indicates that the current input message model parameters are unreasonable, and the input message model parameters need to be readjusted. If there is no conflict, generate a scheduling table.

[0021] Scheduling table loading: Design a scheduling configuration module and deploy the generated scheduling table to the scheduling configuration module.

[0022] Step 3: Use FPGA to load the scheduling table into the scheduling configuration module, integrate Ethernet transmission, and perform periodic time slot allocation for the link, successively for protocol control frames, real-time data, and non-real-time data, to ensure the stability of time synchronization and the delay determinacy of TT stream transmission. The specific implementation is as follows:

[0023] Calculate the cycle time: Obtain the time required for protocol control frame transmission through the design of the time synchronization core module. , obtain the time required for transmitting real-time data through the message model parameters. , set the time required for transmitting non-real-time data to be the same as that for transmitting real-time data. , and use the superposition of the times for transmitting protocol control frames, real-time data, and non-real-time data as the time cycle for transmitting information in the link. ;

[0024] Protocol control frame sending: In the first part of each time cycle, send the protocol control frame PCF according to the management and control of the time synchronization core module.

[0025] Real-time data sending: In the second part of each time cycle, the time synchronization core module provides the local time. According to the matching relationship between the real-time data and the sending time in the scheduling table, when reaching a specific time node, output a sending instruction to guide the sending of real-time data in the Ethernet data cache, that is, the TT time-triggered stream.

[0026] Non-real-time data sending: In the third part of each time cycle, send the non-real-time data in the Ethernet data cache, including RC rate-limited streams and BE best-effort forwarding streams.

[0027] The method described in the test data delay determinacy transmission method of TTE integrated with Ethernet designed by the present invention is applicable to the Xilinx ARTIX-7 FPGA chip, model XC7A200T-2FBG484I, and the PHY chip is Realtek RTL8211EG.

[0028] The beneficial effects of the present invention are as follows:

[0029] (1)The self-designed time synchronization core module adopts a command-condition interactive signal control scheme, which optimizes the previous time-triggered Ethernet implementation scheme based on FPGA, enabling the time synchronization accuracy of multiple nodes to reach 50 ns and having long-term stability.

[0030] (2)The scheduling table is generated by combining the deadline-first maximum matching algorithm, which has the advantages of both the deadline-first and maximum matching algorithms. It can balance the link load on the premise of reducing the real-time data packet loss rate and can support complex environments with dynamic changes and large traffic throughput.

[0031] (3)The FPGA is used to integrate the time synchronization function and the scheduling table generation function into the traditional Ethernet, and periodically transmit protocol control frames, real-time data, and non-real-time data. On the basis of time synchronization, it can be compatible with the functions of the traditional Ethernet and at the same time achieve the deterministic transmission of the delay of the real-time data TT stream. Description of the Drawings

[0032] Figure 1 It is a schematic diagram of the principle of the method for deterministic transmission of test data delay of a TTE integrated Ethernet according to the present invention;

[0033] Figure 2 It is a schematic diagram of the principle of the time synchronization core module of the present invention;

[0034] Figure 3 It is a flow chart of the scheduling table generation of the present invention;

[0035] Figure 4 It is a system architecture diagram of the TTE integrated Ethernet according to the present invention. Detailed Embodiments

[0036] The present invention will be further described in detail below with reference to the accompanying drawings.

[0037] As Figure 1As shown in the figure, the present invention discloses a method for deterministic transmission of test data delay in the integration of TTE and Ethernet. The method includes: designing a time synchronization core module in the TTE protocol using FPGA, which can process the received protocol control frame (PCF), and achieve high-precision time synchronization of multiple nodes through transparent clock update, solidification, and compression algorithms. At the same time, the command-condition interaction method is used to control the status and other core signals; generating a scheduling table using the maximum matching algorithm combined with deadline priority, including eight steps: scheduling parameter input, period calculation, shortest path calculation, deadline priority algorithm preprocessing, maximum matching algorithm reordering, message allocation, conflict detection, and scheduling table loading, to reduce the packet loss rate of real-time data and balance the link load; loading the scheduling table into the scheduling configuration module using FPGA, integrating Ethernet transmission, and performing periodic time slot allocation for the link, successively for protocol control frames, real-time data, and non-real-time data, to ensure the stability of time synchronization and the delay determinacy of TT stream transmission. The chip used is the ARTIX-7 FPGA chip of Xilinx, model XC7A200T-2FBG484I, and the PHY chip is Realtek RTL8211EG. The specific implementation details are as follows:

[0038] 1. Time synchronization core module: Perform time synchronization between communication parties according to the AS6802 protocol under the TTE standard. This module can process the received protocol control frame (PCF), and achieve high-precision time synchronization of multiple nodes through transparent clock update, solidification, and compression algorithms. At the same time, the command-condition interaction method is used to control the status and other core signals. The module structure is as Figure 2 shown.

[0039] This module has three design advantages: First, the PCF process of this module is clearly processed. After entering from the receiving module, the solidification and compression algorithms are executed in sequence, and then enter the sending module. Second, this module uses the command-condition interaction method to control the status and other core signals, that is, by means of the input condition signals and output commands interacted with other modules through statectrl. Third, the module outputs local_clk, which represents the time node where the device is located. It can be used to compare with other devices to calibrate the time synchronization accuracy, and also to support the specific time scheduling of TT messages.

[0040] The functions of each module are as follows:

[0041] ① PCF receiving module PR (PCF Receive): Extract relevant information of the PCF frame from PCF_RX and splice it into PCF_aRX, and at the same time has the function of caching data.

[0042] ②PermanentProc (PP) module: The received PCF_aRX PCF frame is processed by the curing algorithm to obtain the PCF_perm curing PCF frame. It should have channels for executing multiple curing algorithms in parallel.

[0043] ③Compression processing module CP (CompressProc): Executes compression algorithm on the received PCF_perm solidified PCF frame to obtain PCF_comp compressed PCF frame. It should have channels for executing multiple compression algorithms in parallel.

[0044] ④PCF sending module PT (PCFTransmit): The received PCF_comp compressed PCF frame is combined with the sending instruction information COM_TX to form a PCF frame for sending.

[0045] ⑤Timeout control module TO (TimeOut): Generates a local timer and timeout signal based on the current state.

[0046] ⑥Clique Detection Module CD (CliqueDetect): Performs synchronous and asynchronous clique detection at corresponding time nodes according to instructions, and generates local synchronous and asynchronous member group vectors.

[0047] ⑦ Synchronous calculation module SCP (SyncCompute): performs frame synchronization calculations at corresponding time nodes according to instructions and generates clock correction values.

[0048] ⑧Local clock control module LCC (LocalClkCtrl): updates the local clock according to instructions and status, and has the function of clock correction.

[0049] ⑨Local integration cycle control module LCYC (LocalCycleCtrl): updates the local integration cycle according to instructions and status.

[0050] ⑩State control module SC (StateCtrl): updates the current state and sends instructions to each module based on the current local maintenance signal.

[0051] 2. Combined with the maximum matching algorithm with cutoff priority: This method can generate a scheduling table, which refers to the matching relationship between the real-time data TT flow and the sending time, which can reduce the packet loss rate of real-time data and balance the link load. The method flow is as follows Figure 3 .

[0052] The process is described as follows:

[0053] Input message model parameters, including terminal node information, switch information, transmission link information, and parameters of all TT message information;

[0054] Period calculation: Based on the idea of TDMA (Time Division Multiple Access), perform periodic time slot allocation for TT messages. Define the matrix period MC and the basic period BC. Within one MC, a TT message is sent at least once, and within one BC, a TT message is sent at most once.

[0055] Shortest path calculation: Select the Dijkstra algorithm. For each message source node, generate a shortest path tree respectively to determine the shortest path for each TT message.

[0056] Deadline priority preprocessing: Perform priority pre-sorting on all TT messages in ascending order of the deadline.

[0057] Maximum matching sorting: Re-sort all TT messages based on the in-degree and out-degree of all nodes. Define the node with the largest out-degree as the sending node and the node with the smallest in-degree as the receiving node. Give priority to allocating priorities to TT messages with the sending node and the receiving node of this node pair as the source node and the destination node.

[0058] Message allocation: Allocate each TT message to the matrix period according to the pre-sorted priority.

[0059] Conflict detection: Examine whether each TT message exceeds the deadline. If there is a conflict, it means that the current input message model parameters are unreasonable, and the input message model parameters need to be adjusted again. If there is no conflict, generate a scheduling table.

[0060] Scheduling table loading: Design a scheduling configuration module and deploy the generated scheduling table to the scheduling configuration module.

[0061] 3. TTE integrated Ethernet system architecture: This architecture uses FPGA to load the scheduling table into the scheduling configuration module, integrates Ethernet transmission, performs periodic time slot allocation for the link, for protocol control frames, real-time data, and non-real-time data in sequence, to ensure the stability of time synchronization and the delay determinacy of TT stream transmission. The system architecture is as Figure 4 .

[0062] Workflow: The system conducts data interaction with the outside world through the on-board PHY chip via an Ethernet cable. The RGMII and GMII format conversions are performed by the conversion module. After receiving a message, it will be split into the ARP or UDP or time synchronization core module according to its category. Specifically, ARP frames enter the ARP processing module, RC, BE, and TT stream information enter the UDP processing module, and PCF frames enter the time synchronization core module. The output data of the three will be transmitted to the Ethernet control module, and through gate-level control, it is determined which module's data to send to the output port. The scheduling table configuration module reads in the generated scheduling table and the local clock of the time synchronization core module. When it reaches the receiving time point of a certain message, a receiving trigger signal is given to the receiving module to open the window for reception. When it reaches the sending time point of a certain message, a trigger signal is given to the UDP processing module to command it to send the corresponding TT message to guide the transmission of real-time data.

[0063] The functions of each module are as follows:

[0064] ① GMII2RGMII conversion module: It realizes the data format conversion inside and outside the FPGA. The FPGA receives network port data through the PHY chip internally, and double-edge sampling is adopted, that is, 4-bit data is collected at both the rising and falling edges of the clock. However, the internal logic of the FPGA only operates at the rising edge of the clock. Therefore, this module is needed to convert the double-edge four-bit RGMII signal into a single-edge eight-bit GMII signal.

[0065] ② Data receiving module: It realizes operations such as MAC layer frame decoding, error checking, and data splitting. According to its category, it is split into the ARP or UDP or time synchronization core module. Specifically, ARP frames enter the ARP processing module, RC, BE, and TT stream information enter the UDP processing module, and PCF frames enter the time synchronization core module.

[0066] ③ ARP processing module: It follows the ARP protocol to obtain the physical MAC address of the device connected to the Ethernet cable.

[0067] ④ UDP processing module: It transmits Ethernet frames following the IP / UDP protocol.

[0068] ⑤ Time synchronization core module: It transmits the protocol control frame PCF following the AS6802 protocol under the TTE standard, and maintains time synchronization between the communication parties through data interaction, and outputs the local time to provide a time standard.

[0069] ⑥ Ethernet control module: The Ethernet control module determines through gate-level control based on the current working state of the device to forward the output data of the ARP module, UDP module, or time synchronization core module to the network port.

[0070] ⑦ Data sending module: It realizes the MAC layer frame assembly operation.

[0071] ⑧ Scheduling table configuration module: The scheduling table configuration module reads in the generated scheduling table and the local clock of the time synchronization core module. When the receiving time point of a certain message arrives, it gives a receiving trigger signal to the receiving module to open the window for reception. When the sending time point of a certain message arrives, it gives a trigger signal to the UDP processing module to command it to send the corresponding TT message to guide the transmission of real-time data.

[0072] The design of this system makes signal processing clearer. The time synchronization core module integrates the time synchronization function with traditional Ethernet, and the scheduling table configuration module integrates the generated scheduling table scheme with traditional Ethernet. On the basis of time synchronization, it can be compatible with the functions of traditional Ethernet and at the same time achieve deterministic transmission of the delay of the real-time data TT stream.

[0073] The content not detailed in the specification of the present invention belongs to the prior art well-known to those skilled in the art.

[0074] The specific embodiments described above have further elaborated on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for transmitting test data with time delay deterministic in TTE-converged Ethernet, characterized in that: The method comprises: Step 1: Design the time synchronization core module in accordance with the TTE protocol, process the received protocol control frame PCF, implement high-precision time synchronization of multiple nodes through transparent clock update, solidification and compression algorithms, and use the command-condition interaction method to control the status and core signals; Step 2: Generate a scheduling table using a maximum matching algorithm combined with a cutoff priority, wherein the scheduling table is used to characterize the matching relationship between the real-time data TT stream and the sending time; including: Input message model parameters, including terminal node information, switch information, transmission link information, and parameters of all TT message information; Cycle calculation, based on the idea of ​​TDMA time division multiple access, the TT message is allocated periodic time slots, and the matrix cycle MC and the basic cycle BC are defined. A TT message is sent at least once in a matrix cycle MC, and a TT message is sent at most once in a matrix cycle BC; For the shortest path calculation, the Dijkstra algorithm is used to generate a shortest path tree for each message source node and determine the shortest path for each TT message; Deadline priority preprocessing, pre-prioritizes all TT messages in order of deadline from small to large; Maximum matching sorting, re-sorting all TT messages based on the in-and-out degrees of all nodes, defining the node with the largest out-degree as the sending node and the node with the smallest in-degree as the receiving node, and assigning priorities to the TT messages of the source node and the target node, which are composed of the sending node and the receiving node; Message allocation, assigning each TT message to a matrix cycle according to the pre-sorted priority; Conflict detection: Check whether each TT message exceeds the deadline. If there is a conflict, it means that the current input message model parameters are unreasonable. The input message model parameters are readjusted. If there is no conflict, a scheduling table is generated. Load the schedule, design the schedule configuration module, and deploy the generated schedule to the schedule configuration module; Step 3: Use FPGA to load the scheduling table into the scheduling configuration module, and combine it with the time synchronization core module to periodically allocate time slots for protocol control frames, real-time data, and non-real-time data in turn.

2. The method for transmitting test data with time delay deterministic in TTE-converged Ethernet according to claim 1, characterized in that: The step one comprises: Design the PCF receiving module to parse the UDP data packets obtained by the network layer, extract the integration period, member group, synchronization priority, synchronization domain, PCF frame type and transparent clock field; design the PCF sending module to obtain the integration period, member group, synchronization priority, synchronization domain, PCF frame type and transparent clock field according to the core signal parameters of the current system after the sending condition is triggered, and frame it into a UDP data packet and send it to the network layer; Design transparent clock update, solidification and compression algorithms. The transparent clock update is used to record the cumulative transmission delay update in the entire link transmission, including dynamic and static delays. The solidification algorithm is used to reorder the receiving time points and transparent clock values ​​of the PCF frames on each link to ensure that the receiving and sending order of each PCF frame are the same, and the sending and receiving intervals are equal. The compression algorithm is used to integrate the PCF frames received by the CM device from multiple SM devices, obtain the local clock difference of each SM based on the solidified time point in each PCF frame, and execute the compression algorithm to obtain a weighted and unified compression time point, which is used as the standard to correct the local clock of each device. Design the time synchronization core module, execute the corresponding algorithm and complete the management of local status and core signals according to the command-condition interaction method.

3. The method for transmitting test data with time delay deterministic in TTE-converged Ethernet according to claim 2, characterized in that: The method of executing the corresponding algorithm and completing the management of the local state and core signal according to the command-condition interaction method includes: the solidification processing module and the compression processing module execute the corresponding solidification and compression algorithms, the state control module manages the local state jump, maintains the state core signal, the timeout module detects whether the time in the current state exceeds the threshold limit, maintains the time_out core signal, the clustering detection module detects whether the number of local member groups exceeds the threshold limit, maintains the local_member core signal, the local time control module controls the local time count and jump, maintains the local_clk core signal, the local cycle control module controls the local cycle count and jump, maintains the local_cycle core signal, and the synchronization calculation module calculates the correction value of the local time according to the input parameters, and maintains the clk_correct core signal.

4. The method for transmitting test data with time delay deterministic in TTE-converged Ethernet according to claim 1, characterized in that: The step three comprises: Calculate the cycle time, obtain the time required for protocol control frame transmission through the design of the time synchronization core module, obtain the time required for real-time data transmission through the message model parameters, set the time required for non-real-time data transmission to be the same as the time required for real-time data transmission, and use the superposition of the three parts of the time for transmission of protocol control frames, real-time data, and non-real-time data as the time cycle time for transmitting information in the link; Protocol control frame sending, in the first part of each time period, according to the management and control of the time synchronization core module, a protocol control frame PCF is sent; Real-time data transmission, in the second part of each time cycle, the time synchronization core module provides local time, and according to the matching relationship between real-time data and transmission time in the schedule table, a transmission instruction is output when a specific time node is reached to guide the transmission of real-time data in the Ethernet data cache, namely, the TT time trigger flow; Non-real-time data transmission: In the third part of each time period, non-real-time data in the Ethernet data buffer is sent, including RC rate limiting flow and BE best effort forwarding flow.

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