Communication device and method with read address bias

Abstract

The invention provides a communication device and method with read address bias. The communication device comprises an MIPI main control chip and at least two sub-chips connected with the MIPI main control chip through a bus, and each sub-chip is provided with an MIPI module. The MIPI modules of the sub-chips on the same bus are configured with register address offsets and register address response ranges, so that register address access ranges of the sub-chips connected to the same bus do not conflict with each other. The MIPI main control chip sends an MIPI reading instruction including register address information to the MIPI module, and the MIPI module controls the bus and outputs the value of the corresponding register if the instruction is judged to be responded according to the register address information, the register address offset and the register address response range. According to the invention, the problem of read-back competition of a plurality of MIPI modules under the same MIPI bus and USID can be well solved, the communication time can be reduced, the read-back capability of each sub-chip can be reserved, and comprehensive testing and debugging are more convenient.

Description

Technical Field

[0001] The present invention relates to the field of MIPI communication technology, and in particular to a communication device and method with read address bias. Background Art

[0002] At present, the integration of RFFE (RF Front End Interface) chips is getting higher and higher, and the same USID (Unique Slave ID, the ID number owned by the RFFE sub-chip, which is unique on the same MIPI bus) often covers multiple RFFE functional components. However, in the chip design stage, for the sake of layout and wiring or chip (die) reuse, the logic circuits may be distributed on different chips, and each logic circuit has complete MIPI functions. This increases the communication speed and makes testing easier and more comprehensive. However, the MIPI protocol is a half-duplex protocol with a readback function. However, for the scenario where multiple MIPI modules are located on the same MIPI bus and USID, there will be a situation where the bus is preempted during readback. For the situation of multiple MIPI modules with the same USID on a single bus, the relevant technology usually only retains the readback capability of the main module, and the readback capability of the sub-module is disabled through GPIO or directly has no readback capability, resulting in a waste of the readback function of the sub-module.

[0003] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0004] The purpose of the present invention is to provide a communication device and method with read address bias to solve the technical problem in the prior art that multiple MIPI modules under the same MIPI bus and USID cause bus competition due to preempting the MIPI bus when reading back. The present invention can well solve the readback competition problem of multiple MIPI modules under the same MIPI bus and USID, and can well retain the readback capability of each sub-chip while reducing the communication time, which is more convenient for comprehensive testing and debugging.

[0005] In order to achieve the above-mentioned object, the present invention is implemented by the following technical scheme: a communication device with read address bias, comprising a MIPI main control chip and at least two sub-chips connected to the MIPI main control chip through a bus, each of the sub-chips is provided with a MIPI module, and the MIPI modules of each of the sub-chips on the same bus are configured with a register address bias and a register address response range, so that the register address access ranges of each of the sub-chips connected to the same bus do not conflict with each other;

[0006] The MIPI master control chip is configured to send a MIPI read instruction to the MIPI module, wherein the MIPI read instruction includes register address information;

[0007] The MIPI module is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address offset and the register address response range, and if so, control the bus and output the value of the corresponding register.

[0008] Optionally, the sub-chips connected to the same bus are connected in parallel.

[0009] Optionally, register address access ranges of the sub-chips connected to the same bus do not conflict with each other, including:

[0010] With respect to the MIPI master control chip, the addressing space formed by the register address access ranges of all the sub-chips connected to the same bus is continuous.

[0011] Optionally, the bus includes a clock signal line and a data signal line;

[0012] The MIPI module includes a main logic control unit and a cache unit, the main logic control unit is connected to the cache unit through a first internal signal line, a second internal signal line and a third internal signal line, the main logic control unit is connected to the MIPI main control chip through the clock signal line, and the cache unit is connected to the MIPI main control chip through the data signal line;

[0013] When the signal on the first internal signal line is at a low level, the MIPI module operates in an instruction receiving state; at this time, the cache unit is configured to receive the MIPI read instruction sent by the MIPI main control core, and send the MIPI read instruction to the main logic control unit through the second internal signal line; the main logic control unit is configured to determine whether to respond to the MIPI read instruction according to the register address information, the register address offset and the register address response range, and if so, set the signal on the first internal signal line to a high level, so that the MIPI module operates in a data readback state;

[0014] When the MIPI module operates in the data read back state, at this time, the main logic control unit is configured to send the value of the corresponding register to the cache unit through the third internal signal line; the cache unit is configured to operate in the push-pull output state to send the value of the corresponding register to the MIPI master control chip; the main logic control unit is also used to set the signal on the first internal signal line to a low level after not responding to the MIPI read instruction or completing the MIPI read instruction, so that the MIPI module operates in the instruction receiving state.

[0015] Optionally, the register address information includes a register starting address and a number of read-back registers, and the MIPI module is configured to: calculate a current internal read address based on the register starting address, the number of read-back registers, the register address offset, and the current read-back number; and determine whether the current internal read address is within the register address response range, and if so, control the bus and output the value of the register corresponding to the current internal read address.

[0016] Optionally, the MIPI module is configured to determine whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chip, and if so, determine whether to respond to the MIPI read instruction based on the register address information, the register address offset and the register address response range.

[0017] Optionally, the MIPI module is configured to, after determining to respond to the MIPI read instruction based on the register address information, the register address offset and the register address response range, further include: determining whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chip, and if so, responding to the MIPI read instruction.

[0018] Optionally, the sub-chip includes a radio frequency front-end interface chip.

[0019] In order to achieve the above object, the present invention further provides a communication method, which is used for any of the above communication devices with read address bias, and the communication method comprises:

[0020] The MIPI master control chip sends a MIPI read instruction to the MIPI module, wherein the MIPI read instruction includes register address information;

[0021] The MIPI module determines whether to respond to the MIPI read instruction according to the register address information, the register address offset and the register address response range, and if so, controls the bus and outputs the value of the corresponding register.

[0022] Optionally, the communication method further includes:

[0023] The register address offset and / or the register address response range are updated online.

[0024] Compared with the prior art, the communication device and method with read address bias provided by the present invention have the following advantages:

[0025] The communication device with read address bias provided by the present invention comprises a MIPI main control chip and at least two sub-chips connected to the MIPI main control chip through a bus, each of the sub-chips is provided with a MIPI module, and the MIPI modules of each of the sub-chips on the same bus are configured with a register address bias and a register address response range, so that the register address access ranges of each of the sub-chips connected to the same bus do not conflict with each other; the MIPI main control chip is configured to send a MIPI read instruction to the MIPI module, and the MIPI read instruction includes register address information; the MIPI module is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address bias and the register address response range, and if so, control the bus and output the value of the corresponding register. Therefore, in the communication device with read address bias provided by the present invention, the MIPI modules of each of the sub-chips connected to the same bus are configured with register address bias and register address response range, and the register address access ranges of each of the sub-chips connected to the same bus can be made non-conflicting with each other. Therefore, the readback competition problem of multiple MIPI modules under the same MIPI bus and USID can be well solved, the communication time can be reduced while the readback capability of each sub-chip can be well retained, and comprehensive testing and debugging are more convenient.

[0026] Since the communication method provided by the present invention and the communication device with read address bias provided by the present invention belong to the same inventive concept, the communication method provided by the present invention at least has all the advantages of the communication device with read address bias provided by the present invention. For details of the beneficial effects of the communication method provided by the present invention, please refer to the above description of the beneficial effects of the communication device with read address bias provided by the present invention, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the overall structure of a communication device with a read address bias provided in Embodiment 1 of the present invention;

[0028] Figure 2 A schematic diagram of a first application scenario of the communication device with read address bias provided by the present invention;

[0029] Figure 3 A schematic diagram of a second application scenario of the communication device with read address bias provided by the present invention;

[0030] Figure 4 A schematic diagram of the structure of a MIPI module of a communication device with a read address bias provided by the present invention;

[0031] Figure 5 An example timing diagram of a communication device with a read address bias provided by the present invention when executing a MIPI read instruction;

[0032] Figure 6 An example timing diagram of a communication device with a read address bias provided by the present invention when executing a MIPI read instruction;

[0033] Figure 7 A schematic diagram of the flow chart of the MIPI module of the communication device with read address bias provided by the present invention when executing a MIPI write instruction;

[0034] Figure 8 A schematic diagram of the overall flow of the communication method provided in Embodiment 2 of the present invention;

[0035] The reference numerals are as follows:

[0036] MIPI main control chip-100; sub-chips-210, 220, 230, 240, 250; MIPI modules-211, 221, 231, 241, 251; main logic control unit-2111, cache unit-2112;

[0037] Clock signal lines - SCLK, SCLK1, SCLK2, data signal lines - SDATA, DATA1, DATA2;

[0038] A first internal signal line -SDATA_OEN, a second internal signal line -SDATA_I, and a third internal signal line -SDATA_O. DETAILED DESCRIPTION

[0039] The following is a further detailed description of the communication device and method with read address bias proposed by the present invention in conjunction with the accompanying drawings. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Any modification of the structure, change of the proportional relationship or adjustment of the size, in the case of the same or similar effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific environment to be applied and used. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or part with the same function, and its repeated description is omitted. In this specification, similar reference numerals and letters are used to refer to similar items, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures. In addition, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0040] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. The singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features.

[0041] It should be understood that when an element is referred to as being "connected," "connected to," or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly connected to" another element, there are no intervening elements.

[0042] The core idea of ​​the present invention is to provide a communication device and method with read address bias. The present invention can well solve the readback competition problem of multiple MIPI modules under the same MIPI bus and USID, and can well retain the readback capability of each sub-chip while reducing the communication time, which is more convenient for comprehensive testing and debugging.

[0043] Embodiment 1

[0044] In order to realize the above idea, this embodiment provides a communication device with a read address bias. For example, see Figure 1 , Figure 1 The overall structure diagram of the communication device with read address bias provided by the first embodiment of the present invention. Figure 1 It can be seen that the communication device with read address bias provided in this embodiment includes a MIPI main control chip 100 and at least two sub-chips ( Figure 1, three sub-chips 210, 220 and 230 are shown in the figure, each of the sub-chips 210, 220 and 230 is respectively provided with a MIPI module 211, 221 and 231, and the MIPI modules 211, 221 and 231 of each of the sub-chips 210, 220 and 230 on the same bus are configured with a register address offset and a register address response range, so that the register address access ranges of each of the sub-chips 210, 220 and 230 connected to the same bus do not conflict with each other. Specifically, the MIPI master control chip 100 is configured to send a MIPI read instruction to the MIPI modules 211, 221 and 231, and the MIPI read instruction includes register address information; the MIPI modules 211, 221 and 231 are configured to determine whether to respond to the MIPI read instruction according to the register address information, the register address offset and the register address response range, and if so, control the bus and output the value of the corresponding register.

[0045] Therefore, in the communication device with read address bias provided by the present invention, the MIPI modules 211, 221 and 231 of each of the sub-chips 210, 220 and 230 connected to the same bus are configured with register address bias and register address response range, and the register address access ranges of each of the sub-chips 210, 220 and 230 connected to the same bus do not conflict with each other. Therefore, the read-back competition problem of multiple MIPI modules 211, 221 and 231 under the same MIPI bus and USID can be well solved, and the read-back capability of each sub-chip 210, 220 and 230 can be well retained while reducing the communication time, which is more convenient for comprehensive testing and debugging.

[0046] It should be noted that, as those skilled in the art can understand, the MIPI modules 211, 221 and 231, in addition to the functions described herein, also have various functions that should be supported by the MIPI protocol. Furthermore, the MIPI read instruction in this article is a MIPI instruction whose operation type is a register read instruction. For more detailed information about the MIPI instructions and the MIPI protocol, please refer to the content related to the MIPI protocol known to those skilled in the art. Due to space limitations, this article will not elaborate on this. In addition, it should be understood that the three sub-chips 210, 220 and 230 located on the same bus in this article are only exemplary and not a limitation of the present invention. The present invention does not limit the number of sub-chips.

[0047] Exemplarily, unless otherwise specified, the sub-chips 210, 220 and 230 in each embodiment of the present invention are defaulted to RF front-end interface chips. But it is obvious that those skilled in the art should be able to understand that the present invention does not place too many restrictions on the specific types of the sub-chips 210, 220 and 230. The sub-chips 210, 220 and 230 may also be other chips other than the RF front-end interface chip. For example, the sub-chips 210, 220 and 230 may be, but are not limited to, video decoding chips, display interface chips, and common mode filter chips. Further, the bus is a MIPI bus, and the MIPI master chip 100 is a device that controls the MIPI signal bus (Signal Bus) of the control system. The present invention does not place too many restrictions on the MIPI master chip 100. For example, the MIPI master chip 100 may be an RFIC (radio frequency integrated circuit) in a mobile phone system.

[0048] Preferably, in some of the exemplary embodiments, please continue to refer to Figure 1 ,from Figure 1 It can be seen that the sub-chips 210, 220 and 230 connected to the same bus are connected in parallel. Therefore, the present invention can not only effectively avoid excessive wiring, but also simplify the control complexity of the communication interaction between the MIPI modules 211, 221 and 231 and each of the sub-chips 210, 220 and 230.

[0049] It should be understood that the communication device with read address bias provided by the present invention does not impose too many restrictions on its application scenarios. For example, in some of the embodiments, see Figure 2 , Figure 2 A schematic diagram of a first application scenario of a communication device with a read address bias provided by the present invention. Figure 2 It can be seen that in this application scenario, multiple sub-chips 210, 220 and 230 located on the same bus can be integrated into the same highly integrated chip. For example, in some other implementations, see Figure 3 , Figure 3 A schematic diagram of a second application scenario of the communication device with read address bias provided by the present invention. Figure 3 It can be seen that in this application scenario, multiple sub-chips 210, 220 and 230 located on the same bus can be integrated with multiple sub-chips 240 and 250 located on another bus in the same highly integrated chip, where the sub-chip 210 is located on these two buses.

[0050] Next, the MIPI modules 211, 221 and 231 of each of the sub-chips 210, 220 and 230 on the same bus are configured with a register address offset and a register address response range, so that the register address access ranges of each of the sub-chips 210, 220 and 230 connected to the same bus do not conflict with each other. The following is described:

[0051] First, the register address offset is the offset value of the address built into each of the MIPI modules 211, 221 and 231, and the register address offsets of each of the MIPI modules 211, 221 and 231 on the same bus are different. Secondly, the register address response range can be understood as the register addressing space of the sub-chips 210, 220 and 230 where the MIPI modules 211, 221 and 231 are located. Again, Figure 1 For the sub-chip 210 in the example, if its register address offset is a and its internal read address addressing space is d~e, then relative to the MIPI main control chip 100, the register address access range of the sub-chip 210 is (a+d)~(a+e). After receiving the register address d in the MIPI read instruction, the MIPI module 211 will calculate da to obtain the internal read address c, and then determine whether c is within its register address response range, that is, only when c≥d and c≤e (in other words, d≥(a+d) and d≤(a+e)), the MIPI module 211 will respond to the MIPI read instruction. More specifically, still based on Figure 1 For example, if the register address offset of sub-chip 210 is 0x00 and the register address response range is 0x00~0x3F, in order to avoid the register address access range of sub-chips 220 and 230 from conflicting with the register address access range of sub-chip 210, the register address offset of sub-chip 220 should be greater than 0x3F, for example, the register address offset of sub-chip 220 is 0x40 and the register address response range is 0x00~0x3F. Similarly, the register address offset of sub-chip 230 should be greater than 0x7F, for example, the register address offset of sub-chip 230 is 0x8A and the register address response range is 0x0A~0x3F. In this scenario, when the register address of the MIPI read command sent by the MIPI master control chip 100 is 0x00~0x3F, the MIPI module 211 of the sub-chip 210 will respond to the command; when the register address of the MIPI read command sent by the MIPI master control chip 100 is 0x40~0x7F, the MIPI module 221 of the sub-chip 220 will respond to the command; when the register address of the MIPI read command sent by the MIPI master control chip 100 is 0x8A~0xBF, the MIPI module 231 of the sub-chip 230 will respond to the command.

[0052] It should be understood that, for each of the sub-chips 210, 220 and 230 located on the same bus, the present invention does not impose too many restrictions on their register address offsets and read address response ranges. The register address offsets and read address response ranges of each sub-chip 210, 220 and 230 can be the same or different. However, the register address access ranges of each sub-chip 210, 220 and 230 obtained by the register address offset and the read address response range cannot conflict with each other. In order to ensure that the register address access range of each sub-chip 210, 220 and 230 is unique relative to the MIPI master chip 100, preferably, the register address offsets of each sub-chip 210, 220 and 230 are different.

[0053] Preferably, in some exemplary implementations, the register address access ranges of the sub-chips 210, 220 and 230 connected to the same bus do not conflict with each other, including:

[0054] With respect to the MIPI master chip 100, the addressing space formed by the register address access ranges of all the sub-chips 210, 220 and 230 connected to the same bus is continuous. Therefore, the communication device with read address bias provided by the present invention can make the readback control logic of the MIPI master chip 100 and each MIPI module 211, 221 and 231 simpler.

[0055] For example, as exemplified above: the register address offset of sub-chip 210 is 0x00 and the register address response range is 0x00-0x3F, the register address offset of sub-chip 220 is 0x40 and the register address response range is 0x00-0x3F, the register address offset of sub-chip 230 is 0x8A and the register address response range is 0x00-0x35, in this scenario, the addressing space formed by sub-chip 210 and sub-chip 220 is continuous, while the addressing space formed by sub-chip 220 and sub-chip 230 is discontinuous. However, if the register address offset of sub-chip 230 is 0X80 and the register address response range is 0x00-0x3F, the addressing space formed by sub-chips 210, 220 and 230 is continuous.

[0056] Preferably, in some of the exemplary embodiments, please continue to refer to Figure 1 ,from Figure 1 It can be seen that the bus includes a clock signal line SCLK and a data signal line SDATA, and the MIPI modules 211 , 221 and 231 output the values ​​of the corresponding registers through the data signal line SDATA.

[0057] Preferably, in some of the exemplary embodiments, please continue to refer to Figure 1 and Figure 4 ,in, Figure 4 A schematic diagram of the structure of a MIPI module of a communication device with a read address bias provided by the present invention. Figure 1 and Figure 4 It can be seen that the bus includes a clock signal line SCLK and a data signal line SDATA. For ease of understanding and explanation, the MIPI module 221 is used as an example in this article. The structures of the MIPI module 221 and the MIPI module 231 are similar to the structure of the MIPI module 221, and are not described in detail in this article. Figure 4 It can be seen that the MIPI module 211 includes a main logic control unit 2111 and a cache unit 2112. The main logic control unit 2111 and the cache unit 2112 are connected through a first internal signal line SDATA_OEN, a second internal signal line SDATA_I and a third internal signal line SDATA_O. The main logic control unit 2111 is connected to the MIPI master control chip 100 through the clock signal line SCLK, and the cache unit 2112 is connected to the MIPI master control chip 100 through the data signal line SDATA.

[0058] Specifically, when the signal on the first internal signal line SDATA_OEN is at a low level, the MIPI module 211 operates in an instruction receiving state (i.e., at this time, the port of the cache unit 2112 connected to the data signal line SDATA is in a high impedance state); at this time, the cache unit 2112 is configured to receive the MIPI read instruction sent by the MIPI main control core, and send the MIPI read instruction to the main logic control unit 2111 through the second internal signal line SDATA_I; the main logic control unit 2111 is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address offset and the register address response range. If so, the signal on the first internal signal line SDATA_OEN is set to a high level, so that the MIPI module 211 operates in a data read back state.

[0059] When the MIPI module 211 works in the data read back state, the main logic control unit 2111 is configured to send the value of the corresponding register to the cache unit 2112 through the third internal signal line SDATA_O; the cache unit 2112 is configured to work in the push-pull output state to send the value of the corresponding register to the MIPI master control chip 100.

[0060] The main logic control unit 2111 is further used to set the signal on the first internal signal line SDATA_OEN to a low level after not responding to the MIPI read instruction or completing the MIPI read instruction, so that the MIPI module 211 operates in the instruction receiving state.

[0061] Therefore, in the communication device with read address bias provided by the present invention, the MIPI module 211 adopts a modular design of the main logic control unit 2111 and the cache unit 2112, which has simple logic and is easy to implement.

[0062] It should be noted that, as those skilled in the art can understand, the communication device with read address bias provided by the present invention does not limit the communication method between the main logic control unit 2111 and the cache unit 2112. For example, in some other exemplary implementations, the main logic control unit 2111 and the cache unit 2112 may also be connected through other IO interfaces, which is not limited herein.

[0063] Preferably, in some exemplary embodiments, the register address information includes a register start address and a readback register quantity, and the MIPI modules 211, 221, and 231 are configured to: calculate the current internal read address according to the register start address, the readback register quantity, the register address offset, and the current readback quantity; and determine whether the current internal read address is within the register address response range, and if so, control the bus and output the value of the register corresponding to the current internal read address. It can be seen that in the communication device with read address offset provided by the present invention, the MIPI modules 211, 221, and 231 will only occupy the bus to send back data when the register address information in the MIPI read instruction is within the register address range after its own offset. By reasonably setting the register address offset of each MIPI module 211, 221, and 231, it can be ensured that only one MIPI module 211, 221, or 231 occupies the bus at the same time, thereby well solving the readback competition problem.

[0064] Preferably, in some exemplary embodiments, the MIPI modules 211, 221 and 231 are configured to determine whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chips 210, 220 and 230, and if so, determine whether to respond to the MIPI read instruction according to the register address information, the register address offset and the register address response range. Therefore, the communication device with read address offset provided by the present invention can further improve communication efficiency by determining whether to respond to the MIPI read instruction according to the register address after determining that the USID matches when performing a readback operation.

[0065] For example, please combine Figure 1 and Figure 4 , and see Figure 5 , Figure 5 A flow chart of the MIPI module of the communication device with read address bias provided by the present invention when executing a MIPI write instruction. Figure 5 It can be seen that in this example, the process of the MIPI module 211 writing instructions is roughly as follows:

[0066] SA1: After determining that the start signal (SSC, Sequence Start Condition) of the MIPI command is received, all MIPI data packets start from SSC. SSC is a combination of a specific clock signal and a data signal: the clock signal line SCLK remains at a low level, and a high level pulse appears on the data signal line SDATA), execute step SA2;

[0067] SA2: After determining that the USID corresponding to the MIPI instruction matches the USID of the sub-chip 210, if the instruction is a read instruction (i.e., the MIPI read instruction in this article), if so, execute step SA3; if not, after processing the instruction, return to execute step SA1;

[0068] SA3: extracting the register address information in the MIPI read instruction to obtain a register start address and a number of read-back registers; subtracting the register address offset configured in the MIPI module 211 from the register start address information to obtain a current internal read address, and resetting the current read-back number to 0;

[0069] SA4: Determine whether the current internal read address is within the register address response range configured in the MIPI module 211. If so, pull the first internal signal line SDATA_OEN high, and output the value of the register corresponding to the current internal read address to the cache unit 2112 through the third internal signal line SDATA_O, so that the cache unit 2112 outputs the value of the register to the MIPI module 211 through the data signal line SDATA; if not, pull the first internal signal line SDATA_OEN low, so that the cache unit 2112 enters the data receiving state;

[0070] SA5: Determine whether the MIPI read instruction is completed. If not, increment the current internal read address and return to execute step SA4; if so, execute step SA6.

[0071] Exemplarily, the current readback number is added by 1, and it is determined whether the current readback number is greater than or equal to the readback register number. If not, the MIPI read instruction has not ended, the current internal read address is incremented, and the process returns to step SA4; if yes, the MIPI read instruction ends, and step SA6 is executed;

[0072] SA6: Pull the first internal signal line SDATA_OEN low so that the cache unit 2112 enters a data receiving state, and returns to step SA1.

[0073] See also Figure 6 , Figure 6 This is an example timing diagram of the communication device with read address offset provided by the present invention when executing MIPI read instructions. A further example is as follows, taking the scenario in which the register address offset of the sub-chip 210 as exemplified above is 0x00 and the register address response range is 0x00-0x3F, the register address offset of the sub-chip 220 is 0x40 and the register address response range is 0x00-0x3F, and the register address offset of the sub-chip 230 is 0x80 and the register address access range is 00x00-0x3F, the register address information read by the MIPI master chip 100 are read address 1 (for example, the register starting address is 0x2F and the number of read-back registers is 3), read address 2 (for example, the register starting address is 0x5A and the number of read-back registers is 10), and read address 3 (for example, the register starting address is 0x9D and the number of read-back registers is 8) as examples, from Figure 6 It can be seen that the MIPI main control chip 100 and the three sub-chips 210 , 220 and 230 control the data signal line SDATA alternately.

[0074] In addition, it should be noted that, as can be understood by those skilled in the art, the communication device with read address offset provided by the present invention does not impose too many restrictions on executing MIPI write instructions. For example, see Figure 7 , Figure 7 This is an example timing diagram of a communication device with a read address bias provided by the present invention when executing a MIPI read instruction. Figure 7 As shown, in some exemplary implementations, when executing a MIPI write instruction, all MIPI modules 211, 221 and 231 may respond to the MIPI write instruction and update their corresponding internal registers according to information such as register addresses and register values ​​in the command.

[0075] It should be noted that, as can be understood by those skilled in the art, the above examples are only exemplary descriptions of preferred embodiments of the present invention. For example, in some exemplary embodiments, the MIPI modules 211, 221 and 231 are configured to, after determining to respond to the MIPI read instruction based on the register address information, the register address offset and the register address response range, further include: determining whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chips 210, 220 and 230, and if so, responding to the MIPI read instruction.

[0076] Embodiment 2

[0077] This embodiment provides a communication method, which is used in the communication device with read address bias described in any implementation of embodiment 1. For example, see Figure 8 , Figure 8 The overall flow chart of the communication method provided in this embodiment is as follows. Figure 8 It can be seen that the communication method provided in this embodiment includes:

[0078] S100: The MIPI master control chip 100 sends a MIPI read instruction to the MIPI modules 211, 221 and 231, where the MIPI read instruction includes register address information;

[0079] S200: The MIPI modules 211, 221 and 231 determine whether to respond to the MIPI read instruction according to the register address information, the register address offset and the register address response range, and if so, control the bus and output the value of the corresponding register.

[0080] Since the communication method provided by the present invention and the communication device with read address bias provided by the present invention belong to the same inventive concept, the communication method provided by the present invention at least has all the advantages of the communication device with read address bias provided by the present invention. For details of the beneficial effects of the communication method provided by the present invention, please refer to the above description of the beneficial effects of the communication device with read address bias provided by the present invention, which will not be repeated here.

[0081] Since the basic principle of the communication method provided by the present invention is the same as that of the communication device with read address bias provided by the present invention, for the parts not mentioned in the communication method provided in this embodiment, please refer to the relevant description of Embodiment 1 for adaptive understanding.

[0082] Preferably, in some exemplary embodiments, the communication method further comprises: updating the register address offset and / or the register address response range online. Thus, the communication method provided by the present invention can make the present invention better adaptable to different usage scenarios by updating the register address offset and / or the register address response range online. Different usage scenarios include but are not limited to the addition of sub-chips.

[0083] It should be noted that those skilled in the art should be able to understand that the present invention does not limit the specific method of updating the register address offset and / or the register address response range. For example, in some embodiments, the register address offset and / or the register address response range can be updated through GPIO; in other embodiments, the register address offset and / or the register address response range can also be updated by register writing; in still other embodiments, the register address offset and / or the register address response range can also be updated by Efuse burning.

[0084] Compared with the prior art, the communication device and method with read address bias provided by the present invention have the following advantages:

[0085] The communication device with read address bias provided by the present invention is configured with a register address bias and a register address response range on the MIPI modules of each of the sub-chips connected to the same bus, and can ensure that the register address access ranges of each of the sub-chips connected to the same bus do not conflict with each other. Therefore, the readback competition problem of multiple MIPI modules under the same MIPI bus and USID can be well solved, the communication time can be reduced while the readback capability of each sub-chip can be well retained, and comprehensive testing and debugging are more convenient.

[0086] Since the communication method provided by the present invention and the communication device with read address bias provided by the present invention belong to the same inventive concept, the communication method provided by the present invention at least has all the advantages of the communication device with read address bias provided by the present invention. For details of the beneficial effects of the communication method provided by the present invention, please refer to the above description of the beneficial effects of the communication device with read address bias provided by the present invention, which will not be repeated here.

[0087] It should be noted that the devices and methods disclosed in the embodiments of this article can also be implemented in other ways. The device implementation described above is only schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of this article. In this regard, each box in the flowchart or block diagram can represent a part of a module, program or code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented by a dedicated hardware-based system for performing a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0088] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0089] The above description is only a description of the preferred implementation of the communication device and method with read address bias provided by the present invention, and is not any limitation on the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure content belong to the protection scope of the present invention. Obviously, technicians in this field can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations belong to the scope of the present invention and its equivalent technology, the present invention is also intended to include these modifications and variations.

Claims

1. A communication device with a read address bias, characterized in that: It comprises a MIPI main control chip and at least two sub-chips connected to the MIPI main control chip through a bus, each of the sub-chips is provided with a MIPI module, and the MIPI modules of the sub-chips on the same bus are configured with a register address offset and a register address response range, so that the register address access ranges of the sub-chips connected to the same bus do not conflict with each other; The MIPI master control chip is configured to send a MIPI read instruction to the MIPI module, wherein the MIPI read instruction includes register address information; The MIPI module is configured to determine whether to respond to the MIPI read instruction based on the register address information, the register address offset and the register address response range, and if so, control the bus and output the value of the corresponding register.

2. The communication device according to claim 1, characterized in that The sub-chips connected to the same bus are connected in parallel.

3. The communication device according to claim 1, characterized in that The register address access ranges of the sub-chips connected to the same bus do not conflict with each other, including: With respect to the MIPI master control chip, the addressing space formed by the register address access ranges of all the sub-chips connected to the same bus is continuous.

4. The communication device according to claim 1, characterized in that: The bus includes a clock signal line and a data signal line; The MIPI module includes a main logic control unit and a cache unit, the main logic control unit is connected to the cache unit through a first internal signal line, a second internal signal line and a third internal signal line, the main logic control unit is connected to the MIPI main control chip through the clock signal line, and the cache unit is connected to the MIPI main control chip through the data signal line; When the signal on the first internal signal line is at a low level, the MIPI module operates in an instruction receiving state; at this time, the cache unit is configured to receive the MIPI read instruction sent by the MIPI main control core, and send the MIPI read instruction to the main logic control unit through the second internal signal line; the main logic control unit is configured to determine whether to respond to the MIPI read instruction according to the register address information, the register address offset and the register address response range, and if so, set the signal on the first internal signal line to a high level, so that the MIPI module operates in a data readback state; When the MIPI module operates in the data read back state, at this time, the main logic control unit is configured to send the value of the corresponding register to the cache unit through the third internal signal line; the cache unit is configured to operate in the push-pull output state to send the value of the corresponding register to the MIPI master control chip; the main logic control unit is also used to set the signal on the first internal signal line to a low level after not responding to the MIPI read instruction or completing the MIPI read instruction, so that the MIPI module operates in the instruction receiving state.

5. The communication device according to claim 1, characterized in that: The register address information includes a register starting address and a number of read-back registers, and the MIPI module is configured to: calculate a current internal read address based on the register starting address, the number of read-back registers, the register address offset, and the current read-back number; and determine whether the current internal read address is within the register address response range, and if so, control the bus and output the value of the register corresponding to the current internal read address.

6. The communication device according to claim 1, characterized in that: The MIPI module is configured to determine whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chip, and if so, determine whether to respond to the MIPI read instruction based on the register address information, the register address offset and the register address response range.

7. The communication device according to claim 1, characterized in that: The MIPI module is configured to, after determining to respond to the MIPI read instruction based on the register address information, the register address offset and the register address response range, further include: determining whether the USID corresponding to the MIPI read instruction matches the USID of the sub-chip, and if so, responding to the MIPI read instruction.

8. The communication device according to claim 1, characterized in that: The sub-chip includes a radio frequency front-end interface chip.

9. A communication method, characterized in that: For a communication device with a read address bias as claimed in any one of claims 1 to 8, the communication method comprises: The MIPI master control chip sends a MIPI read instruction to the MIPI module, wherein the MIPI read instruction includes register address information; The MIPI module determines whether to respond to the MIPI read instruction according to the register address information, the register address offset and the register address response range, and if so, controls the bus and outputs the value of the corresponding register.

10. The communication method according to claim 9, characterized in that: The communication method further comprises: The register address offset and / or the register address response range are updated online.

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