Semiconductor device

Abstract

There is provided a semiconductor device including: a substrate including a first active pattern and a second active pattern spaced apart from each other; a first gate structure disposed on the first active pattern; a second gate structure disposed on the second active pattern; and a channel semiconductor pattern disposed between the second active pattern and the second gate structure, in which the first gate structure includes a first insulating pattern, a second insulating pattern, and a first high-k dielectric pattern stacked on the first active pattern, the second gate structure includes a third insulating pattern and a second high-k dielectric pattern stacked on the channel semiconductor pattern, and wherein a thickness of the third insulating pattern is in a range of # imgabs 0 # to # imgabs 1 #.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0114348 filed in the Korean Intellectual Property Office on August 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the inventive concept relate to a semiconductor device. Background Art

[0003] Semiconductor devices are widely used in the electronics industry due to their small size, multi-functions and / or low cost characteristics. Semiconductor devices can be classified into any of semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices having both the functions of semiconductor memory devices and semiconductor logic devices.

[0004] With the demand for high-speed and / or low-power electronic devices, high-speed and / or low-voltage semiconductor devices used in electronic devices are also needed, and therefore, highly integrated semiconductor devices have been developed. However, the reliability and electrical characteristics of semiconductor devices may deteriorate due to the high integration of semiconductor devices. Therefore, various technologies for increasing the reliability and electrical characteristics of semiconductor devices have been developed. Summary of the invention

[0005] According to an embodiment of the present invention, a semiconductor device includes: a substrate including a first active pattern and a second active pattern spaced apart from each other; a first gate structure disposed on the first active pattern; a second gate structure disposed on the second active pattern; and a channel semiconductor pattern disposed between the second active pattern and the second gate structure, wherein the first gate structure includes a first insulating pattern, a second insulating pattern, and a first high-k dielectric pattern stacked on the first active pattern, wherein the second gate structure includes a third insulating pattern and a second high-k dielectric pattern stacked on the channel semiconductor pattern, and wherein the thickness of the third insulating pattern is between 100 and 150 nm. to within the range.

[0006] According to an embodiment conceived in the present invention, a semiconductor device includes: a substrate including a first active pattern and a second active pattern spaced apart from each other; a first gate structure disposed on the first active pattern; and a second gate structure disposed on the second active pattern, wherein the first gate structure includes a first insulating pattern, a second insulating pattern, a first high-k dielectric pattern, and a first conductive pattern stacked on the first active pattern, wherein the second gate structure includes a third insulating pattern, a second high-k dielectric pattern, and a second conductive pattern stacked on the second active pattern, wherein the first insulating pattern is disposed between the first active pattern and the second insulating pattern, and wherein a thickness of the third insulating pattern is 30% or less of a thickness of the second high-k dielectric pattern.

[0007] According to an embodiment of the inventive concept, a semiconductor device includes: a substrate including a cell active pattern on a cell region and a first peripheral active pattern and a second peripheral active pattern spaced apart from each other on a peripheral region adjacent to the cell region; a word line disposed in the substrate and crossing the cell active pattern; a bit line disposed on the substrate and crossing the word line; a bit line contact disposed on a central portion of each of the cell active patterns and connected to a corresponding bit line of the bit lines; a storage node contact disposed on an end of each of the cell active patterns; a bonding pad disposed on each of the storage node contacts; a capacitor disposed on the bonding pad; a first peripheral gate pattern disposed on the first peripheral active pattern; and a second A peripheral gate pattern is arranged on a second peripheral active pattern; and a channel semiconductor pattern is arranged between the second peripheral active pattern and the second peripheral gate pattern, wherein the first peripheral gate pattern includes a first insulating pattern, a second insulating pattern, a first high-k dielectric pattern, a first lower conductive pattern, a first upper conductive pattern and a first covering pattern stacked on the first peripheral active pattern, wherein the second peripheral gate pattern includes a third insulating pattern, a second high-k dielectric pattern, a second lower conductive pattern, a second upper conductive pattern and a second covering pattern stacked on the channel semiconductor pattern, and wherein the sum of the thickness of the first insulating pattern and the thickness of the second insulating pattern is in the range of 90% to 110% of the thickness of the third insulating pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a semiconductor device according to an embodiment of the inventive concept.

[0009] Figure 2 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0010] Figure 3 It is along Figure 2 8 and 9 are cross-sectional views taken along line AA′ and line BB′ to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0011] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 5 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0013] Figure 6 It is along Figure 5 8 is a cross-sectional view taken along line CC′ of FIG. 1 to illustrate a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0014] Embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which embodiments of the inventive concept are shown.

[0015] Figure 1 is a block diagram illustrating a semiconductor device according to an embodiment of the inventive concept.

[0016] Reference Figure 1 , the semiconductor device may include a cell block CB and a peripheral block PB at least partially surrounding each of the cell blocks CB. The semiconductor device may be a memory device, and each of the cell blocks CB may include a cell circuit such as a memory integrated circuit. The peripheral block PB may include various peripheral circuits for operating the cell circuit, and the peripheral circuit may be electrically connected to the cell circuit.

[0017] The peripheral block PB may include a sense amplifier circuit SA and a sub-word line driver circuit SWD. For example, the sense amplifier circuits SA may face each other in a first direction D1 with the cell block CB interposed therebetween, and the sub-word line driver circuits SWD may face each other in a second direction D2 with the cell block CB interposed therebetween. The peripheral block PB may further include a power driver circuit and a ground driver circuit for driving the sense amplifier, but embodiments of the inventive concept are not limited thereto.

[0018] Figure 2 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 3 It is along Figure 2 8 and 9 are cross-sectional views taken along line AA′ and line BB′ to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0019] Reference Figure 2 and Figure 3, a semiconductor device according to an embodiment of the inventive concept may include a substrate 100 , a first gate structure GS1 , and a second gate structure GS2 .

[0020] The substrate 100 may include a first peripheral area PA1 and a second peripheral area PA2. The first peripheral area PA1 and the second peripheral area PA2 may be portions of the substrate 100 on which a Figure 1 The substrate 100 may be a silicon substrate. In an embodiment of the inventive concept, the substrate 100 may be a silicon-on-insulator (SOI) substrate.

[0021] In this specification, the first direction D1 may be a direction parallel to the top surface of the substrate 100 .

[0022] The second direction D2 may be a direction parallel to the top surface of the substrate 100 and crossing the first direction D1 .

[0023] The third direction D3 may be a direction substantially perpendicular to the top surface of the substrate 100 .

[0024] A first peripheral active pattern ACT1 , which may be defined by a peripheral device isolation layer, may be disposed on the first peripheral area PA1 of the substrate 100 .

[0025] A pair of first dopant regions 144a may be disposed in the first peripheral active pattern ACT1. The pair of first dopant regions 144a may be spaced apart from each other along the first direction D1 in the first peripheral active pattern ACT1 and the first gate structure GS1 may be disposed between the pair of first dopant regions 144a. For example, the pair of first dopant regions 144a are located at opposite sides of the first gate structure GS1. Here, other regions of the first peripheral active pattern ACT1 except the channel region and the pair of first dopant regions 144a may be the first body region.

[0026] The pair of first dopant regions 144a may correspond to source / drain regions. The pair of first dopant regions 144a may be doped regions having a first conductivity type (eg, n-type). The first body region may have a second conductivity type (eg, p-type) different from the first conductivity type.

[0027] The first gate structure GS1 may be disposed on the first peripheral active pattern ACT1. In the present specification, the first gate structure GS1 may also be referred to as a first peripheral gate pattern GS1. A pair of the first dopant region 144a and the first gate structure GS1 may constitute an NMOS transistor.

[0028] The first gate structure GS1 may include a first insulating pattern 120 a , a second insulating pattern 120 b , a first high-k dielectric pattern 122 a , a first conductive pattern M1 , and a first capping pattern 140 a sequentially stacked on the first peripheral active pattern ACT1 .

[0029] The first insulating pattern 120a and the second insulating pattern 120b in the first gate structure GS1 may be disposed between the first peripheral active pattern ACT1 and the first conductive pattern M1. The first insulating pattern 120a may be disposed closer to the first peripheral active pattern ACT1 than the second insulating pattern 120b. For example, the first insulating pattern 120a is disposed between the first peripheral active pattern ACT1 and the second insulating pattern 120b.

[0030] The first and second insulating patterns 120a and 120b may have a first thickness TH1 and a second thickness TH2, respectively. The sum of the first thickness TH1 and the second thickness TH2 may be to For example, the first insulating pattern 120a and the second insulating pattern 120b may include silicon oxide.

[0031] The first high-k dielectric pattern 122a may be disposed on the second insulating pattern 120b. The first high-k dielectric pattern 122a may include a high-k dielectric material. For example, the first high-k dielectric pattern 122a may include at least one metal oxide, such as hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO) or lead scandium tantalum oxide (PbScTaO).

[0032] The first conductive pattern M1 may be disposed on the first high-k dielectric pattern 122a. The first conductive pattern M1 may include a first lower conductive pattern 130a and a first upper conductive pattern 138a.

[0033] The first lower conductive pattern 130a may be disposed on the first high-k dielectric pattern 122a. For example, a bottom surface 130ab of the first lower conductive pattern 130a may be coplanar with a top surface of the first high-k dielectric pattern 122a. For example, the first lower conductive pattern 130a may include dopant-doped polysilicon. The first lower conductive pattern 130a may have a first conductivity type (e.g., n-type).

[0034] The first upper conductive pattern 138a may be disposed on the first lower conductive pattern 130a. For example, the first upper conductive pattern 138a may include a metal such as aluminum (Al), tungsten (W), or copper (Cu).

[0035] The first capping pattern 140a may be disposed on the first upper conductive pattern 138a. A level of a top surface of the first capping pattern 140a may correspond to a level of a top surface GS1t of the first gate structure GS1. For example, the first capping pattern 140a may include silicon nitride.

[0036] The second peripheral active pattern ACT2 defined by the peripheral device isolation layer may be disposed on the second peripheral area PA2 of the substrate 100. The second peripheral active pattern ACT2 may include a first semiconductor material. For example, the first semiconductor material may be silicon (Si). A pair of second dopant regions 144b may be disposed in the second peripheral active pattern ACT2. The pair of second dopant regions 144b may be spaced apart from each other along the first direction D1 in the second peripheral active pattern ACT2 and the second gate structure GS2 may be disposed between the pair of second dopant regions 144b. For example, the pair of second dopant regions 144b may be disposed at opposite sides of the second gate structure GS2. Here, other regions of the second peripheral active pattern ACT2 except the channel region and the pair of second dopant regions 144b may be defined as a second main region.

[0037] A pair of second dopant regions 144b may correspond to source / drain regions. A pair of second dopant regions 144b may be dopant regions having a conductivity type different from the first conductivity type. For example, a pair of second dopant regions 144b may be dopant regions having a second conductivity type (e.g., p-type). The second body region may have a first conductivity type different from the second conductivity type (e.g., n-type).

[0038] The channel semiconductor pattern CSL may be disposed on the second peripheral active pattern ACT2. The channel semiconductor pattern CSL may include a second semiconductor material. The second semiconductor material may be different from the first semiconductor material, and, for example, the second semiconductor material may be silicon germanium (SiGe). The level of the top surface CSLt of the channel semiconductor pattern CSL may be higher than the level of the top surface 120bt of the second insulating pattern 120b described above. For example, the channel semiconductor pattern CSL may include silicon germanium (SiGe). For example, the thickness CSLD of the channel semiconductor pattern CSL may be in the range of 7nm to 9nm.

[0039] The second gate structure GS2 may be disposed on the second peripheral active pattern ACT2. The channel semiconductor pattern CSL may be disposed between the second peripheral active pattern ACT2 and the second gate structure GS2. In the present specification, the second gate structure GS2 may also be referred to as the second peripheral gate pattern GS2. The level of the top surface GS2t of the second gate structure GS2 may be higher than the level of the top surface GS1t of the first gate structure GS1. The difference between the level of the top surface GS2t of the second gate structure GS2 and the level of the top surface GS1t of the first gate structure GS1 may be 8nm or less. A pair of second dopant regions 144b and the second gate structure GS2 may constitute a PMOS transistor.

[0040] The second gate structure GS2 may include a third insulating pattern 120 c , a second high-k dielectric pattern 122 b , a second conductive pattern M2 , and a second capping pattern 140 b sequentially stacked on the channel semiconductor pattern CSL.

[0041] The third insulating pattern 120c in the second gate structure GS2 may be disposed between the channel semiconductor pattern CSL and the second conductive pattern M2. In other words, the channel semiconductor pattern CSL may be disposed between the second peripheral active pattern ACT2 and the third insulating pattern 120c, and the third insulating pattern 120c may be in contact with the channel semiconductor pattern CSL. The level of the top surface 120ct of the third insulating pattern 120c may be higher than the level of the top surface 120bt of the second insulating pattern 120b.

[0042] The third insulating pattern 120c may have a third thickness TH3. The third thickness TH3 may be 15% or less of the thickness of the second gate structure GS2. The third thickness TH3 may be to For example, the third thickness TH3 may be to In an embodiment of the present inventive concept, the sum of the first thickness TH1 of the first insulating pattern 120a and the second thickness TH2 of the second insulating pattern 120b may be in the range of 90% to 110% of the third thickness TH3 of the third insulating pattern 120c. In an embodiment of the present inventive concept, the third thickness TH3 of the third insulating pattern 120c may be substantially equal to the sum of the first thickness TH1 of the first insulating pattern 120a and the second thickness TH2 of the second insulating pattern 120b. The third insulating pattern 120c may include, for example, silicon oxide.

[0043] The bonding energy between the first insulation pattern 120 a and the first peripheral active pattern ACT1 may be greater than the bonding energy between the third insulation pattern 120 c and the channel semiconductor pattern CSL.

[0044] The second high-k dielectric pattern 122b may be disposed on the third insulating pattern 120c. The third thickness TH3 of the third insulating pattern 120c may be 30% or less of the thickness 122bd of the second high-k dielectric pattern 122b. The second high-k dielectric pattern 122b may include a high-k dielectric material. For example, the second high-k dielectric pattern 122b may include at least one metal oxide, such as hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0045] The second conductive pattern M2 may be disposed on the second high-k dielectric pattern 122b. The second conductive pattern M2 may include a second lower conductive pattern 130b and a second upper conductive pattern 138b.

[0046] The second lower conductive pattern 130b may be disposed on the second high-k dielectric pattern 122b. For example, the second lower conductive pattern 130b may include dopant-doped polysilicon. The second lower conductive pattern 130b may have a second conductivity type (eg, p-type).

[0047] The second upper conductive pattern 138b may be disposed on the second lower conductive pattern 130b. For example, the second upper conductive pattern 138b may include a metal such as aluminum (Al), tungsten (W), or copper (Cu).

[0048] The second capping pattern 140b may be disposed on the second upper conductive pattern 138b. A top surface of the second capping pattern 140b may have a level substantially the same as or the same as a level of a top surface GS2t of the second gate structure GS2. The second capping pattern 140b may include, for example, silicon nitride.

[0049] The first spacers 142 may be disposed on the side surfaces of each of the first gate structure GS1 and the second gate structure GS2, respectively. The first spacers 142 may be spaced apart from each other in the first direction D1 with each of the first gate structure GS1 and the second gate structure GS2 interposed therebetween. For example, each of the first spacers 142 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0050] The first interlayer insulating layer 146 may be disposed on the first and second peripheral active patterns ACT1 and ACT2 and may cover the first and second gate structures GS1 and GS2 and the first spacer 142. For example, the first interlayer insulating layer 146 may include at least one of silicon nitride and silicon oxide.

[0051] The capping layer 148 may cover the top surface of the first interlayer insulating layer 146. The capping layer 148 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride. A plurality of interconnection layers may be disposed on the capping layer 148.

[0052] In a semiconductor device according to an embodiment of the present invention, a sum of a first thickness TH1 and a second thickness TH2 of a first insulating pattern 120a and a second insulating pattern 120b included in a first gate structure GS1 may be in a range of 90% to 110% of a third thickness TH3 of a third insulating pattern 120c included in a second gate structure GS2. In an embodiment of the present invention, the third thickness TH3 may be 30% or less of a thickness 122bd of a second high-k dielectric pattern 122b. In an embodiment of the present invention, the third thickness TH3 may be in a range of 100% to 110% of a third thickness TH3 of a third insulating pattern 120c included in a second gate structure GS2. to within the range.

[0053] As a result, a height difference between the first gate structure GS1 on the first peripheral active pattern ACT1 and the second gate structure GS2 on the second peripheral active pattern ACT2 can be reduced. In addition, since the thickness of the third insulating pattern 120c is reduced, a current value flowing through the second peripheral active pattern ACT2 can be increased.

[0054] 4A to 4F is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. More specifically, 4A to 4F It shows the manufacturing Figure 3 A cross-sectional view of a method of manufacturing a semiconductor device is shown in FIG.

[0055] Reference Figure 4A A first peripheral active pattern ACT1 defined by the peripheral device isolation layer and including the first dopant region 144a may be provided, and a second peripheral active pattern ACT2 defined by the peripheral device isolation layer and including the second dopant region 144b may be provided. In addition, a channel semiconductor pattern CSL may be provided on the second peripheral active pattern ACT2.

[0056] For example, a channel semiconductor layer may be formed on the top surface ACT2t of the second peripheral active pattern ACT2 instead of the top surface ACT1t of the first peripheral active pattern ACT1 by a selective epitaxial growth (SEG) process. Thereafter, an etching process may be performed on the channel semiconductor layer to form a channel semiconductor pattern CSL. The channel semiconductor pattern CSL may have a shape in which the width of the channel semiconductor layer in the first direction D1 is reduced. After forming the channel semiconductor pattern CSL, a dopant implantation process may be performed on the second peripheral active pattern ACT2 except for a portion of the second peripheral active pattern ACT2 covered by the channel semiconductor pattern CSL, thereby forming the second dopant region 144b.

[0057] Reference Figure 4B , a first insulating layer 120Pa may be formed on the first peripheral active pattern ACT1, the second peripheral active pattern ACT2, and the channel semiconductor pattern CSL. At this time, the first insulating layer 120Pa formed on the second peripheral active pattern ACT2 may cover the side surface and the top surface of the channel semiconductor pattern CSL. The thickness of the first insulating layer 120Pa formed on the first peripheral active pattern ACT1 may be equal to the above-mentioned first thickness TH1.

[0058] The formation of the first insulating layer 120Pa may be performed by an ISSG (In-Situ Steam Generation) process. For example, the first insulating layer 120Pa may be formed by using a hydrogen molecule (H 2 ) and oxygen molecules (O 2 ) is formed by the reaction of oxygen molecules (O 2 ) can be in the gas phase.

[0059] 3H 2 +3O 2 →2H 2 O+2O*+2OH

[0060] In an embodiment of the present inventive concept, the ISSG (In-Situ Steam Generation) process can be achieved by using ozone (O 3 ) instead of oxygen molecules (O 2 ) to carry out.

[0061] In an embodiment of the present inventive concept, the oxygen molecules (O 2 ) performs a heat treatment process instead of an ISSG (In Situ Steam Generation) process to generate oxygen radicals (O radicals) to form the first insulating layer 120Pa.

[0062] Thereafter, a mask pattern PR may be formed to protect the first insulating layer 120Pa formed on the first peripheral active pattern ACT1. At this time, the mask pattern PR may be formed to expose a portion of the first insulating layer 120Pa formed on the top surface of the second peripheral active pattern ACT2 and a portion of the first insulating layer 120Pa formed on the top surface and side surfaces of the channel semiconductor pattern CSL.

[0063] Reference Figure 4C , an etching process may be performed on the first peripheral active pattern ACT1 and the second peripheral active pattern ACT2 by using the mask pattern PR formed on the first peripheral active pattern ACT1 as an etching mask. The etching process may include a wet etching process or a dry etching process. The first insulating layer 120Pa formed on the second peripheral active pattern ACT2 may be removed by the etching process. Next, the mask pattern PR may be removed, and the first insulating layer 120Pa may remain on the first peripheral active pattern ACT1. After removing the mask pattern PR, a cleaning process may be performed to remove byproducts and contaminants on the first insulating layer 120Pa and the second peripheral active pattern ACT2.

[0064] Reference Figure 4D , a second insulating layer 120Pb may be formed on the second peripheral active pattern ACT2 and the first insulating layer 120Pa formed on the first peripheral active pattern ACT1. At this time, the second insulating layer 120Pb located on the second peripheral active pattern ACT2 may cover the side surface and the top surface of the channel semiconductor pattern CSL.

[0065] The second insulating layer 120Pb may be formed by using oxygen radicals (O radicals) which are formed by irradiating ultraviolet light to oxygen molecules (O 2 ) is generated.

[0066] UV lamp + O 2 →O*+O*

[0067] In an embodiment of the present inventive concept, the oxygen molecules (O 2 ) is performed a heat treatment process instead of irradiating ultraviolet light to generate oxygen radicals (O radicals) to form the second insulating layer 120Pb.

[0068] In an embodiment of the present inventive concept, the second insulating layer 120Pb may be formed by using oxygen radicals (O radicals) which are generated by irradiating ultraviolet light to ozone (O 3 ) is generated.

[0069] UV lamp + O 3 →O 2 +O*

[0070] At this time, the second insulating layer 120Pb formed on the first peripheral active pattern ACT1 may have a second thickness TH2, and the second insulating layer 120Pb formed on the top surface of the channel semiconductor pattern CSL may be formed to have a third thickness TH3. Due to the high oxidizing ability of germanium (Ge) included in the channel semiconductor pattern CSL, the third thickness TH3 of the second insulating layer 120Pb formed on the top surface of the channel semiconductor pattern CSL may be greater than the second thickness TH2 of the second insulating layer 120Pb formed on the first peripheral active pattern ACT1. The sum of the first thickness TH1 and the second thickness TH2 may be in the range of 90% to 110% of the third thickness TH3.

[0071] Reference Figure 4E A high-k dielectric layer 122P, a lower conductive layer 130P, an upper conductive layer 138P, and a capping layer 140P may be sequentially formed on the second insulating layer 120Pb. At this time, the high-k dielectric layer 122P disposed on the second peripheral active pattern ACT2 may be formed to cover the second insulating layer 120Pb.

[0072] Reference Figure 4F A patterning process can be performed on the first insulating layer 120Pa, the second insulating layer 120Pb, the high-k dielectric layer 122P, the lower conductive layer 130P, the upper conductive layer 138P and the covering layer 140P formed on the first peripheral active pattern ACT1 to form a first gate structure GS1 including a first insulating pattern 120a, a second insulating pattern 120b, a first high-k dielectric pattern 122a, a first lower conductive pattern 130a, a first upper conductive pattern 138a and a first covering pattern 140a.

[0073] In addition, a patterning process may be performed on the second insulating layer 120Pb, the high-k dielectric layer 122P, the lower conductive layer 130P, the upper conductive layer 138P, and the capping layer 140P formed on the second peripheral active pattern ACT2, thereby forming a second gate structure GS2 including a third insulating pattern 120c, a second high-k dielectric pattern 122b, a second lower conductive pattern 130b, a second upper conductive pattern 138b, and a second capping pattern 140b. For example, the patterning process may include an etching process using a mask pattern.

[0074] Next, a first spacer 142 may be formed on a side surface of each of the first gate structure GS1 and the second gate structure GS2. The first spacers 142 may be spaced apart from each other in the first direction D1 with each of the first gate structure GS1 and the second gate structure GS2 disposed therebetween. For example, the first gate structure GS1 may be disposed between a pair of first spacers 142, and the second gate structure GS2 may be disposed between the pair of first spacers 142.

[0075] Afterwards, refer again to Figure 3 A first interlayer insulating layer 146 may be formed to cover the first gate structure GS1 and the second gate structure GS2 , and then a capping layer 148 may be formed to cover the first interlayer insulating layer 146 , thereby manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0076] In a method of manufacturing a semiconductor device according to an embodiment of the inventive concept, the first insulating pattern 120a may be formed on the first peripheral active pattern ACT1 by using an ISSG (In-Situ Steam Generation) process, and then, the first insulating pattern 120a may be formed by irradiating ultraviolet light onto oxygen molecules (O 2 ) are formed on the first peripheral active pattern ACT1 and the second peripheral active pattern ACT2, respectively. Here, since the first insulating pattern 120a is formed by the ISSG (In-Situ Steam Generation) process, the thickness of the first insulating pattern 120a can be accurately controlled, and defects of the first peripheral active pattern ACT1 can be reduced. As a result, the value of the current flowing through the first peripheral active pattern ACT1 can be increased.

[0077] In addition, in the method of manufacturing a semiconductor device according to an embodiment of the present invention, the first insulating pattern 120a formed on the first peripheral active pattern ACT1 and the third insulating pattern 120c formed on the second peripheral active pattern ACT2 can be formed by using an ISSG (in-situ steam generation) process and ultraviolet (UV) light, respectively, and can be formed independently of each other. Therefore, regardless of the formation process of the first insulating pattern 120a formed by the ISSG (in-situ steam generation) process, the third thickness TH3 of the third insulating pattern 120c can be adjusted. In other words, the third thickness TH3 of the third insulating pattern 120c can be adjusted to 110% or less of the sum of the first thickness TH1 of the first insulating pattern 120a and the second thickness TH2 of the second insulating pattern 120b, and therefore, the height difference between the transistors formed by the first gate structure GS1 and the second gate structure GS2 can be reduced.

[0078] Figure 5 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 6 It is along Figure 5 8 is a cross-sectional view taken along line CC′ of FIG. 1 to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0079] Reference Figure 5 and Figure 6 , a substrate 100 including a cell region CR may be provided. The cell region CR may be a portion of the substrate 100 on which a Figure 1 The area of ​​the unit block CB.

[0080] The cell active patterns CACT may be disposed on the cell region CR of the substrate 100. When viewed in a plan view, the cell active patterns CACT may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the cell active patterns CACT may have a strip shape extending in a fourth direction D4 that is parallel to the bottom surface of the substrate 100 and intersects the first direction D1 and the second direction D2.

[0081] The device isolation layer 120 may be disposed between the cell active patterns CACT on the cell region CR. The device isolation layer 120 may be disposed in the substrate 100 to define the cell active patterns CACT. The cell active patterns CACT may be part of the substrate 100.

[0082] The word lines WL may cross the cell active pattern CACT and the device isolation layer 120 on the cell region CR. The word lines WL may be disposed in grooves formed in the cell active pattern CACT and the device isolation layer 120. The word lines WL may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. The word lines WL may be buried in the substrate 100.

[0083] The first cell dopant region 110b and the second cell dopant region 110c may be disposed in the cell active pattern CACT. Each of the first cell dopant regions 110b may be disposed between a pair of word lines WL crossing each of the cell active patterns CACT. The second cell dopant region 110c may be disposed in both edge regions of each of the cell active patterns CACT.

[0084] The buffer pattern 306 may cover the cell active pattern CACT, the device isolation layer 120, and the word line WL on the substrate 100. For example, the buffer pattern 306 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0085] The bit lines BL may be disposed on the buffer pattern 306. The bit lines BL may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. Each of the bit lines BL may include a barrier pattern 331 and a metal-containing pattern 330 sequentially stacked on the buffer pattern 306.

[0086] The cell polysilicon pattern 310c may be disposed between the bit line BL and the buffer pattern 306. The first cell ohmic pattern may be disposed between the barrier pattern 331 and the corresponding cell polysilicon pattern 310c. For example, the first cell ohmic pattern may include silicide.

[0087] Bit line contacts DC may be disposed between the bit lines BL and the first cell dopant regions 110b, respectively. The bit lines BL may be electrically connected to the first cell dopant regions 110b through the bit line contacts DC. The bit line contacts DC may include, for example, dopant-doped polysilicon or undoped polysilicon.

[0088] The bit line contact DC may be disposed in the recessed portion RE. The recessed portion RE may be disposed in an upper portion of the first cell dopant region 110b and an upper portion of the device isolation layer 120 adjacent to the bit line contact DC. The first filling insulating pattern 314c and the second filling insulating pattern 315c may fill the remaining portion of the recessed portion RE.

[0089] The cell capping pattern 350c may extend in the second direction D2 on each bit line BL. For example, the cell capping pattern 350c may include silicon nitride.

[0090] The bit line spacer SPc may cover a side surface of each cell polysilicon pattern 310c, an upper side surface of each bit line contact DC, a side surface of each bit line BL, and a side surface of the cell cover pattern 350c. The bit line spacer SPc may extend in the second direction D2 on a side surface of each bit line BL.

[0091] The bit line spacer SPc may include a first sub-spacer 321 and a second sub-spacer 325 spaced apart from each other. For example, the first sub-spacer 321 and the second sub-spacer 325 may be spaced apart from each other by an air gap AG. The first sub-spacer 321 may be in contact with a side surface of each bit line BL and may extend onto a side surface of the cell capping pattern 350c. The second sub-spacer 325 may be disposed along a side surface of the first sub-spacer 321. For example, each of the first sub-spacer 321 and the second sub-spacer 325 may include silicon nitride.

[0092] The upper spacer 360 may cover a portion of a side surface of the first sub-spacer 321, and may extend onto a top surface of the second sub-spacer 325. The upper spacer 360 may also cover the air gap AG.

[0093] The storage node contacts BC may be disposed between the bit lines BL adjacent to each other. The storage node contacts BC may be spaced apart from each other in the first direction D1 and the second direction D2. The storage node contacts BC may include dopant-doped polysilicon or undoped polysilicon.

[0094] The second unit ohmic pattern 341c may be disposed on each storage node contact BC. For example, the second unit ohmic pattern 341c may include silicide.

[0095] The cell diffusion barrier pattern 342c may conformally cover the second cell ohmic pattern 341c, the bit line spacer SPc, and the cell capping pattern 350c. For example, the cell diffusion barrier pattern 342c may include a metal nitride (e.g., TiN, TSN, TaN, etc.). The second cell ohmic pattern 341c may be disposed between the cell diffusion barrier pattern 342c and each storage node contact BC.

[0096] The bonding pads LP may be disposed on the storage node contacts BC, respectively. The bonding pads LP may be spaced apart from each other in the first direction D1 and the second direction D2. The bonding pads LP may include a metal (eg, tungsten).

[0097] When viewed in a plan view, the filling pattern 400 may at least partially surround each of the bonding pads LP. The filling pattern 400 may be disposed between the bonding pads LP adjacent to each other.

[0098] The lower electrodes BE may be disposed on the bonding pads LP, respectively. For example, the lower electrodes BE may include at least one of dopant-doped polysilicon, metal nitride (e.g., titanium nitride), and metal (e.g., tungsten, aluminum, or copper). For example, each of the lower electrodes may have a cylindrical shape, a hollow cylindrical shape, or a cup shape; however, the inventive concept is not limited thereto. The upper support pattern SS1 may support the upper side surface of the lower electrode BE, and the lower support pattern SS2 may support the lower side surface of the lower electrode BE. The upper support pattern SS1 and the lower support pattern SS2 may include an insulating material (such as silicon nitride, silicon oxide, and / or silicon oxynitride).

[0099] The etch stop pattern 420 may be disposed on the filling pattern 400 between the lower electrodes BE. The dielectric layer DL may cover the surface of the lower electrode BE and the surfaces of the upper support pattern SS1 and the lower support pattern SS2. For example, the dielectric layer DL may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material. The upper electrode TE may be disposed on the dielectric layer DL and may fill the space between the lower electrodes BE. For example, the upper electrode TE may include at least one of dopant-doped polysilicon, dopant-doped silicon germanium, metal nitride (e.g., titanium nitride), and metal (e.g., tungsten, aluminum, or copper). The lower electrode BE, the dielectric layer DL, and the upper electrode TE may constitute a capacitor CA.

[0100] A semiconductor device according to an embodiment of the present invention may include a first gate structure located on a first active pattern and a second gate structure located on a second active pattern. The first gate structure may include a first insulating pattern, a second insulating pattern, and a first high-k dielectric pattern sequentially stacked on the first active pattern. The second gate structure may include a third insulating pattern and a second high-k dielectric pattern sequentially stacked on the second active pattern. Here, the thickness of the third insulating pattern may be between 100 and 150 nm. to As a result, by the thin thickness of the third insulating pattern, the height difference between the first gate structure and the second gate structure can be reduced, and the current value flowing through the second active pattern can be increased.

[0101] In addition, the first insulating pattern may be formed on the first active pattern by an ISSG (In-Situ Steam Generation) process, and the third insulating pattern may be separately formed by using ultraviolet (UV) light after the first insulating pattern is formed. As a result, the interface characteristics of the first active pattern may be improved to increase the current value flowing through the first active pattern, and the thickness of the third insulating pattern may be adjusted to 110% or less of the sum of the thickness of the first insulating pattern and the thickness of the second insulating pattern, regardless of the process of forming the first insulating pattern.

[0102] While the inventive concepts have been described with reference to example embodiments of the inventive concepts, persons skilled in the art will understand that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concepts.

Claims

1. A semiconductor device, comprising: a substrate including a first active pattern and a second active pattern spaced apart from each other; A first gate structure is disposed on the first active pattern; a second gate structure disposed on the second active pattern; and a channel semiconductor pattern disposed between the second active pattern and the second gate structure, The first gate structure includes a first insulating pattern, a second insulating pattern and a first high-k dielectric pattern stacked on the first active pattern. The second gate structure includes a third insulating pattern and a second high-k dielectric pattern stacked on the channel semiconductor pattern, and Wherein, the thickness of the third insulating pattern is to within the range.

2. The semiconductor device according to claim 1, wherein The second active pattern includes a first semiconductor material, Wherein, the channel semiconductor pattern comprises a second semiconductor material, and The first semiconductor material is different from the second semiconductor material.

3. The semiconductor device according to claim 2, wherein: A top surface of the channel semiconductor pattern has a level higher than a top surface of the second insulating pattern.

4. The semiconductor device according to claim 1, wherein The first gate structure further includes a first lower conductive pattern, a first upper conductive pattern, and a first capping pattern stacked on the first high-k dielectric pattern, and The second gate structure further includes a second lower conductive pattern, a second upper conductive pattern and a second covering pattern stacked on the second high-k dielectric pattern.

5. The semiconductor device according to claim 1, wherein The first to third insulating patterns include silicon oxide.

6. The semiconductor device according to claim 1, wherein A difference between a level of a top surface of the first gate structure and a level of a top surface of the second gate structure is 8 nm or less.

7. The semiconductor device according to claim 1, wherein The channel semiconductor pattern includes silicon germanium, wherein the first active pattern includes first dopant regions spaced apart from each other in a first direction and the first gate structure is disposed between the first dopant regions, wherein the first direction is parallel to a top surface of the substrate, wherein the second active pattern includes second dopant regions spaced apart from each other in the first direction and the second gate structure is disposed between the second dopant regions, wherein the first dopant region has a first conductivity type, wherein the second dopant region has a second conductivity type, and The first conductivity type is different from the second conductivity type.

8. The semiconductor device according to claim 1, wherein A coupling energy between the first active pattern and the first insulating pattern is greater than a coupling energy between the channel semiconductor pattern and the third insulating pattern.

9. The semiconductor device according to claim 1, wherein: The sum of the thickness of the first insulation pattern and the thickness of the second insulation pattern is equal to the thickness of the third insulation pattern.

10. A semiconductor device, comprising: a substrate including a first active pattern and a second active pattern spaced apart from each other; A first gate structure is disposed on the first active pattern; as well as a second gate structure, disposed on the second active pattern, The first gate structure includes a first insulating pattern, a second insulating pattern, a first high-k dielectric pattern and a first conductive pattern stacked on the first active pattern. The second gate structure includes a third insulating pattern, a second high-k dielectric pattern and a second conductive pattern stacked on the second active pattern. wherein the first insulating pattern is disposed between the first active pattern and the second insulating pattern, and Wherein a thickness of the third insulating pattern is 30% or less of a thickness of the second high-k dielectric pattern.

11. The semiconductor device according to claim 10, wherein A difference between a level of a top surface of the first gate structure and a level of a top surface of the second gate structure is 8 nm or less.

12. The semiconductor device according to claim 10, further comprising: a channel semiconductor pattern disposed between the second active pattern and the third insulating pattern, The top surface of the third insulation pattern has a level higher than that of the second insulation pattern.

13. The semiconductor device according to claim 10, wherein: Each of the first to third insulating patterns includes silicon oxide.

14. The semiconductor device according to claim 10, further comprising: The interlayer insulating layer is disposed on the first active pattern and the second active pattern and covers the first gate structure and the second gate structure.

15. A semiconductor device, comprising: a substrate including a cell active pattern on a cell region and a first peripheral active pattern and a second peripheral active pattern spaced apart from each other on a peripheral region adjacent to the cell region; a word line disposed in the substrate and crossing the cell active pattern; A bit line is disposed on the substrate and crosses the word line; a bit line contact disposed on a central portion of each of the cell active patterns and connected to a corresponding one of the bit lines; a storage node contact disposed on an end portion of each of the cell active patterns; a bonding pad disposed on each of the storage node contacts; A capacitor disposed on the bonding pad; a first peripheral gate pattern, disposed on the first peripheral active pattern; a second peripheral gate pattern disposed on the second peripheral active pattern; and a channel semiconductor pattern disposed between the second peripheral active pattern and the second peripheral gate pattern, wherein the first peripheral gate pattern includes a first insulating pattern, a second insulating pattern, a first high-k dielectric pattern, a first lower conductive pattern, a first upper conductive pattern, and a first capping pattern stacked on the first peripheral active pattern, wherein the second peripheral gate pattern includes a third insulating pattern, a second high-k dielectric pattern, a second lower conductive pattern, a second upper conductive pattern, and a second capping pattern stacked on the channel semiconductor pattern, and The sum of the thickness of the first insulation pattern and the thickness of the second insulation pattern is 90% to 110% of the thickness of the third insulation pattern.

16. The semiconductor device according to claim 15, wherein: Each of the first to third insulating patterns includes silicon oxide, and Wherein, the channel semiconductor pattern comprises silicon germanium.

17. The semiconductor device according to claim 15, further comprising: a spacer on a side surface of each of the first peripheral gate pattern and the second peripheral gate pattern; an interlayer insulating layer disposed on the first peripheral gate pattern and the second peripheral active pattern; as well as The outer covering layer is arranged on the interlayer insulating layer.

18. The semiconductor device according to claim 15, wherein A top surface of the channel semiconductor pattern has a level higher than a top surface of the second insulating pattern.

19. The semiconductor device according to claim 15, wherein: The sum of the thickness of the first insulating pattern and the thickness of the second insulating pattern is to within the range.

20. The semiconductor device according to claim 15, wherein A difference between a level of a top surface of the first peripheral gate pattern and a level of a top surface of the second peripheral gate pattern is 8 nm or less.

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