Integrated circuit device and method of manufacturing the same

Abstract

An integrated circuit device and a method of manufacturing the integrated circuit device are provided. An integrated circuit device includes a transistor on a substrate and a capacitor structure electrically connected to the transistor. The capacitor structure includes a lower electrode, a lower interface film on the lower electrode, a capacitor dielectric film on the lower interface film, an upper interface film on the capacitor dielectric film, and an upper electrode on the upper interface film. The lower interface film includes: a first lower interface layer including a metal oxide doped with an impurity; a second lower interface layer including substantially the same material as that of the first lower interface layer and doped with nitrogen; and a third lower interface layer including the same material as that of the capacitor dielectric film and doped with nitrogen, the upper interface film including: a first upper interface layer including a metal oxide; a second upper interface layer including the same material as that of the first upper interface layer and doped with nitrogen; and a third upper interface layer including the same material as that of the capacitor dielectric film and doped with nitrogen.

Description

Technical Field

[0001] The inventive concept relates to an integrated circuit device and a method of manufacturing the integrated circuit device, and more particularly, to an integrated circuit device including a capacitor and a method of manufacturing the integrated circuit device. Background Art

[0002] Recently, with the rapid development of miniaturized semiconductor process technology, the high integration density of integrated circuit devices has accelerated, and the area of ​​each unit has been continuously reduced. Therefore, the area that the capacitor in each unit can occupy is also reduced. For example, with the increase of the integration density of integrated circuit devices such as dynamic random access memory (DRAM), the area of ​​each unit is reduced, while the required capacitance is maintained or increased. Therefore, it is necessary to overcome the space limitations of the capacitor and the limitations of the design rules and increase the capacitance of the capacitor to maintain the desired electrical characteristics. Summary of the invention

[0003] The inventive concept provides an integrated circuit device capable of reducing a leakage current flowing through a capacitor dielectric film and a method of manufacturing the same.

[0004] The inventive concept is not limited to the above-mentioned contents, and those skilled in the art will clearly understand the inventive concept from the following description.

[0005] According to one aspect of the inventive concept, an integrated circuit device is provided, the integrated circuit device comprising: a transistor, the transistor being located on a substrate; and a capacitor structure, the capacitor structure being electrically connected to the transistor. The capacitor structure comprises: a lower electrode; a lower interface film, the lower interface film being located on the lower electrode; a capacitor dielectric film, the capacitor dielectric film being located on the lower interface film; an upper interface film, the upper interface film being located on the capacitor dielectric film; and an upper electrode, the upper electrode being located on the upper interface film. The lower interface film includes: a first lower interface layer, the first lower interface layer includes a metal oxide doped with impurities; a second lower interface layer, the second lower interface layer includes a material substantially the same as that of the first lower interface layer and is doped with nitrogen; and a third lower interface layer, the third lower interface layer includes a material the same as that of the capacitor dielectric film and is doped with nitrogen, the first lower interface layer to the third lower interface layer are sequentially stacked on the lower electrode, and wherein the upper interface film includes: a first upper interface layer, the first upper interface layer includes a metal oxide; a second upper interface layer, the second upper interface layer includes a material the same as that of the first upper interface layer and is doped with nitrogen; and a third upper interface layer, the third upper interface layer includes a material the same as that of the capacitor dielectric film and is doped with nitrogen, the first upper interface layer to the third upper interface layer are sequentially stacked on the upper electrode.

[0006] According to another aspect of the inventive concept, an integrated circuit device is provided, comprising: a plurality of lower electrodes, the plurality of lower electrodes being located on a substrate; a support member, the support member being located between the plurality of lower electrodes; an upper electrode, the upper electrode being located on the plurality of lower electrodes; a capacitor dielectric film, the capacitor dielectric film being located between the plurality of lower electrodes and the upper electrode; a lower interface film, the lower interface film being located between the plurality of lower electrodes and the capacitor dielectric film, the lower interface film having a multilayer structure with different nitrogen doping concentrations; and an upper interface film, the upper interface film being located between the upper electrode and the capacitor dielectric film, the upper interface film having a multilayer structure with different nitrogen doping concentrations.

[0007] According to another aspect of the inventive concept, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a lower electrode on a substrate; forming a lower interface material layer on the lower electrode; forming a dielectric material layer on the lower interface material layer; doping the entire dielectric material layer and a portion of the lower interface material layer with nitrogen by performing a first heat treatment using nitrogen on the substrate; forming a capacitor dielectric film on the dielectric material layer doped with nitrogen; forming a first upper interface material layer on the capacitor dielectric film; doping the entire first upper interface material layer and a portion of the capacitor dielectric film with nitrogen by performing a second heat treatment using nitrogen on the substrate; forming a second upper interface material layer on the first upper interface material layer doped with nitrogen; and forming an upper electrode on the second upper interface material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various example embodiments may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a layout diagram of an integrated circuit device according to various example embodiments;

[0010] Figure 2 is a cross-sectional view of an integrated circuit device according to various example embodiments;

[0011] Figure 3 yes Figure 2 An enlarged cross-sectional view of the region CX in FIG.

[0012] Figure 4A and Figure 4B is a graph showing changes in electrical characteristics according to the presence or absence of an upper interface film in an integrated circuit device according to various example embodiments;

[0013] Figure 5A and Figure 5Bis a graph showing changes in electrical characteristics according to the presence or absence of a lower interface film in an integrated circuit device according to various example embodiments;

[0014] Figure 6 and Figure 7 is a cross-sectional view of an integrated circuit device according to various example embodiments;

[0015] Figures 8 to 10 is a cross-sectional view of an integrated circuit device according to various example embodiments;

[0016] Figures 11 to 13 is a flow chart of a method of manufacturing an integrated circuit device according to various example embodiments;

[0017] Figures 14 to 24 are cross-sectional views of stages in a method of fabricating an integrated circuit device according to various example embodiments; and

[0018] Fig.25 is a block diagram of a system including an integrated circuit device according to various example embodiments. DETAILED DESCRIPTION

[0019] Hereinafter, various exemplary embodiments are described in detail with reference to the accompanying drawings.

[0020] For example, “at least one of A, B, and C” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0021] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, the associated numerical value is intended to include manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value. Moreover, when the words "approximately" and "substantially" are used in conjunction with geometric shapes, it is intended that the precision of the geometric shapes is not required, but the range of shapes is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "approximately" or "substantially", it should be understood that these numerical values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0022] One or more of the elements disclosed above may include a processing circuit such as hardware with a logic circuit, a hardware / software combination such as a processor running software, or a combination thereof, or may be implemented in a processing circuit such as hardware with a logic circuit, a hardware / software combination such as a processor running software, or a combination thereof. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0023] Figure 1 is a layout diagram of an integrated circuit device 10 according to various example embodiments. Figure 2 It is along Figure 1 1 is a cross-sectional view of the integrated circuit device 10 taken along line AA′ in FIG. Figure 3 yes Figure 2 Magnified view of region CX.

[0024] refer to Figures 1 to 3 The integrated circuit device 10 may include a lower electrode 170 located above a substrate 110 , a support member SPT supporting the lower electrode 170 , a capacitor dielectric film 180 located on the lower electrode 170 , and an upper electrode 190 located on the capacitor dielectric film 180 .

[0025] The substrate 110 may include an active region AC defined by an isolation film 112. The substrate 110 may correspond to a wafer including silicon (Si). In some embodiments, the substrate 110 may correspond to a wafer including a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). However, example embodiments are not limited thereto. The substrate 110 may have a silicon on insulator (SOI) structure. The substrate 110 may include a conductive region, such as a well doped with impurities or a structure doped with impurities.

[0026] For example, the isolation film 112 may have a shallow trench isolation (STI) structure. The isolation film 112 may include an insulating material filling the isolation trench 112T in the substrate 110. The insulating material may include fluoride silicate glass (FSG), undoped silicate glass (USG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma enhanced tetraethylorthosilicate (PE-TEOS), or eastern siloxane (TOSZ), but example embodiments are not limited thereto.

[0027] The active region AC may have a relatively long island shape. A long axis of the active region AC may be arranged in a K direction parallel to the top surface of the substrate 110. The active region AC may be doped with p-type or n-type impurities.

[0028] The substrate 110 may include a gate line trench 120T extending in the X direction. The gate line trench 120T may intersect the active region AC and be at a depth from the top surface of the substrate 110. A portion of the gate line trench 120T may extend to the inside of the isolation film 112. The bottom of the gate line trench 120T in the isolation film 112 may be located at a lower level than the bottom of the gate line trench 120T in the active region AC.

[0029] The source / drain region 114 may be located on the active region AC on each of opposite sides of the gate line trench 120T. The source / drain region 114 may include an impurity region doped with impurities of a different conductivity type from the active region AC. The source / drain region 114 may be doped with n-type or p-type impurities.

[0030] The gate structure 120 may be formed in the gate line trench 120T. The gate structure 120 may include a gate insulating layer 122, a gate electrode layer 124, and a gate capping layer 126 sequentially formed on the inner wall of the gate line trench 120T.

[0031] The gate insulating layer 122 may be conformally formed to a certain thickness on the inner wall of the gate line trench 120T. The gate insulating layer 122 may include at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), and a high-k material having a higher dielectric constant than silicon oxide. However, example embodiments are not limited thereto.

[0032] The gate electrode layer 124 may be formed on the gate insulating layer 122 to fill the gate line trench 120T to a certain height from the bottom of the gate line trench 120T. The gate electrode layer 124 may include a work function control layer (not shown) on the gate insulating layer 122 and a buried metal layer (not shown) on the work function control layer, wherein the buried metal layer fills the bottom of the gate line trench 120T.

[0033] The gate capping layer 126 may be on the gate electrode layer 124 and may fill the remaining portion of the gate line trench 120T. For example, the gate capping layer 126 may include at least one selected from the group consisting of silicon oxide, silicon oxynitride, and silicon nitride.

[0034] The bit line structure 130 may be on the source / drain region 114 and may extend in the Y direction perpendicular to the X direction. The bit line structure 130 may include a bit line contact 132, a bit line 134, and a bit line capping layer 136 sequentially stacked on the substrate 110. For example, the bit line contact 132 may include polysilicon, the bit line 134 may include a metal material, and the bit line capping layer 136 may include silicon nitride or silicon oxynitride.

[0035] The first interlayer insulating film 142 may be on the substrate 110. The bit line contact 132 may pass through the first interlayer insulating film 142 to be connected to the source / drain region 114. The bit line 134 and the bit line capping layer 136 may be on the first interlayer insulating film 142. The second interlayer insulating film 144 may be on the first interlayer insulating film 142, and may cover the side surface of the bit line 134 and the side surface and top surface of the bit line capping layer 136.

[0036] The contact structure 150 may be on the source / drain region 114. The first interlayer insulating film 142 and the second interlayer insulating film 144 may surround the sidewalls of the contact structure 150. In some embodiments, the contact structure 150 may include a lower contact (not shown), a metal silicide layer (not shown), and an upper contact (not shown) sequentially stacked on the substrate 110.

[0037] The capacitor structure CS may be on the second interlayer insulating film 144. The capacitor structure CS may include a lower electrode 170 electrically connected to the contact structure 150, a capacitor dielectric film 180 conformally covering the lower electrode 170, and an upper electrode 190 located on the capacitor dielectric film 180. An etch stop film 160 having an opening 160T may be on the second interlayer insulating film 144, and a bottom of the lower electrode 170 may be in the opening 160T of the etch stop film 160.

[0038] It is shown that the plurality of capacitor structures CS are respectively arranged on the plurality of contact structures 150 repeatedly arranged in the X direction and the Y direction, but example embodiments are not limited thereto. Differently, the plurality of capacitor structures CS may be arranged in a honeycomb pattern on the plurality of contact structures 150 repeatedly arranged in the X direction and the Y direction.

[0039] The lower electrode 170 may include a metal nitride, a metal, or a combination thereof. For example, the lower electrode 170 may include at least one selected from the group consisting of TiN, TaN, WN, Ru, Pt, and Ir. The lower electrode 170 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). However, example embodiments are not limited thereto.

[0040] The lower electrode 170 may have a very large aspect ratio. For example, the aspect ratio of the lower electrode 170 may be about 10 to about 30. In detail, the diameter of the lower electrode 170 may be about 20 nm to about 100 nm, and the height of the lower electrode 170 may be about 500 nm to about 4000 nm, but the lower electrode 170 is not limited to these sizes. Since the lower electrode 170 has a large aspect ratio, the lower electrode 170 may collapse or break.

[0041] The support member SPT may prevent the lower electrode 170 from collapsing or breaking. The support member SPT may have a plate shape including a support member pattern contacting the lower electrode 170 .

[0042] The capacitor dielectric film 180 may be on the outer surface of each of the lower electrode 170 and the support member SPT. The capacitor dielectric film 180 may have a single layer structure or a multilayer structure. The capacitor dielectric film 180 may include a high-k material having a higher dielectric constant relative to silicon oxide. For example, the dielectric constant of the capacitor dielectric film 180 may be about 10 to about 25.

[0043] In some embodiments, the capacitor dielectric film 180 may include at least one selected from the group consisting of zirconium oxide, hafnium oxide, and aluminum oxide. For example, the capacitor dielectric film 180 may have, but is not limited to, a single-layer structure of zirconium oxide, a double-layer structure of zirconium oxide and aluminum oxide, or a triple-layer structure of zirconium oxide, hafnium oxide, and aluminum oxide. However, example embodiments are not limited thereto.

[0044] The upper electrode 190 may be on the capacitor dielectric film 180. The upper electrode 190 may be conformally formed on the capacitor dielectric film 180 and may cover the lower electrode 170, wherein the capacitor dielectric film 180 is located between the upper electrode 190 and the lower electrode 170. The upper electrode 190 may include a metal nitride, a metal, or a combination thereof. For example, the upper electrode 190 may include at least one selected from the group consisting of TiN, TaN, WN, Ru, Pt, and Ir. However, example embodiments are not limited thereto.

[0045] Furthermore, in the integrated circuit device 10 of the present inventive concept, the lower interface film 170L may be between the lower electrode 170 and the capacitor dielectric film 180 , and the upper interface film 190L may be between the upper electrode 190 and the capacitor dielectric film 180 .

[0046] The lower interface film 170L is first described below. The lower interface film 170L may have a three-layer structure of a first lower interface layer 171, a second lower interface layer 172, and a third lower interface layer 173. In detail, the lower interface film 170L may include a structure in which the first lower interface layer 171, the second lower interface layer 172, and the third lower interface layer 173 are sequentially stacked on the lower electrode 170, wherein the first lower interface layer 171 includes a metal oxide doped with impurities, the second lower interface layer 172 includes a material substantially the same as that of the first lower interface layer 171 and is doped with nitrogen, and the third lower interface layer 173 includes a material substantially the same as that of the capacitor dielectric film 180 and is doped with nitrogen.

[0047] Here, the metal oxide included in the first lower interface layer 171 may include titanium oxide, and the impurities included in the first lower interface layer 171 may include a pentavalent element. In detail, the impurities included in the first lower interface layer 171 may include, but are not limited to, vanadium (V), niobium (Nb), tantalum (Ta), phosphorus (P), or antimony (Sb). However, example embodiments are not limited thereto.

[0048] The nitrogen doping concentration in the second lower interface layer 172 may be higher than the nitrogen doping concentration in the first lower interface layer 171. In other words, the first lower interface layer 171 and the second lower interface layer 172 may be distinguished from each other by the difference in nitrogen doping concentration therebetween. The nitrogen doping concentration in the third lower interface layer 173 may be higher than the nitrogen doping concentration in the capacitor dielectric film 180 facing the third lower interface layer 173. In other words, the third lower interface layer 173 and the capacitor dielectric film 180 may be distinguished from each other by the difference in nitrogen doping concentration therebetween. According to the characteristics of the manufacturing process, the doping of nitrogen included in the second lower interface layer 172 and the doping of nitrogen included in the third lower interface layer 173 may be performed by a single first heat treatment ( Fig.21 P1) in is executed simultaneously, which is described below.

[0049] The upper interface film 190L is described below. The upper interface film 190L may have a three-layer structure of a first upper interface layer 191, a second upper interface layer 192, and a third upper interface layer 193. In detail, the upper interface film 190L may include a structure in which the first upper interface layer 191, the second upper interface layer 192, and the third upper interface layer 193 are sequentially stacked on the upper electrode 190, wherein the first upper interface layer 191 includes a metal oxide, the second upper interface layer 192 includes a material substantially the same as that of the first upper interface layer 191 and is doped with nitrogen, and the third upper interface layer 193 includes a material substantially the same as that of the capacitor dielectric film 180 and is doped with nitrogen.

[0050] Here, the metal oxide included in the first upper interface layer 191 may include, but is not limited to, titanium oxide, tantalum oxide, or niobium oxide. Unlike the first lower interface layer 171, the first upper interface layer 191 may not include a pentavalent element as an impurity.

[0051] The nitrogen doping concentration in the second upper interface layer 192 may be higher than the nitrogen doping concentration in the first upper interface layer 191. In other words, the first upper interface layer 191 and the second upper interface layer 192 may be distinguished from each other by the difference in nitrogen doping concentration therebetween. The nitrogen doping concentration in the third upper interface layer 193 may be higher than the nitrogen doping concentration in the capacitor dielectric film 180 facing the third upper interface layer 193. In other words, the third upper interface layer 193 and the capacitor dielectric film 180 may be distinguished from each other by the difference in nitrogen doping concentration therebetween. According to the characteristics of the manufacturing process, the doping of nitrogen included in the second upper interface layer 192 and the doping of nitrogen included in the third upper interface layer 193 may be performed by a single second heat treatment ( Fig.23 P2) in is executed simultaneously, which is described below.

[0052] With the recent rapid development of miniaturized semiconductor process technology, the high integration density of integrated circuit devices 10 has accelerated, and the area of ​​each cell has decreased. Therefore, the area that the capacitor structure CS in each cell can occupy has also decreased. For example, as the integration density of integrated circuit devices 10 such as dynamic random access memory (DRAM) increases, the area of ​​each cell decreases, while the required capacitance remains or increases.

[0053] Therefore, in the capacitor structure CS in which the adjacent lower electrodes 170 are very close to each other and the adjacent upper electrodes 190 are very close to each other due to the reduction in the area of ​​each unit, leakage current may undesirably flow through the capacitor dielectric film 180. Moreover, a high-k material such as zirconium oxide, hafnium oxide, or aluminum oxide may be used for the capacitor dielectric film 180 having high capacitance and high bandgap characteristics, but may cause an increase in leakage current due to a relatively high oxygen vacancy concentration. In other words, what is needed is a structure that maintains desired electrical characteristics by overcoming the space limitations and design rule limitations of the integrated circuit device 10 having a high integration density and increasing the capacitance of the integrated circuit device 10.

[0054] According to the present invention, in order to reduce the leakage current caused by oxygen vacancies in the capacitor dielectric film 180, in the integrated circuit device 10, the lower interface film 170L doped with nitrogen can be arranged between the lower electrode 170 and the capacitor dielectric film 180, and the upper interface film 190L doped with nitrogen can be arranged between the upper electrode 190 and the capacitor dielectric film 180.

[0055] After forming the material constituting the lower interface film 170L and the material constituting the upper interface film 190L, nitrogen may be diffused as a dopant from a process gas (e.g., ammonia or nitrogen) into the lower interface film 170L and the upper interface film 190L through the first heat treatment and the second heat treatment, so that a portion of the lower interface film 170L and a portion of the upper interface film 190L may be doped with nitrogen. It is expected that when each of the lower interface film 170L and the upper interface film 190L is formed as a multilayer structure having different nitrogen concentrations in the above manner, defects caused by oxygen vacancies in the capacitor dielectric film 180 may be mostly eliminated due to nitrogen. According to the experimental example described below, it can be seen that the presence of the lower interface film 170L and the upper interface film 190L may more effectively prevent or reduce the occurrence of leakage current in the capacitor dielectric film 180.

[0056] Finally, by including the lower interface film 170L and the upper interface film 190L each having a multilayer structure with different nitrogen doping concentrations in each capacitor structure CS, leakage current flowing through the capacitor dielectric film 180 between adjacent capacitor structures CS may be reduced in the integrated circuit device 10 .

[0057] Figure 4A and Figure 4B is a graph showing changes in electrical characteristics according to the presence or absence of an upper interface film in an integrated circuit device according to various example embodiments.

[0058] In detail, Figure 4A is a graph showing a comparison of a leakage current in a first experimental example R1 including an upper interface film of the present inventive concept and a leakage current in a comparative example Ref. Figure 4B is a graph showing a comparison of data fail bits in the first experimental example R1 including the upper interface film of the present inventive concept and data fail bits in the comparative example Ref.

[0059] Figure 4A The leakage current characteristics according to the upper interface film 190L (see FIG. 1 ) in the first experimental example R1 and the comparative example Ref are shown. Figure 3 ) exists. Figure 4A By comparing the first experimental example R1 with the comparative example Ref, it can be seen that the upper interface film 190L ( Figure 3 ) of the capacitor dielectric film 180 (see Figure 3 ) have similar capacitance (horizontal axis) and relatively low leakage current (vertical axis).

[0060] Figure 4B The data failure bit characteristics according to the upper interface film 190L ( Figure 3 ) exists. Figure 4BBy comparing the first experimental example R1 with the comparative example Ref, it can be seen that the upper interface film 190L ( Figure 3 ) of the capacitor dielectric film 180 ( Figure 3 ) is similar in capacitance (horizontal axis), while the data failure bits (vertical axis) show a relatively decreasing trend (improved by approximately 1.3 times).

[0061] In other words, this proves that by using the upper interface film 190L ( Figure 3 ) to eliminate defects due to oxygen vacancies in the capacitor dielectric film 180, thereby reducing the amount of electricity flowing through the capacitor dielectric film 180 ( Figure 3 It can also be seen that the electrical characteristics of the integrated circuit device of the present invention are improved.

[0062] Figure 5A and Figure 5B is a graph showing changes in electrical characteristics according to the presence or absence of a lower interface film in an integrated circuit device according to various example embodiments.

[0063] In detail, Figure 5A is a graph showing a comparison of a leakage current in the second experimental example R2 including the lower interface film of the present inventive concept and a leakage current in the comparative example Ref. Figure 5B is a graph showing a comparison of data fail bits in the second experimental example R2 including the lower interface film of the present inventive concept and data fail bits in the comparative example Ref.

[0064] Figure 5A The leakage current characteristics according to the lower interface film 170L (see FIG. Figure 3 ) exists. Figure 5A By comparing the second experimental example R2 with the comparative example Ref, it can be seen that there is a lower interface film 170L ( Figure 3 ) of the capacitor dielectric film 180 (see Figure 3 )'s capacitance (horizontal axis) is relatively high, while its leakage current (vertical axis) is relatively low.

[0065] Figure 5B The data failure bit characteristics according to the lower interface film 170L ( Figure 3 ) exists. Figure 5B By comparing the second experimental example R2 with the comparative example Ref, it can be seen that there is a lower interface film 170L ( Figure 3 ) of the capacitor dielectric film 180 ( Figure 3) are similar in capacitance (horizontal axis), while the data failure bits (vertical axis) show a relatively decreasing trend (improved by approximately 2.3 times).

[0066] In other words, this proves that by using the lower interface film 170L ( Figure 3 ) to eliminate defects due to oxygen vacancies in the capacitor dielectric film 180, thereby reducing the amount of electricity flowing through the capacitor dielectric film 180 ( Figure 3 It can also be seen that the electrical characteristics of the integrated circuit device of the present invention are improved.

[0067] Figure 6 and Figure 7 is a cross-sectional view of an integrated circuit device 20 according to an embodiment. In detail, Figure 6 It is along Figure 1 A cross-sectional view taken along line AA' in FIG. Figure 7 yes Figure 6 Magnified view of area CX2.

[0068] The components of the integrated circuit device 20 and the materials of the components described below are largely and substantially the same as those described above with reference to Figures 1 to 3 Therefore, for convenience of description, the integrated circuit device 20 is described focusing on the differences from the integrated circuit device 10 .

[0069] refer to Figure 6 and Figure 7 The integrated circuit device 20 may include a lower electrode 270 located above the substrate 110 , a support member SPT supporting the lower electrode 270 , a capacitor dielectric film 280 located on the lower electrode 270 , and an upper electrode 290 located on the capacitor dielectric film 280 .

[0070] The lower electrode 270 of the integrated circuit device 20 may have a cylindrical or cup shape having a closed bottom on the contact structure 150 .

[0071] The capacitor structure CS2 may include a lower electrode 270 electrically connected to the contact structure 150 , a capacitor dielectric film 280 conformally covering the lower electrode 270 , and an upper electrode 290 on the capacitor dielectric film 280 .

[0072] When the lower electrode 270 has a cylindrical shape, a surface area of ​​the lower electrode 270 corresponding to the storage electrode may be maximized, and thus, the capacitance of the capacitor structure CS2 may be increased.

[0073] In the integrated circuit device 20 of the present inventive concept, the lower interface film 270L may be between the lower electrode 270 and the capacitor dielectric film 280 , and the upper interface film 290L may be between the upper electrode 290 and the capacitor dielectric film 280 .

[0074] The lower interface film 270L is first described below. The lower interface film 270L may have a three-layer structure of a first lower interface layer 271, a second lower interface layer 272, and a third lower interface layer 273. In detail, the lower interface film 270L may include a structure in which the first lower interface layer 271, the second lower interface layer 272, and the third lower interface layer 273 are sequentially stacked on the lower electrode 270, wherein the first lower interface layer 271 includes a metal oxide doped with impurities, the second lower interface layer 272 includes a material substantially the same as that of the first lower interface layer 271 and is doped with nitrogen, and the third lower interface layer 273 includes a material substantially the same as that of the capacitor dielectric film 280 and is doped with nitrogen.

[0075] The upper interface film 290L is described below. The upper interface film 290L may have a three-layer structure of a first upper interface layer 291, a second upper interface layer 292, and a third upper interface layer 293. In detail, the upper interface film 290L may include a structure in which the first upper interface layer 291, the second upper interface layer 292, and the third upper interface layer 293 are sequentially stacked on the upper electrode 290, wherein the first upper interface layer 291 includes a metal oxide, the second upper interface layer 292 includes a material substantially the same as that of the first upper interface layer 291 and is doped with nitrogen, and the third upper interface layer 293 includes a material substantially the same as that of the capacitor dielectric film 280 and is doped with nitrogen.

[0076] The description of the lower electrode 270, the capacitor dielectric film 280 and the upper electrode 290 can be referred to above. Figures 1 to 3 The description of the lower electrode 170, the capacitor dielectric film 180, and the upper electrode 190 described above is basically the same. The description of the lower interface film 270L between the lower electrode 270 and the capacitor dielectric film 280 and the upper interface film 290L between the upper electrode 290 and the capacitor dielectric film 280 can also be the same as that described in the above reference. Figures 1 to 3 The description of the lower interface film 170L and the upper interface film 190L is substantially the same, and therefore, a detailed description thereof is omitted.

[0077] Figures 8 to 10 is a cross-sectional view of an integrated circuit device according to various example embodiments. In detail, Figure 8 is a layout diagram of an integrated circuit device 30 according to some embodiments. Fig. 9 It is along Figure 8 FIG. 1 is a cross-sectional view of the integrated circuit device 30 taken along line BB′ in FIG. Fig.10 yes Fig. 9 Magnified view of area CX3.

[0078] The components of the integrated circuit device 30 and the materials of the components described below are largely and substantially the same as those described above with reference to Figures 1 to 3 Therefore, for convenience of description, the integrated circuit device 30 is described focusing on the differences from the integrated circuit device 10 .

[0079] refer to Figures 8 to 10 , the integrated circuit device 30 may include a capacitor structure CS3 located on a vertical channel transistor (VCT) structure.

[0080] A lower insulating layer 312 may be on the substrate 310. A plurality of first conductive lines 320 may extend in the Y direction on the lower insulating layer 312 and may be spaced apart from each other in the X direction. A plurality of first insulating patterns 322 may be on the lower insulating layer 312 and may respectively fill spaces between the first conductive lines 320. The first conductive lines 320 may respectively correspond to bit lines BL of the integrated circuit device 30.

[0081] In some embodiments, the first conductive line 320 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the first conductive line 320 may include but is not limited to doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or a combination thereof. However, example embodiments are not limited thereto. The first conductive line 320 may include a single layer or multiple layers of the above materials. In some embodiments, the first conductive line 320 may include a two-dimensional (2D) semiconductor material. For example, a 2D semiconductor material may include graphene, a carbon nanotube, or a combination thereof.

[0082] A plurality of channel layers 330 may be arranged on the first conductive line 320 and may have an island shape spaced apart from each other in the X direction and the Y direction. Each channel layer 330 may have a channel width in the X direction and a channel height in the Z direction, wherein the channel height may be greater than the channel width. The bottom of each channel layer 330 may be used as a first source / drain region (not shown), and the upper portion of the channel layer 330 may be used as a second source / drain region (not shown). The portion of the channel layer 330 between the first source / drain region and the second source / drain region may be used as a channel region (not shown). VCT may refer to a structure in which the channel length of the channel layer 330 extends from the substrate 310 along the Z direction.

[0083] In some embodiments, the channel layer 330 may include an oxide semiconductor. For example, the oxide semiconductor may include Inx Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga y O, or a combination thereof. However, example embodiments are not limited thereto. The channel layer 330 may include a single layer or a multilayer structure of an oxide semiconductor. In some embodiments, the band gap energy of the channel layer 330 may be greater than the band gap energy of silicon. The channel layer 330 may be polycrystalline or amorphous, but is not limited thereto. In some embodiments, the channel layer 330 may include a 2D semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0084] In some embodiments, the gate electrode 340 may surround the sidewall of the channel layer 330 and extend in the X direction. The gate electrode 340 may be a full-surround gate type completely surrounding the sidewall of the channel layer 330. The gate electrode 340 may correspond to a word line WL of the integrated circuit device 30.

[0085] In some embodiments, gate electrode 340 may be a dual-gate type. For example, gate electrode 340 may include a first sub-gate electrode (not shown) facing a first sidewall of channel layer 330 and a second sub-gate electrode (not shown) facing a second sidewall opposite to the first sidewall of channel layer 330 .

[0086] In some embodiments, the gate electrode 340 may be a single gate type, and may extend along the X direction by covering only the first sidewall of the channel layer 330 .

[0087] The gate electrode 340 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the gate electrode 340 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x , or a combination thereof.

[0088] The gate insulating layer 350 may surround the sidewalls of the channel layer 330 and may be located between the channel layer 330 and the gate electrode 340. In some embodiments, the gate insulating layer 350 may include silicon nitride, silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k material may include a metal oxide or a metal oxynitride. For example, the high-k material of the gate insulating layer 350 may include, but is not limited to, HfO. 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 , or a combination thereof.

[0089] A first buried insulating layer 342 surrounding a lower sidewall of the channel layer 330 may be on the first insulating pattern 322. A second buried insulating layer 344 may be over the first buried insulating layer 342 and may surround an upper sidewall of the channel layer 330 and cover the gate electrode 340.

[0090] The capacitor contact 360 may be on the channel layer 330. The capacitor contact 360 may overlap vertically with the channel layer 330. A plurality of capacitor contacts 360 may be arranged in a matrix form and spaced apart from each other in the X direction and the Y direction. The capacitor contact 360 may include, but is not limited to, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or a combination thereof. An upper insulating layer 362 may be on the second buried insulating layer 344 and may surround the sidewalls of the capacitor contact 360.

[0091] The etch stop film 364 may be on the upper insulating layer 362, and the capacitor structure CS3 may be on the etch stop film 364. The capacitor structure CS3 may include a lower electrode 370, a capacitor dielectric film 380, and an upper electrode 390. The lower electrode 370 may be electrically connected to the capacitor contact 360. The capacitor dielectric film 380 may cover the lower electrode 370. The upper electrode 390 may be on the capacitor dielectric film 380 and cover the lower electrode 370. The support member SPT may be on the sidewall of the lower electrode 370.

[0092] In the integrated circuit device 30 of the present inventive concept, the lower interface film 370L may be between the lower electrode 370 and the capacitor dielectric film 380 , and the upper interface film 390L may be between the upper electrode 390 and the capacitor dielectric film 380 .

[0093] The lower interface film 370L is first described below. The lower interface film 370L may have a three-layer structure of a first lower interface layer 371, a second lower interface layer 372, and a third lower interface layer 373. In detail, the lower interface film 370L may include a structure in which the first lower interface layer 371, the second lower interface layer 372, and the third lower interface layer 373 are sequentially stacked on the lower electrode 370, wherein the first lower interface layer 371 includes a metal oxide doped with impurities, the second lower interface layer 372 includes a material substantially the same as that of the first lower interface layer 371 and is doped with nitrogen, and the third lower interface layer 373 includes a material substantially the same as that of the capacitor dielectric film 380 and is doped with nitrogen.

[0094] The upper interface film 390L is described below. The upper interface film 390L may have a three-layer structure of a first upper interface layer 391, a second upper interface layer 392, and a third upper interface layer 393. In detail, the upper interface film 390L may include a structure in which the first upper interface layer 391, the second upper interface layer 392, and the third upper interface layer 393 are sequentially stacked on the upper electrode 390, wherein the first upper interface layer 391 includes a metal oxide, the second upper interface layer 392 includes a material substantially the same as that of the first upper interface layer 391 and is doped with nitrogen, and the third upper interface layer 393 includes a material substantially the same as that of the capacitor dielectric film 380 and is doped with nitrogen.

[0095] The description of the lower electrode 370, the capacitor dielectric film 380 and the upper electrode 390 can be referred to above. Figures 1 to 3 The description of the lower electrode 170, the capacitor dielectric film 180, and the upper electrode 190 described above is basically the same. The description of the lower interface film 370L between the lower electrode 370 and the capacitor dielectric film 380 and the upper interface film 390L between the upper electrode 390 and the capacitor dielectric film 380 can also be the same as that described in the above reference. Figures 1 to 3The description of the lower interface film 170L and the upper interface film 190L is substantially the same, and therefore, a detailed description thereof is omitted.

[0096] Figures 11 to 13 is a flow chart of a method of manufacturing an integrated circuit device according to an embodiment.

[0097] When the embodiment can be modified, the order of operations may be different from the order in which the operations are described. For example, two operations described as being performed sequentially may be performed substantially simultaneously or in a reverse order.

[0098] refer to Fig.11 , the method S10 of manufacturing an integrated circuit device may include a sequence of operations S110 to S160 .

[0099] Method S10 may include: in operation S110, forming a gate structure and a contact structure on a substrate; in operation S120, forming a lower electrode on the contact structure; in operation S130, forming a lower interface film on the lower electrode; in operation S140, forming a capacitor dielectric film on the lower interface film; in operation S150, forming an upper interface film on the capacitor dielectric film; and in operation S160, forming an upper electrode on the upper interface film.

[0100] Reference below Figures 14 to 24 The technical characteristics of operations S110 to S160 are described in detail.

[0101] refer to Fig.12 , operation S130 of forming the lower interface film in the method S10 may include sub-operations S131 to S134 .

[0102] In method S10, operation S130 may include: in sub-operation S131, forming a lower interface material layer on the lower electrode; in sub-operation S132, forming a dielectric material layer on the lower interface material layer; in sub-operation S133, doping the entire dielectric material layer and a portion of the lower interface material layer with nitrogen by performing a first heat treatment using nitrogen on the substrate; and in sub-operation S134, forming a lower interface film consisting of a first lower interface layer to a third lower interface layer.

[0103] Here, the first heat treatment may include, but is not limited to, heat treatment using ammonia gas, plasma heat treatment using nitrogen gas, or plasma heat treatment using ammonia gas. However, example embodiments are not limited thereto.

[0104] refer to Fig.13 , operation S150 of forming the lower interface film in the method S10 may include sub-operations S151 to S154 .

[0105] In method S10, operation S150 may include: in sub-operation S151, forming a first upper interface material layer on a capacitor dielectric film; in sub-operation S152, doping the entire first upper interface material layer and a portion of the capacitor dielectric film with nitrogen by performing a second heat treatment using nitrogen on the substrate; in sub-operation S153, forming a second upper interface material layer on the first upper interface material layer doped with nitrogen; and in sub-operation S154, forming an upper interface film consisting of the first upper interface layer to the third upper interface layer.

[0106] Here, the second heat treatment may include, but is not limited to, heat treatment using ammonia gas, plasma heat treatment using nitrogen gas, or plasma heat treatment using ammonia gas. However, example embodiments are not limited thereto.

[0107] Figures 14 to 24 are cross-sectional views of stages in a method of fabricating an integrated circuit device according to an embodiment.

[0108] For ease of description, Figures 14 to 24 is along Figure 1 Cross-sectional view along line A-A'.

[0109] refer to Fig.14 , an isolation trench 112T may be formed in the substrate 110 , and an isolation film 112 defining the active area AC may be formed in the isolation trench 112T.

[0110] Subsequently, a mask pattern (not shown) may be formed on the substrate 110, and a plurality of gate line trenches 120T may be formed in the substrate 110 by using the mask pattern as an etching mask. The gate line trenches 120T may extend parallel to each other, and each gate line trench 120T may have a line shape crossing the active region AC.

[0111] Subsequently, a gate insulating layer 122 may be formed on the inner wall of each gate line trench 120T. A gate electrode layer 124 may be formed by forming a gate conductive layer (not shown) on the gate insulating layer 122 to fill each gate line trench 120T, and then removing the upper portion of the gate conductive layer to a certain height using an etch-back process.

[0112] Subsequently, a gate capping layer 126 may be formed in the gate line trench 120T by forming an insulating material to fill the remaining portion of the gate line trench 120T and planarizing the insulating material to expose the top surface of the substrate 110. At this time, the mask pattern may be removed.

[0113] Subsequently, source / drain regions 114 may be formed by implanting impurity ions into a portion of substrate 110 at each of opposite sides of gate structure 120. Alternatively, source / drain regions 114 may be formed on active region AC by implanting impurity ions into substrate 110 after forming isolation film 112.

[0114] refer to Fig.15 , a first interlayer insulating film 142 may be formed on the substrate 110 , and an opening may be formed in the first interlayer insulating film 142 to expose a top surface of the source / drain region 114 .

[0115] A bit line contact 132 electrically connected to the source / drain region 114 may be formed in the opening by forming a conductive layer on the first interlayer insulating film 142 to fill the opening and planarizing an upper portion of the conductive layer.

[0116] Subsequently, the bit line 134 and the bit line capping layer 136 may be formed to extend in the Y direction parallel to the top surface of the substrate 110 by sequentially forming a conductive layer and an insulating layer on the first interlayer insulating film 142 and then patterning the conductive layer and the insulating layer. Although not shown, a bit line spacer may be further formed on the sidewalls of the bit line 134 and the sidewalls of the bit line capping layer 136.

[0117] Subsequently, a second interlayer insulating film 144 may be formed on the first interlayer insulating film 142 to cover the bit line 134 and the bit line capping layer 136 .

[0118] Subsequently, openings may be formed in the first interlayer insulating film 142 and the second interlayer insulating film 144 to expose the top surface of the source / drain region 114, and a contact structure 150 may be formed in the openings of the first interlayer insulating film 142 and the second interlayer insulating film 144. In some example embodiments, the contact structure 150 may be formed by sequentially forming a lower contact (not shown), a metal silicide layer (not shown), and an upper contact (not shown) in the openings of the first interlayer insulating film 142 and the second interlayer insulating film 144.

[0119] refer to Fig.16 , an etch stop film 160 , a mold layer ML, a support member forming layer SPTL, and a sacrificial layer SL may be sequentially formed on the second interlayer insulating film 144 and the contact structure 150 .

[0120] The mold layer ML may include silicon oxide. For example, the mold layer ML may be formed using a material such as BPSG, spin-on dielectric (SOD), PSG, PE-TEOS, or low-pressure TEOS (LP TEOS). The mold layer ML may be formed to a thickness of about 500 nm to about 4000 nm, but is not limited thereto.

[0121] Subsequently, a support member forming layer SPTL may be formed in the mold layer ML. The support member forming layer SPTL may include silicon oxide, silicon nitride, or silicon oxynitride.

[0122] Subsequently, a sacrificial layer SL may be formed on the mold layer ML. For example, the sacrificial layer SL may be formed using a material such as TEOS, BPSG, PSG, USG, SOD, or high density plasma oxide (HDP). The sacrificial layer SL may be formed to a thickness of about 50 nm to about 200 nm, but is not limited thereto.

[0123] Subsequently, a mask pattern MP may be formed by coating a photoresist on the sacrificial layer SL and patterning the photoresist through exposure and development. Fig.19 ) may be defined by the mask pattern MP. An anti-reflective coating (ARC) (not shown) may also be formed on the sacrificial layer SL.

[0124] refer to Fig.17 The through holes PH may be formed by sequentially etching the sacrificial layer SL, the support forming layer SPTL, and the mold layer ML using the mask pattern MP as an etching mask.

[0125] Subsequently, the opening 160T may be formed by removing a portion of the etch stop film 160 exposed at the bottom of the through hole PH. The top surface of the contact structure 150 may be exposed through the through hole PH and the opening 160T.

[0126] Subsequently, the mask pattern MP may be removed through an ashing process and a stripping process.

[0127] refer to Fig.18 , the lower electrode forming layer 170P may be formed to conformally cover the inner wall of the through hole PH and the inner wall of the opening 160T.

[0128] In various example embodiments, the lower electrode-forming layer 170P may be formed on side surfaces of the etch stop film 160, side surfaces of the mold layer ML, side surfaces of the supporter-forming layer SPTL, and side surfaces and a top surface of the sacrificial layer SL so as to contact the top surface of the contact structure 150. For example, the lower electrode-forming layer 170P may be formed using CVD or ALD.

[0129] refer to Fig.19 , the lower electrode forming layer 170P can be removed by using a node separation process (see Fig.18 ) above the top surface of the mold layer ML and the sacrificial layer SL (see Fig.18 ) to form the lower electrode 170.

[0130] The node separation process may remove the sacrificial layer SL through an etch-back process or chemical mechanical polishing (CMP).

[0131] Subsequently, the mold layer ML may be removed. For example, when the mold layer ML includes silicon oxide, the mold layer ML may be completely removed through a wet etching process using hydrofluoric acid or buffered oxide etchant (BOE).

[0132] During the wet etching process, the support member SPT is not etched but holds and firmly supports the lower electrode 170, thereby preventing the lower electrode 170 from collapsing or breaking. The lower electrode 170 may be formed on the contact structure 150 to have a columnar shape extending in the Z direction perpendicular to the top surface of the substrate 110.

[0133] refer to Fig. 20 , a lower interface material layer 170LP may be formed on an outer surface of the lower electrode 170 and an outer surface of the support member SPT, and a dielectric material layer 180P may be formed on the lower interface material layer 170LP.

[0134] A lower interface material layer 170LP may be first formed on the outer surface of the lower electrode 170 and the outer surface of the support member SPT. The lower interface material layer 170LP may include a metal oxide doped with impurities. In detail, the metal oxide included in the lower interface material layer 170LP may include titanium oxide, and the impurities included in the lower interface material layer 170LP may include a pentavalent element. For example, the impurities included in the lower interface material layer 170LP may include, but are not limited to, vanadium (V), niobium (Nb), tantalum (Ta), phosphorus (P), or antimony (Sb).

[0135] Subsequently, a dielectric material layer 180P may be formed on the lower interface material layer 170LP. The dielectric material layer 180P may include at least one selected from the group consisting of zirconium oxide, hafnium oxide, and aluminum oxide. The thickness of the dielectric material layer 180P may be 10 angstroms, but is not limited thereto.

[0136] refer to Fig.21 , a lower interface material layer 170LP may be formed thereon (see Fig. 20 ) and dielectric material layer 180P (see Fig. 20 ) is performed on the substrate 110.

[0137] In some embodiments, the first thermal treatment P1 may be performed at a temperature of about 300° C. to about 500° C. for several minutes to several hours. In some cases, the first thermal treatment P1 may be accompanied by a plasma treatment. The first thermal treatment P1 is not limited to these values. During the first thermal treatment P1, nitrogen included in the process gas (ammonia or nitrogen) may be diffused throughout the dielectric material layer 180P as a dopant (see Fig. 20 ) and the upper portion of the lower interface material layer 170LP (see Fig. 20 )middle.

[0138] Therefore, a portion (e.g., a lower portion) of the lower interface material layer 170LP that is not doped with nitrogen may be formed as a first lower interface layer 171. A portion (e.g., an upper portion) of the lower interface material layer 170LP that is doped with nitrogen may be formed as a second lower interface layer 172. The dielectric material layer 180P doped with nitrogen may be formed as a third lower interface layer 173. In other words, the first lower interface layer 171 and the second lower interface layer 172 may be distinguished from each other by the difference in nitrogen doping concentration therebetween.

[0139] Through this process, a lower interface film 170L including first to third lower interface layers 171 , 172 , and 173 may be formed on the lower electrode 170 .

[0140] refer to Fig. 22 , a primary capacitor dielectric film P180 may be formed on the lower interface film 170L, and an upper interface material layer 190P may be formed on the primary capacitor dielectric film P180.

[0141] A primary capacitor dielectric film P180 may be first formed on the outer surface of the lower interface film 170L. The primary capacitor dielectric film P180 may include at least one selected from the group consisting of zirconium oxide, hafnium oxide, and aluminum oxide. The thickness of the primary capacitor dielectric film P180 may be 40 angstroms, but is not limited thereto.

[0142] Subsequently, an upper interface material layer 190P may be formed on the primary capacitor dielectric film P180. The upper interface material layer 190P may include a metal oxide. In detail, the metal oxide included in the upper interface material layer 190P may include, but is not limited to, titanium oxide, tantalum oxide, or niobium oxide. Fig. 20 ), the upper interface material layer 190P may not include a pentavalent element as an impurity.

[0143] refer to Fig.23 , an upper interface material layer 190P may be formed thereon (see Fig. 22 ) and the primary capacitor dielectric film P180 (see Fig. 22 ) is subjected to a second heat treatment P2.

[0144] In some embodiments, the second thermal treatment P2 may be performed at a temperature of about 300° C. to about 500° C. for several minutes to several hours. In some cases, the second thermal treatment P2 may be accompanied by a plasma treatment. The second thermal treatment P2 is not limited to these values. During the second thermal treatment P2, nitrogen included in the process gas (ammonia or nitrogen) may be diffused as a dopant throughout the upper interface material layer 190P (see Fig. 22 ) and the upper portion of the primary capacitor dielectric film P180 (see Fig. 22 ).

[0145] Therefore, a portion (e.g., a lower portion) of the primary capacitor dielectric film P180 that is not doped with nitrogen may be formed as the capacitor dielectric film 180. A portion (e.g., an upper portion) of the primary capacitor dielectric film P180 that is doped with nitrogen may be formed as a third upper interface layer 193. The upper interface material layer 190P doped with nitrogen may be formed as a second upper interface layer 192.

[0146] refer to Fig.24 , a first upper interface layer 191 may be formed on the second upper interface layer 192 .

[0147] The first upper interface layer 191 may include a metal oxide. In detail, the metal oxide included in the first upper interface layer 191 may include, but is not limited to, titanium oxide, tantalum oxide, or niobium oxide. In other words, the first upper interface layer 191 and the second upper interface layer 192 may be distinguished from each other by the difference in nitrogen doping concentration between them.

[0148] Through this process, an upper interface film 190L including first to third upper interface layers 191 , 192 , and 193 may be formed on the capacitor dielectric film 180 .

[0149] Return to reference Figure 2 , an upper electrode 190 may be formed on the upper interface film 190L.

[0150] The upper electrode 190 may be formed on the capacitor dielectric film 180 so as to completely fill the space defined by the adjacent lower electrodes 170. The upper electrode 190 may be conformally formed on the capacitor dielectric film 180 to cover each lower electrode 170 with the capacitor dielectric film 180 therebetween.

[0151] In some embodiments, the upper electrode 190 may include a metal nitride, a metal, or a combination thereof. For example, the upper electrode 190 may include at least one selected from the group consisting of TiN, TaN, WN, Ru, Pt, and Ir.

[0152] The integrated circuit device 10 may be completely formed by sequentially performing the above-mentioned processes.

[0153] By including the lower interface film 170L and the upper interface film 190L each having a multilayer structure with different nitrogen doping concentrations in each capacitor structure CS, leakage current flowing through the capacitor dielectric film 180 between adjacent capacitor structures CS may be reduced in the integrated circuit device 10 .

[0154] Fig.25 is a block diagram of a system 1000 including an integrated circuit device according to an embodiment.

[0155] refer to Fig.25 , the system 1000 may include a controller 1010 , an input / output (I / O) device 1020 , a memory device 1030 , an interface 1040 , and a bus 1050 .

[0156] System 1000 may include a mobile system, or a system for transmitting or receiving information. In some embodiments, the mobile system may include a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

[0157] The controller 1010 may control executable programs in the system 1000 and include a microprocessor, a digital signal processor, a microcontroller, and the like.

[0158] The I / O device 1020 may be used for data input or output of the system 1000. The system 1000 may be connected to an external device such as a personal computer (PC) or a network using the I / O device 1020 and exchange data therewith. For example, the I / O device 1020 may include a touch screen, a touch pad, a keyboard, or a display.

[0159] The memory device 1030 may store data used for the operation of the controller 1010 or data that has been processed by the controller 1010. The memory device 1030 may include the above-described integrated circuit device 10, 20, or 30 according to the inventive concept.

[0160] The interface 1040 may correspond to a data transmission path between the system 1000 and an external device. The controller 1010 , the I / O device 1020 , the memory device 1030 , and the interface 1040 may communicate with each other through the bus 1050 .

[0161] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: A transistor, wherein the transistor is located on a substrate; as well as a capacitor structure electrically connected to the transistor, Wherein, the capacitor structure comprises: Lower electrode, A lower interface film, the lower interface film being located on the lower electrode; a capacitor dielectric film, the capacitor dielectric film being located on the lower interface film; an upper interface film, the upper interface film being located on the capacitor dielectric film; and an upper electrode, the upper electrode being located on the upper interface film, Wherein, the lower interface membrane comprises: a first lower interface layer, the first lower interface layer comprising a metal oxide doped with impurities; a second lower interface layer, the second lower interface layer comprising a material substantially the same as that of the first lower interface layer and doped with nitrogen; and a third lower interface layer, the third lower interface layer comprising a material that is the same as that of the capacitor dielectric film and is doped with nitrogen, the first to third lower interface layers being sequentially stacked on the lower electrode, and Wherein, the upper interface film comprises: a first upper interface layer, the first upper interface layer comprising a metal oxide; a second upper interface layer, the second upper interface layer comprising the same material as that of the first upper interface layer and doped with nitrogen; and A third upper interface layer includes a material that is the same as that of the capacitor dielectric film and is doped with nitrogen, and the first to third upper interface layers are sequentially stacked on the upper electrode.

2. The integrated circuit device according to claim 1, wherein: The metal oxide included in the first lower interface layer includes titanium oxide, and the impurities included in the first lower interface layer include a pentavalent element.

3. The integrated circuit device according to claim 2, wherein: The nitrogen doping concentration in the second lower interface layer is higher than the nitrogen doping concentration in the first lower interface layer.

4. The integrated circuit device according to claim 1, wherein: The impurities included in the first lower interface layer include at least one of vanadium, niobium, tantalum, phosphorus, and antimony.

5. The integrated circuit device according to claim 1, wherein: The metal oxide included in the first upper interface layer includes at least one of titanium oxide, tantalum oxide, and niobium oxide.

6. The integrated circuit device according to claim 5, wherein: The nitrogen doping concentration in the second upper interface layer is higher than the nitrogen doping concentration in the first upper interface layer.

7. The integrated circuit device according to claim 1, wherein: The capacitor dielectric film includes at least one selected from the group consisting of zirconium oxide, hafnium oxide, and aluminum oxide.

8. The integrated circuit device according to claim 7, wherein: A nitrogen doping concentration in each of the third lower interface layer and the third upper interface layer is higher than a nitrogen doping concentration in the capacitor dielectric film.

9. The integrated circuit device according to claim 1, wherein: The doping of nitrogen included in the second lower interface layer and the doping of nitrogen included in the third lower interface layer are simultaneously performed through a single process.

10. The integrated circuit device according to claim 1, wherein: The doping of nitrogen included in the second upper interface layer and the doping of nitrogen included in the third upper interface layer are simultaneously performed through a single process.

11. An integrated circuit device, comprising: A plurality of lower electrodes, wherein the plurality of lower electrodes are located on the substrate; A support member, wherein the support member is located between the plurality of lower electrodes; an upper electrode, the upper electrode being located on the plurality of lower electrodes; a capacitor dielectric film, the capacitor dielectric film being located between the plurality of lower electrodes and the upper electrode; A lower interface film, the lower interface film being located between the plurality of lower electrodes and the capacitor dielectric film, the lower interface film having a multilayer structure with different nitrogen doping concentrations; as well as An upper interface film is located between the upper electrode and the capacitor dielectric film, and has a multilayer structure with different nitrogen doping concentrations.

12. The integrated circuit device according to claim 11, wherein: The lower interface film comprises: a first lower interface layer, the first lower interface layer comprising a metal oxide doped with impurities; a second lower interface layer, the second lower interface layer comprising the same material as that of the first lower interface layer and doped with nitrogen; and a third lower interface layer, the third lower interface layer comprising a material that is the same as that of the capacitor dielectric film and is doped with nitrogen, the first to third lower interface layers being sequentially stacked on the plurality of lower electrodes, and Wherein, the upper interface film comprises: a first upper interface layer, the first upper interface layer comprising a metal oxide; a second upper interface layer, the second upper interface layer comprising the same material as that of the first upper interface layer and doped with nitrogen; and A third upper interface layer includes a material that is the same as that of the capacitor dielectric film and is doped with nitrogen, and the first to third upper interface layers are sequentially stacked on the upper electrode.

13. The integrated circuit device according to claim 12, wherein: The metal oxide included in the first lower interface layer includes titanium oxide, The impurities included in the first lower interface layer include pentavalent elements, and The nitrogen doping concentration in the second lower interface layer is higher than the nitrogen doping concentration in the first lower interface layer.

14. The integrated circuit device according to claim 12, wherein: The metal oxide included in the first upper interface layer includes at least one of titanium oxide, tantalum oxide and niobium oxide, and The nitrogen doping concentration in the second upper interface layer is higher than the nitrogen doping concentration in the first upper interface layer.

15. The integrated circuit device according to claim 11, wherein: The capacitor dielectric film includes at least one selected from the group consisting of zirconium oxide, hafnium oxide, and aluminum oxide.

16. A method of manufacturing an integrated circuit device, the method comprising: forming a lower electrode on the substrate; forming a lower interface material layer on the lower electrode; forming a dielectric material layer on the lower interface material layer; doping the entire dielectric material layer and a portion of the lower interface material layer with nitrogen by performing a first thermal treatment using nitrogen on the substrate; forming a capacitor dielectric film on the dielectric material layer doped with nitrogen; forming a first upper interface material layer on the capacitor dielectric film; doping the entire first upper interface material layer and a portion of the capacitor dielectric film with nitrogen by performing a second thermal treatment using nitrogen on the substrate; forming a second upper interface material layer on the first upper interface material layer doped with nitrogen; as well as An upper electrode is formed on the second upper interface material layer.

17. The method according to claim 16, wherein: The integrated circuit device includes a lower interface film located between the lower electrode and the capacitor dielectric film, the lower interface film including: a first lower interface layer, wherein the first lower interface layer is composed of a portion of the lower interface material layer that is not doped with nitrogen, a second lower interface layer, the second lower interface layer being composed of a portion of the lower interface material layer doped with nitrogen, and a third lower interface layer, the third lower interface layer being composed of the dielectric material layer doped with nitrogen, and Wherein, the integrated circuit device further includes an upper interface film located between the upper electrode and the capacitor dielectric film, and the upper interface film includes: a first upper interface layer, wherein the first upper interface layer is composed of the second upper interface material layer not doped with nitrogen, a second upper interface layer, the second upper interface layer being composed of the first upper interface material layer doped with nitrogen, and A third upper interface layer is formed by a portion of the capacitor dielectric film doped with nitrogen.

18. The method according to claim 17, wherein: The doping of nitrogen included in the second lower interface layer and the doping of nitrogen included in the third lower interface layer are simultaneously performed through the first heat treatment.

19. The method according to claim 17, wherein: The doping of nitrogen included in the second upper interface layer and the doping of nitrogen included in the third upper interface layer are simultaneously performed through the second heat treatment.

20. The method according to claim 16, wherein: The first heat treatment and the second heat treatment each include plasma treatment using ammonia gas or nitrogen gas.

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