Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device and a preparation method thereof, and a storage system. The semiconductor device comprises a stacking structure and a first grid line gap structure. The stacking structure comprises insulating layers and gate layers which are stacked alternately, the first gate line gap structure penetrates through the stacking structure in the stacking direction of the stacking structure and extends in the first direction, and the first direction and the stacking direction intersect with each other. Wherein the first grid line gap structure comprises a first conducting layer, a second conducting layer and a first dielectric layer, the first conducting layer surrounds the side wall of the second conducting layer, and the first dielectric layer is located between the second conducting layer and the first conducting layer. The first grid line gap structure comprises the two conductive layers which are mutually insulated, and the first conductive layer and the second conductive layer can form a capacitor structure as a part of structure of some circuits, so that the function of the first grid line gap structure is increased, and the utilization rate of the first grid line gap structure is improved.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more specifically, to a semiconductor device and a method for manufacturing the same, and a storage system. Background Art

[0002] NAND memory devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limit. In order to further increase storage capacity and reduce the storage cost per bit, 3D NAND memory is proposed. In the 3D NAND memory structure, a stacked memory structure is realized by vertically stacking multiple layers of data storage units.

[0003] The 3D NAND memory includes a gate line gap structure, but currently the utilization rate of the gate line gap structure is too low.

[0004] Application Contents

[0005] The purpose of the present application is to provide a semiconductor device and a method for manufacturing the same, and a storage system, aiming to improve the utilization rate of the first gate line gap structure.

[0006] In a first aspect, the present application provides a semiconductor device, the semiconductor device comprising:

[0007] A stacked structure comprising alternately stacked insulating layers and gate layers;

[0008] A first gate line gap structure, which penetrates the stack structure along a stacking direction of the stack structure and extends along a first direction, wherein the first direction intersects the stacking direction;

[0009] The first gate line gap structure includes a first conductive layer, a second conductive layer and a first dielectric layer, the first conductive layer surrounds the side wall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.

[0010] In some embodiments, the first gate line gap structure further includes:

[0011] The second dielectric layer extends along the first direction, and the second conductive layer surrounds the sidewall of the second dielectric layer.

[0012] In some embodiments, the first gate line gap structure further includes:

[0013] A first isolation layer is located between the stacked structure and the first conductive layer.

[0014] In some embodiments, the semiconductor device further comprises:

[0015] A first partition structure extending along the stacking direction and located at two ends of the first conductive layer along the first direction;

[0016] The first partition structure partitions the first conductive layer into a first electrode and a second electrode, the first electrode and the second electrode are respectively located on both sides of the first dielectric layer along a second direction, and the first direction, the second direction and the stacking direction intersect each other.

[0017] In some embodiments, the semiconductor device further comprises:

[0018] A second partition structure extending along the stacking direction and located at two ends of the second conductive layer along the first direction;

[0019] The second partition structure partitions the second conductive layer into a third electrode and a fourth electrode, the third electrode and the fourth electrode are respectively located on both sides of the second dielectric layer along a second direction, and the first direction, the second direction and the stacking direction intersect each other.

[0020] In some embodiments, the semiconductor device includes a main body region and an edge region located at the periphery of the main body region, the edge region includes a first edge region and a second edge region located at both sides of the main body region in a second direction, and the first direction, the second direction and the stacking direction intersect each other;

[0021] The first gate line gap structure is located in the first edge region and the second edge region.

[0022] In some embodiments, the first edge region has two first gate line gap structures arranged along the first direction and parallel to each other, and the second edge region has two first gate line gap structures arranged along the first direction and parallel to each other.

[0023] In some embodiments, the semiconductor device includes a core region and a non-core region adjacent to the core region in the first direction, and the first gate line gap structure is located in the non-core region and disposed along the first direction.

[0024] In some embodiments, the semiconductor device further comprises:

[0025] The second gate line gap structure penetrates the stacking structure of the core area along the stacking direction and is arranged along the first direction, and one end of the second gate line gap structure along the first direction is connected to the first gate line gap structure.

[0026] In some embodiments, the second gate line gap structure includes:

[0027] a third conductive layer, arranged along the first direction and connected to the first conductive layer;

[0028] The second isolation layer surrounds the side wall of the third conductive layer and is connected to the first isolation layer.

[0029] In some embodiments, a width of the second gate line gap structure along a second direction is smaller than a width of the first gate line gap structure along the second direction, and the first direction, the second direction and the stacking direction intersect with each other.

[0030] In some embodiments, the semiconductor device further comprises:

[0031] The peripheral circuit is located at one side of the stack structure, and the peripheral circuit includes a charge pump circuit. The plurality of first gate line gap structures are connected to the charge pump circuit via connection contacts.

[0032] In some embodiments, a plurality of the first conductive layers in a plurality of the first gate line gap structures are connected in parallel, and a plurality of the second conductive layers in a plurality of the first gate line gap structures are connected in parallel.

[0033] In a second aspect, the present application provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising:

[0034] forming a stacked structure, the stacked structure comprising insulating layers and gate layers stacked alternately;

[0035] A first gate line gap structure is formed that penetrates the stacking structure along the stacking direction of the stacking structure, wherein the first gate line gap structure extends along a first direction, the first direction intersects with the stacking direction, the first gate line gap structure includes a first conductive layer, a second conductive layer and a first dielectric layer, the first conductive layer surrounds the side wall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.

[0036] In some embodiments, the semiconductor device includes a main body region and an edge region located at the periphery of the main body region, the edge region includes a first edge region and a second edge region located at both sides of the main body region in a second direction, and the first direction, the second direction and the stacking direction intersect each other;

[0037] The step of forming a first gate line gap structure penetrating the stack structure along a stacking direction of the stack structure comprises:

[0038] Forming a first gate line gap penetrating the stack structure along a stacking direction of the stack structure, wherein the first gate line gap is located in the first edge region and the second edge region and extends along the first direction;

[0039] A first isolation layer, a first conductive layer, a first dielectric layer, a second conductive layer and a second dielectric layer are sequentially formed in the first gate line gap.

[0040] In some embodiments, the semiconductor device includes a main body region and an edge region located at the periphery of the main body region, the main body region includes a core region and a non-core region adjacent to the core region in the first direction, and the first gate line gap structure is located in the non-core region;

[0041] The method for preparing the semiconductor device further includes:

[0042] A second gate line gap structure of the stacking structure penetrating the core area along the stacking direction is formed.

[0043] In some embodiments, the step of forming the first gate line gap structure and the step of forming the second gate line gap structure include:

[0044] Forming a groove penetrating the stacked structure along a stacking direction of the stacked structure, the groove comprising a first gate line gap located in the non-core area and a second gate line gap located in the core area, and the width of the first gate line gap in the second direction is greater than the width of the second gate line gap in the second direction, and the first direction, the second direction and the stacking direction intersect each other;

[0045] An isolation layer, a conductive layer, a first dielectric layer, a second conductive layer and a second dielectric layer are sequentially formed in the groove, the isolation layer includes a first isolation layer located in the first gate line gap and a second isolation layer located in the second gate line gap, the conductive layer includes a first conductive layer located in the first gate line gap and a third conductive layer located in the second gate line gap, and the second isolation layer and the third conductive layer fill the second gate line gap.

[0046] In some embodiments, the method for preparing the semiconductor device further includes:

[0047] A peripheral circuit is formed on one side of the stack structure, wherein the peripheral circuit includes a charge pump circuit, and a plurality of the first gate line gap structures are connected to the charge pump circuit via connection contacts.

[0048] In a third aspect, the present application provides a storage system, including:

[0049] The semiconductor device in any of the above embodiments;

[0050] A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

[0051] The present application provides a semiconductor device and a method for manufacturing the same, as well as a storage system. The semiconductor device includes a stacking structure and a first gate line gap structure. The stacking structure includes alternately stacked insulating layers and gate layers. The first gate line gap structure penetrates the stacking structure along the stacking direction of the stacking structure and extends along a first direction, wherein the first direction intersects with the stacking direction. The first gate line gap structure includes a first conductive layer, a second conductive layer and a first dielectric layer, wherein the first conductive layer surrounds the sidewall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer. Since the first gate line gap structure includes two mutually insulated conductive layers, the first conductive layer and the second conductive layer can form a capacitor structure as a part of some circuit structures, the present application makes full use of the first gate line gap structure, increases the function of the first gate line gap structure, and improves the utilization rate of the first gate line gap structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0053] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device provided in some embodiments of the present application;

[0054] Figure 2 is a working schematic diagram of a charge pump circuit provided in some embodiments of the present application;

[0055] Figure 3 is a schematic diagram of the structure of a capacitor in a charge pump circuit provided in some embodiments of the present application;

[0056] Figure 4 is a schematic diagram of a top view of a semiconductor device provided in some embodiments of the present application;

[0057] Figure 5a is a schematic cross-sectional structure diagram of a semiconductor device provided in some embodiments of the present application;

[0058] Figure 5b Some embodiments of the present application provide Figure 5a A schematic diagram of the cross-sectional structure of the first gate line gap structure along B-B1;

[0059] Figure 6 is a partial cross-sectional structural schematic diagram of a first gate line gap structure and a second gate line gap structure provided in some embodiments of the present application;

[0060] Figure 7 is a schematic diagram of a cross-sectional structure of a semiconductor device provided by some embodiments of the present application along the YZ plane direction;

[0061] Figure 8is a schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present application;

[0062] Figures 9a-9d is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application;

[0063] Figure 10a-10c is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application;

[0064] Fig.11 It is a schematic diagram of the structure of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0065] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0066] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0067] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0068] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower or upper structure, or may have a range that is less than the range of the lower or upper structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure whose thickness is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer (wherein contacts, interconnect lines and / or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

[0069] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0070] This article uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the stacking direction. The first direction, the second direction, and the stacking direction intersect with each other, that is, X, Y, and Z intersect with each other, for example, they may be perpendicular to each other, or at a certain angle.

[0071] The semiconductor device in the embodiment of the present application can be a wafer, or a three-dimensional memory or a part of a three-dimensional memory. The three-dimensional memory can be applied to communication products, consumer electronics products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronics products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0072] See also Figure 1 , Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor device provided in some embodiments of the present application.

[0073] The semiconductor device 100 includes a stacked structure 10 and a first gate line gap structure 11. The stacked structure 10 includes an insulating layer 101 and a gate layer 102 that are alternately stacked. The first gate line gap structure 11 penetrates the stacked structure 10 along the stacking direction (Z) of the stacked structure 10 and extends along a first direction (X). The first gate line gap structure 11 includes a first conductive layer 111, a second conductive layer 112 and a first dielectric layer 113. The first conductive layer 111 surrounds the sidewall of the second conductive layer 112. The first dielectric layer 113 is located between the second conductive layer 112 and the first conductive layer 111.

[0074] The number of layers of the stacking structure 10 determines the number of storage units it contains in the stacking direction (Z). For example, the number of layers of the stacking structure 10 can be 32 layers, 64 layers, 96 layers, 128 layers, etc., and the more layers the stacking structure 10 has, the higher the integration of the corresponding three-dimensional memory.

[0075] The material of the insulating layer 101 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the gate layer 102 may include a conductive layer, such as tungsten. In some embodiments, the gate layer 102 may include a dielectric layer (such as a high-K dielectric layer) and a conductive layer, and the conductive layer may include a first conductive layer (such as titanium carbide) and a second conductive layer (such as tungsten) formed in sequence.

[0076] The material of the first conductive layer 111 and the second conductive layer 112 may include at least one of polysilicon and metal, and the material of the first dielectric layer 113 includes but is not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride, and the first dielectric layer 113 is used to isolate the first conductive layer 111 and the second conductive layer 112. In some embodiments, the first conductive layer 111 and the second conductive layer 112 may also include some semiconductor conductive materials, such as silicon (Si) and germanium (Ge).

[0077] like Figure 1 As shown, the first dielectric layer 113 surrounds the sidewall and bottom of the second conductive layer 112, and the second conductive layer 112 surrounds the sidewall and bottom of the first dielectric layer 113. Since the first gate line gap structure 11 includes two mutually insulated conductive layers, the first conductive layer 111 and the second conductive layer 112 can form a capacitor structure as a part of some circuit structures, so the present application can make full use of the first gate line gap structure 11, which not only increases the function of the first gate line gap structure 11, but also saves some circuit area.

[0078] For example, the semiconductor device 100 may include a peripheral circuit 12, and the peripheral circuit 12 may include a charge pump circuit, an analog circuit, etc., and these circuits include at least one capacitor. The peripheral circuit 12 may be located on one side of the stacking structure 10 along the stacking direction (Z) and connected to the first gate line gap structure 11. Specifically, the peripheral circuit 12 may be connected to the first conductive layer 111 and the second conductive layer 112 through a connecting contact (not shown). Specifically, the stacking structure 10 has a side close to the bottom of the first gate line gap structure 11 and a side away from the bottom of the first gate line gap structure 11. The peripheral circuit 12 may be connected to the side of the stacking structure 10 close to the bottom of the first gate line gap structure 11 by bonding (such as Figure 1 As shown in FIG. 1 ), it can also be connected to a side of the stacked structure 10 away from the bottom of the first gate line gap structure 11. Therefore, the capacitor in the peripheral circuit 12 can be transferred to the first gate line gap structure 11, saving the area of ​​the peripheral circuit 12 and making full use of the first gate line gap structure 11 to realize its capacitor function.

[0079] See also Figure 2 and Figure 3 , Figure 2 is a schematic diagram of the operation of the charge pump circuit provided in some embodiments of the present application, Figure 3 It is a schematic diagram of the structure of the capacitor in the charge pump circuit provided in some embodiments of the present application.

[0080] The charge pump circuit includes switches S1, S2, S3 and S4, and capacitors C1 and C2 connected in parallel. During the operation of the semiconductor device 100, the charge pump circuit converts the low voltage V DD Pull to the operating voltage Vout The capacitor C1 may be formed by connecting a plurality of capacitor structures in parallel, and the capacitor C2 may also be formed by connecting a plurality of capacitor structures in parallel. Since C1 and C2 are connected in parallel, all capacitor structures may be connected in parallel through a charge pump circuit.

[0081] The structure of the capacitor is as follows Figure 3 As shown, multiple capacitor structures C0 can be connected in parallel to form Figure 2 A capacitor C1 / C2 is provided in the capacitor structure C0, and each capacitor structure C0 includes a first plate C01 and a second plate C02. Wherein, one plate is taken from each capacitor structure C0 and connected together, and another plate in each capacitor structure C0 is connected together. For example, the first plates C01 of each capacitor structure C0 are all connected in parallel, and the second plates C02 of each capacitor structure C0 are all connected in parallel. The first plate C01 can be the first conductive layer 111 in the above-mentioned embodiment, and the second plate C02 can be the second conductive layer 112 in the above-mentioned embodiment, that is, the multiple first conductive layers 111 in the multiple first gate line gap structures 11 are all connected in parallel, and the multiple second conductive layers 112 in the multiple first gate line gap structures 11 are all connected in parallel.

[0082] See also Figure 4 , Figure 4 It is a schematic diagram of the top view structure of the semiconductor device provided in some embodiments of the present application.

[0083] The semiconductor device 100 includes a plurality of storage planes, each of which includes a main region P1 and an edge region P2 located at the periphery of the main region P1 , that is, the edge region P2 surrounds the main region P1 . Figure 4 It is mainly used to show the position of the first gate line gap structure 11. Figure 1 Can be Figure 4 Schematic diagram of the cross-sectional structure of the first gate line gap structure 11 along A-A1.

[0084] In some embodiments, the first gate line gap structure 11 may be located in the edge region P2 around the main region P1. For example, the first gate line gap structure 11 may be in the shape of a U-shaped rectangle, that is, two rectangles of different sizes.

[0085] In some embodiments, the first gate line gap structure 11 may be located only in the edge region P2 on both sides of the main region P1 along the first direction (X), that is, the first gate line gap structure 11 may extend along the second direction (Y), and the first gate line gap structure 11 is the long sides of two rectangles.

[0086] In some embodiments, the edge region P2 includes a first edge region P21 and a second edge region P22 located on both sides of the main region P1 in the second direction (Y). The first gate line gap structure 11 may be located only in the first edge region P21 and the second edge region P22, that is, the first gate line gap structure 11 extends along the first direction (X), and the first gate line gap structure 11 is the short sides of two rectangles. Specifically, the first edge region P21 has two first gate line gap structures 11 arranged along the first direction (X) and parallel to each other, and the second edge region P22 has two first gate line gap structures 11 arranged along the first direction (X) and parallel to each other.

[0087] In some embodiments, the first gate line gap structure 11 further includes a second dielectric layer 114 extending along the first direction (X), and the second conductive layer 112 surrounds the sidewall and bottom of the second dielectric layer 114. The second dielectric layer 114 can be made of the same material as the first dielectric layer 113.

[0088] In some embodiments, the first gate line gap structure 11 further includes a first isolation layer 115, which is located between the stacked structure 10 and the first conductive layer 111 to isolate the gate layer 102 from the first conductive layer 111. The material of the first isolation layer 115 includes but is not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.

[0089] like Figure 4 As shown, the semiconductor device 100 may include a plurality of memory blocks G arranged along a first direction (X), and the first gate line gap structure 11 close to the main region P1 may isolate adjacent memory blocks G.

[0090] See also Figure 5a and Figure 5b , Figure 5a is a schematic cross-sectional structure diagram of a semiconductor device provided in some embodiments of the present application, Figure 5b Some embodiments of the present application provide Figure 5a For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiment, and only the structures different from those in the above embodiment are described in detail in this embodiment.

[0091] The first gate line gap structure 11' in the semiconductor device 100' includes a first conductive layer 111', a second conductive layer 112', a first dielectric layer 113', a second dielectric layer 114' and a first isolation layer 115'. The bottom of the first conductive layer 111' is disconnected by the first dielectric layer 113', and the bottom of the second conductive layer 112' is disconnected by the second dielectric layer 114'. The first gate line gap structure 11' also includes a first partition structure 1110 and a second partition structure 1120. The first partition structure 1110 extends along the stacking direction (Z) and is located at the two ends of the first conductive layer 111' along the first direction (X).

[0092] The first partition structure 1110 and the first dielectric layer 113' partition the first conductive layer 111' into a first electrode 111a and a second electrode 111b. The first electrode 111a and the second electrode 111b are respectively located on both sides of the first dielectric layer 113' along the second direction (Y).

[0093] The second partition structure 1120 extends along the stacking direction (Z) and is located at both ends of the second conductive layer 112' along the first direction (X). The second partition structure 1120 and the second dielectric layer 114' partition the second conductive layer 112' into a third electrode 112a and a fourth electrode 112b, and the third electrode 112a and the fourth electrode 112b are respectively located on both sides of the second dielectric layer 114' along the second direction (Y). Therefore, the first electrode 111a and the third electrode 112a can form Figure 3 The second electrode 111 b and the fourth electrode 112 b can form a capacitor structure C0 in 3 .

[0094] See also Figure 6 and Figure 7 , Figure 6 is a partial cross-sectional structural diagram of a first gate line gap structure and a second gate line gap structure provided in some embodiments of the present application, Figure 7 : is a schematic diagram of a cross-sectional structure of a semiconductor device provided in some embodiments of the present application along the YZ plane direction. Figure 7 The middle left figure is a schematic diagram of the cross-sectional structure of the semiconductor device along the YZ plane at the second gate line gap. Figure 7 The right figure is a schematic diagram of the cross-sectional structure of the semiconductor device along the YZ plane at the first gate line gap.

[0095] The semiconductor device 200 includes a core region S1 and a non-core region S2 adjacent to the core region S1 in the first direction (X), and the first gate line gap structure 21 is located in the non-core region S2 and arranged along the first direction (X). The first gate line gap structure 21 includes a first conductive layer 211, a second conductive layer 212, a first dielectric layer 213, a second dielectric layer 214 and a first isolation layer 215.

[0096] In some embodiments, the core region S1 may be located on both sides of the non-core region S2 along the first direction (X), that is, the non-core region S2 is located in the middle of the core region S1.

[0097] In some embodiments, the semiconductor device 200 may include a body region and an edge region located at the periphery of the body region, and the body region may include the core region S1 and the non-core region S2 .

[0098] In some embodiments, the semiconductor device 200 further includes a second gate line gap structure 22 located in the core region S1, the second gate line gap structure 22 penetrates the stacked structure 20 of the core region S1 along the stacking direction (Z) and is arranged along the first direction (X). The stacked structure 20 includes an insulating layer 201 and a gate layer 202 that are alternately stacked.

[0099] like Figure 6 As shown, one end of the second gate line gap structure 22 along the first direction (X) is connected to the first gate line gap structure 21 , and the first gate line gap structure 21 and the second gate line gap structure 22 form a continuous gate line gap structure to divide different storage blocks.

[0100] It should be noted that Figure 6 Only a partial structure of the connection between the first gate line gap structure 21 and the second gate line gap structure 22 is shown. Specifically, the second gate line gap structure 22 includes a third conductive layer 221 and a second isolation layer 225, and the third conductive layer 221 is arranged along the first direction (X) and connected to the first conductive layer 211. The second isolation layer 225 surrounds the sidewall of the third conductive layer 221 and is connected to the first isolation layer 215. The first isolation layer 215 and the second isolation layer 225 together surround the sidewalls and bottom of the third conductive layer 221 and the first conductive layer 211.

[0101] In some embodiments, the width W1 of the second gate line gap structure 22 along the second direction (Y) is smaller than the width W2 of the first gate line gap structure 21 along the second direction (Y). Therefore, the first gate line gap structure 21 has more space for arranging two conductive layers.

[0102] In some embodiments, Figure 7As shown, the junction between the first isolation layer 215 and the gate layer 202 has a convex structure, and the junction between the second isolation layer 225 and the gate layer 202 has a convex structure.

[0103] In some embodiments, referring to FIG5 , a first partition structure may be provided at the connection between the first conductive layer 211 and the third conductive layer 221 to partition the first conductive layer 211 into a first electrode and a second electrode. A second partition structure may be provided at both ends of the second conductive layer 212 along the first direction (X) to partition the second conductive layer 212 into a third electrode and a fourth electrode.

[0104] The semiconductor device provided by the present application includes a stacking structure and a first gate line gap structure. The stacking structure includes an insulating layer and a gate layer that are alternately stacked, and the first gate line gap structure runs through the stacking structure along the stacking direction (Z) of the stacking structure, and extends along a first direction (X), and the first direction (X) and the stacking direction (Z) intersect each other. Wherein, the first gate line gap structure includes a first conductive layer, a second conductive layer and a first dielectric layer, the first conductive layer surrounds the side wall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer. Since the first gate line gap structure includes two mutually insulated conductive layers, the first conductive layer and the second conductive layer can form a capacitor structure as a part of the structure of some circuits. Therefore, the present application can make full use of the first gate line gap structure 21, improve the utilization rate of the first gate line gap structure 21, and reduce area waste. The first gate line gap structure can not only separate storage blocks, but also form a capacitor structure, and on the other hand, it can also save the area of ​​the corresponding peripheral circuit.

[0105] See also Figure 8 , Figure 8 is a schematic diagram of a method for preparing a semiconductor device provided in some embodiments of the present application. Figures 9a-9d , Figures 9a-9d 1 is a schematic diagram of the structure of the semiconductor device provided in some embodiments of the present application during the preparation process. This embodiment takes the preparation of the above-mentioned semiconductor device 100 as an example to illustrate the preparation method of the semiconductor device 100. Figure 1 , Figure 4 5 , the method for preparing the semiconductor device includes the following steps S1 - S2 .

[0106] Step S1: forming a stacked structure 10 , wherein the stacked structure 10 includes insulating layers 101 and gate layers 102 that are alternately stacked.

[0107] Step S2: forming a first gate line gap structure 11 that penetrates the stacking structure 10 along the stacking direction (Z) of the stacking structure 10, wherein the first gate line gap structure 11 extends along a first direction (X), and the first direction (X) intersects with the stacking direction (Z), and the first gate line gap structure 11 includes a first conductive layer 111, a second conductive layer 112 and a first dielectric layer 113, wherein the first conductive layer 111 surrounds the side wall of the second conductive layer 112, and the first dielectric layer 113 is located between the second conductive layer 112 and the first conductive layer 111.

[0108] For details, see Figure 9a , forming a first gate line gap 116 that penetrates the stack structure 10 along the stacking direction (Z) of the stack structure 10, the first gate line gap 116 is located in the first edge area P21 and the second edge area P22, and extends along the first direction (X).

[0109] See also Figures 9a-9d and Figure 1 A first isolation layer 115 , a first conductive layer 111 , a first dielectric layer 113 , a second conductive layer 112 and a second dielectric layer 114 are sequentially formed in the first gate line gap 116 .

[0110] You can refer to Figure 1 The method for preparing a semiconductor device may further include: forming a peripheral circuit 12 on one side of the stacked structure 10. The peripheral circuit 12 includes a charge pump circuit, and the plurality of first gate line gap structures 11 are connected to the charge pump circuit via connection contacts.

[0111] See also Figure 10a-10c , Figure 10a-10c 2 is a schematic diagram of the structure of the semiconductor device provided in some embodiments of the present application during the preparation process. This embodiment takes the preparation of the above-mentioned semiconductor device 200 as an example to illustrate the preparation method of the semiconductor device 200. Figure 6 and Figure 7 The method for preparing the semiconductor device includes steps S1-S2.

[0112] Step S1: forming a stacked structure 20 , wherein the stacked structure 20 includes insulating layers 201 and gate layers 202 that are alternately stacked.

[0113] Step S2: forming a first gate line gap structure 21 that penetrates the stacking structure 20 along the stacking direction (Z) of the stacking structure 20, wherein the first gate line gap structure 21 extends along a first direction (X), and the first direction (X) intersects with the stacking direction (Z), and the first gate line gap structure 21 includes a first conductive layer 211, a second conductive layer 212 and a first dielectric layer 213, wherein the first conductive layer 211 surrounds the side wall of the second conductive layer 212, and the first dielectric layer 213 is located between the second conductive layer 212 and the first conductive layer 211.

[0114] The method for manufacturing the semiconductor device further includes: forming a second gate line gap structure 22 of the stacked structure 20 that penetrates the core area S1 along the stacking direction (Z).

[0115] In some embodiments, the second gate line gap structure 22 may be formed together with the first gate line gap structure 21. The step of forming the first gate line gap structure 21 and the step of forming the second gate line gap structure 22 include the following steps.

[0116] 1) See Fig.10a and Figure 6 , forming a groove penetrating the stack structure 20 along the stacking direction (Z) of the stack structure 20, the groove including a first gate line gap T1 located in the non-core area S2 and a second gate line gap T2 located in the core area S1, and the width of the first gate line gap T1 in the second direction (Y) is greater than the width of the second gate line gap T2 in the second direction (Y).

[0117] in, Fig.10a The middle left figure is a schematic diagram of the cross-sectional structure of the second gate line gap T2 along the YZ plane. Fig.10a The right figure is a schematic diagram of the cross-sectional structure of the first gate line gap T1 along the YZ plane.

[0118] The method for preparing the semiconductor device further includes: forming a first storage channel structure CH1 and a second storage channel structure CH2 in the stacked structure 20 of the non-core region S2 and the core region S1, respectively. The first storage channel structure CH1 is adjacent to the first gate line gap T1, and the second storage channel structure CH2 is adjacent to the second gate line gap T2. Different from the second storage channel structure CH2, a lead-out contact CHC is also formed on the top of the first storage channel structure CH1.

[0119] 2) See Figure 10a-10cAn isolation layer, a conductive layer, a first dielectric layer 213, a second conductive layer 212 and a second dielectric layer 114 are sequentially formed in the groove, the isolation layer includes a first isolation layer 115 located in the first gate line gap T1 and a second isolation layer 225 located in the second gate line gap T2, the conductive layer includes a first conductive layer 211 located in the first gate line gap T1 and a third conductive layer 221 located in the second gate line gap T2, and the second isolation layer 225 and the third conductive layer 221 fill the second gate line gap T2.

[0120] The deposition process may be used to sequentially deposit an isolation layer, a conductive layer, a first dielectric layer 213, a second conductive layer 212, and a second dielectric layer 114 in the first gate line gap T1 and the second gate line gap T2. Since the width of the first gate line gap T1 is greater than the width of the second gate line gap T2, when the isolation layer and the conductive layer fill the second gate line gap T2, there is still space in the first gate line gap T1 to continue to deposit the first dielectric layer 213, the second conductive layer 212, and the second dielectric layer 114.

[0121] like Fig.10b As shown, the isolation layer and the conductive layer are also deposited on the stacked structure 20 of the core region S1 and the non-core region S2. Fig.10c As shown, the first dielectric layer 213 and the second conductive layer 212 are also deposited on the stacked structure 20 of the core region S1. Figure 7 As shown, the method for manufacturing the semiconductor device 00 may further include: removing the isolation layer, the conductive layer, the first dielectric layer 213 and the second conductive layer 212 located on the stacked structure 20 by using a chemical mechanical polishing process.

[0122] The method for preparing a semiconductor device provided in an embodiment of the present application forms two mutually insulated conductive layers in the first gate line gap T1, wherein the first conductive layer 211 and the second conductive layer 212 can form a capacitor structure as a part of the structure of some circuits. Therefore, the present application can make full use of the first gate line gap structure 21, improve the utilization rate of the first gate line gap structure 21, reduce area waste, and save some circuit area.

[0123] See also Fig.11 , Fig.11 3 is a schematic diagram of the structure of a storage system provided in some embodiments of the present application. The storage system 300 includes a semiconductor device 301 and a controller 302. The semiconductor device 301 may be a semiconductor device in any of the above embodiments, and the semiconductor device 301 may be prepared by the method for preparing a semiconductor device in the above embodiments. The controller 302 is electrically connected to the semiconductor device 301 and is used to control the semiconductor device 301 to store data. The semiconductor device 301 may perform an operation of storing data based on the control of the controller 302.

[0124] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0125] The semiconductor device 301 may include a stacked structure and a first gate line gap structure. The stacked structure includes alternately stacked insulating layers and gate layers, the first gate line gap structure penetrates the stacked structure along the stacking direction of the stacked structure and extends along a first direction, and the first direction intersects the stacking direction. The first gate line gap structure includes a first conductive layer, a second conductive layer and a first dielectric layer, the first conductive layer surrounds the side wall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.

[0126] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A stacked structure comprising alternately stacked insulating layers and gate layers; A first gate line gap structure, which penetrates the stack structure along a stacking direction of the stack structure and extends along a first direction, wherein the first direction intersects the stacking direction; The first gate line gap structure includes a first conductive layer, a second conductive layer and a first dielectric layer, the first conductive layer surrounds the side wall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.

2. The semiconductor device according to claim 1, wherein: The first gate line gap structure further includes: The second dielectric layer extends along the first direction, and the second conductive layer surrounds the sidewall of the second dielectric layer.

3. The semiconductor device according to claim 2, characterized in that The first gate line gap structure further includes: A first isolation layer is located between the stacked structure and the first conductive layer.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A first partition structure extending along the stacking direction and located at two ends of the first conductive layer along the first direction; The first partition structure partitions the first conductive layer into a first electrode and a second electrode, the first electrode and the second electrode are respectively located on both sides of the first dielectric layer along a second direction, and the first direction, the second direction and the stacking direction intersect each other.

5. The semiconductor device according to claim 2, wherein: The semiconductor device further comprises: A second partition structure extending along the stacking direction and located at two ends of the second conductive layer along the first direction; The second partition structure partitions the second conductive layer into a third electrode and a fourth electrode, the third electrode and the fourth electrode are respectively located on both sides of the second dielectric layer along a second direction, and the first direction, the second direction and the stacking direction intersect each other.

6. The semiconductor device according to claim 1, wherein: The semiconductor device comprises a main body region and an edge region located at the periphery of the main body region, wherein the edge region comprises a first edge region and a second edge region located at both sides of the main body region in a second direction, and the first direction, the second direction and the stacking direction intersect each other; The first gate line gap structure is located in the first edge region and the second edge region.

7. The semiconductor device according to claim 6, characterized in that The first edge region has two first gate line gap structures arranged along the first direction and parallel to each other, and the second edge region has two first gate line gap structures arranged along the first direction and parallel to each other.

8. The semiconductor device according to claim 3, characterized in that The semiconductor device includes a core region and a non-core region adjacent to the core region in the first direction, and the first gate line gap structure is located in the non-core region and arranged along the first direction.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device further comprises: The second gate line gap structure penetrates the stacking structure of the core area along the stacking direction and is arranged along the first direction, and one end of the second gate line gap structure along the first direction is connected to the first gate line gap structure.

10. The semiconductor device according to claim 9, characterized in that The second gate line gap structure comprises: a third conductive layer, arranged along the first direction and connected to the first conductive layer; The second isolation layer surrounds the side wall of the third conductive layer and is connected to the first isolation layer.

11. The semiconductor device according to claim 9, characterized in that The width of the second gate line gap structure along the second direction is smaller than the width of the first gate line gap structure along the second direction, and the first direction, the second direction and the stacking direction intersect each other.

12. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The peripheral circuit is located at one side of the stack structure, and the peripheral circuit includes a charge pump circuit. The plurality of first gate line gap structures are connected to the charge pump circuit via connection contacts.

13. The semiconductor device according to claim 12, characterized in that A plurality of the first conductive layers in a plurality of the first gate line gap structures are connected in parallel, and a plurality of the second conductive layers in a plurality of the first gate line gap structures are connected in parallel.

14. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: forming a stacked structure, the stacked structure comprising insulating layers and gate layers stacked alternately; A first gate line gap structure is formed that penetrates the stacking structure along the stacking direction of the stacking structure, wherein the first gate line gap structure extends along a first direction, the first direction intersects with the stacking direction, the first gate line gap structure includes a first conductive layer, a second conductive layer and a first dielectric layer, the first conductive layer surrounds the side wall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: The semiconductor device comprises a main body region and an edge region located at the periphery of the main body region, wherein the edge region comprises a first edge region and a second edge region located at both sides of the main body region in a second direction, and the first direction, the second direction and the stacking direction intersect each other; The step of forming a first gate line gap structure penetrating the stack structure along a stacking direction of the stack structure comprises: Forming a first gate line gap penetrating the stack structure along a stacking direction of the stack structure, wherein the first gate line gap is located in the first edge region and the second edge region and extends along the first direction; A first isolation layer, a first conductive layer, a first dielectric layer, a second conductive layer and a second dielectric layer are sequentially formed in the first gate line gap.

16. The method for preparing a semiconductor device according to claim 14, characterized in that: The semiconductor device comprises a main body region and an edge region located at the periphery of the main body region, the main body region comprises a core region and a non-core region adjacent to the core region in the first direction, and the first gate line gap structure is located in the non-core region; The method for preparing the semiconductor device further includes: A second gate line gap structure of the stacking structure penetrating the core area along the stacking direction is formed.

17. The method for preparing a semiconductor device according to claim 16, characterized in that: The step of forming the first gate line gap structure and the step of forming the second gate line gap structure include: Forming a groove penetrating the stacked structure along a stacking direction of the stacked structure, the groove comprising a first gate line gap located in the non-core area and a second gate line gap located in the core area, and the width of the first gate line gap in the second direction is greater than the width of the second gate line gap in the second direction, and the first direction, the second direction and the stacking direction intersect each other; An isolation layer, a conductive layer, a first dielectric layer, a second conductive layer and a second dielectric layer are sequentially formed in the groove, the isolation layer includes a first isolation layer located in the first gate line gap and a second isolation layer located in the second gate line gap, the conductive layer includes a first conductive layer located in the first gate line gap and a third conductive layer located in the second gate line gap, and the second isolation layer and the third conductive layer fill the second gate line gap.

18. The method for preparing a semiconductor device according to claim 14, characterized in that: The method for preparing the semiconductor device further includes: A peripheral circuit is formed on one side of the stack structure, wherein the peripheral circuit includes a charge pump circuit, and a plurality of the first gate line gap structures are connected to the charge pump circuit via connection contacts.

19. A storage system, characterized in that: include: The semiconductor device according to any one of claims 1 to 13; A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

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