Semiconductor memory device

Abstract

The invention provides a semiconductor memory device that suppresses a decrease in reliability. The device is provided with: a semiconductor substrate including a first region, a second region, and a third region, which are respectively a source region or a drain region, and which are arranged apart from each other in order in a first direction in an element region; a first conductor layer having a first opening; a second conductor layer having a second opening and arranged apart from the first conductor layer in the first direction; a first contact connected to the first region and passing through the first opening; a second contact connected to the third region and passing through the second opening; and a third conductor layer and a fourth conductor layer which are provided between the first conductor layer and the second conductor layer, and are arranged in the first direction in order to be separated from each other. The third conductor layer is disposed away from the first conductor layer. The fourth conductor layer is disposed away from the second conductor layer. The first conductor layer and the first contact are connected to each other so as to have substantially the same potential. The second conductor layer and the second contact are connected to each other so as to have substantially the same potential.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-140398 (filing date: August 30, 2023). This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor memory device. Background Art

[0004] As a semiconductor memory device capable of storing data in a nonvolatile manner, a NAND (Not-AND) type flash memory is known. In a semiconductor memory device such as a NAND type flash memory, a three-dimensional memory structure is adopted for high integration and large capacity. Summary of the invention

[0005] The present invention provides a semiconductor storage device which suppresses the reduction of reliability.

[0006] The semiconductor storage device of the embodiment comprises: a semiconductor substrate including a device region, and a first region, a second region, and a third region which are source regions or drain regions and are arranged in sequence along a first direction away from each other in the device region; a first conductive layer, which is arranged above the device region and has a first opening; a second conductive layer, which is arranged above the device region and has a second opening and is arranged away from the first conductive layer in the first direction; a first contact, which is connected to the first region through the first opening; a second contact, which is connected to the third region through the second opening. An opening portion; a first storage cell connected to a first contact; a second storage cell connected to a second contact; and a third conductor layer and a fourth conductor layer, which are arranged between the first conductor layer and the second conductor layer above the element region and are arranged in sequence away from each other in a first direction; the third conductor layer is arranged away from the first conductor layer; the fourth conductor layer is arranged away from the second conductor layer; the first conductor layer and the first contact are connected to each other in a manner that they have approximately the same potential; the second conductor layer and the second contact are connected to each other in a manner that they have approximately the same potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment.

[0008] Figure 2 This is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device according to the embodiment.

[0009] Figure 3is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor memory device according to an embodiment.

[0010] Figure 4 This is a circuit diagram showing an example of the configuration of a row decoder module, a driver module, and a memory cell array of a semiconductor memory device according to an embodiment.

[0011] Figure 5 This is a circuit diagram showing an example of the configuration of a block decoder included in the semiconductor storage device according to the embodiment.

[0012] Figure 6 FIG. 1 is a top view showing an example of a planar structure of a row decoder module of the semiconductor memory device according to the embodiment.

[0013] Figure 7 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the embodiment.

[0014] Figure 8 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to an embodiment. Figure 7 A cross-sectional view taken along line VIII-VIII.

[0015] Fig. 9 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to an embodiment. Figure 7 A cross-sectional view taken along line IX-IX.

[0016] Fig.10 This is a cross-sectional view showing an example of a structure of a transfer transistor included in the semiconductor memory device according to the embodiment during manufacturing.

[0017] Fig.11 This is a cross-sectional view showing an example of a structure of a transfer transistor included in the semiconductor memory device according to the embodiment during manufacturing.

[0018] Fig.12 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the first variation.

[0019] Fig.13 This is a graph showing an example of the surface breakdown voltage of the transfer transistor according to the first variation.

[0020] Fig.14A FIG. 1 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a first variation. Fig.12 A cross-sectional view of line XIV-XIV.

[0021] Fig. 14BFIG. 1 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a first variation. Fig.12 A cross-sectional view of line XIV-XIV.

[0022] Fig. 14C yes Fig.14A An enlarged sectional view of the single-dot dash line frame.

[0023] Fig.14D yes Fig. 14B An enlarged sectional view of the single-dot dash line frame.

[0024] Fig.15 This is a graph showing an example of the on-current of the transfer transistor according to the first variation.

[0025] Fig.16 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the second variation.

[0026] Fig.17 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a second variation. Fig.16 A cross-sectional view taken along line XVII-XVII.

[0027] Fig.18 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a second variation. Fig.16 A cross-sectional view taken along line XVIII-XVIII.

[0028] Fig.19 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the third variation.

[0029] Fig. 20 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to a third variation. Fig.19 Cross-sectional view of line XX-XX.

[0030] Fig.21 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the fourth variation.

[0031] Fig. 22 is an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to a fourth variation, along the Fig.21 A cross-sectional view of line XXII-XXII.

[0032] Fig.23 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the fifth variation.

[0033] Fig.24 is an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to a fifth variation, along Fig.23 A cross-sectional view of line XXIV-XXIV.

[0034] Fig.25 It is a top view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to a sixth variation. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments will be described with reference to the drawings. Dimensions and ratios in the drawings are not necessarily the same as those in actual objects.

[0036] In the following description, components having substantially the same function and configuration are denoted by the same reference numerals. In order to distinguish between components having the same configuration, different letters or numbers may be added to the end of the same reference numerals.

[0037] 1. Implementation Method

[0038] 1.1 Composition

[0039] 1.1.1 Memory System

[0040] Figure 1 This is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment.

[0041] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2 .

[0042] The memory system 3 is, for example, an SD TM The memory system 3 is configured to be connected to an external host device (not shown).

[0043] The memory controller 2 is composed of an integrated circuit such as a SoC (system-on-a-chip). The memory controller 2 controls the semiconductor memory device 1 based on a request from the host device. Specifically, for example, the memory controller 2 writes data requested to be written from the host device to the semiconductor memory device 1. In addition, the memory controller 2 reads data requested to be read from the host device from the semiconductor memory device 1 and sends it to the host device.

[0044] The semiconductor storage device 1 is, for example, a NAND flash memory. The semiconductor storage device 1 stores data in a nonvolatile manner. The semiconductor storage device 1 is connected to a memory controller 2 via a NAND bus B.

[0045] The NAND bus B is, for example, a bus based on an SDR (single data rate) interface, a Toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0046] 1.1.2 Semiconductor storage devices

[0047] Next, refer to Figure 1 The block diagram shown in FIG. 1 illustrates the internal structure of the semiconductor memory device 1 of the embodiment. The semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0048] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The block BLK is a collection of a plurality of memory cell transistors that can store data non-volatilely, and is used, for example, as a unit for deleting data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. For example, one memory cell transistor is associated with one bit line and one word line.

[0049] The command register 11 holds the command CMD received by the semiconductor storage device 1 from the memory controller 2. The command CMD includes, for example, a command for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like.

[0050] The address register 12 holds the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a page address PA, a block address BA, and a column address CA. For example, the page address PA, the block address BA, and the column address CA are used to select a word line, a block BLK, and a bit line, respectively.

[0051] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 based on the command CMD stored in the command register 11 to perform read, write, and erase operations.

[0052] The driver module 14 generates voltages used in read operations, write operations, and erase operations, etc. Then, based on, for example, the page address PA held in the address register 12 , the driver module 14 applies the generated voltages to the signal lines corresponding to the selected word lines.

[0053] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0054] The sense amplifier module 16 transmits data DAT between the memory controller 2 and the memory cell array 10. The data DAT includes write data and read data. More specifically, the sense amplifier module 16 transmits the write data received from the memory controller 2 to the memory cell array 10 in a write operation. In addition, the sense amplifier module 16 performs a determination of the data stored in the memory cell transistor based on the voltage of the bit line in a read operation. Then, the sense amplifier module 16 transmits the result of the determination to the memory controller 2 as read data.

[0055] 1.1.3 Circuit structure of storage cell array

[0056] Figure 2 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a semiconductor memory device according to an embodiment. Figure 2 In FIG. 1 , one block BLK among a plurality of blocks BLK included in the memory cell array 10 is shown. Figure 2 In the example shown, the block BLK includes, for example, five string units SU0 to SU4.

[0057] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer greater than 1). Each NAND string NS includes, for example, storage cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each of the storage cell transistors MT0 to MT7 includes a control gate and a charge storage layer to hold data in a non-volatile manner. Each of the selection transistors ST1 and ST2 is used to select the string unit SU during various operations. In addition, in the following description, the storage cell transistors MT0 to MT7 are also referred to as storage cell transistors MT.

[0058] In each NAND string NS, the storage cell transistors MT0 to MT7 are connected in series. One end of the selection transistor ST1 is connected to the associated bit line BL, and the other end of the selection transistor ST1 is connected to one end of the storage cell transistors MT0 to MT7 connected in series. One end of the selection transistor ST2 is connected to the other end of the storage cell transistors MT0 to MT7 connected in series. The other end of the selection transistor ST2 is connected to the source line SL.

[0059] In the same block BLK, the control gates of the storage cell transistors MT0 to MT7 are respectively connected to the word lines WL0 to WL7. The gates of the selection transistors ST1 in the string units SU0 to SU4 are respectively connected to the selection gate lines SGD0 to SGD4. In contrast, the gates of the multiple selection transistors ST2 are commonly connected to the selection gate line SGS. However, this is not limited to this, and the gates of the multiple selection transistors ST2 can also be respectively connected to multiple different selection gate lines for each string unit SU. In addition, in the following description, when the word lines WL0 to WL7 are not distinguished, they are referred to as word lines WL. In addition, when the selection gate lines SGD0 to SGD4 are not distinguished, they are referred to as selection gate lines SGD.

[0060] Each of the bit lines BL0 to BLm connects one NAND string NS included in each string unit SU in common among a plurality of blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared among a plurality of blocks BLK, for example.

[0061] A collection of multiple storage cell transistors MT connected to a common word line WL in one string unit SU is called a cell unit CU, for example. For example, the storage capacity of a cell unit CU including storage cell transistors MT each storing 1 bit of data is defined as "1 page of data". The cell unit CU may have a storage capacity of more than 2 pages of data depending on the number of bits of data stored in the storage cell transistors MT.

[0062] In addition, the circuit structure of the memory cell array 10 of the semiconductor memory device 1 of the embodiment is not limited to the structure described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and the number of selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0063] 1.1.4 Cross-sectional structure of semiconductor storage device

[0064] Next, use Figure 3 A cross-sectional structure of semiconductor memory device 1 according to the embodiment will be described. Figure 3 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor memory device according to an embodiment. Figure 3] The cross-sectional structure of two string units SU among five string units SU included in one block BLK is shown.

[0065] In the drawings referred to below, the X direction corresponds to the extending direction of the word lines WL, the Y direction corresponds to the extending direction of the bit lines BL, and the Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate forming the semiconductor memory device 1.

[0066] The memory cell array 10 includes conductive layers 21, 22, 24, and 25 disposed above a semiconductor substrate 20, a plurality of conductive layers 23, and a plurality of memory pillars MP ( Figure 3 In the following description, the direction in which the memory cell array 10 is disposed relative to the semiconductor substrate 20 is referred to as the upward direction. In addition, the opposite direction is referred to as the downward direction.

[0067] An insulator layer 30 is provided on the semiconductor substrate 20. The insulator layer 30 includes, for example, a peripheral circuit PERI corresponding to the row decoder module 15 or the like.

[0068] The conductor layer 21 is stacked on the insulating layer 30. The conductor layer 21 is formed into a plate shape extending along the XY plane, for example. The conductor layer 21 is used as the source line SL. The conductor layer 21 is composed of a conductive material, for example, an N-type semiconductor to which impurities are added, or a metal material such as a stacked film of titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), tantalum nitride (TaN) and tantalum (Ta), titanium (Ti), titanium nitride (TiN) and tungsten (W), and a stacked film of titanium nitride (TiN) and tungsten silicide (WSi). In addition, the conductor layer 21 may also be a stacked structure of semiconductors and metal materials such as a stacked film of titanium nitride (TiN), tungsten silicide (WSi) and polysilicon.

[0069] An insulating layer 31 is provided on the conductive layer 21. A conductive layer 22 is stacked on the insulating layer 31. The conductive layer 22 is formed in a plate shape extending along the XY plane, for example. The conductive layer 22 is used as a selection gate line SGS. The conductive layer 22 contains, for example, tungsten (W).

[0070] An insulator layer 32 is provided on the conductor layer 22. On the insulator layer 32, eight conductor layers 23 and eight insulator layers 33 are stacked in order of conductor layer 23, insulator layer 33, ..., conductor layer 23, insulator layer 33. The conductor layer 23 is formed, for example, in a plate shape extending along the XY plane. The eight stacked conductor layers 23 are used as word lines WL0 to WL7 in order from the conductor layer 21 side. The conductor layer 23 contains, for example, tungsten (W).

[0071] The conductor layer 24 and the insulator layer 34 are sequentially stacked on the uppermost insulating layer 33. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane. The stacked conductor layer 24 is used as a selection gate line SGD. The conductor layer 24 contains, for example, tungsten (W). The conductor layer 24 is electrically separated to each string unit SU by, for example, a slit SHE.

[0072] An insulating layer 34 is provided on the conductive layer 24. A conductive layer 25 is provided on the insulating layer 34. The conductive layer 25 is formed in a linear shape extending in the Y direction, for example, and functions as a bit line BL. The conductive layer 25 includes, for example, copper (Cu).

[0073] The memory pillars MP extend in the Z direction below the conductor layer 25 and penetrate the conductor layers 22 and 24 and the conductor layers 23. The bottom of each memory pillar MP is located below the insulating layer 31 and is in contact with the conductor layer 21.

[0074] Each of the memory pillars MP includes, for example, a core member 35 , a semiconductor film 36 , a tunnel insulating film 37 , a charge storage film 38 , a bulk insulating film 39 , and a semiconductor portion 26 .

[0075] The core member 35 is extended in, for example, the Z direction. The upper end of the core member 35 is included in a layer above the conductor layer 24, and the lower end of the core member 35 is included in a layer below the conductor layer 22. The core member 35 is made of, for example, silicon oxide (SiO2).

[0076] The semiconductor film 36 is provided to cover the side surface and the lower surface of the core member 35. The upper end of the semiconductor film 36 reaches the same position as the upper end of the core member 35. The lower end of the semiconductor film 36 is in contact with the conductor layer 21. The semiconductor film 36 includes, for example, polycrystalline silicon.

[0077] The tunnel insulating film 37 covers the side surfaces of the semiconductor film 36. The tunnel insulating film 37 includes, for example, silicon oxide (SiO2).

[0078] The charge storage film 38 covers the side surfaces of the tunnel insulating film 37. The charge storage film 38 includes, for example, an insulator capable of storing charges. The insulator is, for example, silicon nitride (SiN).

[0079] The bulk insulating film 39 covers the side surfaces of the charge storage film 38. The bulk insulating film 39 includes, for example, silicon oxide (SiO2).

[0080] The semiconductor portion 26 is in contact with the semiconductor film 36 and is provided so as to cover the upper end of the core member 35. The conductor layer 27 functioning as a columnar contact CV is provided on the upper end of the semiconductor portion 26. The upper end of the conductor layer 27 is in contact with the conductor layer 25.

[0081] In the structure of the memory column MP described above, the portion where the memory column MP intersects with the conductor layer 22 functions as the selection transistor ST2. In addition, the portion where the memory column MP intersects with the conductor layer 23 functions as the storage cell transistor MT. In addition, the portion where the memory column MP intersects with the conductor layer 24 functions as the selection transistor ST1. In addition, the semiconductor film 36 functions as the channels of the storage cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. In addition, the charge storage film 38 functions as the charge storage layer of the storage cell transistor MT.

[0082] 1.1.5 Line Decoder Module

[0083] Next, a configuration example of the row decoder block 15 included in the peripheral circuit PERI will be described.

[0084] 1.1.5.1 Overall composition

[0085] use Figure 4 The overall structure of the row decoder module 15 will be described. Figure 4 This is a circuit diagram for explaining an example of the configuration of a row decoder module, a driver module, and a memory cell array of a semiconductor memory device according to an embodiment.

[0086] The row decoder module 15 includes row decoders RD0-RDn. The row decoders RD0-RDn are used to select the block BLK. The row decoders RD0-RDn are associated with the blocks BLK0-BLKn respectively.

[0087] Each row decoder RD includes, for example, a block decoder BD, and transmission transistors TW0 to TW7, TS, and TD0 to TD4. The transmission transistors TW0 to TW7, TS, and TD0 to TD4 are, for example, high-voltage N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The transmission transistors TW0 to TW7 are associated with word lines WL0 to WL7, respectively. In addition, in the following description, when the transmission transistors TW0 to TW7 are not distinguished, they are simply referred to as transmission transistors TW. The transmission transistors TS and TD0 to TD4 are associated with selection gate lines SGS and SGD0 to SGD4, respectively. In addition, in the following description, when the transmission transistors TD0 to TD4 are not distinguished, they are simply referred to as transmission transistors TD. In addition, the high-voltage MOSFET is a MOSFET having a physical film thickness of a gate insulating film of 10 nm or more. The gate-source voltage of the high-voltage N-channel MOSFET can be, for example, a voltage of 10 V or more.

[0088] The block decoder BD decodes the block address BA. For example, based on the result of the decoding, the block decoder BD applies a voltage of an "H (High)" level and a voltage of an "L (Low)" level to the transfer gate line BLKSEL.

[0089] Transfer transistors TW0 to TW7, TS and TD0 to TD4 are connected to blocks BLK corresponding to the driver module 14 via signal lines CG0 to CG7, CGS and CGD0 to CGD4, respectively. In the following description, signal lines CG0 to CG7, CGS and CGD0 to CGD4 are simply referred to as signal lines CG when not being distinguished.

[0090] More specifically, in each row decoder RD, the gate of the transfer transistor TD is connected to the transfer gate line BLKSEL. The first end of each transfer transistor TD is connected to the driver module 14 via the corresponding signal line CG among the signal lines CGD0 to CGD4. The second end of the transfer transistor TD is connected to the corresponding selection gate line SGD among the selection gate lines SGD0 to SGD4.

[0091] The gate of each transfer transistor TW is connected to the transfer gate line BLKSEL. The first end of each transfer transistor TW is connected to the driver module 14 via the corresponding signal line CG among the signal lines CG0 to CG7. The second end of each transfer transistor TW is connected to the corresponding word line WL among the word lines WL0 to WL7.

[0092] The gate of the transfer transistor TS is connected to the transfer gate line BLKSEL. The first end of the transfer transistor TS is connected to the driver module 14 via the signal line CGS. The second end of the transfer transistor TS is connected to the selection gate line SGS.

[0093] When a voltage of "H" level is applied to the transmission gate line BLKSEL, the transmission transistors TW, TS and TD are turned on. As a result, the voltages of the signal lines CG0 to CG7, CGS and CGD0 to CGD4 are respectively transmitted to the word lines WL0 to WL7, the selection gate line SGS and the selection gate lines SGD0 to SGD4 via the transmission transistors TW0 to TW7, TS and TD0 to TD4. When a voltage of "L" level is applied to the transmission gate line BLKSEL, the transmission transistors TW, TS and TD are turned off.

[0094] 1.1.5.2 Block Decoder

[0095] use Figure 5 The configuration of the block decoder BD included in each row decoder RD will be described. Figure 5 This is a circuit diagram for explaining an example of the configuration of a block decoder included in the semiconductor memory device according to the embodiment.

[0096] like Figure 5 As shown, the block decoder BD includes a logic circuit LC, a logical product circuit AND, inverters INV1 and INV2, and transistors T1, T2, T3, and T4.

[0097] Transistors T1, T2 and T4 are N-channel MOSFETs. Transistor T3 is a P-channel MOSFET. Transistors T2, T3 and T4 are high-voltage MOSFETs whose physical thickness of gate insulating films is thicker than that of transistor T1. The physical thickness of the gate insulating film of each of transistors T2, T3 and T4 is, for example, 10 nm or more. In addition, the gate-source voltage of each of transistors T2, T3 and T4 may be, for example, a voltage of 10 V or more. On the other hand, the physical thickness of the gate insulating film of transistor T1 is, for example, thinner than 10 nm. In addition, the gate-source voltage of transistor T1 is, for example, a voltage lower than 10 V.

[0098] The block address BA is input to the first end of the logic circuit LC from the address register 12. For example, the power supply voltage VDD is applied to the second end of the logic circuit LC. The logic circuit LC is driven by the power supply voltage VDD. A signal based on the block address BA is output from the third end of the logic circuit LC. In the case where the block address BA input to the logic circuit LC is the block address BA assigned to the block BLK corresponding to the logic circuit LC, a signal of "H" level is output from the second end of the logic circuit LC. In the case where the block address BA input to the logic circuit LC is not the block address BA assigned to the block BLK corresponding to the logic circuit LC, a signal of "L" level is output from the second end of the logic circuit LC.

[0099] The first terminal of the logical product circuit AND is connected to the third terminal of the logic circuit LC. For example, the power supply voltage VDD is applied to the second terminal of the logical product circuit AND. The logical product circuit AND is driven by the power supply voltage VDD. A signal based on the logical product operation of the signal output from the third terminal of the logic circuit LC is output from the third terminal of the logical product circuit AND.

[0100] The first terminal of the inverter INV1 is connected to the third terminal of the logical product circuit AND. For example, the power supply voltage VDD is applied to the second terminal of the inverter INV1. The inverter INV1 is driven by the power supply voltage VDD. The third terminal of the inverter INV1 is connected to the node N1. The inversion signal of the signal output from the third terminal of the logical product circuit AND is output from the third terminal of the inverter INV1.

[0101] The first terminal of the inverter INV2 is connected to the node N1. For example, the power supply voltage VDD is applied to the second terminal of the inverter INV2. The inverter INV2 is driven by the power supply voltage VDD. The third terminal of the inverter INV2 outputs an inverted signal of the signal output from the third terminal of the inverter INV1.

[0102] The first terminal of the transistor T1 is connected to the third terminal of the inverter INV2. The power supply voltage VDD is applied to the gate of the transistor T1. The second terminal of the transistor T1 is connected to the transistor T2.

[0103] The first terminal of the transistor T2 is connected to the second terminal of the transistor T1. The power supply voltage VDD is applied to the gate of the transistor T2. The second terminal of the transistor T2 is connected to the transfer gate line BLKSEL.

[0104] The first terminal of the transistor T3 is connected to the transfer gate line BLKSEL. The gate of the transistor T3 is connected to the node N1. The second terminal of the transistor T3 is connected to the transistor T4 together with the back gate of the transistor T3.

[0105] The first terminal of the transistor T4 is connected to the second terminal of the transistor T3 and the back gate of the transistor T3. The gate of the transistor T4 is connected to the transmission gate line BLKSEL. The second terminal of the transistor T4 is connected to the node VRDEC. A high voltage is applied to the node VRDEC, and the high voltage is set to enable the transmission transistors TW, TS and TD to transmit the voltage supplied to the corresponding signal line CG to the word line WL, the selection gate line SGS and the selection gate line SGD respectively by being transmitted to the transmission gate line BLKSEL through the transistors T3 and T4.

[0106] According to the above configuration, the block decoder BD outputs a signal of "H" level to the transfer gate line BLKSEL when the corresponding block BLK is selected, and outputs a signal of "L" level to the transfer gate line BLKSEL when the corresponding block BLK is not selected.

[0107] 1.1.5.3 Planar Structure of the Line Decoder Module

[0108] use Figure 6 The planar structure of the row decoder module 15 of the semiconductor memory device 1 according to the embodiment will be described. Figure 6 1 is a top view showing an example of a planar structure of a row decoder module of a semiconductor memory device according to an embodiment. In addition, in the following description, the transmission transistors TW0 to TW7, TS, and TD0 to TD4 included in the row decoder RDi, and the block decoder BD are also referred to as transmission transistors TW0_i to TW7_i, TS_i, and TD0_i to TD4_i, and block decoder BD_i, respectively. i is an integer greater than 0 and less than n.

[0109] The row decoder module 15 is disposed on the semiconductor substrate 20 .

[0110] The semiconductor substrate 20 is provided with an N-type well region 40. The N-type well region 40 is a region containing N-type impurities. The N-type well region 40 is provided in, for example, a rectangular region.

[0111] A P-type well region 41 is provided in the N-type well region 40. The P-type well region 41 is a region containing P-type impurities. The P-type well region 41 is provided in, for example, a rectangular region.

[0112] The set of row decoders RD(2j) and RD(2j+1) is provided in, for example, a rectangular region. j is an integer greater than or equal to 0 and less than or equal to (n-1) / 2.

[0113] The group of row decoders RD0 and RD1, the group of row decoders RD2 and RD3, the group of row decoders RD4 and RD5, ... are sequentially arranged, for example, along the Y direction.

[0114] In the group of row decoders RD(2j) and RD(2j+1), transfer transistors TS_(2j) and TS_(2j+1), TW0_(2j) and TW0_(2j+1),…, TW7_(2j) and TW7_(2j+1), TD0_(2j) and TD0_(2j+1)…, and TD4_(2j) and TD4_(2j+1) are respectively arranged in, for example, a P-type well region 41.

[0115] In the set of row decoders RD( 2 j ) and RD( 2 j+1 ), block decoders BD_( 2 j ) and BD_( 2 j+1 ) are provided, for example, outside the N-type well region 40 .

[0116] In addition, a plurality of transfer transistors TW_(2j) and TW_(2j+1), TS_(2j) and TS_(2j+1), and TD_(2j) and TD_(2j+1) are provided in a matrix arrayed in the X and Y directions, for example.

[0117] 1.1.5.4 Transmission transistor

[0118] The configurations of the transfer transistors TW, TS, and TD included in the semiconductor memory device 1 according to the embodiment will be described.

[0119] (Plane structure)

[0120] use Figure 7 The planar structure of the transfer transistors TW, TS, and TD will be described. Figure 7 FIG. 1 is a top view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to an embodiment. Figure 7 In the example shown, the main Figure 6 The illustrated configuration includes a planar structure of transfer transistors TW0_0 and TW0_1. Figure 7 1, a portion of the transfer transistor TW1_0, a portion of the transfer transistor TW1_1, a portion of the transfer transistor TW0_2, and a portion of the transfer transistor TW1_2 are simultaneously shown. The structure of the group of transfer transistors TW_(2j) and TW_(2j+1), the structure of the group of TS_(2j) and TS_(2j+1), and the structure of the group of TD_(2j) and TD_(2j+1) are substantially the same as each other. The following mainly describes the structure of the transfer transistors TW0_0 and TW0_1.

[0121] The P-type well region 41 (element region) is electrically divided into P-type well regions 41A and 41B by, for example, an insulator layer 50 that functions as an element isolation region. In a plan view, the insulator layer 50 surrounds the P-type well region 41B. The P-type well region 41B is Figure 7 The P-type well region 41A is provided in an area not shown outside the area surrounded by the insulating layer 50. The insulating layer 50 is provided in a grid shape, for example, to separate the groups of the plurality of transfer transistors TW, TS, and TD arranged in a matrix.

[0122] In the P-type well region 41B, the transfer transistors TW0_0 and TW0_1 are arranged in sequence along the Y direction. In the following description, the end of the transfer transistors TW0_0 and TW0_1 where the transfer transistor TW0_0 is provided is referred to as one end. In addition, the end of the transfer transistors TW0_0 and TW0_1 where the transfer transistor TW0_1 is provided is referred to as the other end.

[0123] In the P-type well region 41B, N – Impurity diffusion regions 42, 43 and 44. – The impurity diffusion regions 42 , 43 , and 44 are N-type impurity diffusion regions such as phosphorus (P) and arsenic (As).

[0124] In N – The impurity diffusion region 42 is provided with an electrode 201. – The impurity diffusion region 43 is provided with an electrode 202. – The impurity diffusion region 44 is provided with an electrode 203. The region where the electrodes 201, 202, and 203 are provided is Figure 7 The area enclosed by the dotted line.

[0125] The electrode 201 functions as the first terminal of the transfer transistor TW0_0. The electrode 203 functions as the first terminal of the transfer transistor TW0_1. The electrode 202 functions as the second terminal of the transfer transistor TW0_0 and the second terminal of the transfer transistor TW0_1. In this way, the transfer transistors TW0_0 and TW0_1 share the electrode 202.

[0126] A contact 61 is connected to the electrode 201. The contact 61 is connected to the word line WL0 of the block BLK0. A contact 62 is connected to the electrode 202. The contact 62 is connected to the signal line CG0. A contact 63 is connected to the electrode 203. The contact 63 is connected to the word line WL0 of the block BLK1. Figure 7 In the example shown, the number of contact points provided at each electrode 201, 202, and 203 is one, but the present invention is not limited thereto. The number of contact points provided at each electrode 201, 202, and 203 may be two or more.

[0127] Above the P-type well region 41B, five electrodes 101 , 105 , 107 , 106 , and 102 are provided in order from one end to the other end along the Y direction via a gate insulating film.

[0128] The electrode 101 has an opening portion that is opened so as to surround the contact 61. The opening portion corresponds to the region where the electrode 201 is provided. In addition, a side surface of the outer periphery of the electrode 101 and a side surface of the inner periphery of the electrode 101 corresponding to the opening portion are provided. Figure 7 Side walls not shown in the figure.

[0129] In addition, the electrode 101 is connected to the contact point 67. The contact point 67 is electrically connected to the contact point 61 via the conductor layer 66. Thus, the electrode 101 is connected to the contact point 61 so as to have substantially the same potential as that of the contact point 61.

[0130] The electrode 102 has an opening portion that is opened so as to surround the contact 63. The opening portion corresponds to the region where the electrode 203 is provided. In addition, a side surface of the outer periphery of the electrode 102 and a side surface of the inner periphery of the electrode 102 corresponding to the opening portion are provided. Figure 7 Side walls not shown in the figure.

[0131] In addition, the electrode 102 is connected to the contact point 68. The contact point 68 is electrically connected to the contact point 63 via the conductor layer 66. Thus, the electrode 102 is connected to the contact point 63 so as to have substantially the same potential as that of the contact point 63.

[0132] The electrode 105 functions as a gate of the transfer transistor TW0_0. Figure 7 Side walls not shown in the figure.

[0133] The electrode 106 functions as a gate of the transfer transistor TW0_1. Figure 7 Side walls not shown in the figure.

[0134] The electrode 107 has an opening portion that is opened so as to surround the contact 62. The opening portion corresponds to the region where the electrode 202 is provided. In addition, a side surface of the outer periphery of the electrode 107 and a side surface of the inner periphery of the electrode 107 corresponding to the opening portion are provided. Figure 7 Side walls not shown in the figure.

[0135] In addition, the electrode 107 is connected to the contact point 69. The contact point 69 is electrically connected to the contact point 62 via the conductor layer 66. Thus, the electrode 107 is connected to the contact point 62 so as to have substantially the same potential as the contact point 62.

[0136] Two adjacent electrodes among the electrodes 101 , 102 , 105 , 106 , and 107 are provided to be spaced apart from each other so as to form a slit.

[0137] Figure 7 The overlapping distance L shown in the figure represents the distance between the electrodes 105 and N when viewed from the Z direction. – The overlapping distance L is the distance in the Y direction between the impurity diffusion regions 42 and each other. – The distance in the Y direction at which the impurity diffusion regions 44 overlap each other. The overlapping distance L is, for example, 0.2 μm to 0.6 μm. The overlapping distance L can be, for example, any distance that can ensure the required withstand voltage at the time of cutoff in the write action and the erase action. The width Ws is the slit width in the Y direction between the adjacent electrodes among the electrodes 101, 102, 105, 106 and 107 when viewed from the Z direction. The width Ws is, for example, 0.1 μm to 0.2 μm. The width Wg is the width in the Y direction from the inner periphery of the electrode 105 side of the opening portion of the electrode 101 to the outer periphery of the electrode 105 side of the electrode 101 when viewed from the Z direction, or the width in the Y direction from the inner periphery of the electrode 106 side of the opening portion of the electrode 102 to the outer periphery of the electrode 106 side of the electrode 102. The width Wg is, for example, 0.1 μm to 0.3 μm.

[0138] With the above-described configuration of the electrodes 105 and 106 , the electrodes 105 and 106 are provided so as to sandwich the electrode 202 in the Y direction in a plan view.

[0139] A contact 64 for applying a voltage to the electrode 105 is provided on the electrode 105. The contact 64 is connected to the transfer gate line BLKSEL of the block BLK0. A contact 65 for applying a voltage to the electrode 106 is provided on the electrode 106. The contact 65 is connected to the transfer gate line BLKSEL of the block BLK1. Figure 7 In the example shown, the number of contact points provided at each electrode 105 and 106 is one, but the present invention is not limited thereto. The number of contact points provided at each electrode 105 and 106 may be two or more.

[0140] In general, when performing various operations such as a write operation, a read operation, and an erase operation, a voltage higher than the ground voltage VSS (0 V) is applied to the electrodes 105 and 106 .

[0141] In the region where the insulator layer 50 is provided, a shielding conductor layer 400 is provided on the insulator layer 50 so as to surround, for example, the P-type well region 41B. The shielding conductor layer 400 includes, for example, polysilicon. The shielding conductor layer 400 may also be provided in a grid shape similarly to the insulator layer 50. Figure 7 Side walls not shown in the figure.

[0142] The shield conductor layer 400 is in a state where the ground voltage VSS is applied, in a floating state, or in a state where the potential is the same as that of the P-type well region 41B. The shield conductor layer 400 suppresses the generation of leakage current between the transfer transistors during various operations.

[0143] (Section structure)

[0144] use Figure 8 The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 will be described. Figure 8 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to an embodiment. Figure 7 The following is a cross-sectional view of the line VIII-VIII. Figure 8 The configuration of the transfer transistor in cross section is shown.

[0145] The upper end of the insulating layer 50 is located above the upper end of the P-type well region 41B. The lower end of the insulating layer 50 is located above the lower end of the N-type well region 40 and below the lower end of the P-type well region 41B.

[0146] N – The lower end of each of the impurity diffusion regions 42 , 43 , and 44 is provided above the lower end of the P-type well region 41B.

[0147] The electrode 201 includes N + The impurity diffusion region 211 and the conductor layer 221. + The lower end of the impurity diffusion region 211 is set at a – The lower end of the impurity diffusion region 42 is located above. + The impurity diffusion region 211 is N – The impurity diffusion region 42 is an impurity diffusion region containing N-type impurities such as phosphorus (P) or arsenic (As) at a high concentration. + The upper end of the conductor layer 221 is, for example, N –The upper end of the impurity diffusion region 42 is high. The conductive layer 221 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0148] Electrode 202 includes N + The impurity diffusion region 212 and the conductor layer 222. + The lower end of the impurity diffusion region 212 is set at a – The lower end of the impurity diffusion region 43 is located above. + The impurity diffusion region 212 is N – The impurity diffusion region 43 is an impurity diffusion region containing N-type impurities such as phosphorus (P) or arsenic (As) at a high concentration. + The upper end of the conductor layer 222 is, for example, – The upper end of the impurity diffusion region 43 is high. The conductor layer 222 is provided on the N + The impurity diffusion region 212 is on the upper surface. The conductive layer 222 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0149] Electrode 203 includes N + The impurity diffusion region 213 and the conductor layer 223. + The lower end of the impurity diffusion region 213 is set at a – The lower end of the impurity diffusion region 44 is located above. + The impurity diffusion region 213 is N – The impurity diffusion region 44 is an impurity diffusion region containing N-type impurities such as phosphorus (P) or arsenic (As) at a high concentration. + The upper end of the conductor layer 223 is, for example, – The upper end of the impurity diffusion region 44 is high. The conductor layer 223 is provided on the N + On the upper surface of the impurity diffusion region 213. The conductive layer 223 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0150] A gate insulating film 51 is provided on the upper surface of the region of the P-type well region 41B excluding the electrodes 201 , 202 , and 203 . The upper end of the gate insulating film 51 is provided below the upper end of the insulating layer 50 .

[0151] The electrode 101 includes conductive layers 111 and 121. The upper end of the conductive layer 111 is provided at a position above the upper end of the insulating layer 50. The conductive layer 111 is provided on the upper surface of a portion of the gate insulating film 51 provided on the other end side of the electrode 201, provided on the upper surface of a portion of the gate insulating film 51 provided on the one end side of the electrode 201, and provided on the upper surface of a portion of the insulating layer 50 provided on the other end side of the portion of the insulating layer 50 provided on the one end side of the P-type well region 41B. The conductive layer 121 is provided on the upper surface of the conductive layer 111. The conductive layer 111 includes, for example, polycrystalline silicon. The conductive layer 121 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0152] The electrode 102 includes conductive layers 112 and 122. The upper end of the conductive layer 112 is provided at a position above the upper end of the insulating layer 50. The conductive layer 112 is provided on the upper surface of a portion of the gate insulating film 51 provided on one end side of the electrode 203, on the upper surface of a portion of the gate insulating film 51 provided on the other end side of the electrode 203, and on the upper surface of a portion of the insulating layer 50 provided on the other end side of the P-type well region 41B. The conductive layer 122 is provided on the upper surface of the conductive layer 112. The conductive layer 112 includes, for example, polycrystalline silicon. The conductive layer 122 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0153] The electrode 105 includes conductive layers 115 and 125. The upper end of the conductive layer 115 is provided at a position above the upper end of the insulating layer 50. The conductive layer 115 is provided on the upper surface of the portion of the gate insulating film 51 provided between the electrode 201 and the electrode 202. The conductive layer 125 is provided on the upper surface of the conductive layer 115. The conductive layer 115 includes, for example, polycrystalline silicon. The conductive layer 125 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0154] The electrode 106 includes conductive layers 116 and 126. The upper end of the conductive layer 116 is provided at a position above the upper end of the insulating layer 50. The conductive layer 116 is provided on the upper surface of the portion of the gate insulating film 51 provided between the electrode 202 and the electrode 203. The conductive layer 126 is provided on the upper surface of the conductive layer 116. The conductive layer 116 includes, for example, polycrystalline silicon. The conductive layer 126 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0155] The electrode 107 includes conductive layers 117 and 127. The upper end of the conductive layer 117 is provided at a position above the upper end of the insulating layer 50. The conductive layer 117 is provided on the upper surface of the portion of the gate insulating film 51 provided on one end side and the other end side of the electrode 202. The conductive layer 127 is provided on the upper surface of the conductive layer 117. The conductive layer 117 includes, for example, polycrystalline silicon. The conductive layer 127 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0156] The shielding conductor layer 400 includes conductor layers 410 and 420. The conductor layer 410 is provided on the upper surface of a portion of the insulating layer 50 provided on one end side of the P-type well region 41B, and on the upper surface of a portion of the insulating layer 50 provided on the other end side of the P-type well region 41B. The conductor layer 420 is provided on the upper surface of the conductor layer 410. The conductor layer 410 includes, for example, polycrystalline silicon. The conductor layer 420 includes, for example, nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0157] Side walls 52_1, 52_2, 52_3, and 52_4 are provided on the side surfaces of each of the electrodes 101 and 102. In the following description, when the side walls 52_1, 52_2, 52_3, and 52_4 are not distinguished, they are simply referred to as side walls 52. The upper ends of the side walls 52 are located at a height lower than the upper ends of the electrodes 101 and 102.

[0158] The side wall 52_1 includes a first portion and a second portion. The first portion of the side wall 52_1 is provided on the upper surface of the insulating layer 50 in such a manner as to be in contact with one end of a portion of the electrode 101 provided on the one end side of the electrode 201 in the Y direction. In addition, the second portion of the side wall 52_1 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with the other end of a portion of the electrode 101 provided on the other end side of the electrode 201 in the Y direction.

[0159] The side wall 52_2 includes a first portion and a second portion. The first portion of the side wall 52_2 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with the other end of the portion of the electrode 101 provided on the one end side of the electrode 201 in the Y direction. In addition, the second portion of the side wall 52_2 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with one end of the portion of the electrode 101 provided on the other end side of the electrode 201 in the Y direction. The first portion of the side wall 52_2 and the second portion of the side wall 52_2 are provided adjacent to the electrode 201 along the Y direction.

[0160] The side wall 52_3 includes a first portion and a second portion. The first portion of the side wall 52_3 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with one end of a portion of the electrode 102 provided on one end side relative to the electrode 203 in the Y direction. In addition, the second portion of the side wall 52_3 is provided on the upper surface of the insulating layer 50 in such a manner as to be in contact with the other end of a portion of the electrode 102 provided on the other end side relative to the electrode 203 in the Y direction.

[0161] The side wall 52_4 includes a first portion and a second portion. The first portion of the side wall 52_4 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with the other end of the portion of the electrode 102 provided on the one end side of the electrode 203 in the Y direction. In addition, the second portion of the side wall 52_4 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with one end of the portion of the electrode 102 provided on the other end side of the electrode 203 in the Y direction. The first portion of the side wall 52_4 and the second portion of the side wall 52_4 are provided adjacent to the electrode 203 along the Y direction.

[0162] Side walls 53_1 and 53_2 are provided on the side surfaces of the shield conductor layer 400 . In the following description, when the side walls 53_1 and 53_2 are not distinguished, they are simply referred to as side walls 53 . The upper end of the side wall 53 is located at a height lower than the upper end of the shield conductor layer 400 .

[0163] The side wall 53_1 includes a first portion and a second portion. The first portion of the side wall 53_1 is provided on the upper surface of the insulating layer 50 in such a manner as to be in contact with the other end of the portion of the shielding conductor layer 400 provided on the one end side of the P-type well region 41B in the Y direction. The first portion of the side wall 53_1 is provided so as to be adjacent to the first portion of the side wall 52_1 in the Y direction. In addition, the second portion of the side wall 53_1 is provided on the upper surface of the insulating layer 50 in such a manner as to be in contact with one end of the portion of the shielding conductor layer 400 provided on the other end side of the P-type well region 41B in the Y direction. The second portion of the side wall 53_1 is provided so as to be adjacent to the second portion of the side wall 52_3 in the Y direction.

[0164] The side wall 53_2 includes a first portion and a second portion. The first portion of the side wall 53_2 is provided on the upper surface of the insulating layer 50 in such a manner as to be in contact with one end of a portion of the shielding conductor layer 400 provided on one end side of the P-type well region 41B in the Y direction. In addition, the second portion of the side wall 53_2 is provided on the upper surface of the insulating layer 50 in such a manner as to be in contact with the other end of a portion of the shielding conductor layer 400 provided on the other end side of the P-type well region 41B in the Y direction. In addition, for example, in an area not shown in the figure, the second portion of the side wall 53_2 is provided so as to be adjacent to the side walls provided on the transfer transistors TW0_2 and TW0_3 along the Y direction.

[0165] Side walls 54_1, 54_2, 54_3, and 54_4 are provided on the side surfaces of each of the electrodes 105, 106, and 107. In the following description, when the side walls 54_1, 54_2, 54_3, and 54_4 are not distinguished, they are simply referred to as side walls 54. The upper ends of the side walls 54 are located at a height lower than the upper ends of the electrodes 105, 106, and 107.

[0166] The side wall 54_1 includes a first portion and a second portion. The first portion of the side wall 54_1 is provided on the upper surface of the gate insulating film 51 so as to be in contact with one end of the portion of the electrode 105 in the Y direction. In addition, the second portion of the side wall 54_1 is provided on the upper surface of the gate insulating film 51 so as to be in contact with the other end of the portion of the electrode 105 in the Y direction.

[0167] The side wall 54_2 includes a first portion and a second portion. The first portion of the side wall 54_2 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with one end of the portion of the electrode 106 in the Y direction. In addition, the second portion of the side wall 54_2 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with the other end of the portion of the electrode 106 in the Y direction.

[0168] The side wall 54_3 includes a first portion and a second portion. The first portion of the side wall 54_3 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with one end of a portion of the electrode 107 provided on the one end side of the electrode 202 in the Y direction. In addition, the second portion of the side wall 54_3 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with the other end of a portion of the electrode 107 provided on the other end side of the electrode 202 in the Y direction.

[0169] The side wall 54_4 includes a first portion and a second portion. The first portion of the side wall 54_4 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with the other end of the portion of the electrode 107 provided on the one end side of the electrode 202 in the Y direction. In addition, the second portion of the side wall 54_4 is provided on the upper surface of the gate insulating film 51 in such a manner as to be in contact with one end of the portion of the electrode 107 provided on the other end side of the electrode 202 in the Y direction. The first portion of the side wall 54_4 and the second portion of the side wall 54_4 are provided adjacent to the electrode 202 in the Y direction.

[0170] A plurality of conductive layers 66 are provided above the electrodes 101, 102, 105, 106, and 107. Each of the plurality of conductive layers 66 is connected to corresponding wirings such as the selection gate lines SGS and SGD0 to SGD4 of each of the plurality of blocks BLK, the word lines WL0 to WL7 of each of the plurality of blocks BLK, the transfer gate lines BLKSEL of each of the plurality of row decoders RD, and the signal lines CGS, CG0 to CG7, and CGD0 to CGD4. Each of the plurality of conductive layers 66 is provided in a line shape extending in the X direction, for example, in a region not shown.

[0171] The lower end of the contact 61 is in contact with the conductive layer 221. The upper end of the contact 61 is connected to the word line WL0 of the block BLK0 via a corresponding conductive layer 66 among the plurality of conductive layers 66.

[0172] The lower end of the contact point 62 is in contact with the conductive layer 222. The upper end of the contact point 62 is connected to the signal line CG0 via a corresponding conductive layer 66 among the plurality of conductive layers 66.

[0173] The lower end of the contact 63 is in contact with the conductive layer 223. The upper end of the contact 63 is connected to the word line WL0 of the block BLK1 via a corresponding conductive layer 66 among the plurality of conductive layers 66.

[0174] The lower end of the contact 64 is in contact with the conductive layer 125. The upper end of the contact 64 is connected to the transfer gate line BLKSEL of the block BLK0 via a corresponding conductive layer 66 among the plurality of conductive layers 66.

[0175] The lower end of the contact 65 is in contact with the conductive layer 126. The upper end of the contact 65 is connected to the transfer gate line BLKSEL of the block BLK1 via a corresponding conductive layer 66 among the plurality of conductive layers 66.

[0176] use Fig. 9 The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 is further described. Fig. 9 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to an embodiment. Figure 7The following is a cross-sectional view of the IX-IX line. Fig. 9 The configuration of the transfer transistor in cross section is shown.

[0177] The gate insulating film 51 is provided on the P-type well region 41B in the entire region sandwiched by the insulating layer 50 .

[0178] The conductive layer 111 is provided on the upper surface of a portion on one end side of the gate insulating film 51 and on the upper surface of a portion on the other end side of the portion of the insulating layer 50 provided on one end side of the P-type well region 41B. The conductive layer 112 is provided on the upper surface of a portion on the other end side of the gate insulating film 51 and on the upper surface of a portion on one end side of the portion of the insulating layer 50 provided on the other end side of the P-type well region 41B.

[0179] exist Fig. 9 In the cross section shown, the second portion of the side wall 52_1 is provided to be in contact with the other end of the portion of the conductor layer 111 in the Y direction. The first portion of the side wall 54_1 is provided to be in contact with one end of the portion of the conductor layer 115 in the Y direction. The second portion of the side wall 52_1 and the first portion of the side wall 54_1 are provided to be in contact with each other along the Y direction.

[0180] Similarly, the second portion of the side wall 54_1 and the first portion of the side wall 54_3 are disposed in contact with each other along the Y direction. The second portion of the side wall 54_3 and the first portion of the side wall 54_2 are disposed in contact with each other along the Y direction. The second portion of the side wall 54_2 and the first portion of the side wall 52_3 are disposed in contact with each other along the Y direction.

[0181] The lower end of the contact 67 is in contact with the conductor layer 121. Figure 7 and Fig. 9 As shown, the upper end of the contact 67 is electrically connected to the contact 61 via the conductor layer 66. Thus, the conductor layer 121 (electrode 101) is connected to the contact 61 so as to have substantially the same potential.

[0182] The lower end of the contact 68 is connected to the conductor layer 122. Figure 7 and Fig. 9 As shown, the upper end of the contact 68 is electrically connected to the contact 63 via the conductor layer 66. Thus, the conductor layer 122 (electrode 102) is connected to the contact 63 so as to have substantially the same potential.

[0183] The lower end of the contact 69 is connected to the conductor layer 127. Figure 7 and Fig. 9 As shown, the upper end of the contact 69 is electrically connected to the contact 62 via the conductor layer 66. Thus, the conductor layer 127 (electrode 107) is connected to the contact 62 so as to have substantially the same potential.

[0184] 1.2 Method of manufacturing transfer transistor

[0185] Fig.10 and Fig.11 It is a cross-sectional view showing an example of a structure of a transfer transistor TW included in the semiconductor memory device 1 according to the embodiment during manufacturing. Fig.10 and Fig.11 The cross-sectional view shown shows Figure 8 Corresponding cross-sectional structure. Hereinafter, an example of a manufacturing method related to the formation of the conductive layers 121 , 122 , 125 , 126 , 127 , 420 , 221 , 222 , and 223 will be mainly described.

[0186] like Fig.10 As shown, for the exposed N – The impurity diffusion regions 42, 43 and 44 are selectively ion-implanted with N-type impurities to form N + Impurity diffusion regions 211 , 212 and 213 .

[0187] Then, a self-aligned silicide formation process is performed. Fig.11 As shown, electrodes 101 , 102 , 105 , 106 , 107 , 201 , 202 , and 203 , and a shielding conductor layer 400 are formed.

[0188] More specifically, in the formation of N + A metal film is stacked on the structure after the impurity diffusion regions 211, 212, and 213. The metal film is, for example, a film containing nickel (Ni), nickel platinum (NiPt), and cobalt (Co). Then, by anisotropic etching using a pattern of a resist material, the portion of the metal film stacked outside the predetermined region where the transfer transistors TW, TS, and TD are set when viewed from above is removed. The anisotropic etching in this process is, for example, RIE (Reactive Ion Etching). Then, by heat treating the structure on which the metal film is formed, the conductive layers 111, 112, 115, 116, 117, and 410, as well as N + The silicon contained in each of the impurity diffusion regions 211, 212, and 213 reacts with the metal element contained in the metal film. + Silicide (conductive layers 121, 122, 125, 126, 127, 420, 221, 222, and 223) is formed on the upper surface of each of the impurity diffusion regions 211, 212, and 213. In addition, after the conductive layers 121, 122, 125, 126, 127, 420, 221, 222, and 223 are formed, the unreacted metal film is removed. By such a self-aligned silicide formation process, as Fig.11 As shown, in the conductive layers 111, 112, 115, 116, 117 and 410, and N + On the upper surface of each of the impurity diffusion regions 211 , 212 , and 213 , the conductive layers 121 , 122 , 125 , 126 , 127 , 420 , 221 , 222 , and 223 are formed.

[0189] In addition, if Fig. 9 As shown, the area between electrode 101 and electrode 105 is closed by side walls 52_1 and 54_1. The area between electrode 105 and electrode 107 is closed by side walls 54_1 and 54_3. The area between electrode 107 and electrode 106 is closed by side walls 52_3 and 54_2. The area between electrode 106 and electrode 102 is closed by side walls 52_3 and 54_2. This is because the slit width in the Y direction between adjacent electrodes among electrodes 101, 102, 105, 106 and 107, that is, the width Ws, is relatively small. Therefore, in Figure 7 In the area shown, a full salicide process can be applied.

[0190] 1.3 Effects of implementation methods

[0191] According to the embodiment, it is possible to suppress a decrease in the reliability of a semiconductor memory device. The effects of the embodiment will be described below.

[0192] In the semiconductor memory device 1 of the embodiment, N-type well regions 41B are provided in sequence along the Y direction. – Impurity diffusion regions 42, 43 and 44. –Electrodes 201, 202, and 203 are provided in the impurity diffusion regions 42, 43, and 44, respectively. Electrode 201 functions as the first terminal of the transmission transistor TW0_0. Electrode 203 functions as the first terminal of the transmission transistor TW0_1. Electrode 202 functions as the second terminal of the transmission transistor TW0_0 and the second terminal of the transmission transistor TW0_1. Electrode 201 is connected to word line WL0 of block BLK corresponding to transmission transistor TW0_0 via contact 61. Electrode 202 is connected to signal line CG0 via contact 62. Electrode 203 is connected to word line WL0 of block BLK corresponding to transmission transistor TW0_1 via contact 63. Electrode 101 having an opening surrounding contact 61 and electrode 102 having an opening surrounding contact 63 are provided above P-type well region 41B. Furthermore, an electrode 105 that functions as a gate of the transfer transistor TW0_0, an electrode 106 that functions as a gate of the transfer transistor TW0_1, and an electrode 107 having an opening that surrounds the contact 62 are provided above the P-type well region 41B. With such a structure of the electrodes 101, 102, 105, 106, and 107, it is possible to suppress a change in the characteristics of the transfer transistors TW0_0 and TW0_1 caused by a change in the potential of each conductive layer 66 provided above the transfer transistors TW0_0 and TW0_1. Therefore, it is possible to suppress a reduction in the reliability of the semiconductor memory device 1.

[0193] In addition, only in the adjacent N – When a conductive layer serving as a gate is provided between impurity diffusion regions, for example, N – The resistance value of the impurity diffusion region is affected by the voltage change of the conductive layer (wiring) provided above the transistor. This influence is particularly significant in N – In a high-voltage transistor in which the resistance value of the impurity diffusion region is relatively high, this may not be negligible from the viewpoint of voltage resistance and reliability, and is not preferable. – A method for changing the resistance value of the impurity diffusion region is known to be to set the wiring relative to N to such an extent that the influence can be ignored. – However, when this method is used, the aspect ratio of the contact becomes large, which may make it difficult to form the contact and may reduce the characteristics of the semiconductor memory device.

[0194] According to the semiconductor memory device 1 of the embodiment, the electrode 101 is provided so as to surround the contact 61. In addition, the electrode 102 is provided so as to surround the contact 63. In addition, the electrodes 105 and 106 are provided so as to function as gates. In addition, the electrode 107 is provided so as to surround the contact 62. By configuring the electrodes 101, 102, 105, 106, and 107 in this way, the electrodes 101 and 102 can transmit N –The upper surface of each of the impurity diffusion regions 42, 43 and 44 is entirely covered. In addition, when performing various operations such as writing, reading and erasing, a voltage higher than the ground voltage VSS is applied to the electrodes 101, 102, 105, 106 and 107. According to the above, the electrodes 101, 102, 105, 106 and 107 can shield the electric field formed by the conductive layer 66. Therefore, when performing various operations such as writing, reading and erasing, the N – The resistance values ​​of the impurity diffusion regions 42, 43, and 44 vary. – Even when the resistance value of the impurity diffusion region is relatively high, the aspect ratio of the contact can be suppressed from increasing, and the reliability reduction of the transfer transistors TW0_0 and TW0_1 caused by the potential change of each conductive layer 66 can be suppressed.

[0195] According to the embodiment, the transfer transistors TW0_0 and TW0_1 share the electrode 202. With such a configuration, it is possible to suppress an increase in the area occupied by the transfer transistors TW0_0 and TW0_1 in the semiconductor substrate 20. Therefore, it is possible to suppress an increase in the size of the semiconductor memory device 1.

[0196] In addition, according to the embodiment, the reliability reduction of the semiconductor memory device can be suppressed by improving the surface withstand voltage. The surface withstand voltage refers to the breakdown withstand voltage caused by the pn junction between the source or drain and the well region (semiconductor substrate) near the gate when a high potential difference is generated between the gate and the source or drain when 0V is applied to the gate.

[0197] The electrodes 101, 102, and 107 are respectively at substantially the same potential as the contacts 61, 63, and 62, and are not used as gates. Thus, even when 0 V is applied to the gates, that is, the electrodes 105 and 106, the electric field concentration in the well region near the contacts 61, 62, and 63 can be alleviated. As a result, the surface withstand voltage can be improved. Therefore, the reliability reduction of the transmission transistors TW0_0 and TW0_1 caused by the potential change of the conductor layer 66 can be suppressed, and the surface withstand voltage of the transmission transistors TW0_0 and TW0_1 can be improved.

[0198] 2. Variations

[0199] Additionally, the described embodiments may be modified in various ways.

[0200] The following describes a semiconductor storage device according to a modified example. The following describes the structure and manufacturing method of the semiconductor storage device according to the modified example, focusing on the differences from the semiconductor storage device 1 according to the embodiment. The semiconductor storage device according to the modified example can also achieve the same effects as the embodiment.

[0201] 2.1 Variation 1

[0202] The position of the slit between the electrode 101 and the electrode 105 may be changed compared to the above-described embodiment.

[0203] In the following description, regarding the configuration of the transfer transistor according to the first variation, the configuration different from that of the embodiment will be mainly described.

[0204] use Fig.12 The planar structure of the transfer transistors TW0_0 and TW0_1 according to the first variation will be described. Fig.12 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the first variation.

[0205] In addition, Fig.12 In the example shown, N – The impurity diffusion regions 42, 43, and 44 are also arranged around the P-type well region 41B (active region), for example. – The end of the impurity diffusion region 42 is arranged outside the end of the P-type well region 41B (active region) in the +X direction, -X direction, and +Y direction. – The end of the impurity diffusion region 43 is arranged outside the end of the P-type well region 41B (active region) in the +X direction and the -X direction. – The end of the impurity diffusion region 44 is arranged outside the end of the P-type well region 41B (active region) in the +X direction, -X direction and -Y direction. That is, when viewed from the Z direction, the P-type well region 41B (active region) is arranged to cross the N – The impurity diffusion regions 42, 43 and 44 are arranged in a manner. – The impurity diffusion region 42 may also be arranged to be shared by the transfer transistors TW0_0 and TW1_0 adjacent to each other in the X direction. – The impurity diffusion region 43 may also be arranged to be shared by the transfer transistors TW0_0 and TW1_0 adjacent to each other in the X direction, and shared by the transfer transistors TW0_1 and TW1_1 adjacent to each other in the X direction. – The impurity diffusion region 44 may be arranged so as to be shared by the transfer transistors TW0_1 and TW1_1 adjacent to each other in the X direction.

[0206] The slit S between the electrodes 101 and 105 is directed toward N – The impurity diffusion region 42 and N – The channels between the impurity diffusion regions 43 are in opposite directions ( Fig.12The electrodes 101 and 105 are arranged so as to be displaced in the +Y direction of the slit S. That is, the slit S is displaced in the direction of the arrow Ar.

[0207] Fig.13 1 is a graph showing an example of the surface withstand voltage of the transfer transistor of the first variation. The horizontal axis represents the drain voltage. The vertical axis represents the drain current. The graph shows data of Example 1, Example 2, and Example 3. Example 1, Example 2, and Example 3 are data of increasing the displacement of the position of the slit S in order.

[0208] The surface withstand voltage improves from Example 1 to Example 3, that is, as the displacement of the position of the slit S becomes larger.

[0209] The potential gradient and the surface withstand voltage will be described with reference to FIG. 14 . Fig.14A and Fig. 14B FIG. 1 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a first variation. Fig.12 The sectional view of the XIV-XIV line. Fig.14A and Fig. 14B In, with Figure 8 In comparison, left and right are expressed oppositely. Fig.14A This shows a case where the displacement of the position of the slit S is small as in Example 1. Fig. 14B This indicates a case where the position of the slit S is greatly displaced as in Example 3. Fig. 14C and Fig.14D Each of the Fig.14A and Fig. 14B An enlarged view of the dashed-dotted box shown.

[0210] exist Fig. 14B and Fig.14D In, with Fig.14A and Fig. 14C Compared with the above, the position of the slit S is displaced more. Fig. 14B and Fig.14D In, with Fig.14A and Fig. 14C In comparison, the width of the electrode 101 in the Y direction is smaller. Fig. 14B and Fig.14D In, with Fig.14A and Fig. 14C In comparison, the width Wg is smaller. Fig. 14B and Fig.14D In, with Fig.14A and Fig. 14C In comparison, electrodes 105 and N – The impurity diffusion regions 42 have a large overlap along the Y direction. Fig. 14B and Fig.14D In, with Fig.14A and Fig. 14CIn comparison, the overlapping distance L is longer.

[0211] FIG. 14A to FIG. 14D This shows an example of data deletion operation of the semiconductor memory device 1. A voltage of, for example, 23.5V is applied to the contact point 61. A voltage of 0V (off) is applied to the contact point 64. A voltage of 0.5V is applied to the contact point 62.

[0212] exist FIG. 14A to FIG. 14D , equipotential lines from the contact point 61 to the semiconductor substrate 20 with respect to the electric field lines are schematically shown.

[0213] exist Fig.14A and Fig. 14C In the embodiment, due to the 0V electrode 105, the potential difference near the electrode 105 is large. That is, the equipotential lines near the electrode 105 become denser. It is possible that a high electric field is generated in the area where the equipotential lines are dense, and surface leakage occurs. The surface leakage is indicated by the dotted arrow, which is the leakage of 0V to the P-type well region 41B of the semiconductor substrate 20.

[0214] exist Fig. 14B and Fig.14D In the process, the displacement of the slit S causes the electrodes 105 and N – The overlap of the impurity diffusion region 42 is increased (the overlap distance L is extended). That is, by making the N overlapped with the electrode 105 in the Z direction – The impurity diffusion region 42 is increased, and the N-type region overlapping the gate electrode 105 in the Z direction is – The voltage drop in the impurity diffusion region 42 increases. – The potential difference at the junction on the other end side of the impurity diffusion region 42 can reduce surface leakage. In other words, it is possible to improve the surface withstand voltage.

[0215] Fig.15 1 is a graph showing an example of the on-current of the transfer transistor of the first variation. The horizontal axis represents the gate voltage. The vertical axis represents the drain current. The graph shows data of Example 1, Example 2, and Example 3. Example 1, Example 2, and Example 3 are data of increasing the displacement of the position of the slit S in sequence.

[0216] The on-current is improved from Example 1 to Example 3, that is, as the position of the slit S is shifted, it is because the electrodes 105 and N – The greater the overlap of the impurity diffusion regions 42 in the Y direction, the greater the on-current.

[0217] In addition, the slit between the electrode 102 and the electrode 106 may be directed toward the N – The impurity diffusion region 43 and N –The channels between the impurity diffusion regions 44 are in opposite directions ( Fig.12 The electrodes 102 and 106 are arranged in a manner so as to be displaced in the -Y direction).

[0218] According to the configuration of the transfer transistor as described above, it is possible to achieve the same effects as those of the embodiment.

[0219] 2.2 Variation 2

[0220] In contrast to the above-described embodiment, a portion of the electrodes 101 and 102 may be cut off.

[0221] In the following description, regarding the configuration of the transfer transistor according to the second variation, the configuration different from that of the embodiment will be mainly described.

[0222] use Fig.16 The planar structure of the transfer transistors TW0_0 and TW0_1 according to the second variation will be described. Fig.16 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the second variation.

[0223] The electrode 101 has a slit S1 extending from the end of the electrode 101 facing the electrode 105 to the opening. That is, the inner periphery of the electrode 101 is connected to the outer periphery of the electrode 101. The opening of the electrode 101 is connected to the slit between the electrode 101 and the electrode 105.

[0224] The electrode 102 has a slit S2 extending from the end of the electrode 102 facing the electrode 106 to the opening. That is, the inner periphery of the electrode 102 is connected to the outer periphery of the electrode 102. The opening of the electrode 102 is connected to the slit between the electrode 102 and the electrode 106.

[0225] In addition, the opening of the electrode 107 may be connected to the slit between the electrode 107 and the electrode 105. The opening of the electrode 107 may be connected to the slit between the electrode 107 and the electrode 106.

[0226] use Fig.17 The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the second variation will be described. Fig.17 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a second variation. Fig.16 A cross-sectional view taken along line XVII-XVII.

[0227] like Fig.17 As shown, in the second variation, the portion of the electrode 101 provided on the other end side of the electrode 201 is not provided. Also, the portion of the electrode 102 provided on the one end side of the electrode 203 is not provided.

[0228] According to the configuration of the transfer transistor as described above, it is possible to achieve the same effects as those of the embodiment and the first variation.

[0229] In addition, in the second variation, the characteristics of the surface withstand voltage and the on-current are substantially equivalent to those of the embodiment.

[0230] In the second variation, the electrode 101 has a slit S1, and the electrode 102 has a slit S2. That is, the opening of the electrode 101 is connected to the slit between the electrode 101 and the electrode 105, and the opening of the electrode 102 is connected to the slit between the electrode 102 and the electrode 106. Therefore, in the second variation, compared with the embodiment, even when the slit width Ws is small, it is easy to manufacture the semiconductor memory device 1.

[0231] In addition, use Fig.18 The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the second variation will be described. Fig.18 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor memory device according to a second variation. Fig.16 A cross-sectional view of the XVIII-XVIII line. Fig.18 In the figure, structures other than the gate insulating film 51, the electrode 101 and the side wall 52_5 are omitted.

[0232] like Fig.18 As shown, the region of the slit S1 may be closed by a side wall 52_5 provided on the side surface of the electrode 101 in the X direction. Similarly, the region of the slit S2 (not shown) may be closed by a side wall provided on the side surface of the electrode 102 in the X direction.

[0233] 2.3 Variation 3

[0234] In the above-described embodiment, an example in which the electrode 107 and the contact 69 are provided is shown, but the present invention is not limited thereto. The electrode 107 and the contact 69 may not be provided.

[0235] In the following description, regarding the configuration of the transfer transistor according to the third variation, the configuration different from that of the embodiment will be mainly described.

[0236] use Fig.19 The planar structure of the transfer transistors TW0_0 and TW0_1 according to the third variation will be described. Fig.19 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the third variation.

[0237] like Fig.19As shown, the electrode 107 is not provided in the third variation. Therefore, the structures of the drain side and the source side of the transfer transistor TW are different. That is, the structures of the drain side and the source side of the transfer transistor TW are asymmetrical. The electrode 107 is not provided on the other end side, that is, the drain side, of the transfer transistor TW0_0. On the other hand, the electrode 101 is provided on one end side, that is, the source side, of the transfer transistor TW0_1. The electrode 107 is not provided on one end side, that is, the drain side of the transfer transistor TW0_1. On the other hand, the electrode 102 is provided on the other end side, that is, the source side of the transfer transistor TW0_1.

[0238] When viewed from the Z direction, the electrodes 105 and N – The impurity diffusion regions 43 do not overlap each other. – The outer peripheral end of the impurity diffusion region 43 is substantially flush with the plane. – The impurity diffusion regions 43 do not overlap each other. – The outer peripheral end of the impurity diffusion region 43 is substantially flush with the plane, thereby further improving the surface withstand voltage.

[0239] use Fig. 20 The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the third variation will be described. Fig. 20 is a diagram showing an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to a third variation. Fig.19 Cross-sectional view of line XX-XX.

[0240] like Fig. 20 As shown, N – The impurity diffusion region 43 is not covered by the electrode 107 .

[0241] According to the configuration of the transfer transistor described above, it is possible to achieve the same effects as those of the embodiment, the first variation, and the second variation.

[0242] In addition, the third variation can be applied to, for example, – The requirement on the surface withstand voltage of the impurity diffusion region 42 is relatively loose, but – The impurity diffusion region 43 side needs a portion with high cutoff characteristics. Fig.19 and Fig. 20 In the embodiment, the third variation is described as an example of the structure of the transfer transistor TW included in the row decoder RD, but the third variation can also be applied to, for example, a peripheral circuit and a booster circuit.

[0243] 2.4 Variation 4

[0244] In the above-described embodiment, an example in which a silicide blocking film is not provided is shown, but the present invention is not limited thereto. A silicide blocking film may be provided.

[0245] In the following description, regarding the configuration of the transfer transistor of the fourth modification, the configuration different from that of the third modification will be mainly described.

[0246] use Fig.21 The planar structure of the transfer transistors TW0_0 and TW0_1 according to the fourth variation will be described. Fig.21 It is a top view showing an example of a cross-sectional structure of a transfer transistor included in the semiconductor memory device according to the fourth variation.

[0247] like Fig.21 As shown, in the region near the electrode 202 viewed from the Z direction, a silicide blocking film 500 for preventing silicide is provided so as to prevent the P-type well region 41B from being silicided.

[0248] use Fig. 22 The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the fourth variation will be described. Fig. 22 is an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to a fourth variation, along the Fig.21 A cross-sectional view of line XXII-XXII.

[0249] like Fig. 22 As shown, the silicide blocking film 500 is provided on the upper surface of the P-type well region 41B. A portion of the silicide blocking film 500 is provided on the upper surface of a portion of the electrodes 105 and 106 .

[0250] 2.5 Variation 5

[0251] In the above embodiment, the ends of the electrodes 101, 102, 105, 106 and 107 are arranged outside the P-type well region 41B, but the present invention is not limited thereto. The ends of the electrodes 101, 102, 105, 106 and 107 may be arranged inside the P-type well region 41B.

[0252] In the following description, regarding the configuration of the transfer transistor of the fifth variation, the configuration different from that of the embodiment will be mainly described.

[0253] use Fig.23 The planar structure of the transfer transistors TW0_0 and TW0_1 according to the fifth variation will be described. Fig.23 It is a top view showing an example of a planar structure of a transfer transistor included in the semiconductor memory device according to the fifth variation.

[0254] The electrodes 101 , 102 , 105 , 106 , and 107 are provided inside a P-type well region 41B (active region) provided in the semiconductor substrate 20 as viewed from the Z direction.

[0255] use Fig.24 The cross-sectional structure of the transfer transistors TW0_0 and TW0_1 according to the fifth variation will be described. Fig.24 is an example of a cross-sectional structure of a transfer transistor included in a semiconductor storage device according to a fifth variation, along Fig.23 A cross-sectional view of line XXIV-XXIV.

[0256] The electrodes 101 and 102 are arranged so as not to reach the insulator layer 50 (not to contact the insulator layer 50). That is, the electrode 101 is arranged on the other end side of the insulator layer 50. In addition, the electrode 102 is arranged on the one end side of the insulator layer 50. Thus, the distance between the electrodes of the transmission transistors TW0_0 and TW0_1 and the electrodes of the transmission transistors TW1_0 and TW1_1 can be made longer. Therefore, leakage between adjacent elements such as field inversion leakage and punch-through leakage can be suppressed.

[0257] According to the configuration of the transfer transistor described above, it is possible to achieve the same effects as those of the embodiment, the first variation, the second variation, the third variation, and the fourth variation.

[0258] 2.6 Variation 6

[0259] In the fifth variation, the ends of the electrodes 101, 102, 105, 106, and 107 are arranged inside the P-type well region 41B, but the invention is not limited thereto. Parts of the ends of the electrodes 105 and 106 may be arranged outside the P-type well region 41B.

[0260] In the following description, regarding the configuration of the transfer transistor of the sixth variation, the configuration different from that of the fifth variation will be mainly described.

[0261] use Fig.25 The planar structure of the transfer transistors TW0_0 and TW0_1 according to the sixth variation will be described. Fig.25 It is a top view showing an example of a planar structure of a transfer transistor included in a semiconductor memory device according to a sixth variation.

[0262] When viewed from the Z direction, the electrodes 101, 102, and 107 are arranged on the inner side of the P-type well region 41B (active region) provided in the semiconductor substrate 20. When viewed from the Z direction, the electrodes 105 and 106 are arranged to extend from the P-type well region 41B to the X direction. That is, in the X direction, a portion of the electrode 105 and the electrode 106 are arranged on the outer side than the P-type well region 41B. As a result, when viewed from the Z direction, the area where the electrode 105 and the electrode 106 overlap with the P-type well region 41B becomes larger, and leakage from the P-type well region 41B to adjacent elements can be suppressed. Therefore, the stability of the characteristics of TW_0 and TW0_1 of the transmission transistor when the current is cut off can be improved.

[0263] According to the configuration of the transfer transistor described above, it is possible to achieve the same effects as those of the embodiment, the first variation, the second variation, the third variation, the fourth variation, and the fifth variation.

[0264] Although some embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the present invention. The embodiments may be implemented in various other ways, and various omissions, substitutions, and changes may be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and their equivalents.

[0265] [Explanation of Symbols]

[0266] 1 Semiconductor storage device

[0267] 2 Memory Controller

[0268] 3 Memory system

[0269] 10 Storage Cell Array

[0270] 11 Instruction register

[0271] 12 Address register

[0272] 13 Sequencer

[0273] 14 Driver module

[0274] 15-line decoder module

[0275] 16 Sense Amplifier Module

[0276] 20 Semiconductor substrate

[0277] 21~25,103,110~114,121~124,130~132,221~223,300,301,410,420,430 Conductor layer

[0278] 400 Shielding conductor layer

[0279] 26 Semiconductor Division

[0280] 30~34,50,80,90~93 Insulation layer

[0281] 35 core components

[0282] 36 Semiconductor film

[0283] 37 Tunnel insulation film

[0284] 38 Charge storage membrane

[0285] 39 insulation films

[0286] 51 Gate insulating film

[0287] 52,53 Sidewall

[0288] 70~73 Resist materials

[0289] 101,102,104,201~203 electrodes

[0290] BLK Block

[0291] SU String Unit

[0292] NS NAND string

[0293] MT Memory Cell Transistor

[0294] ST1, ST2 select transistor

[0295] BL bit line

[0296] WL Word Line

[0297] SGS,SGD select gate line

[0298] TS,TW0~TW7,TD Transmission transistor

[0299] CGS, CG0~CG7, CGD0~CGD4 signal lines.

Claims

1. A semiconductor storage device comprising: A semiconductor substrate comprising a device region, and a first region, a second region, and a third region which are respectively source regions or drain regions and are arranged in sequence and spaced apart from each other along a first direction in the device region; A first conductive layer, provided above the device region, having a first opening; a second conductive layer, disposed above the device region, having a second opening, and spaced apart from the first conductive layer in the first direction; a first contact connected to the first region through the first opening; a second contact connected to the third region through the second opening; A first storage cell connected to the first contact; a second storage cell connected to the second contact; as well as The third conductor layer and the fourth conductor layer are disposed above the device region and between the first conductor layer and the second conductor layer, and are sequentially arranged away from each other in the first direction; and The third conductive layer is spaced apart from the first conductive layer; The fourth conductor layer is spaced apart from the second conductor layer; The first conductive layer and the first contact are connected to each other in a manner that they have substantially the same potential; The second conductor layer and the second contact are connected to each other so as to have substantially the same potential.

2. The semiconductor memory device according to claim 1, further comprising: a third contact connected to the second region through between the third conductive layer and the fourth conductive layer.

3. The semiconductor storage device according to claim 2, further comprising: a fifth conductive layer, provided between the third conductive layer and the fourth conductive layer above the element region, and having a third opening for the third contact to pass through; and The fifth conductor layer is disposed apart from the third conductor layer and the fourth conductor layer; The fifth conductor layer and the third contact are connected to each other so as to have substantially the same potential.

4. The semiconductor memory device according to claim 3, wherein the first conductive layer has a first slit extending from an end portion of the first conductive layer facing the third conductive layer to the first opening; The second conductive layer has a second slit extending from an end portion of the second conductive layer facing the fourth conductive layer to the second opening.

5. The semiconductor storage device according to claim 3, wherein the first conductor layer, the second conductor layer, the third conductor layer, the fourth conductor layer and the fifth conductor layer are arranged on the inner side of an active area provided in the semiconductor substrate when viewed from a direction substantially perpendicular to the semiconductor substrate.

6. The semiconductor memory device according to claim 3, wherein the first conductive layer, the second conductive layer, and the fifth conductive layer are provided inside an active region provided in the semiconductor substrate when viewed from a direction substantially perpendicular to the semiconductor substrate; When viewed from a direction substantially perpendicular to the semiconductor substrate, the third conductive layer and the fourth conductive layer are provided so as to extend from the active region in a second direction substantially perpendicular to the first direction and substantially parallel to the semiconductor substrate.

7. A semiconductor storage device according to claim 2, wherein the third conductor layer and the second region do not overlap with each other when observed from a direction approximately perpendicular to the semiconductor substrate, and the fourth conductor layer and the second region do not overlap with each other when observed from a direction approximately perpendicular to the semiconductor substrate. 8 . The semiconductor memory device according to claim 1 , wherein the first region and the third conductive layer overlap with each other when viewed in a direction substantially perpendicular to the semiconductor substrate. 9 . The semiconductor memory device according to claim 8 , wherein the first region and the third conductive layer overlap each other within a range of 0.2 μm to 0.6 μm in the first direction when viewed from a direction substantially perpendicular to the semiconductor substrate.

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