Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a stacked structure; a source structure; a channel structure penetrating the stacked structure, the channel structure being connected to the source structure; and a first memory layer interposed between the channel structure and the stack structure. The source structure includes a first protrusion protruding between the first memory layer and the channel structure.

Description

[0001] This application is a divisional application of the invention patent application with the original application number 202010903257.3 (application date: September 1, 2020, invention name: semiconductor device and method for manufacturing the semiconductor device) Technical Field

[0002] The present disclosure generally relates to semiconductor devices and methods for manufacturing the same, and more particularly, to a three-dimensional semiconductor device and a method for manufacturing the same. Background Art

[0003] Semiconductor devices include integrated circuits configured using metal oxide semiconductor field effect transistors (MOSFETs). As the size and design rules of semiconductor devices are gradually reduced, the shrinkage of MOSFETs is gradually accelerating.

[0004] The shrinking of MOSFET may cause a short channel effect, etc., and thus, the operating characteristics of the semiconductor device may be deteriorated. Therefore, various methods have been studied for forming a semiconductor device with better performance while overcoming limitations caused by high integration of the semiconductor device.

[0005] In addition, such integrated circuits pursue operational reliability and low power consumption. Therefore, methods of forming devices with higher reliability and lower power consumption in a smaller space have been studied. Summary of the invention

[0006] According to one aspect of the present disclosure, a semiconductor device is provided, which may include: a stacked structure; a source structure including a first protrusion protruding toward the stacked structure; a channel structure penetrating the stacked structure, the channel structure connected to the source structure; a first tunnel insulating layer inserted between the channel structure and the stacked structure; a first data storage layer inserted between the first tunnel insulating layer and the stacked structure; and a first barrier layer inserted between the first data storage layer and the stacked structure, wherein the first protrusion contacts a bottom surface of the first tunnel insulating layer, a bottom surface of the first data storage layer, and a side wall of the first barrier layer.

[0007] According to another aspect of the present disclosure, a semiconductor device is provided, which may include: a source structure; a stacked structure; a channel structure, which penetrates the stacked structure and is connected to the source structure; and a first memory layer, which is inserted between the channel structure and the stacked structure, wherein the source structure includes a first protrusion protruding between the first memory layer and the channel structure, wherein the first protrusion has a stepped structure.

[0008] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, which may include the following steps: forming a source sacrificial layer; forming a stacked structure above the source sacrificial layer; forming a memory layer, wherein the memory layer penetrates the stacked structure and includes a tunnel insulating layer and a data storage layer surrounding the tunnel insulating layer; removing the source sacrificial layer to expose the memory layer; and removing a first exposed area of ​​the data storage layer, wherein when the first exposed area of ​​the data storage layer is removed, a portion of the second exposed area of ​​the tunnel insulating layer is removed.

[0009] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, which may include the following steps: forming a source structure including a source sacrificial layer; forming a stacked structure above the source structure; forming a channel structure penetrating the stacked structure, a tunnel insulating layer surrounding the channel structure, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer; removing the source sacrificial layer to expose the blocking layer; etching the blocking layer to expose the data storage layer; etching the data storage layer to expose the tunnel insulating layer; and selectively etching the tunnel insulating layer, wherein the concentration of nitrogen in the tunnel insulating layer is higher than the concentration of nitrogen in the blocking layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Examples of embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the examples of embodiments to those skilled in the art.

[0011] Embodiments provide a semiconductor device capable of improving operation reliability and a method of manufacturing the semiconductor device.

[0012] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0013] Figure 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 1B It is along Figure 1A A cross-sectional view taken along line AA' is shown.

[0015] Figure 1C yes Figure 1B An enlarged view of area B is shown.

[0016] Figure 1D yes Figure 1C An enlarged view of area C is shown.

[0017] Figure 1E yes Figure 1C An enlarged view of area D is shown.

[0018] Figure 2A is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 2B yes Figure 2A An enlarged view of area E is shown.

[0020] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I , Figure 3J and Figure 3K It is shown Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E A cross-sectional view of a method for manufacturing a semiconductor device shown.

[0021] Figure 4A , Figure 4B and Figure 4C It is shown Figure 2A and Figure 2B A cross-sectional view of a method for manufacturing a semiconductor device shown.

[0022] Figure 5 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0023] Figure 6 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to describe the embodiments of the concepts according to the present disclosure, the specific structural or functional descriptions disclosed herein are only illustrative. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described herein.

[0025] Figure 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A A cross-sectional view taken along line AA' is shown. Figure 1C yes Figure 1B An enlarged view of area B is shown. Figure 1D yes Figure 1CAn enlarged view of area C is shown. Figure 1E yes Figure 1C An enlarged view of area D is shown.

[0026] Reference Figures 1A to 1E , the semiconductor device according to these embodiments may include a source structure SCS. The source structure SCS may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. In an example, the first direction D1 and the second direction D2 may be perpendicular to each other.

[0027] In an example, the source structure SCS may be disposed on a substrate. In an example, the substrate may be a semiconductor substrate. In an example, the substrate may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth process.

[0028] In an example, the source structure SCS may be disposed on an insulating layer. The insulating layer may be an insulating layer covering peripheral circuit elements and peripheral circuit lines. The peripheral circuit elements and peripheral circuit lines may be disposed in the insulating layer. In an example, the peripheral circuit elements may include elements constituting a row decoder, a column decoder, a page buffer circuit, and an input / output circuit. The peripheral circuit line may be electrically connected to the peripheral circuit elements. In an example, the insulating layer may include an oxide.

[0029] The source structure SCS may include a first source layer SL1, an etch stop layer ES on the first source layer SL1, and a second source layer SL2 on the etch stop layer ES. The first source layer SL1, the etch stop layer ES, and the second source layer SL2 may be stacked in sequence along a third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2. In an example, the third direction D3 may be perpendicular to the first direction D1 and the second direction D2. The first source layer SL1 and the second source layer SL2 may be spaced apart from each other by the etch stop layer ES. The etch stop layer ES may be disposed between the first source layer SL1 and the second source layer SL2.

[0030] Each of the first source layer SL1, the etch stop layer ES, and the second source layer SL2 may have a plate shape extending along a plane defined by the first direction D1 and the second direction D2. The etch stop layer ES may include an insulating material. In an example, the etch stop layer ES may include at least one of SiCO and SiCN. The first source layer SL1 may include a semiconductor material. In an example, the first source layer SL1 may include polysilicon. The second source layer SL2 may include a semiconductor material. In an example, the second source layer SL2 may include doped polysilicon. The etch stop layer ES may include a material different from that of the first source layer SL1 and the second source layer SL2.

[0031] The stacked structure STS may be disposed on the source structure SCS. The stacked structure STS may be in contact with the source structure SCS. The stacked structure STS may be disposed on the second source layer SL2. The stacked structure STS may include a conductive pattern CP and an insulating pattern IP alternately stacked in a third direction D3. The insulating pattern IP may be disposed on the second source layer SL2, and the conductive pattern and the insulating pattern IP may be alternately stacked on the insulating pattern IP. The bottom surface of the insulating pattern IP of the stacked structure STS may be in contact with the top surface SCS_T of the source structure SCS. The bottom surface of the insulating pattern IP of the stacked structure STS may be in contact with the top surface SL2_T of the second source layer SL2 of the source structure SCS.

[0032] The insulating pattern IP may include an insulating material. In an example, the insulating pattern IP may include an oxide. The conductive pattern CP may include a conductive material. In an example, the conductive pattern CP may include at least one of a doped silicon layer, a metal silicide layer, tungsten, nickel, and cobalt. The conductive pattern CP may be used as a word line connected to a memory cell or a selection line connected to a selection transistor.

[0033] The stack structure STS may further include a barrier film BR. The barrier film BR may be formed between the conductive pattern CP and the insulating pattern IP. The barrier film BR may cover the surface of the insulating pattern IP. The conductive pattern CP and the insulating pattern IP may be spaced apart from each other by the barrier film BR. In an example, the barrier film BR may include aluminum oxide.

[0034] The stack structure STS may further include an upper insulating pattern 110. The upper insulating pattern 110 may be disposed at the uppermost portion of the stack structure STS. The upper insulating pattern 110 may include an insulating material. In an example, the upper insulating pattern 110 may include an oxide.

[0035] A channel structure CS penetrating the stack structure STS, the second source layer SL2, and the etch stop layer ES may be provided. The channel structure CS may extend in the third direction D3. The channel structure CS may be electrically connected to the second source layer SL2.

[0036] The lowermost portion of the channel structure CS may be disposed in the first source layer SL1. The lowermost portion of the channel structure CS may be surrounded by the first source layer SL1. The level of the lowermost portion of the channel structure CS may be lower than the level of the top surface of the first source layer SL1, and may be higher than the level of the bottom surface of the first source layer SL1. The level of the lowermost portion of the channel structure CS may be lower than the level of the bottom surface of the etch stop layer ES.

[0037] Each channel structure CS may include a filling layer FI and a channel layer CL surrounding the filling layer FI. The filling layer FI and the channel layer CL may penetrate the stacked structure STS, the second source layer SL2, and the etching stop layer ES. The channel layer CL may be electrically connected to the second source layer SL2. The filling layer FI may include an insulating material. In an example, the filling layer may include an oxide. The channel layer CL may include a semiconductor material. In an example, the channel layer CL may include polysilicon.

[0038] Unlike shown in the drawings, the channel structure CS may not include the filling layer FI and be configured using only the channel layer CL.

[0039] A first memory layer ML1 surrounding an upper portion and a middle portion of the channel structure CS and a second memory layer ML2 surrounding a lower portion of the channel structure CS may be provided. The first memory layer ML1 may surround an upper portion and a middle portion of the channel layer CL, and the second memory layer ML2 may surround a lower portion of the channel layer CL.

[0040] The first memory layer ML1 and the second memory layer ML2 may be spaced apart from each other in the third direction D3. The second source layer SL2 may be disposed between the first memory layer ML1 and the second memory layer ML2. The first memory layer ML1 may be disposed in the stack structure STS. The second memory layer ML2 may be disposed in the first source layer SL1 of the source structure SCS.

[0041] The first memory layer ML1 may include a first tunnel insulating layer TL1 surrounding an upper portion and a middle portion of the channel layer CL, a first data storage layer DL1 surrounding the first tunnel insulating layer TL1, and a first barrier layer BKL1 surrounding the first data storage layer DL1. The width of the first tunnel insulating layer TL1 may be smaller than the width of the first barrier layer BKL1. In an example, the width of the first tunnel insulating layer TL1 in the first direction D1 may be defined as a first width W1, and the width of the first barrier layer BKL1 in the first direction D1 may be defined as a second width W2. The first width W1 may be smaller than the second width W2.

[0042] The second memory layer ML2 may include a second tunnel insulating layer TL2 surrounding a lower portion of the channel layer CL, a second data storage layer DL2 surrounding the second tunnel insulating layer TL2, and a second barrier layer BKL2 surrounding the second data storage layer DL2. The width of the second tunnel insulating layer TL2 may be smaller than the width of the second barrier layer BKL2. In an example, the width of the second tunnel insulating layer TL2 in the first direction D1 may be defined as a third width W3, and the width of the second barrier layer BKL2 in the first direction D1 may be defined as a fourth width W4. The third width W3 may be smaller than the fourth width W4. In an example, the third width W3 may be equal to the first width W1. In an example, the fourth width W4 may be equal to the second width W2.

[0043] The first memory layer ML1 may be interposed between the channel structure CS and the stack structure STS, the first tunnel insulating layer TL1 may be interposed between the channel structure CS and the stack structure STS, the first data storage layer DL1 may be interposed between the first tunnel insulating layer TL1 and the stack structure STS, and the first barrier layer BKL1 may be disposed between the first data storage layer DL1 and the stack structure STS.

[0044] The second memory layer ML2 may be interposed between the channel structure CS and the first source layer SL1. The second tunnel insulating layer TL2 may be disposed between the channel structure CS and the first source layer SL1, the second data storage layer DL2 may be interposed between the second tunnel insulating layer TL2 and the first source layer SL1, and the second barrier layer BKL2 may be interposed between the second data storage layer DL2 and the first source layer SL1.

[0045] The first tunnel insulating layer TL1 and the second tunnel insulating layer TL2 may be spaced apart from each other in the third direction D3. The second source layer SL2 may be disposed between the first tunnel insulating layer TL1 and the second tunnel insulating layer TL2. The first data storage layer DL1 and the second data storage layer DL2 may be spaced apart from each other in the third direction. The second source layer SL2 may be disposed between the first data storage layer DL1 and the second data storage layer DL2. The first barrier layer BKL1 and the second barrier layer BKL2 may be spaced apart from each other in the third direction D3. The second source layer SL2 may be disposed between the first barrier layer BKL1 and the second barrier layer BKL2.

[0046] The first tunnel insulating layer TL1 and the second tunnel insulating layer TL2 may include a material through which charges may tunnel. In an example, the first tunnel insulating layer TL1 and the second tunnel insulating layer TL2 may include an oxide including nitrogen.

[0047] The first and second data storage layers DL1 and DL2 may include a material that may capture charges. In an example, the first and second data storage layers DL1 and DL2 may include nitride.

[0048] The first and second blocking layers BKL1 and BKL2 may include a material capable of blocking movement of charges. In an example, the first and second blocking layers BKL1 and BKL2 may include oxide.

[0049] In an example, the concentration of nitrogen of the first data storage layer DL1 and the second data storage layer DL2 may be higher than the concentration of nitrogen of the first barrier layer BKL1 and the second barrier layer BKL2. In an example, the first barrier layer BKL1 and the second barrier layer BKL2 may not contain nitrogen. In an example, the concentration of nitrogen of the first tunnel insulating layer TL1 and the second tunnel insulating layer TL2 may be higher than the concentration of nitrogen of the first barrier layer BKL1 and the second barrier layer BKL2. In an example, the concentration of nitrogen of the first tunnel insulating layer TL1 and the second tunnel insulating layer TL2 may be lower than the concentration of nitrogen of the first data storage layer DL1 and the second data storage layer DL2.

[0050] The etch stop layer ES may be spaced apart from the channel structure CS. A second barrier layer BKL2 of the second memory layer ML2 and a second protrusion P2 to be described later may be disposed between the etch stop layer ES and the channel structure CS.

[0051] The second source layer SL2 of the source structure SCS may include a first protrusion P1 and a second protrusion P2.

[0052] The first protrusion P1 may protrude toward the stack structure STS. The first protrusion P1 may protrude from the top surface SCS_T of the source structure SCS in the third direction. The first protrusion P1 may protrude from the top surface SL2_T of the second source layer SL2 in the third direction D3.

[0053] The first protrusion P1 may have a ring shape surrounding the channel structure CS. The first protrusion P1 may protrude between the first memory layer ML1 and the channel structure CS. The first protrusion P1 may protrude between the first barrier layer BKL1 of the first memory layer ML1 and the channel structure CS.

[0054] The first protrusion P1 may contact the bottom surface TL1_B of the first tunnel insulating layer TL1, the sidewall DL1_S of the first data storage layer DL1, the bottom surface DL1_B of the first data storage layer DL1, and the sidewall BKL1_S of the first barrier layer BLK1. The first protrusion P1 may be located at the same level as the lowermost insulating pattern IP of the stacked structure STS. At least a portion of the first protrusion P1 and at least a portion of the lowermost insulating pattern IP of the stacked structure STS may be located at the same level.

[0055] The bottom surface TL1_B of the first tunnel insulating layer TL1, the bottom surface DL1_B of the first data storage layer DL1, and the bottom surface BKL1_B of the first barrier layer BKL1 may have different levels. The bottom surface DL1_B of the first data storage layer DL1 may be located at a level lower than that of the bottom surface TL1_B of the first tunnel insulating layer TL1. The bottom surface BKL1_B of the first barrier layer BKL1 may be located at a level lower than that of the bottom surface DL1_B of the first data storage layer DL1. The top surface SCS_T of the source structure may be in contact with the bottom surface BKL1_B of the first barrier layer BKL1. The top surface SL2_T of the second source layer SL2 may be in contact with the bottom surface BKL1_B of the first barrier layer BKL1.

[0056] The first protrusion P1 may have a stepped structure. A surface of the first protrusion P1 contacting the first tunnel insulating layer TL1, the first data storage layer DL1, and the first barrier layer BKL1 may have a stepped shape. The surface of the first protrusion P1 may be formed in a stepped shape along the bottom surface BKL1_B of the first barrier layer BKL1, the side wall DL1_S of the first data storage layer DL1, the bottom surface DL1_B of the first data storage layer DL1, and the side wall BKL1_S of the first barrier layer BKL1.

[0057] The first protrusion P1 may include a first portion P1a and a second portion P1b. The first portion P1a may contact the bottom surface TL1_B of the first tunnel insulation layer TL1 and the sidewall DL1_S of the first data storage layer DL1. The second portion P1b may contact the bottom surface DL1_B of the first data storage layer DL1 and the sidewall BKL1_S of the first barrier layer BKL1.

[0058] Each of the first portion P1a and the second portion P1b may have a constant width. In an example, the width of each of the first portion P1a and the second portion P1b in the first direction D1 may be constant. The first portion P1a and the second portion P1b may have different widths. The width of the second portion P1b may be greater than the width of the first portion P1a. In an example, the width of the first portion P1a in the first direction D1 may be defined as a fifth width W5, and the width of the second portion P1b in the first direction D1 may be defined as a sixth width W6. The sixth width W6 may be greater than the fifth width W5. In an example, the fifth width W5 may be equal to the second width W2.

[0059] The first protrusion P1 may be disposed between the top surface SL2_T of the second source layer SL2 and the bottom surface TL1_B of the first tunnel insulating layer TL1. The first protrusion P1 may be disposed between the first barrier layer BKL1 and the channel structure CS.

[0060] The first portion P1a of the first protrusion P1 may be disposed between the bottom surface TL1_B of the first tunnel insulation layer TL1 and the bottom surface DL1_B of the first data storage layer DL1. The first portion P1a of the first protrusion P1 may be disposed between the channel layer CL and the sidewall DL1_S of the first data storage layer DL1. The second portion P1b of the first protrusion P1 may be disposed between the bottom surface DL1_B of the first data storage layer DL1 and the bottom surface BKL1_B of the first barrier layer BKL1. The second portion P1b of the first protrusion P1 may be disposed between the channel layer CL and the sidewall BKL1_S of the first barrier layer BKL1.

[0061] The first protrusion P1 may be a portion of the second source layer SL2. The first protrusion P1 may include a semiconductor material. In an example, the first protrusion P1 may include doped polysilicon.

[0062] The second protrusion P2 may protrude from the bottom surface SL2_B of the second source layer SL2 in an opposite direction to the third direction D3. The second protrusion P2 may protrude toward the first source layer SL1.

[0063] The second protrusion P2 may have a ring shape surrounding the channel structure CS. The second protrusion P2 may protrude between the second memory layer ML2 and the channel structure CS. The second protrusion P2 may protrude between the second barrier layer BKL2 of the second memory layer ML2 and the channel structure CS.

[0064] The second protrusion P2 may contact the top surface TL2_T of the second tunnel insulating layer TL2, the sidewall DL2_S of the second data storage layer DL2, the top surface DL2_T of the second data storage layer DL2, and the sidewall BKL2_S of the second barrier layer BKL2. The second protrusion P2 may be located at the same level as the etch stop layer ES. At least a portion of the second protrusion P2 and at least a portion of the etch stop layer ES may be located at the same level.

[0065] The top surface TL2_T of the second tunnel insulating layer TL2, the top surface DL2_T of the second data storage layer DL2, and the top surface BKL2_T of the second barrier layer BKL2 may have different levels. The top surface DL2_T of the second data storage layer DL2 may be located at a level lower than that of the top surface BKL2_T of the second barrier layer BKL2. The top surface TL2_T of the second tunnel insulating layer TL2 may be located at a level lower than that of the top surface DL2_T of the second data storage layer DL2. The bottom surface SL2_B of the second source layer SL2 may contact the top surface BKL2_T of the second barrier layer BKL2.

[0066] The second protrusion P2 may have a stepped structure. The surface of the second protrusion P2 contacting the second tunnel insulating layer TL2, the second data storage layer DL2, and the second barrier layer BKL2 may have a stepped shape. The surface of the second protrusion P2 may be formed in a stepped shape along the top surface TL2_T of the second tunnel insulating layer TL2, the side wall DL2_S of the second data storage layer DL2, the top surface DL2_T of the second data storage layer DL2, and the side wall BLK2_S of the second barrier layer BKL2.

[0067] The second protrusion P2 may include a third portion P2a and a fourth portion P2b. The third portion P2a may contact the top surface TL2_T of the second tunnel insulating layer TL2 and the sidewall DL2_S of the second data storage layer DL2. The fourth portion P2b may contact the top surface DL2_T of the second data storage layer DL2 and the sidewall BKL2_S of the second barrier layer BKL2.

[0068] Each of the third portion P2a and the fourth portion P2b may have a constant width. In an example, the width of each of the third portion P2a and the fourth portion P2b in the first direction D1 may be constant. The third portion P2a and the fourth portion P2b may have different widths. The width of the fourth portion P2b may be greater than the width of the third portion P2a. In an example, the width of the third portion P2a in the first direction D1 may be defined as a seventh width W7, and the width of the fourth portion P2b in the first direction D1 may be defined as an eighth width W8. The eighth width W8 may be greater than the seventh width W7. In an example, the seventh width W7 may be equal to the fourth width W4.

[0069] The second protrusion P2 may be disposed between the bottom surface SL2_B of the second source layer SL2 and the top surface TL2_T of the second tunnel insulating layer TL2. The second protrusion P2 may be disposed between the second barrier layer BKL2 and the channel structure CS.

[0070] The third portion P2a of the second protrusion P2 may be disposed between the top surface TL2_T of the second tunnel insulation layer TL2 and the top surface DL2_T of the second data storage layer DL2. The third portion P2a of the second protrusion P2 may be disposed between the channel layer CL and the sidewall DL2_S of the second data storage layer DL2. The fourth portion P2b of the second protrusion P2 may be disposed between the top surface DL2_T of the second data storage layer DL2 and the top surface BKL2_T of the second barrier layer BKL2. The fourth portion P2b of the second protrusion P2 may be disposed between the sidewall BKL2_S of the channel layer CL and the second barrier layer BKL2.

[0071] The second protrusion P2 may be a portion of the second source layer SL2. The second protrusion P2 may include a semiconductor material. In an example, the second protrusion P2 may include doped polysilicon.

[0072] The first insulating layer 120 may be disposed on the stack structure STA. The first insulating layer 120 may cover the channel structure CS and the first memory layer ML1. The first insulating layer 120 may include an insulating material. In an example, the first insulating layer 120 may include an oxide.

[0073] A slit structure SLS penetrating the stack structure STS and the first insulating layer 120 may be provided. The slit structure SLS may extend in the second direction D2. The slit structure SLS may extend in the third direction D3. The slit structure SLS may penetrate the stack structure STS and the first insulating layer 120 in the third direction D3. The slit structure SLS may be disposed between the channel structures CS. The channel structure CS of the first group and the channel structure CS of the second group may be spaced apart from each other in the first direction D1, with the slit structure SLS interposed therebetween.

[0074] The slit structure SLS may include a first spacer SP1, a second spacer SP2, and a common source line CSL. The second spacer SP2 may be disposed on both sides of the common source line CSL. The second spacers SP2 may be spaced apart from each other in the first direction D1. The common source line CSL may be disposed between the second spacers SP2. The second spacer SP2 may be formed along both sidewalls of the common source line CSL.

[0075] The first spacers SP1 may be disposed at both sides of the common source line CSL. The first spacers SP1 may be spaced apart from each other in the first direction D1. The second spacers SP2 and the common source line CSL may be disposed between the first spacers SP1. The first spacers SP1 may be formed along sidewalls of the second spacers SP2.

[0076] The common source line CSL may be electrically connected to the source structure SCS. The common source line CSL may be electrically connected to the second source layer SL2. The common source line CSL may be integrally formed with the second source layer SL2. In other words, the common source line CSL may be coupled to the second source layer SL2 without any border. The common source line CSL and the conductive pattern CP may be electrically isolated from each other by the first spacer SP1 and the second spacer SP2.

[0077] Each of the first spacer SP1, the second spacer SP2, and the common source line CSL may extend in the second direction D2 and the third direction D3. The first spacer SP1 may have a curved bottom surface.

[0078] A portion of the barrier film BR may be formed between the insulating pattern IP and the first spacer SP1 of the stack structure STS.

[0079] The first spacer SP1 may include a first portion extending in the third direction D3 and a second portion protruding from the first portion. The second portion may protrude from the first portion in the first direction D1 or in an opposite direction to the first direction D1. The second portion may contact the conductive pattern CP.

[0080] The first spacer SP1 may include an insulating material. In an example, the first spacer SP1 may include an oxide. The second spacer SP2 may include an insulating material. In an example, the second spacer SP2 may include a nitride. The common source line CSL may include a conductive material. In an example, the common source line CSL may include at least one of doped polysilicon and tungsten.

[0081] A bit line contact BCT connected to the channel structure CS may be provided. The bit line contact BCT may be electrically connected to the channel layer CL of the channel structure CS. The bit line contact BCT may penetrate the first insulating layer 120. The bit line contact BCT may include a conductive material. In an example, the bit line contact BCT may include tungsten, aluminum, or copper. The bit line contact BCT may be connected to a bit line.

[0082] The material included in the etch stop layer may have an etching selectivity with respect to the material included in each of the first source layer SL1, the second source layer SL2, the insulating pattern IP, and the first spacer SP1 and the second spacer SP2. The material included in the etch stop layer ES may have an etching selectivity with respect to the material included in each of the first tunnel insulating layer TL1 and the second tunnel insulating layer TL2, the first data storage layer DL1 and the second data storage layer DL2, the first barrier layer BKL1 and the second barrier layer BKL2, and the channel layer CL. In an example, the material included in the etch stop layer ES may have an etching selectivity with respect to oxide, nitride, and semiconductor material.

[0083] In the semiconductor device according to these embodiments, the first protrusion P1 as a part of the second source layer SL2 can be formed in a stepped shape. Therefore, the contact area between the second source layer SL2 and the channel structure CS can be increased. In addition, the first protrusion P1 is formed relatively close to the source selection line, so the junction overlap region of the channel layer CL can be formed relatively easily.

[0084] In the example, the junction overlap region is formed without any high heat treatment process, so that the characteristic change of the source selection line caused by the high heat treatment process can be prevented. Therefore, a stable gate induced drain leakage (GIDL) current can be generated during the erase operation, and the cut-off leakage of the source selection line can be minimized. Therefore, the reliability of the erase operation can be ensured. In addition, the characteristics of the source selection line are improved, so that the number of source selection lines can be minimized.

[0085] Figure 2Ais a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 2B yes Figure 2A An enlarged view of area E is shown.

[0086] The semiconductor device according to these embodiments can be used with Figures 1A to 1E The semiconductor memory devices shown are similar.

[0087] Reference Figure 2A and Figure 2B , the first barrier layer BLK1 may include a first barrier portion BKL1a and a second barrier portion BKL1b. The first barrier portion BKL1a may be a portion surrounding the first data storage layer DL1. The second barrier portion BKL1b may be a portion spaced apart from the first data storage layer DL1.

[0088] The first blocking portion BKL1a may have a constant width. The second blocking portion BKL1b may have a constant width. The width of the second blocking portion BKL1b may be smaller than the width of the first blocking portion BKL1a. In an example, the width of the first blocking portion BKL1a in the first direction D1 may be defined as a first width W1, and the width of the second blocking portion BKL1b in the first direction may be defined as a second width W2. The first width W1 may be greater than the second width W2.

[0089] An upper portion of the second barrier portion BKL1b and a lower portion of the first barrier portion BKL1a may be connected to each other. A bottom surface of the second barrier portion BKL1b may be at the same level as a bottom surface of the lowermost insulation pattern IP of the stack structure STS.

[0090] The second source layer SL2 may include a third protrusion P3. The third protrusion P3 may protrude from the top surface of the second source layer SL2 in the third direction D3. The third protrusion P3 may contact the bottom surface of the first tunnel insulating layer TL1, the bottom surface of the first data storage layer DL1, the bottom surface of the first barrier BKL1a, and the sidewalls of the second barrier BKL1b.

[0091] The bottom surface of the first tunnel insulating layer TL1, the bottom surface of the first data storage layer DL1, and the bottom surface of the first barrier BKL1a may be located at the same level. The third protrusion P3 may be disposed between the sidewalls of the channel layer CL and the second barrier BKL1b. The second barrier BKL1b may surround the third protrusion P3. The first barrier BKL1a may be located at a level higher than that of the third protrusion P3. The second barrier BKL1b may be located at the same level as the third protrusion P3.

[0092] The second barrier layer BKL2 may include a third barrier portion BKL2a and a fourth barrier portion BKL2b. The third barrier portion BKL2a may be a portion surrounding the second data storage layer DL2. The fourth barrier portion BKL2b may be a portion spaced apart from the second data storage layer DL2.

[0093] The third blocking portion BKL2a may have a constant width. The fourth blocking portion BKL2b may have a constant width. The width of the fourth blocking portion BKL2b may be smaller than the width of the third blocking portion BKL2a. In an example, the width of the third blocking portion BKL2a in the first direction D1 may be defined as a third width W3, and the width of the fourth blocking portion BKL2b in the first direction D1 may be defined as a fourth width W4. The third width W3 may be greater than the fourth width W4.

[0094] A lower portion of the fourth barrier BKL2b and an upper portion of the third barrier BKL2a may be connected to each other. A top surface of the fourth barrier BKL2b may be at a level higher than that of the etch stop layer ES.

[0095] The second source layer SL2 may include a fourth protrusion P4. The fourth protrusion P4 may protrude from the bottom surface of the second source layer SL2 in an opposite direction to the third direction D3. The fourth protrusion P4 may contact a top surface of the second tunnel insulating layer TL2, a top surface of the second data storage layer DL2, a top surface of the third barrier BKL2a, and a sidewall of the fourth barrier BKL2b.

[0096] The top surface of the second tunnel insulating layer TL2, the top surface of the second data storage layer DL2, and the top surface of the third barrier BKL2a may be located at the same level. The fourth protrusion P4 may be disposed between the channel layer CL and the sidewall of the fourth barrier BKL2b. The fourth barrier BKL2b may surround the fourth protrusion P4. The third barrier BKL2a may be located at a level lower than that of the fourth protrusion P4. The fourth barrier BKL2b may be located at the same level as the fourth protrusion P4.

[0097] In the semiconductor device according to the embodiments, the third protrusion P3 is formed relatively close to the source selection line, and thus the junction overlap region of the channel layer CL may be relatively easily formed.

[0098] In the example, the junction overlap region is formed without any high heat treatment process, so that the characteristic change of the source selection line caused by the high heat treatment process can be prevented. Therefore, a GIDL current can be generated during an erase operation, and the cut-off leakage of the source selection line can be minimized. Therefore, the reliability of the erase operation can be ensured. In addition, the characteristics of the source selection line are improved, so that the number of source selection lines can be minimized.

[0099] FIG. 3A to FIG. 3K It is shown Figures 1A to 1E A cross-sectional view of a method for manufacturing a semiconductor device shown.

[0100] For the convenience of description, refer to Figures 1A to 1E The described components are referred to by like reference numerals, and duplicate descriptions will be omitted.

[0101] The following manufacturing method is only Figures 1A to 1E An embodiment of a method for manufacturing a semiconductor memory device is shown, and Figures 1A to 1E The manufacturing method of the semiconductor memory device shown may not be limited to the method described below.

[0102] Reference Figure 3A , an etch stop layer ES and a source sacrificial layer SFL may be sequentially formed on the first source layer SL1. The first source layer SL1, the etch stop layer ES, and the source sacrificial layer SFL may be sequentially stacked in the third direction D3. The first source layer SL1 and the source sacrificial layer SFL may be spaced apart from each other in the third direction D3, and the etch stop layer ES may be disposed between the first source layer SL1 and the source sacrificial layer SFL.

[0103] The first source layer SL1 may include a semiconductor material. In an example, the first source layer SL1 may include polysilicon. The etch stop layer ES may include an insulating material. In an example, the etch stop layer ES may include at least one of SiCO and SiCN. The source sacrificial layer SFL may include a semiconductor material. In an example, the source sacrificial layer SFL may include polysilicon.

[0104] Reference Figure 3B , a stacked structure STS may be formed on the source sacrificial layer SFL. The stacked structure STS may include stacked insulating layers IL and stacked sacrificial layers FL. The stacked insulating layers IL and the stacked sacrificial layers FL may be alternately stacked in the third direction D3. The stacked insulating layer IL may be disposed on the source sacrificial layer SFL, and the stacked insulating layers IL and the stacked sacrificial layers FL may be alternately stacked on the stacked insulating layer IL.

[0105] The stacked insulating layer IL and the stacked sacrificial layer FL may include an insulating material. In an example, the stacked insulating layer IL may include an oxide. In an example, the stacked sacrificial layer FL may include a nitride.

[0106] Although the case where the stacked sacrificial layer FL is replaced with the conductive pattern CP after the stacked insulating layer IL and the stacked sacrificial layer FL is described in the embodiments, the present disclosure is not limited thereto. In an example, the channel structure CS and the memory layer ML may be formed after alternately forming the stacked insulating layer IL and the conductive layer.

[0107] Reference Figure 3C, a channel structure CS and a memory layer ML penetrating the stacked structure STS, the source sacrificial layer SFL, and the etch stop layer ES may be formed. The channel structure CS and the memory layer ML may penetrate the stacked insulating layer IL and the stacked sacrificial layer FL of the stacked structure STS.

[0108] The channel structure CS may include a channel layer CL and a filling layer FI. The memory layer ML may include a tunnel insulating layer TL, a data storage layer DL, and a barrier layer BKL.

[0109] The process of forming the channel structure CS and the memory layer ML may include a process of forming a first hole HO1 penetrating the stack structure STS, the source sacrificial layer SFL and the etch stop layer ES, and a process of sequentially forming a blocking layer BKL, a data storage layer DL, a tunnel insulating layer TL, a channel layer CL and a filling layer FI in the first hole HO1.

[0110] In an example, the tunnel insulating layer TL may include an oxide including nitrogen. The data storage layer DL may include a material that can capture charges. In an example, the data storage layer DL may include a nitride. The blocking layer BKL may include a material capable of blocking the movement of charges. In an example, the blocking layer BKL may include an oxide. In an example, the blocking layer BKL may not include nitrogen.

[0111] In an example, the concentration of nitrogen of the tunnel insulating layer TL may be higher than the concentration of nitrogen of the blocking layer BKL. In an example, the tunnel insulating layer TL may include nitrogen, and the blocking layer BKL may not include nitrogen.

[0112] The width of the blocking layer BKL may be greater than the width of the tunnel insulating layer TL. In an example, the width of the blocking layer BKL in the first direction D1 may be greater than the width of the tunnel insulating layer TL in the first direction D1.

[0113] A first trench TR1 penetrating the stack structure STS may be formed. The first trench TR1 may extend in the second direction D2. The first trench TR1 may penetrate the stacked insulating layer IL and the stacked sacrificial layer FL of the stack structure STS. The bottom surface of the first trench TR1 may be located in the source sacrificial layer SFL. The bottom surface of the first trench TR1 may be defined by the source sacrificial layer SFL. The bottom surface of the first trench TR1 may be located between the top surface and the bottom surface of the source sacrificial layer SFL.

[0114] According to the process of forming the first hole HO1 and the process of forming the first trench TR1 , the stacked insulating layer IL and the stacked sacrificial layer FL may be patterned to form the insulating pattern IP and the sacrificial pattern FP.

[0115] Reference Figure 3D , a sacrificial oxide layer FOL, a conductive pattern CP and a barrier film BR may be formed.

[0116] The sacrificial oxide layer FOL may be formed by oxidizing a portion of the source sacrificial layer SFL. The surface of the source sacrificial layer SFL exposed by the first trench TR1 may be oxidized to form the sacrificial oxide layer FOL. In an example, the surface of the source sacrificial layer SFL may be oxidized by supplying oxygen through the first trench TR1. The sacrificial oxide layer FOL may include an insulating material. In an example, the sacrificial oxide layer FOL may include an oxide.

[0117] The process of forming the conductive pattern CP and the barrier film BR may include a process of forming a blank space between the insulating patterns IP by selectively removing the sacrificial pattern FP, a process of forming the barrier film BR along the surface of the insulating pattern IP, the surface of the channel structure CS and the surface of the sacrificial oxide layer FOL, a process of filling the blank space by forming a conductive layer along the surface of the barrier film BR, and a process of forming the conductive pattern CP by patterning the conductive layer.

[0118] The conductive layer may completely fill the empty space and fill a portion of the first trench TR1. Portions of the conductive layer formed in the empty space may be isolated from each other, thereby forming a conductive pattern CP.

[0119] Reference Figure 3E , a spacer SP may be formed in the first trench TR1. The spacer SP may include an insulating material. In an example, the spacer SP may include first to fourth spacers SP1, SP2, SP3, and SP4. The process of forming the spacer SP may include a process of forming a first spacer SP1 on the surface of the barrier film BR and the conductive pattern CP, a process of forming a second spacer SP2 on the surface of the first spacer SP1, a process of forming a third spacer SP3 on the surface of the second spacer SP2, and a process of forming a fourth spacer SP4 on the surface of the third spacer SP3.

[0120] The spacer SP may fill a portion of the first trench TR1. In other words, the spacer SP may not completely fill the first trench TR1. The portion of the first trench TR1 not filled by the spacer SP may be defined as the second trench TR2. The second trench TR2 may extend in the second direction D2. The surface of the fourth spacer SP4 may be exposed through the second trench TR2. The second trench TR2 may be defined by the surface of the fourth spacer SP4.

[0121] The first to fourth spacers SP1, SP2, SP3, and SP4 may include an insulating material. In an example, the first spacer SP1 and the third spacer SP3 may include an oxide. In an example, the second spacer SP2 and the fourth spacer SP4 may include a nitride.

[0122] Reference Figure 3F, a third trench TR3 may be formed. The third trench TR3 may extend in the second trench TR2. The third trench TR3 may penetrate the spacer SP and the sacrificial oxide layer FOL. The third trench TR3 may penetrate the first to fourth spacers SP1, SP2, SP3, and SP4. The bottom surface of the third trench TR3 may be located in the source sacrificial layer SFL. In an example, the third trench TR3 may be formed by an etch-back process. When the third trench TR3 is formed, the source sacrificial layer SFL may be exposed. The source sacrificial layer SFL may be exposed through the second trench TR2 and the third trench TR3.

[0123] Reference Figure 3G , the source sacrificial layer SFL may be removed. The source sacrificial layer SFL may include a material different from that of the etch stop layer ES. The material included in the source sacrificial layer SFL may have an etching selectivity relative to the material included in the etch stop layer ES. The source sacrificial layer SFL may include a material different from that of the spacer SP. The material included in the source sacrificial layer SFL may have an etching selectivity relative to the material included in the spacer SP. The source sacrificial layer SFL may include a material different from that of the sacrificial oxide layer FOL. The material included in the source sacrificial layer SFL may have an etching selectivity relative to the material included in the sacrificial oxide layer FOL.

[0124] The source sacrificial layer SFL may be removed by an etching process. The source sacrificial layer SFL may be removed by a wet etching process or a dry etching process. The etching process may be performed using an etching material capable of selectively removing the source sacrificial layer SFL.

[0125] When the source sacrificial layer SFL is removed, a first cavity CA1 may be formed. An empty space formed by removing the source sacrificial layer SFL may be defined as the first cavity CA1. When the first cavity CA1 is formed, a top surface of the etch stop layer ES may be exposed, the barrier layer BKL of the memory layer ML may be exposed, and a bottom surface of the lowermost insulating pattern IP of the stack structure STS may be exposed.

[0126] A portion of the barrier layer BKL exposed by the first cavity CA1 may be defined as a first exposed region BKL_E. When the source sacrificial layer SFL is removed, the first exposed region BKL_E of the barrier layer BKL may be exposed. The first exposed region BKL_E of the barrier layer BKL may be disposed between the stack structure STS and the etch stop layer ES.

[0127] Reference Figure 3H, the first exposed area BKL_E of the blocking layer BKL may be removed. The first exposed area BKL_E of the blocking layer BKL may be removed by an etching process. The process of removing the first exposed area BKL_E of the blocking layer BKL may be performed using a first etching material. In an example, the first exposed area BKL_E of the blocking layer BKL may be removed by a dry etching process. In an example, the dry etching process may be a dry cleaning process.

[0128] When the first exposed region BKL_E of the barrier layer BKL is removed, the barrier layer BKL may be separated into the first barrier layer BKL1 and the second barrier layer BKL2. The first barrier layer BLK1 and the second barrier layer BKL2 may be spaced apart from each other in the third direction DR3.

[0129] The etch stop layer ES may prevent the first source layer SL1 from being exposed when the first exposed region BKL_E of the blocking layer BKL is removed. The etch stop layer ES may protect the first source layer SL1 from being affected by the first etching material when the first exposed region BKL_E of the blocking layer BKL is removed.

[0130] The sacrificial oxide layer FOL may be removed at the same time as the first exposed region BKL_E of the blocking layer BKL is removed or through a separate process.

[0131] Portions of the first spacer SP1 and the third spacer SP3 may be removed at the same time as the first exposed region BKL_E of the barrier layer BKL is removed or through a separate process. Portions of the first spacer SP1 exposed by the third trench TR3 may be removed, and portions of the third spacer SP3 exposed by the third trench TR3 may be removed.

[0132] The material included in the fourth spacer SP4 may have an etching selectivity with respect to the material included in the blocking layer BKL. The first to third spacers SP1, SP2, and SP3 may be protected by the fourth spacer SP4.

[0133] When the first exposed region BKL_E of the barrier layer BKL is removed, the first cavity CA1 may expand, and the data storage layer DL may be exposed through the first cavity CA1.

[0134] A portion of the data storage layer DL exposed by the first cavity CA1 may be defined as a second exposure area DL_E. When the first exposure area BKL_E of the barrier layer BKL is removed, the second exposure area DL_E of the data storage layer DL may be exposed. The second exposure area DL_E of the data storage layer DL may be disposed between the stack structure STS and the etch stop layer ES.

[0135] Reference Fig. 3I, the second exposed area DL_E of the data storage layer DL may be removed. The second exposed area DL_E of the data storage layer DL may be removed by an etching process. The process of removing the second exposed area DL_E of the data storage layer DL may be performed using a second etching material.

[0136] In an example, the second etching material may be a material capable of etching nitride. In an example, the second etching material may include phosphoric acid and water. In an example, the second etching material may further include another material as well as phosphoric acid and water.

[0137] The second etching material may etch nitride faster than the second etching material etches oxide. In an example, the second etching material may etch nitride five to twenty times faster than the second etching material etches oxide.

[0138] In an example, the second exposed area DL_E of the data storage layer DL may be removed by a wet etching process. In an example, the wet etching process may be a leaching process.

[0139] When the second exposed area DL_E of the data storage layer DL is removed, the data storage layer DL may be separated into the first data storage layer DL1 and the second data storage layer DL2. The first data storage layer DL1 and the second data storage layer DL2 may be spaced apart from each other in the third direction D3.

[0140] When the second exposed area DL_E of the data storage layer DL is removed, a portion of the data storage layer DL adjacent to the second exposed area DL_E may be removed together. Therefore, the bottom surface of the first data storage layer DL1 may be located at a level higher than that of the bottom surface of the first barrier layer BKL1, and the top surface of the second data storage layer DL2 may be located at a level lower than that of the top surface of the second barrier layer BLK2.

[0141] When the second exposed region DL_E of the data storage layer DL is removed, the first cavity CA1 may expand, and the tunnel insulating layer TL may be exposed through the first cavity CA1.

[0142] A portion of the tunnel insulating layer TL exposed by the first cavity CA1 may be defined as a third exposed region TL_E. When the second exposed region DL_E of the data storage layer DL_E is removed, the third exposed region TL_E of the tunnel insulating layer TL may be exposed. The third exposed region TL_E of the tunnel insulating layer TL may be disposed between the bottom surface of the first data storage layer DL1 and the top surface of the second data storage layer DL2.

[0143] When the second exposed area DL_E of the data storage layer DL_E is removed, a portion of the third exposed area TL_E of the tunnel insulation layer TL may be removed together with the second exposed area DL_E of the data storage layer DL_E. A portion of the third exposed area TL_E of the tunnel insulation layer TL may be removed by the second etching material that removes the data storage layer DL.

[0144] In an example, the tunnel insulating layer TL may be etched slower than the data storage layer DL by the second etching material. Therefore, when the second exposed region DL_E of the data storage layer DL_E is removed, a portion of the third exposed region TL_E of the tunnel insulating layer TL may remain.

[0145] In an example, since the nitrogen concentration of the tunnel insulating layer TL is lower than that of the data storage layer DL, a portion of the third exposed region TL_E of the tunnel insulating layer TL may remain when the second exposed region DL_E of the data storage layer DL is removed.

[0146] A portion of the third exposed region TL_E of the tunnel insulating layer TL that is not removed but remains may be defined as a remaining portion TL_R. The remaining portion TL_R of the tunnel insulating layer TL may be located between the first cavity CA1 and the channel structure CS.

[0147] When portions of the second exposed region DL_E of the data storage layer DL and the third exposed region TL_E of the tunnel insulating layer TL are removed, the first and second barrier layers BKL1 and BLK2 may not be etched.

[0148] In an example, since the nitrogen concentration of the first and second barrier layers BKL1 and BKL2 is lower than that of the tunnel insulating layer TL, the first and second barrier layers BKL1 and BKL2 may not be etched, or the etching amount of the first and second barrier layers BKL1 and BKL2 may be less than that of the tunnel insulating layer TL.

[0149] The etch stop layer ES may prevent the first source layer SL from being exposed when the second exposed area DL_E of the data storage layer DL and the third exposed area TL_E of the tunnel insulating layer TL are removed. The etch stop layer ES may protect the first source layer SL1 from being affected by the second etching material when the second exposed area DL_E of the data storage layer DL and the third exposed area TL_E of the tunnel insulating layer TL are removed.

[0150] The fourth spacer SP4 may be removed at the same time as the second exposed region DL_E of the data storage layer DL and the third exposed region TL_E of the tunnel insulating layer TL are removed or by a separate process. When the fourth spacer SP4 is removed, the sidewall of the third spacer SP3 may be exposed.

[0151] A portion of the second spacer SP2 may be removed at the same time as the second exposed region DL_E of the data storage layer DL and the third exposed region TL_E of the tunnel insulation layer TL are removed or by a separate process. A portion of the second spacer SP2 exposed by the third trench TR3 may be removed.

[0152] When the data storage layer DL is etched, the first spacers SP1 and the second spacers SP2 may be protected by the third spacers SP3.

[0153] Reference Figure 3J , the remaining portion TL_R of the tunnel insulating layer TL may be removed. The remaining portion TL_R of the tunnel insulating layer TL may be removed by an etching process. The process of removing the remaining portion TL_R of the tunnel insulating layer TL may be performed using a third etching material. In an example, the third etching material may be a material capable of etching an oxide containing nitrogen. In an example, the remaining portion TL_R of the tunnel insulating layer TL may be etched by a dry etching process. In an example, the dry etching process may be a dry cleaning process.

[0154] When the remaining portion TL_R of the tunnel insulation layer TL is etched, the tunnel insulation layer TL may be separated into the first tunnel insulation layer TL1 and the second tunnel insulation layer TL2. The first tunnel insulation layer TL1 and the second tunnel insulation layer TL2 may be spaced apart from each other in the third direction D3.

[0155] When the remaining portion TL_R of the tunnel insulation layer TL is removed, a portion of the tunnel insulation layer TL adjacent to the remaining portion TL_R of the tunnel insulation layer TL may be removed together with the remaining portion TL_R of the tunnel insulation layer TL. Therefore, the bottom surface of the first tunnel insulation layer TL1 may be located at a level higher than that of the bottom surface of the first data storage layer DL1, and the top surface of the second tunnel insulation layer TL2 may be located at a level lower than that of the top surface of the second data storage layer DL2.

[0156] When the remaining portion TL_R of the tunnel insulating layer TL is removed, the first cavity CA1 may be expanded. The channel structure CS may be exposed through the first cavity CA1.

[0157] The remaining portion TL_R of the tunnel insulating layer TL may be selectively etched relative to the first barrier layer BKL1 and the second barrier layer BKL2. In other words, when the remaining portion TL_R of the tunnel insulating layer TL is etched, the first barrier layer BKL1 and the second barrier layer BKL2 may not be etched, or the etching amount of the first barrier layer BKL1 and the second barrier layer BKL2 may be less than the etching amount of the remaining portion TL_R of the tunnel insulating layer TL. When the remaining portion TL_R of the tunnel insulating layer TL is removed, the first barrier layer BKL1 and the second barrier layer BKL2 may not be lost.

[0158] The remaining portion TL_R of the tunnel insulating layer TL may be selectively etched under the condition that the tunnel insulating layer TL has a high etching selectivity with respect to the first and second barrier layers BKL1 and BKL2. In an example, the condition that the tunnel insulating layer TL has a high etching selectivity with respect to the first and second barrier layers BKL1 and BKL2 may correspond to a difference in nitrogen concentration between the first and second barrier layers BKL1 and BKL2.

[0159] In an example, the remaining portion TL_R of the tunnel insulating layer TL may be selectively etched by allowing a material included in the tunnel insulating layer TL and materials included in the first and second barrier layers BKL1 and BKL2 to be different from each other and using a material capable of selectively etching the tunnel insulating layer TL.

[0160] In an example, since the nitrogen concentration of the first and second barrier layers BKL1 and BKL2 is lower than that of the tunnel insulating layer TL, the first and second barrier layers BKL1 and BKL2 may not be etched, or the etching amount of the first and second barrier layers BKL1 and BKL2 may be less than that of the tunnel insulating layer TL.

[0161] The etch stop layer ES may prevent the first source layer SL from being exposed when the remaining portion TL_R of the tunnel insulating layer TL is removed. The etch stop layer ES may protect the first source layer SL1 from the third etching material when the remaining portion TL_R of the tunnel insulating layer TL is removed.

[0162] When the first tunnel insulating layer TL1 and the second tunnel insulating layer TL2 are formed due to the removal of the remaining portion TL_R of the tunnel insulating layer TL, the first memory layer ML1 including the first tunnel insulating layer TL1, the first data storage layer DL1, and the first barrier layer BKL1 may be formed, and the second memory layer ML2 including the second tunnel insulating layer TL2, the second data storage layer DL2, and the second barrier layer BKL2 may be formed. The first memory layer ML1 and the second memory layer ML2 may be spaced apart from each other in the third direction D3.

[0163] The space formed between the first barrier layer BKL1 and the channel structure may be defined by the second cavity CA2. The space formed between the second barrier layer BKL2 and the channel structure CS may be defined as a third cavity CA3. The second cavity CA2 may be defined by the channel layer CL, the bottom surface of the first tunnel insulating layer TL1, the bottom surface and sidewalls of the first data storage layer DL1, and the sidewalls of the first barrier layer BKL1. The third cavity CA3 may be defined by the channel layer CL, the top surface of the second tunnel insulating layer TL2, the top surface and sidewalls of the second data storage layer DL2, and the sidewalls of the second barrier layer BKL2.

[0164] The third spacer SP3 may be removed at the same time as the remaining portion TL_R of the tunnel insulating layer TL is removed or through a separate process. When the third spacer SP3 is removed, the sidewalls of the second spacer SP2 may be exposed.

[0165] When the tunnel insulating layer TL is etched, the first spacer SP1 may be protected by the second spacer SP2 .

[0166] A portion of the first spacer SP1 may be removed at the same time as the remaining portion TL_R of the tunnel insulation layer TL is removed or through a separate process. When a portion of the first spacer SP1 is removed, the first spacer SP1 may have a curved bottom surface.

[0167] Reference Figure 3K , a second source layer SL2 may be formed between the first source layer SL1 and the stacked structure STS. The second source layer SL2 may be electrically connected to the channel layer CL of the channel structure CS. The second source layer SL2 may include a first protrusion P1 in the second cavity CA2 and a second protrusion P2 in the third cavity CA3. The second source layer SL2 may include a semiconductor material. In an example, the second source layer SL2 may include doped polysilicon.

[0168] The dopant in the second source layer SL2 may diffuse into the channel layer CL. In an example, the dopant may diffuse into the channel layer CL through a thermal treatment process. The dopant in the second source layer SL2 may diffuse into the channel layer CL through the first protrusion P1 of the second source layer SL2 and form a junction overlap region.

[0169] In the method for manufacturing a semiconductor device according to these embodiments, a portion of the third exposed region TL_E of the tunnel insulating layer TL is removed while the second exposed region DL_E of the data storage layer DL is removed. Subsequently, the remaining portion TL_R of the tunnel insulating layer TL is removed. Therefore, the first tunnel insulating layer TL1 and the first data storage layer DL1 may define a stepped surface, and a first protrusion P1 having a stepped structure may be formed.

[0170] A common source line CSL connected to the second source layer SL2 may be formed. The common source line CSL may be formed while the second source layer SL2 is formed or after the second source layer SL2 is formed. The common source line CSL may be formed between the first spacers SP1. The common source line CSL may be formed between the second spacers SP2. The common source line CSL may be formed integrally with the second source layer SL2. In other words, the common source line CSL may be coupled to the second source layer SL2 without any border. The common source line CSL may include a conductive material. In an example, the common source line CSL may include at least one of doped polysilicon and tungsten.

[0171] FIG. 4A to FIG. 4C It is shown Figure 2A and Figure 2B A cross-sectional view of a method for manufacturing a semiconductor device shown.

[0172] Except for the following parts, the manufacturing method according to these embodiments can be FIG. 3A to FIG. 3K The manufacturing method shown is similar.

[0173] The following manufacturing method is only Figure 2A and Figure 2B An embodiment of a method for manufacturing a semiconductor memory device is shown, and Figure 2A and Figure 2B The manufacturing method of the semiconductor memory device shown may not be limited to the method described below.

[0174] Reference Figure 4A , similar to reference 3A to 3H The manufacturing method described may form a first source layer SL1, an etch stop layer ES, a stack structure, a channel structure CS, and a spacer SP. The stack structure STS may include a conductive pattern CP, an insulating pattern IP, and a barrier film BR. The spacer may include first to third spacers SP1, SP2, and SP3.

[0175] The barrier layer may be etched to form a first barrier layer BKL1 and a second barrier layer BKL2. The data storage layer may be etched to form a first data storage layer DL1 and a second data storage layer DL2. When the data storage layer is etched, a portion of the tunnel insulation layer TL may be removed together with the data storage layer, and a remaining portion TL_R of the tunnel insulation layer TL may be formed. In an example, since the concentration of nitrogen of the tunnel insulation layer TL is lower than the concentration of nitrogen of the data storage layer, the remaining portion TL_R of the tunnel insulation layer TL may remain.

[0176] Reference Figure 4B , the remaining portion TL_R of the tunnel insulating layer TL may be removed. The remaining portion TL_R of the tunnel insulating layer TL may be removed by an etching process. When the remaining portion TL_R of the tunnel insulating layer TL is removed, the tunnel insulating layer TL may be separated into a first tunnel insulating layer TL1 and a second tunnel insulating layer TL2.

[0177] The first tunnel insulation layer TL1 can be etched so that the level of the bottom surface of the first tunnel insulation layer TL1 is equal to the level of the bottom surface of the first data storage layer DL1, and the second tunnel insulation layer TL2 can be etched so that the level of the top surface of the second tunnel insulation layer TL2 is equal to the level of the top surface of the second data storage layer DL2.

[0178] When the remaining portion TL_R of the tunnel insulating layer TL is removed, portions of the first and second barrier layers BKL1 and BKL2 may be removed together with the remaining portion TL_R of the tunnel insulating layer TL. The remaining portion TL_R of the tunnel insulating layer TL may be etched so that the etching speed of the tunnel insulating layer TL is faster than that of the first and second barrier layers BKL1 and BKL2.

[0179] In the example, since the nitrogen concentration of the first and second barrier layers BKL1 and BKL2 is lower than that of the tunnel insulating layer TL, and the thickness of the first and second barrier layers BKL1 and BKL2 is thicker than that of the tunnel insulating layer TL, the second barrier portion BKL1b of the first barrier layer BKL1 and the fourth barrier portion BKL2b of the second barrier layer BKL2 may remain.

[0180] A portion of the first barrier layer BKL1 may be removed to define a first barrier portion BKL1a and a second barrier portion BKL1b. A bottom surface of the first barrier portion BKL1a may be formed at the same level as a bottom surface of the first tunnel insulating layer TL1 and a bottom surface of the first data storage layer DL1. A fourth cavity CA4 may be defined by a sidewall of the second barrier portion BKL1b, the first barrier portion BKL1a, a bottom surface of the first tunnel insulating layer TL1, and a bottom surface of the first data storage layer DL1.

[0181] A portion of the second barrier layer BKL2 may be removed to define a third barrier BKL2a and a fourth barrier BKL2b. A top surface of the third barrier BKL2a may be formed at the same level as a top surface of the second tunnel insulating layer TL2 and a top surface of the second data storage layer DL2. A fifth cavity CA5 may be defined by a sidewall of the fourth barrier BKL2b, a top surface of the third barrier BKL2a, a top surface of the second tunnel insulating layer TL2, and a top surface of the second data storage layer DL2.

[0182] The upper portion of the etch stop layer ES may be removed at the same time as the remaining portion TL_R of the tunnel insulating layer TL or by a separate process. Since the upper portion of the etch stop layer ES is removed, the level of the top surface of the etch stop layer ES may be lower than that of the second barrier layer BKL2.

[0183] Reference Figure 4C , a second source layer SL2 may be formed between the first source layer SL1 and the stack structure STS. The second source layer SL2 may include a third protrusion P3 in the fourth cavity CA4 and a fourth protrusion P4 in the fifth cavity CA5. Subsequently, a common source line CSL connected to the second source layer SL2 may be formed.

[0184] In the method for manufacturing a semiconductor device according to the embodiments, when the remaining portion TL_R of the tunnel insulating layer TL is removed, the first to fourth barrier portions BKL1a, BKL1b, BKL2a, and BKL2b are formed by removing portions of the first barrier layer BKL1 and the second barrier layer BKL2 together with the remaining portion TL_R of the tunnel insulating layer TL. Therefore, the fourth cavity CA4 and the fifth cavity CA5 may be formed, and the third protrusion P3 and the fourth protrusion P4 may be formed.

[0185] Figure 5 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0186] Reference Figure 5 , a memory system 1100 according to an embodiment of the present disclosure includes a memory device 1120 and a memory controller 1110 .

[0187] Memory device 1120 may include reference Figures 1A to 1E Describing the structure or reference Figure 2A and Figure 2B The memory device 1120 may be a multi-chip package configured using a plurality of flash memory chips.

[0188] The memory controller 1110 is configured to control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation of data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The ECC circuit 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. In addition, the memory controller 1110 may further include a ROM for storing code data and the like for interfacing with the host.

[0189] The memory system 1100 configured as described above may be a memory card or a solid state disk (SSD) in which the memory device 1120 is combined with the controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with the outside (e.g., a host) through one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0190] Figure 6 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure.

[0191] Reference Figure 6 The computing system 1200 according to an embodiment of the present disclosure may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210, which are electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), a mobile D-RAM, and the like may also be included.

[0192] The memory system 1210 may be as described with reference to Figure 5 The configuration is performed using a memory device 1212 and a memory controller 1211 .

[0193] In the semiconductor device according to the present disclosure, the junction overlap region of the channel layer can be formed relatively easily. Therefore, a stable GIDL current is generated during an erase operation, thereby ensuring the reliability of the erase operation.

[0194] Although the present disclosure is shown and described with reference to specific examples of its embodiments, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0195] In the above-mentioned embodiments, all steps may be selectively performed, or some steps may be omitted. In various embodiments, the steps may not be performed in the order described, but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0196] In addition, examples of embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, those terms are only used to illustrate the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and many changes can be made within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can also be made based on the technical scope of the present disclosure.

[0197] CROSS-REFERENCE TO RELATED APPLICATIONS

[0198] This application claims the priority benefit of Korean Patent Application No. 10-2020-0011397 filed on January 30, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Layered structure; a source structure, the source structure comprising a first protrusion protruding toward the stacked structure; a channel structure, the channel structure penetrating the stacked structure, the channel structure connected to the source structure; as well as a first barrier layer interposed between the channel structure and the stacked structure, The first barrier layer includes a first barrier portion and a second barrier portion, and the second barrier portion protrudes further toward the source structure than the first barrier portion. wherein the width of the second blocking portion is smaller than the width of the first blocking portion, and The first blocking portion is closer to the channel structure than the second blocking portion.

2. The semiconductor device according to claim 1, wherein The second barrier portion of the first barrier layer surrounds the first protrusion of the source structure.

3. The semiconductor device according to claim 1, wherein The source structure includes a first source layer and a second source layer interposed between the first source layer and the stacked structure, and Wherein, the second source layer is in contact with the channel structure.

4. The semiconductor device according to claim 3, further comprising a second barrier layer interposed between the channel structure and the first source layer, in, The second barrier layer includes a third barrier portion and a fourth barrier portion protruding further toward the second source layer, and Wherein, the width of the fourth blocking portion is smaller than the width of the third blocking portion.

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