Power device and preparation method thereof

Abstract

The invention discloses a power device and a preparation method thereof, and relates to the technical field of semiconductors. The semiconductor device comprises a semiconductor substrate, a first buffer layer, a second buffer layer, a third buffer layer, a barrier layer, a passivation layer, a first anode, a dielectric layer, a second anode, a cathode, a protection layer, anode conduction metal, cathode conduction metal and a field plate layer. The technical problem of large reverse electric leakage of the power device is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof. Background Art

[0002] A semiconductor device is a semiconductor device made by using a metal contact semiconductor layer. Compared with traditional semiconductor diodes, it has the characteristic of extremely short reverse recovery time. Therefore, semiconductor devices are widely used in switching power supplies, inverters, drivers and other circuits. Gallium nitride material is a third-generation wide bandgap semiconductor material. Due to its large bandgap width, high electron saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance and radiation resistance, it has become the best material for making short-wave optoelectronic devices and high-voltage, high-frequency and high-power devices. In summary, semiconductor devices made of gallium nitride materials combine the advantages of the above-mentioned semiconductor devices and gallium nitride materials, and have the advantages of fast switching speed, high field strength and good thermal performance, and have good development prospects in the power rectifier market.

[0003] However, the reverse leakage of traditional semiconductor device structures is very large, and the strongest electric field is concentrated at the edge of the anode, resulting in uneven distribution of electric field strength, reducing the electric field strength of the main Schottky junction, reducing the withstand voltage of GaN-based semiconductor devices, and affecting the performance of GaN-based semiconductor devices. Although many studies have proposed solutions to the problem of large reverse leakage of Schottky structures, such as using Schottky junction terminals to reduce reverse current, it is difficult to produce low-leakage semiconductor devices using COMS compatible processes. Summary of the invention

[0004] The purpose of the present invention is to provide a power device and a preparation method thereof, which solves the technical problem that the reverse leakage of semiconductor devices is large and it is difficult to manufacture semiconductor devices with low leakage using a CMOS compatible process.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a power device, comprising:

[0007] Semiconductor substrate;

[0008] A first buffer layer, which is disposed on the semiconductor substrate;

[0009] A second buffer layer, which is arranged on a side of the first buffer layer away from the semiconductor substrate;

[0010] a third buffer layer, which is arranged on a side of the second buffer layer away from the first buffer layer;

[0011] a barrier layer, which is arranged on a side of the third buffer layer away from the second buffer layer;

[0012] a passivation layer, which is arranged on a side of the barrier layer away from the third buffer layer;

[0013] a first anode penetrating the passivation layer and extending into the barrier layer;

[0014] a dielectric layer, which is arranged on a side of the passivation layer away from the barrier layer and between the first anode and the barrier layer;

[0015] A second anode, which penetrates the dielectric layer, the passivation layer and extends into the barrier layer;

[0016] a cathode, which is disposed on the dielectric layer and penetrates the dielectric layer and the passivation layer;

[0017] A protective layer, which is disposed on the first anode, the second anode, the cathode and the dielectric layer;

[0018] An anode conductive metal is disposed on a side of the protective layer away from the dielectric layer, and the anode conductive metal is connected to the first anode and the second anode;

[0019] A cathode conductive metal is disposed on a side of the protective layer away from the dielectric layer, and the cathode conductive metal is connected to the cathode;

[0020] A field plate layer is disposed on the protection layer, and the field plate layer is connected to the anode conductive metal, wherein the anode conductive metal, the cathode conductive metal and the field plate layer are formed synchronously.

[0021] The present invention also provides a gallium nitride epitaxial layer, which comprises:

[0022] Semiconductor substrate;

[0023] A first buffer layer, which is disposed on the semiconductor substrate;

[0024] A second buffer layer, which is arranged on a side of the first buffer layer away from the semiconductor substrate;

[0025] a third buffer layer, which is arranged on a side of the second buffer layer away from the first buffer layer;

[0026] The barrier layer is arranged on a side of the third buffer layer away from the second buffer layer.

[0027] In one embodiment of the present invention, the power device further includes a first anode contact hole, the first anode contact hole penetrates the passivation layer and extends into the barrier layer, and the first anode is disposed in the first anode contact hole.

[0028] In one embodiment of the present invention, the power device further includes a second anode contact hole, the second anode contact hole penetrates the dielectric layer, the passivation layer and extends into the barrier layer, and the second anode is disposed in the second anode contact hole.

[0029] In one embodiment of the present invention, the first buffer layer is aluminum nitride.

[0030] In one embodiment of the present invention, the first anode and the second anode include a first metal layer and a second metal layer, wherein the first metal layer is arranged on a side of the dielectric layer away from the passivation layer, and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer at the bottom of the first anode contact hole and the bottom of the second anode contact hole, and the second metal layer is arranged on the first metal layer and fills the first anode contact hole and the second anode contact hole.

[0031] In one embodiment of the present invention, the power device further includes a cathode contact hole, the cathode contact hole penetrates the dielectric layer and the passivation layer, and the cathode is disposed in the cathode contact hole.

[0032] The present invention also provides a method for preparing a power device, which comprises at least the following steps:

[0033] forming a first buffer layer, a second buffer layer, a third buffer layer and a barrier layer in sequence on the substrate;

[0034] forming a passivation layer on the barrier layer;

[0035] forming a first anode contact hole in the passivation layer and the barrier layer, wherein the first anode contact hole penetrates the passivation layer and extends into the barrier layer;

[0036] forming a dielectric layer on the passivation layer and in the first anode contact hole, and patterning the dielectric layer, the passivation layer and the barrier layer to form a second anode contact hole penetrating the dielectric layer, the passivation layer and extending into the barrier layer;

[0037] forming a first metal layer of an anode on the dielectric layer and in the second anode contact hole;

[0038] forming a cathode contact hole penetrating the dielectric layer and the passivation layer on the dielectric layer and the passivation layer;

[0039] forming a second metal layer of the anode on the dielectric layer and the first metal layer of the anode and in the cathode contact hole, thereby obtaining a first anode and a second anode including the first metal layer and the second metal layer and a cathode including the second metal layer;

[0040] forming a protective layer on the dielectric layer, the first anode, the second anode and the cathode;

[0041] The protection layer is patterned to form a field plate layer, and the field plate layer is connected to the first anode and the second anode.

[0042] In one embodiment of the present invention, the second metal layer and the cathode are formed simultaneously, and each of them is a multi-layer metal structure.

[0043] In one embodiment of the present invention, the first anode and the second anode are composed of a first number of stacked metal layers, and the cathode is composed of a second number of stacked metal layers, and the first number is greater than the second number.

[0044] The present invention reduces the lattice mismatch between the substrate and the barrier layer by arranging a multi-layer buffer layer between the substrate and the barrier layer, and increases the anode area by forming a dielectric layer before forming the first metal layer, thereby greatly reducing reverse leakage, and this dielectric layer can be formed simultaneously with the gate dielectric layer of the GaN HEMT (High Electron Mobility Transistor), and is compatible with the CMOS process line; in addition, by adding an anode conduction metal, a cathode conduction metal and a field plate structure, the depletion region of the gallium nitride-based semiconductor device is expanded, the electric field distribution of the gallium nitride-based Schottky barrier diode is optimized, and the withstand voltage performance of the gallium nitride-based power semiconductor device is improved.

[0045] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0047] Figure 1-1 This is a schematic structural diagram of a gallium nitride epitaxial layer of the present invention;

[0048] Figure 1-2 for Figure 1-1 Flow chart of the method for preparing a gallium nitride epitaxial layer;

[0049] Figure 2-1 It is a schematic diagram of the structure of another gallium nitride epitaxial layer of the present invention;

[0050] Figure 2-2 for Figure 2-1Flow chart of the method for preparing a gallium nitride epitaxial layer;

[0051] Figure 3-1 It is a schematic diagram of the structure of another gallium nitride epitaxial layer of the present invention;

[0052] Figure 3-2 for Figure 3-1 Flow chart of the method for preparing a gallium nitride epitaxial layer;

[0053] Figure 4-1 It is a schematic diagram of the structure of another gallium nitride epitaxial layer of the present invention;

[0054] Figure 4-2 for Figure 4-1 Flow chart of the method for preparing a gallium nitride epitaxial layer;

[0055] Figure 5-1 To adopt Figure 1-1 A schematic diagram of the structure of a semiconductor device obtained by growing a gallium nitride epitaxial layer;

[0056] Figure 5-2 for Figure 5-1 A flow chart of a method for preparing a semiconductor device;

[0057] Figure 6-1 To adopt Figure 1-1 A schematic diagram of the structure of another semiconductor device obtained by forming a gallium nitride epitaxial layer;

[0058] Figure 6-2 for Figure 6-1 A flow chart of a method for preparing a semiconductor device;

[0059] Figure 7-1 To adopt Figure 2-1 A schematic diagram of the structure of a semiconductor device obtained by growing a gallium nitride epitaxial layer;

[0060] Figure 7-2 for Figure 7-1 A flow chart of a method for preparing a semiconductor device;

[0061] Figure 8-1 To adopt Figure 2-1 A schematic diagram of the structure of another semiconductor device obtained by forming a gallium nitride epitaxial layer;

[0062] Figure 8-2 for Figure 8-1 A flow chart of a method for preparing a semiconductor device;

[0063] Figure 9-1 To adopt Figure 3-1 A schematic diagram of the structure of a semiconductor device obtained by growing a gallium nitride epitaxial layer;

[0064] Figure 9-2 for Figure 9-1A flow chart of a method for preparing a semiconductor device;

[0065] Figure 10-1 To adopt Figure 3-1 A schematic diagram of the structure of another semiconductor device obtained by forming a gallium nitride epitaxial layer;

[0066] Figure 10-2 for Figure 10-1 A flow chart of a method for preparing a semiconductor device;

[0067] Figure 11-1 To adopt Figure 4-1 A schematic diagram of the structure of a semiconductor device obtained by growing a gallium nitride epitaxial layer;

[0068] Figure 11-2 for Figure 11-1 Flow chart of the method for preparing a semiconductor device. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] Gallium nitride materials have low heat generation rate and high breakdown electric field, and are important materials for the development of high-temperature, high-power electronic devices and high-frequency microwave devices. Gallium nitride materials can be used to prepare new devices such as metal field effect transistors (MESFETs), heterojunction field effect transistors (HFETs), and modulation doped field effect transistors (MODFETs). The modulation doped AlGaN / GaN structure has high electron mobility (2000cm 2 / v·s), high saturation velocity (1×107cm / s), and low dielectric constant make it a preferred material for making microwave devices. GaN has a wide bandgap (3.4eV) and sapphire, silicon carbide and other materials as substrates, good heat dissipation performance, which is conducive to the operation of devices under high-power conditions.

[0071] The gallium nitride epitaxial layer and semiconductor device provided by the present invention can be applied to power semiconductor devices and radio frequency semiconductor devices.

[0072] See also Figure 1-1As shown, the present invention provides a gallium nitride epitaxial layer, including: a semiconductor substrate 1100, a buffer layer 1101, and a barrier layer 1102. The buffer layer 1101 is arranged on the semiconductor substrate 1100, and the barrier layer 1102 is arranged on a side of the buffer layer 1101 away from the semiconductor substrate 1100. The material of the semiconductor substrate 1100 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride, and the material of the buffer layer 1101 can be one or more of aluminum oxide, hafnium oxide, titanium oxide, titanium nitride, aluminum nitride, aluminum gallium nitride or gallium nitride. When the buffer layer 1101 is a multi-layer structure, the lattice constants of different layers gradually change, and the lattice constant near the surface of the semiconductor substrate 1100 is closest to the lattice constant of the semiconductor substrate 1100, and the lattice constant of the top layer is closest to the lattice constant of the barrier layer 1102 formed subsequently, thereby reducing the lattice defects in the buffer layer caused by the lattice constant of the semiconductor substrate 1100, reducing the interface state at the interface between the buffer layer and the semiconductor substrate 1100, and reducing the interface leakage current at the interface. The barrier layer 1102 material can be, for example, one of aluminum gallium nitride or gallium nitride.

[0073] Please also read Figure 1-2 As shown, the method for preparing the gallium nitride epitaxial layer of this embodiment includes at least the following steps:

[0074] In step S1100 , a buffer layer 1101 is grown on a semiconductor substrate 1100 by using an epitaxial growth process. In step S1101 , a barrier layer 1102 is then grown on the buffer layer 1101 by using an epitaxial growth process.

[0075] See also Figure 2-1 As shown, in other embodiments of the present invention, a gallium nitride epitaxial layer may further include: a semiconductor substrate 1200 , a first buffer layer 1201 , a second buffer layer 1202 , a third buffer layer 1203 and a barrier layer 1204 .

[0076] The first buffer layer 1201 is disposed on the semiconductor substrate 1200. The second buffer layer 1202 is disposed on a side of the first buffer layer 1201 away from the semiconductor substrate 1200, and the third buffer layer 1203 is disposed on a side of the second buffer layer 1202 away from the first buffer layer 1201. The barrier layer 1204 is disposed on a side of the third buffer layer 1203 away from the second buffer layer 1202. Based on the above embodiment, the first buffer layer 1201 in this embodiment can be, for example, an aluminum nitride layer, the thickness of the first buffer layer 1201 is, for example, 10nm-300nm, the second buffer layer 1202 can be, for example, a gallium nitride or aluminum gallium nitride layer, and the third buffer layer 1203 can be, for example, a gallium nitride layer. The materials used for the first buffer layer 1201, the second buffer layer 1202, and the third buffer layer 1203 can be, for example, adaptively selected according to the materials used for the semiconductor substrate and the barrier layers.

[0077] Please also read Figure 2-2 As shown, the method for preparing the gallium nitride epitaxial layer of this embodiment includes at least the following steps:

[0078] In step S1200, a first buffer layer 1201, such as an aluminum nitride buffer layer, is grown on a semiconductor substrate 1200, such as a silicon substrate or a silicon carbide substrate, by using an epitaxial growth process. In step S1201, a second buffer layer 1202, such as a gallium nitride buffer layer, is grown on the first buffer layer 1201 by using an epitaxial growth process. In step S1202, a third buffer layer 1203, such as an aluminum gallium nitride buffer layer, is grown on the second buffer layer 1202 by using an epitaxial growth process. In step S1203, an aluminum gallium nitride barrier layer 1204 is grown on the third buffer layer 1203 by using an epitaxial growth process.

[0079] See also Figure 3-1 As shown, in other embodiments of the present invention, a gallium nitride epitaxial layer may further include: a semiconductor substrate 1300 , a first buffer layer 1301 , a post-treatment layer 1302 , a second buffer layer 1303 , and a barrier layer 1304 .

[0080] The first buffer layer 1301 is arranged on the semiconductor substrate 1300, the post-processing layer 1302 is arranged on the side of the first buffer layer 1301 away from the semiconductor substrate 1300, the second buffer layer 1303 is arranged on the side of the post-processing layer 1302 away from the first buffer layer 1301, and the barrier layer 1304 is arranged on the side of the second buffer layer 1303 away from the post-processing layer 1302. The material of the semiconductor substrate 1300 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride. The first buffer layer 1301 can be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1301 is, for example, 10nm-300nm. The post-processing layer 1302 can be, for example, a thin layer of aluminum oxide (Al2O3), and the thickness of the post-processing layer 1302 is 0.5-2nm. The second buffer layer 1303 can be, for example, a gallium nitride layer or an aluminum gallium nitride layer. The material of the barrier layer 1304 is, for example, a gallium nitride layer or an aluminum gallium nitride layer. The present invention grows the first buffer layer 1301 and the post-treatment layer 1302 by PVD to obtain a first buffer layer 1301 of good quality, which facilitates the subsequent preparation and application of gallium nitride-based semiconductor devices.

[0081] Please also read Figure 3-2 As shown, a method for preparing a gallium nitride epitaxial wafer in this embodiment, for example, includes the following steps:

[0082] In step S1301, the material of the semiconductor substrate 1300 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride. The oxide layer on the surface of the semiconductor substrate 1300 is removed by treating with a hydrofluoric acid solution, and then a first buffer layer 1301, such as a single-layer aluminum nitride buffer layer, is deposited by a PVD process, and the thickness range is, for example, 10-50nm. Specifically, an epitaxial semiconductor substrate 1300 (here, for example, a Si substrate is used) is placed on a tray made of SiC material, the tray is placed in a PVD sputtering machine, and transferred to the deposition chamber of the machine. After the semiconductor substrate 1300 is placed in, the deposition chamber is evacuated, and the semiconductor substrate 1300 is heated and heated at the same time. The background vacuum is evacuated to, for example, below 10 -5 -10 -7Torr, the heating temperature is stabilized at, for example, 400°C to 600°C, and the semiconductor substrate 1300 is baked, and the baking time is, for example, 1 to 10 minutes. After the semiconductor substrate 1300 is baked, Ar, N2, and O2 are introduced, and the Ar:N2 flow ratio is, for example, 10:2 to 1:1, and the O2 flow rate is, for example, 0-5% of the sum of the Ar and N2 flows. The total gas flow rate is preferably such that the PVD deposition chamber pressure is maintained at, for example, 2 to 8 mTorr. At the same time, the heating temperature of the semiconductor substrate 1300 is set to the deposition temperature, and the preferred deposition temperature range is, for example, between 400 and 600°C. After the reaction gas is introduced and the deposition temperature is stabilized for, for example, 10 to 60 seconds, the sputtering power supply is turned on to sputter the Al target material, and an AlN crystalline film doped with O is deposited on the semiconductor substrate 1300. The sputtering power can be set to, for example, 1KW to 10KW depending on the deposition rate requirements, and the sputtering time can be set to, for example, 10 seconds to 1000 seconds depending on the thickness.

[0083] In step S1302, further, an ALD process is used to prepare a post-treatment layer 1302, such as an Al2O3 layer. The ALD chamber is evacuated to, for example, 0.05MPa-0.5MPa, the temperature is increased to, for example, 100°C, the precursors are trimethylaluminum and high-purity water, the deposition thickness is, for example, 0.5-2nm, and the deposition time is, for example, 3-25min.

[0084] In step S1303, further, a second buffer layer 1303, such as a gallium nitride buffer layer, is prepared on the post-treatment layer 1302. The preparation of the gallium nitride buffer layer can be achieved by a two-step method. The first step is to control the temperature to, for example, 450°C to 600°C and the pressure to, for example, 200-500torr, to grow a gallium nitride nucleation layer, and then increase the temperature to 950°C to 1200°C to grow a gallium nitride three-dimensional and two-dimensional coating layer. The nucleation layer and subsequent three-dimensional and two-dimensional gallium nitride are collectively referred to as a gallium nitride buffer layer.

[0085] In step S1304, the last step is to grow a barrier layer 1304, such as a gallium nitride barrier layer 1304. The temperature can be controlled to be, for example, 950°C to 1100°C, and the pressure can be, for example, 70torr to 200torr. The gallium nitride barrier layer 1304 is grown on the gallium nitride buffer layer. The gallium nitride barrier layer 1304 has a thickness of, for example, 50-500nm.

[0086] After the epitaxy is completed, the gallium nitride epitaxial layer is obtained by cooling the body.

[0087] Controlling temperature and pressure refers to controlling the temperature and pressure in the reaction chamber for growing epitaxial wafers, specifically the reaction chamber of metal organic chemical vapor deposition (MOCVD) equipment. In implementation, trimethylgallium or triethylgallium is used as gallium source, high-purity ammonia is used as nitrogen source, trimethylindium is used as indium source, trimethylaluminum is used as aluminum source, silane is used as silicon source, tetramethylgermanium is used as germanium source, and bismuthocene magnesium is used as magnesium source.

[0088] See also Figure 4-1 As shown, in other embodiments of the present invention, a gallium nitride epitaxial layer may further include: a semiconductor substrate 1400 , a first buffer layer 1401 , a nano buffer layer 1402 , a second buffer layer 1403 , and a barrier layer 1404 .

[0089] The first buffer layer 1401 is disposed on the semiconductor substrate 1400. The first buffer layer 1401 may be, for example, an aluminum nitride layer. The thickness of the first buffer layer 1401 is, for example, 10 nm to 300 nm. The nano buffer layer 1402 is disposed on a side of the first buffer layer 1401 away from the semiconductor substrate 1400. The second buffer layer 1403 is disposed on a side of the nano buffer layer 1402 away from the first buffer layer 1401. The second buffer layer 1403 may be, for example, a gallium nitride or aluminum gallium nitride layer. The barrier layer 1400 is disposed on a side of the second buffer layer 1403 away from the nano buffer layer 1402. The nano buffer layer 1402 may be, for example, gallium nitride nanocrystals or aluminum gallium nitride nanocrystals.

[0090] Please also read Figure 4-2 As shown, this embodiment also provides a method for preparing a gallium nitride-based epitaxial wafer, which includes the following steps: in step S1401, a first buffer layer 1401 is grown on a semiconductor substrate; in step S1402, a nano buffer layer 1402, such as a gallium nitride nano buffer layer 1402, is prepared on the first buffer layer by using a molecular beam epitaxy process, and a substrate and several molecular beam source furnaces are placed in an ultra-high vacuum system, and various elements constituting the compound, such as Ga, N and doping substances, are respectively placed in different injection furnaces for heating and cracked and ionized in different source furnaces, so that their molecules or atoms are sprayed onto the heated substrate surface at a certain thermal motion speed and a certain proportional intensity beam, and these molecules or atoms interact with the surface and grow a single crystal film. The growth rate of the single crystal film is, for example, 0.01-1μm / h, and the growth temperature is, for example, 500-600℃. In step S1403, further, a second buffer layer 1403, such as a gallium nitride buffer layer, is prepared on the nano buffer layer 1402 by using a PVD process. The preparation of the gallium nitride buffer layer can also be prepared by the two-step method of the above embodiment. In step S1404, a barrier layer 1404 is grown on the second buffer layer 1403. After the epitaxy is completed, the gallium nitride epitaxial wafer layer is obtained by cooling down.

[0091] See also Figure 5-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, including: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 103, an anode 104, a cathode 107, a protective layer 108, a field plate layer 109, an anode conduction metal 110 and a cathode conduction metal 111.

[0092] See also Figure 5-1 As shown, the buffer layer 1101 is arranged on the semiconductor substrate 1100, the barrier layer 1102 is arranged on the side of the buffer layer 1101 away from the semiconductor substrate 1100, and the passivation layer 103 is arranged on the side of the barrier layer 1102 away from the buffer layer 1101. The anode 104 penetrates the passivation layer 1103 and extends into the barrier layer 1102, and the cathode 107 penetrates the passivation layer 1103 and is connected to the barrier layer 1102. The protection layer 108 is arranged on the anode 104 and the cathode 107. The field plate layer 109 is arranged on the protection layer 108, and the field plate layer 109 is located between the anode 104 and the cathode 107. The anode conduction metal 110 is arranged on the field plate layer 109 and is connected to the anode 104, and the cathode conduction metal 111 is arranged on the field plate layer 109 and is connected to the cathode 107. Wherein, the anode 104 and the cathode 107 may include a multi-layer metal layer structure, and the metal layer structure includes but is not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer. The protective layer 108 may be, for example, a PETEOS oxide layer, and the anode conduction metal 110 and the cathode conduction metal 111 may be formed synchronously with the field plate layer 109, and the constituent material may be, for example, copper aluminum silicon (AlSiCu). In this embodiment, by setting the buffer layer 1101, the lattice defects of the barrier layer 1102 caused by the lattice constant of the semiconductor substrate 1100 are reduced, the interface state at the interface between the barrier layer 1102 and the semiconductor substrate 1100 is reduced, and the interface leakage current at the interface is reduced. The structure of the anode conduction metal 110, the cathode conduction metal 111 and the field plate layer 109 balances the electric field distribution, reduces the electric field strength of the main Schottky junction, and thus improves the voltage resistance of the semiconductor device.

[0093] Please also read Figure 5-2 The present invention also provides a method for preparing a semiconductor device, and the specific steps are as follows:

[0094] In step S101 , an epitaxial growth process is used to grow, for example, an aluminum gallium nitride barrier layer 1102 on, for example, a silicon substrate or a silicon carbide substrate.

[0095] In step S102 , a passivation layer 103 , such as silicon nitride, is deposited on the aluminum gallium nitride barrier layer 1102 by, but not limited to, chemical vapor deposition.

[0096] In step S103, the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 are patterned to form an anode 104 and a cathode 107, and the anode 104 and the cathode 107 penetrate the silicon nitride passivation layer 103 and extend into the aluminum gallium nitride barrier layer 1102. More specifically, the steps of patterning the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 to obtain the anode 104 are, for example: coating the silicon nitride passivation layer 103 with photoresist, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 using the patterned photoresist layer as a mask to determine the anode region AZ and the cathode region, and then depositing and patterning the first metal to obtain the first metal layer in the anode region AZ. More specifically, the specific steps for obtaining the first metal layer located in the anode area AZ may be: using but not limited to a magnetron sputtering coating process to deposit metal to form the first metal layer, the material of the first metal layer may be one of titanium nitride and titanium, applying photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer using the patterned photoresist layer as a mask to remove the first metal layer outside the anode area AZ shown in the figure, so as to obtain the first metal layer located in the anode area AZ.

[0097] In step S104, a second metal is deposited and patterned on the first metal layer in the anode area AZ and in the cathode area to obtain a second metal layer and a cathode 107. More specifically, the specific steps for obtaining the anode 104 and the cathode 107 may be: a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer are sequentially deposited on the passivation layer 103, the first metal layer in the anode area AZ and the cathode area using, but not limited to, an electron beam evaporation metal process to form a second metal layer, that is, the second metal layer is a stacked multilayer metal structure, including but not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer; then the second metal layer is subjected to a photolithography and etching process to form a second metal layer of the anode 104 and a cathode 107. More specifically, the anode 104 includes a first metal layer and a second metal layer located in the anode area AZ.

[0098] In step S105, a protective layer 108 is formed on the passivation layer 103, the anode 104, and the cathode 107. More specifically, the protective layer 108 is, for example, a PETEOS (Plasma Enhanced Tetraethylorthosilicate) oxide layer. The specific steps of forming the protective layer 108, for example, a PETEOS oxide layer, may be as follows: a silicon dioxide film is prepared at low temperature on the passivation layer 103, the anode 104, and the cathode 107 using ethyl orthosilicate as a raw material by microwave plasma chemical vapor deposition, that is, the protective layer 108. A photoresist is applied on the protective layer 108, and then the photoresist is exposed and developed to obtain a patterned photoresist layer. Thereafter, the protective layer 108 is etched using the patterned photoresist layer as a mask until the anode 104 and the cathode 107 are exposed, and the residual patterned photoresist layer is removed.

[0099] In step S106 and step S107, a third metal layer is formed on the protective layer 108 and the exposed anode 104 and cathode 107, and the third metal layer is patterned to form a field plate layer 109. An anode conduction metal 110 is formed on the exposed anode 104, and a cathode conduction metal 111 is formed on the exposed cathode 107. More specifically, the steps of forming the anode conduction metal 110, the cathode conduction metal 111 and the field plate layer 109 are as follows: a third metal layer is formed on the protective layer 108 by depositing a metal by, but not limited to, an electron beam evaporation process, and the material of the third metal layer is, for example, copper aluminum silicon (AlSiCu). Then, the third metal layer is subjected to photolithography (resin coating, exposure and development) and etching processes to form the anode conduction metal 110, the cathode conduction metal 111 and the field plate layer 109. The field plate layer 109 is located in a region between the anode conductive metal 110 and the cathode conductive metal 111 and outside the anode region AZ and connected to the anode conductive metal 110 .

[0100] Please also read Figure 5-2 As shown, in summary, this embodiment provides a method for preparing a semiconductor device, by providing a buffer layer 1101 to reduce the lattice defects of the barrier layer 1102 caused by the lattice constant of the semiconductor substrate 1100, reduce the interface state at the interface between the barrier layer 1102 and the semiconductor substrate 1100, and reduce the interface leakage current at the interface. By providing an anode conductive metal 110, a cathode conductive metal 111 and a field plate, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, and the electric field strength of the main Schottky junction is reduced, thereby improving the withstand voltage of the semiconductor device.

[0101] See also Figure 6-1As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, comprising: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 203, a first anode 204, a dielectric layer 205, a second anode 206, a cathode 207, a protective layer 208, a field plate layer 209, an anode conduction metal 210, and a cathode conduction metal 211. The buffer layer 1101 is arranged on the semiconductor substrate 1100, the barrier layer 1102 is arranged on a side of the buffer layer 1101 away from the semiconductor substrate 1100, and the passivation layer 203 is arranged on a side of the barrier layer 1102 away from the semiconductor substrate 1100. The first anode 204 penetrates the passivation layer 203 and extends into the barrier layer 1102. The dielectric layer 205 is arranged on a side of the passivation layer 203 away from the barrier layer 1102 and between the first anode 204 and the barrier layer 1102. The second anode 206 penetrates the dielectric layer 205 and the passivation layer 203 and extends into the barrier layer 1102. The cathode 207 is disposed on the dielectric layer 205 and penetrates the dielectric layer 205 and the passivation layer 203. The protection layer 208 is disposed on the first anode 204, the second anode 206, the cathode 207 and the dielectric layer 205. The field plate layer 209, the anode conduction metal 210 and the cathode conduction metal 211 are disposed on the protection layer 208, the field plate layer 209 is located between the anode conduction metal 210 and the cathode conduction metal 211, and the field plate layer 209 is connected to the anode conduction metal 210. On the basis of the above embodiments, in this embodiment, the material of the dielectric layer 205 is, for example, one of silicon nitride, silicon oxide and tetraethyl orthosilicate, and the first anode 204 and the second anode 206 are provided with a first metal layer and a second metal layer of a multilayer structure, and the material of the first metal layer can be a titanium metal layer or a titanium nitride metal layer, wherein the second metal layer can include but is not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer stacked in sequence. The cathode 207 includes a second metal layer, and the second metal layer of the cathode 207 and the second metal layer of the anode can be formed synchronously and are both multilayer metal structures. In other words, the first anode 204 and the second anode 206 are composed of a first number of stacked metal layers, and the cathode 207 is composed of a second number of stacked metal layers, and the first number is greater than the second number.

[0102] See also Figure 6-1 As shown, in this embodiment, by providing a buffer layer 1101, the lattice defects of the barrier layer 1102 caused by the lattice constant of the semiconductor substrate 1100 are reduced, the interface state at the interface between the barrier layer 1102 and the semiconductor substrate 1100 is reduced, and the interface leakage current at the interface is reduced. By forming a dielectric layer 205 on the passivation layer 203, the anode area is greatly increased, and the reverse leakage is reduced. In addition, by providing an anode conductive metal 210, a cathode conductive metal 211 and a field plate layer 209 structure, the electric field distribution is balanced, and the electric field strength of the main Schottky junction is reduced, thereby improving the voltage resistance of the semiconductor device.

[0103] Please also read Figure 6-2 As shown, the present invention also provides a method for preparing a semiconductor device, the specific steps of which include:

[0104] In step S201 , a buffer layer 1101 and an aluminum gallium nitride barrier layer 1102 are grown on a silicon substrate or a silicon carbide substrate using an epitaxial growth process.

[0105] In step S202 , a silicon nitride passivation layer 203 is deposited on the aluminum gallium nitride barrier layer 1102 using, but not limited to, a chemical vapor deposition process.

[0106] In step S203, step S204 and step S205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 are patterned to form a first anode 204, a dielectric layer 205 is formed on the silicon nitride passivation layer 203 and in the first anode 204, and the dielectric layer 205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 are patterned to form a second anode 206 that penetrates the dielectric layer 205, the silicon nitride passivation layer 203 and extends into the aluminum gallium nitride barrier layer 1102. More specifically, the material of the dielectric layer 205 is, for example, one of silicon nitride, silicon oxide and tetraethyl orthosilicate, and the step of patterning the dielectric layer 205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 to form the second anode 206 penetrating the dielectric layer 205, the silicon nitride passivation layer 203 and extending into the aluminum gallium nitride barrier layer 1102 includes, for example: coating a photoresist on the dielectric layer 205, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the dielectric layer 205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 using the patterned photoresist layer as a mask to form the second anode 206. A first metal layer is formed on the dielectric layer 205 and in the second anode 206, and the first metal layer is patterned to obtain the first metal layer located in the first anode 204 and the second anode 206. More specifically, the specific steps for obtaining the first metal layer located in the first anode 204 and the second anode 206 may be: depositing metal in the second anode 206 region and on the dielectric layer 205 using, but not limited to, a magnetron sputtering coating process to form the first metal layer, the material of the first metal layer may be one of titanium nitride and titanium, coating the first metal layer with photoresist, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer using the patterned photoresist layer as a mask to remove the first metal layer outside the first anode 204 and the second anode 206 to obtain the first metal layer located in the first anode 204 and the second anode 206.

[0107] In step S206, the dielectric layer 205 and the silicon nitride passivation layer 203 are patterned to form a cathode 207 region that penetrates the dielectric layer 205 and the silicon nitride passivation layer 203. More specifically, the step of patterning the dielectric layer 205 and the silicon nitride passivation layer 203 to form a cathode 207 region that penetrates the dielectric layer 205 and the silicon nitride passivation layer 203 can be specifically as follows: a photoresist is applied to the dielectric layer 205, and then the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the dielectric layer 205 and the silicon nitride passivation layer 203 are etched using the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride barrier layer 1102 is exposed to form the cathode 207 region, and the residual patterned photoresist layer is removed. A second metal layer is formed on the dielectric layer 205 and the first metal layer located in the first anode 204 and the second anode 206 and in the cathode 207 region, and the second metal layer is patterned to obtain the second metal layer of the anode and the cathode 207. More specifically, the specific steps for obtaining a complete anode and cathode 207 may be: in the dielectric layer 205, the first metal layer located in the first anode 204 and the second anode 206, and the cathode 207 area, a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer are sequentially deposited using a process of but not limited to electron beam evaporation of metal to form a second metal layer, that is, the second metal layer is a stacked multilayer metal structure, including but not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer, and then the second metal layer is subjected to photolithography and etching processes to form the second metal layer of the anode and the cathode 207. More specifically, the anode includes a first metal layer and a second metal layer located in the first anode 204 and the second anode 206.

[0108] In step S207, a protective layer 208 is formed on the dielectric layer 205 and the anode and cathode 207. More specifically, the protective layer 208 is, for example, a PETEOS (Plasma Enhanced Tetraethy lorthosilicate) oxide layer, and the specific steps of forming the protective layer 208, for example, a PETEOS oxide layer, may be: on the dielectric layer 205, the first anode 204, the second anode 206, and the cathode 207, a silicon dioxide film is prepared at low temperature using, for example, microwave plasma chemical vapor deposition method using ethyl orthosilicate as a raw material, i.e., the protective layer 208.

[0109] In step 208, the protective layer 208 is patterned to expose the first anode 204, the second anode 206 and the cathode 207. More specifically, the step of exposing the first anode 204, the second anode 206 and the cathode 207 may be as follows: a photoresist is coated on the protective layer 208, and then the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the protective layer 208 is etched using the patterned photoresist layer as a mask until the first anode 204, the second anode 206 and the cathode 207 are exposed, and the residual patterned photoresist layer is removed.

[0110] In step S209, a third metal layer is formed on the protective layer 208 and the exposed first anode 204, second anode 206, and cathode 207, and the third metal layer is patterned to form a field plate layer 209, and an anode conduction metal 210 is formed on the exposed first anode 204 and second anode 206, and a cathode conduction metal 211 is formed on the exposed cathode 207. More specifically, the steps of forming the anode conduction metal 210, the cathode conduction metal 211, and the field plate are as follows: a third metal layer is formed on the protective layer 208 by depositing a metal by, but not limited to, an electron beam evaporation process, and the material of the third metal layer is, for example, aluminum silicon copper (AlSiCu); then, the third metal layer is subjected to photolithography (resin coating, exposure, and development) and etching processes to form the anode conduction metal 210, the cathode conduction metal 211, and the field plate layer 209. The field plate layer 209 is located in a region between the anode conductive metal 210 and the cathode conductive metal 211 and outside the anode region AZ and connected to the anode conductive metal 210 .

[0111] See also Figure 7-1As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, which includes: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 303, a first anode contact hole 313, a dielectric layer 305, a second anode contact hole 314, a first anode 304, a second anode 306, a cathode contact hole 315, a cathode 307, a protective layer 308, an anode opening 316, a cathode opening 317, an anode conduction metal 310, a cathode conduction metal 311, and a field plate layer 309. The buffer layer 312 is disposed on the semiconductor substrate 1100. The barrier layer 1102 is disposed on a side of the buffer layer 1101 away from the semiconductor substrate 1100. The passivation layer 303 is disposed on a side of the barrier layer 1102 away from the buffer layer 1101. The first anode contact hole 313 penetrates the passivation layer 303 and extends into the barrier layer 1102. The dielectric layer 305 is disposed on a side of the passivation layer 303 away from the barrier layer 1102 and in the first anode contact hole 313. The second anode contact hole 314 penetrates the dielectric layer 305 and the passivation layer 303 and extends into the barrier layer 1102. The first anode 304 and the second anode 306 are disposed in the first anode contact hole 313 and the second anode contact hole 314, and the first anode 304 and the second anode 306 include a first metal layer and a second metal layer, wherein the first metal layer is disposed on a side of the dielectric layer 305 away from the passivation layer 303 and extends into the first anode contact hole 313 and the second anode contact hole 314 to cover the dielectric layer 305 and the second anode contact hole 314 at the bottom of the first anode contact hole 313, and the second metal layer is disposed on the first metal layer and fills the first anode contact hole 313 and the second anode contact hole 314. The cathode contact hole 315 penetrates the dielectric layer 305 and the passivation layer 303. The cathode 307 is disposed on the dielectric layer 305 and fills the cathode contact hole 315. The protection layer 308 is disposed on the first anode 304, the second anode 306, the cathode 307 and the dielectric layer 305. The anode opening 316 penetrates the protection layer 308 to expose the first anode 304 and the second anode 306. The cathode opening 317 penetrates the protection layer 308 to expose the cathode 307. The anode conduction metal 310 is disposed on the side of the protection layer 308 away from the dielectric layer 305, and the anode conduction metal 310 fills the anode opening 316. The cathode conduction metal 311 is disposed on the side of the protection layer 308 away from the dielectric layer 305, and the cathode conduction metal 311 fills the cathode opening 317. The field plate layer 309 is disposed on the protection layer 308 and is located in the region between the anode conduction metal 310 and the cathode conduction metal 311 and is connected to the anode conduction metal 310, wherein the anode conduction metal 310, the cathode conduction metal 311 and the field plate layer 309 can be formed simultaneously, for example, in the same photolithography and etching process.On the basis of the above-mentioned embodiments, the first anode contact hole 313 and the second anode contact hole 314 of the present embodiment are, for example, strip-shaped grooves, the material of the first metal layer contained in the first anode 304 and the second anode 306 may be a titanium metal layer or a titanium nitride metal layer, and the second metal layer contained in the first anode 304 and the second anode 306 is a multilayer structure, which may include but is not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer stacked in sequence. The cathode 307 and the second metal layer are formed synchronously, for example, in the same electron beam evaporation process, and both are multilayer metal structures. In other words, the first anode 304 and the second anode 306 are composed of a first number of stacked metal layers, and the cathode 307 is composed of a second number of stacked metal layers, and the first number is greater than the second number.

[0112] In this embodiment, the semiconductor device greatly increases the anode area and reduces reverse leakage by forming a dielectric layer 305 on the passivation layer 303. In addition, by providing an anode conductive metal 310, a cathode conductive metal 311 and a field plate structure, the electric field distribution is balanced, the electric field strength of the main Schottky junction is reduced, and the withstand voltage of the semiconductor device is improved.

[0113] Please also read Figure 7-2 As shown, the present invention also provides a method for preparing a semiconductor device, the method comprising the following steps:

[0114] In step S301 , an epitaxial growth process is used to grow, for example, a gallium nitride layer on a silicon substrate or a silicon carbide substrate, and then an epitaxial growth process is used to grow, for example, an aluminum gallium nitride layer on the gallium nitride layer.

[0115] In step S302 , a silicon nitride passivation layer 303 is deposited on the aluminum gallium nitride layer using, but not limited to, a chemical vapor deposition process.

[0116] In step S303, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are patterned to form a first anode contact hole 313, wherein the first anode contact hole 313 penetrates the silicon nitride passivation layer 303 and extends into the aluminum gallium nitride layer. More specifically, the steps of patterning the silicon nitride passivation layer 303 and the aluminum gallium nitride layer to form the first anode contact hole 313 are, for example: coating the silicon nitride passivation layer 303 with photoresist, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the silicon nitride passivation layer 303 and the aluminum gallium nitride layer using the patterned photoresist layer as a mask to form the first anode contact hole 313, wherein the first anode contact hole 313 is a strip-shaped groove.

[0117] In step S304, a dielectric layer 305 is formed on the silicon nitride passivation layer 303 and in the first anode contact hole 313, and the dielectric layer 305, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are patterned to form a second anode contact hole 314 penetrating the dielectric layer 305, the silicon nitride passivation layer 303 and extending into the aluminum gallium nitride layer. More specifically, the material of the dielectric layer 305 is, for example, one of silicon nitride, silicon oxide, and tetraethyl orthosilicate, and the step of patterning the dielectric layer 305, the silicon nitride passivation layer 303, and the aluminum gallium nitride layer to form the second anode contact hole 314 penetrating the dielectric layer 305, the silicon nitride passivation layer 303, and extending into the aluminum gallium nitride layer includes, for example: applying a photoresist on the dielectric layer 305, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the dielectric layer 305, the silicon nitride passivation layer 303, and the aluminum gallium nitride layer using the patterned photoresist layer as a mask to form the second anode contact hole 314. The area where the first anode contact hole 313 and the second anode contact hole 314 are located constitutes the anode area AZ, and the first anode 304 and the second anode 306 fill the first anode contact hole 313 and the second anode contact hole 314, respectively.

[0118] In step S305, a first metal layer is formed on the dielectric layer 305 and in the second anode contact hole 314, and the first metal layer is patterned to obtain the first metal layer located in the anode area AZ. More specifically, the specific steps of obtaining the first metal layer located in the anode area AZ may be: depositing metal in the second anode contact hole 314 and on the dielectric layer 305 using, but not limited to, a magnetron sputtering coating process to form the first metal layer, the material of the first metal layer may be one of titanium nitride and titanium, applying photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer using the patterned photoresist layer as a mask to remove the first metal layer outside the anode area AZ, so as to obtain the first metal layer located in the anode area AZ.

[0119] In step S306, the dielectric layer 305 and the silicon nitride passivation layer 303 are patterned to form a cathode contact hole 315 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303. More specifically, the step of patterning the dielectric layer 305 and the silicon nitride passivation layer 303 to form the cathode contact hole 315 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303 may be as follows: coating the dielectric layer 305 with photoresist, then exposing and developing the photoresist to obtain a patterned photoresist layer, then etching the dielectric layer 305 and the silicon nitride passivation layer 303 using the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride layer is exposed to form the cathode contact hole 315, and removing the remaining patterned photoresist layer.

[0120] In step S307 , a second metal layer is formed on the dielectric layer 305 and the first metal layer in the anode area AZ and in the cathode contact hole 315 , and the second metal layer is patterned to obtain a second metal layer of the first anode 304 and the second anode 306 and a cathode 307 , wherein the cathode 307 fills the cathode contact hole 315 . More specifically, the specific steps for obtaining the first anode 304, the second anode 306 and the cathode 307 may be: a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer are sequentially deposited in the dielectric layer 305, the first metal layer located in the anode area AZ and the cathode contact hole 315 using a process including but not limited to electron beam evaporation of metal to form a second metal layer, that is, the second metal layer is a stacked multilayer metal structure, including but not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer, and then the second metal layer is subjected to photolithography and etching processes to form the first anode 304, the second metal layer of the second anode 306 and the cathode 307. More specifically, the first anode 304 and the second anode 306 include the first metal layer and the second metal layer located in the anode area AZ.

[0121] In step S308 , a protection layer 308 is formed on the dielectric layer 305 , the first anode 304 , the second anode 306 , and the cathode 307 .

[0122] In step S309, the protective layer 308 is patterned to form an anode opening 316 and a cathode opening 317 penetrating the protective layer 308 to respectively expose the first anode 304, the second anode 306 and the cathode 307. More specifically, the step of patterning the protective layer 308 to form the anode opening 316 and the cathode opening 317 penetrating the protective layer 308 may be as follows: coating the protective layer 308 with photoresist, then exposing and developing the photoresist to obtain a patterned photoresist layer, then etching the protective layer 308 using the patterned photoresist layer as a mask until the first anode 304, the second anode 306 and the cathode 307 are exposed, thereby forming the anode opening 316 and the cathode opening 317, and removing the remaining patterned photoresist layer.

[0123] In step S310, a third metal layer is formed on the protective layer 308 and in the anode opening 316 and the cathode opening 317, and the third metal layer is patterned to form a field plate layer 309, an anode conduction metal 310 filling the anode opening 316, and a cathode conduction metal 311 filling the cathode opening 317. More specifically, the steps of forming the anode conduction metal 310, the cathode conduction metal 311, and the field plate are as follows: a third metal layer is formed on the protective layer 308 by depositing a metal by, but not limited to, an electron beam evaporation process, wherein the material of the third metal layer is, for example, copper aluminum silicon (AlSiCu), and then the third metal layer is subjected to photolithography (resin coating, exposure, and development) and etching processes to form the anode conduction metal 310, the cathode conduction metal 311, and the field plate. The field plate layer 309 is located in the region between the anode conduction metal 310 and the cathode conduction metal 311 and outside the anode region AZ and connected to the anode conduction metal 310.

[0124] In summary, this embodiment provides a method for preparing a semiconductor device, by depositing a layer of dielectric material on the surface of the silicon nitride passivation layer 303 and in the first anode contact hole 313 to form a dielectric layer 305, the area of ​​the anode is increased, and the reverse leakage is greatly reduced. This dielectric layer can be formed simultaneously with the gate dielectric layer of the GaN HEMT, and is compatible with the CMOS process line. Furthermore, by providing the anode conduction metal 310, the cathode conduction metal 311 and the field plate layer 309, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, and the electric field strength of the main Schottky junction is reduced, thereby improving the withstand voltage of the semiconductor device.

[0125] See also Figure 8-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, including: a semiconductor substrate 1200, a first buffer layer 1201, a second buffer layer 1202, a third buffer layer 1203, a barrier layer 1204, a passivation layer 503, a first anode contact hole 513, a first anode 504, a dielectric layer 505, a second anode contact hole 514, a second anode 506, a cathode contact hole 515, a cathode 507, a protective layer 508, a field plate layer 509, an anode opening 516, an anode conduction metal 510, a cathode opening 517 and a cathode conduction metal 511.

[0126] See also Figure 8-1 As shown, the semiconductor device in this embodiment is applied Figure 2-1 The gallium nitride epitaxial layer in the embodiment is used as a substrate, and the semiconductor device as described in the previous embodiment is prepared thereon.

[0127] Please also read Figure 8-2 As shown, this embodiment also provides a method for preparing a semiconductor device, and the specific steps thereof include:

[0128] In step S501, prepare Figure 2-1 of GaN epitaxial layer.

[0129] In steps S502-S510, Figure 2-1 The GaN epitaxial layer is Figure 7-2 In steps S302-S310, a semiconductor device is prepared.

[0130] See also Figure 9-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, including: a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, a barrier layer 1304, a passivation layer 603, a first anode contact hole 613, a first anode 604, a dielectric layer 605, a second anode contact hole 614, a second anode 606, a cathode contact hole 617, a cathode 607, a protective layer 608, a field plate layer 609, an anode opening 616, an anode conduction metal 610, a cathode opening 617 and a cathode conduction metal 611.

[0131] See also Figure 9-1 As shown, the semiconductor device in this embodiment is applied Figure 3-1 The gallium nitride epitaxial layer in the embodiment is used as a substrate, and the semiconductor device as described in the previous embodiment is prepared thereon.

[0132] Please also read Figure 9-2 As shown, this embodiment also provides a method for preparing a semiconductor device, which includes the following steps:

[0133] In steps S601-S604, on the semiconductor substrate 1300, a Figure 3-1 Gallium nitride epitaxial layer shown.

[0134] In steps S605-S613, Figure 3-1 The gallium nitride epitaxial layer shown in Figure 7-2 In steps S302-S310, a semiconductor device is prepared.

[0135] See also Figure 10-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, comprising: a semiconductor substrate 1300, a first buffer layer 1301, a post-treatment layer 1302, a second buffer layer 1303, a barrier layer 1304, a dielectric layer 705, a source 704, a drain 706 and a gate 707.

[0136] See also Figure 10-1As shown, the first buffer layer 1301 is disposed on a semiconductor substrate 1300, the post-processing layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, the second buffer layer 1303 is disposed on a side of the post-processing layer 1302 away from the first buffer layer 1301, and the barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-processing layer 1302, the barrier layer 1304 has a band gap wider than the band gap of the second buffer layer 1303, and induces a 2D electron gas (2DEG) in the channel. The dielectric layer 705 is disposed on a side of the barrier layer 1304 away from the second buffer layer 1303. The source 704, the drain 706 and the gate 707 are arranged in the dielectric layer 705, and the source 704, the drain 706 and the gate 707 respectively penetrate the dielectric layer 705 and are connected to the barrier layer 1304, and a part of them protrudes from the top of the dielectric layer 705, wherein the gate 707 extends into the barrier layer 1304 and reaches the bottom of the barrier layer 1304, and the gate 707 has a conical structure, and the ratio of the upper and lower sides of the cone is 1:2-1:4.

[0137] See also Figure 10-1 As shown, based on the above embodiment, in this embodiment, the source 704 and the drain 706 are composed of a third metal layer, which includes a first titanium metal layer, an aluminum metal layer, a second titanium metal layer and a titanium nitride layer in sequence. The gate 707 is composed of a fourth metal layer, which is a nickel-gold alloy.

[0138] Please also read Figure 10-2 As shown, this embodiment also provides a method for preparing a semiconductor device, and the specific steps are as follows:

[0139] In step 701, on a semiconductor substrate 1300, a Figure 3-1 Gallium nitride epitaxial layer shown.

[0140] In step 702, a layer of hafnium oxide (HfO2) may be deposited on the surface of the GaN-based epitaxial wafer using a plasma enhanced chemical vapor deposition method to form a dielectric layer 705. The thickness of the hafnium oxide may be, for example, 2000 angstroms.

[0141] In step 703, the dielectric layer 705 is dry-etched to form a source 704 contact hole and a drain 706 contact hole that are oppositely disposed.

[0142] In step 704, a first metal is deposited in the contact hole of the source 704 and the contact hole of the drain 706, and on the surface of the dielectric layer 705. Specifically, a magnetron sputtering coating process can be used to sequentially deposit a first titanium metal layer, an aluminum metal layer, a second titanium metal layer and a titanium nitride layer in the contact hole of the source 704 and the contact hole of the drain 706, and on the surface of the dielectric layer 705 to form a first metal layer, wherein the thickness of the first titanium metal layer can be, for example, 200 angstroms, the thickness of the aluminum metal layer can be, for example, 1200 angstroms, the thickness of the second titanium metal layer can be, for example, 200 angstroms, and the thickness of the titanium nitride layer can be, for example, 200 angstroms. The first metal is photolithographically etched to expose part of the surface of the dielectric layer 705. The photolithographic procedure includes coating, exposure and development. In this way, the first metal layer on the contact hole of the source 704 constitutes the source 704 of the device, and the first metal layer on the contact hole of the drain 706 constitutes the drain 706 of the device.

[0143] In step 705, dry etching is performed on the exposed surface of the dielectric layer 705 and the gallium nitride layer to form a contact hole for the gate 707. The contact hole for the gate 707 completely penetrates the dielectric layer 705 and passes through the gallium nitride layer directly to the bottom of the gallium nitride layer. The gate 707 has a cone structure, and the ratio of the upper and lower sides of the cone is 1:2-1:4.

[0144] In step 706, a silicon nitride layer is deposited in the contact hole of the gate 707 by using a magnetron sputtering coating process, the silicon nitride layer is not higher than the contact hole of the gate 707, and then Ni / Au is deposited as a second metal on the silicon nitride layer and the outer edge of the contact hole of the gate 707, and the Ni / Au metal thickness ratio is 0.01-0.04 μm / 0.08-0.4 μm, thereby forming the gate 707. Therefore, the gate 707 is a composite structure with multiple materials.

[0145] See also Figure 11-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, including: a semiconductor substrate 1400, a first buffer layer 1401, a nano buffer layer 1402, a second buffer layer 1403, a barrier layer 1404, a passivation layer 803, a first anode contact hole 813, a first anode 804, a dielectric layer 805, a second anode contact hole 814, a second anode 806, a cathode contact hole 815, a cathode 807, a protective layer 808, a field plate layer 809, an anode opening 816, an anode conduction metal 810, a cathode opening 817 and a cathode conduction metal 811.

[0146] See also Figure 11-1 As shown, the semiconductor device in this embodiment is applied Figure 4-1 The gallium nitride epitaxial layer in the embodiment is used as a substrate, and the semiconductor device as described in the previous embodiment is prepared thereon.

[0147] See also Figure 11-1 As shown, in other embodiments, a nano buffer layer 1402 can be simultaneously set between the semiconductor substrate 1400 and the buffer layer, between multiple buffer layers, and between the buffer layer and the barrier layer 1404. The nano buffer layer 1402 provides nucleation points for the growth of subsequent growth layers, which is beneficial to improving the film formation quality of subsequent growth layers.

[0148] Please also read Figure 11-2 As shown, the present invention also provides a method for preparing a semiconductor device, comprising the following steps:

[0149] In steps S801-S804, prepare Figure 4-1 of GaN epitaxial layer.

[0150] In steps S805-S813, Figure 4-1 The gallium nitride epitaxial layer shown in Figure 7-2 In steps S302-S310, a semiconductor device is prepared.

[0151] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A power device, characterized in that: It includes: Semiconductor substrate; a buffer layer disposed on the semiconductor substrate; A barrier layer, which is arranged on a side of the buffer layer away from the semiconductor substrate; A passivation layer, which is arranged on a side of the barrier layer away from the buffer layer; a first anode penetrating the passivation layer and extending into the barrier layer; a dielectric layer, which is arranged on a side of the passivation layer away from the barrier layer and in a first anode contact hole between the first anode and the barrier layer, the first anode contact hole penetrates the passivation layer and extends into the barrier layer, and the first anode is arranged in the first anode contact hole; A second anode, which penetrates the dielectric layer, the passivation layer and extends into the barrier layer; a cathode, which is disposed on the dielectric layer and penetrates the dielectric layer and the passivation layer; A protective layer, which is disposed on the first anode, the second anode, the cathode and the dielectric layer; An anode conductive metal is disposed on a side of the protective layer away from the dielectric layer, and the anode conductive metal is connected to the first anode and the second anode; A cathode conductive metal is disposed on a side of the protective layer away from the dielectric layer, and the cathode conductive metal is connected to the cathode; A field plate layer is disposed on the protection layer, and the field plate layer is connected to the anode conductive metal, wherein the anode conductive metal, the cathode conductive metal and the field plate layer are formed synchronously.

2. A power device according to claim 1, characterized in that: The semiconductor device further comprises a second anode contact hole, the second anode contact hole penetrates the dielectric layer and the passivation layer and extends into the barrier layer, and the second anode is arranged in the second anode contact hole.

3. A power device according to claim 1, characterized in that: The buffer layer is one or more of aluminum oxide, hafnium oxide, titanium oxide, titanium nitride, aluminum nitride, aluminum gallium nitride or gallium nitride.

4. A power device according to claim 1, characterized in that: The first anode and the second anode include a first metal layer and a second metal layer, wherein the first metal layer is arranged on a side of the dielectric layer away from the passivation layer, and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer located at the bottom of the first anode contact hole and the bottom of the second anode contact hole, and the second metal layer is arranged on the first metal layer and fills the first anode contact hole and the second anode contact hole.

5. A power device according to claim 1, characterized in that: The semiconductor device further comprises a cathode contact hole, wherein the cathode contact hole penetrates the dielectric layer and the passivation layer, and the cathode is arranged in the cathode contact hole.

6. A method for preparing a power device, characterized in that: It includes at least the following steps: forming a buffer layer and a barrier layer in sequence on the substrate; forming a passivation layer on the barrier layer; forming a first anode contact hole in the passivation layer and the barrier layer, wherein the first anode contact hole penetrates the passivation layer and extends into the barrier layer; forming a dielectric layer on the passivation layer and in the first anode contact hole, and patterning the dielectric layer, the passivation layer and the barrier layer to form a second anode contact hole penetrating the dielectric layer, the passivation layer and extending into the barrier layer; forming a first metal layer of an anode on the dielectric layer and in the second anode contact hole; forming a cathode contact hole penetrating the dielectric layer and the passivation layer on the dielectric layer and the passivation layer; forming a second metal layer of the anode on the dielectric layer and the first metal layer of the anode and in the cathode contact hole, thereby obtaining a first anode and a second anode including the first metal layer and the second metal layer and a cathode including the second metal layer; forming a protective layer on the dielectric layer, the first anode, the second anode and the cathode; The protection layer is patterned to form a field plate layer, and the field plate layer is connected to the first anode and the second anode.

7. A method for preparing a power device according to claim 6, characterized in that: The second metal layer and the cathode are formed simultaneously and are respectively multi-layer metal structures.

8. The method for preparing a power device according to claim 6, characterized in that: The first anode and the second anode are formed by stacking a first number of metal layers, and the cathode is formed by stacking a second number of metal layers, and the first number is greater than the second number.

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