Semiconductor device

Abstract

This semiconductor device is provided with: a transistor unit; a diode part; a plurality of groove portions; an N-type drift region; a P-type base region provided above the drift region in the transistor section; an N +-type emitter region and a P +-type contact region both provided on the front surface of the semiconductor substrate in the transistor section; a P-type anode region provided above the drift region in the diode portion; a mesa portion of the semiconductor substrate; an interlayer insulating film provided above the semiconductor substrate; a front surface electrode provided above the semiconductor substrate; a trench contact portion that connects the front surface electrode and the mesa portion in the transistor portion; and a front contact portion in which the front electrode and the mesa portion are connected in the diode portion, the lower end of the front contact portion being disposed above the lower end of the trench contact portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] In a semiconductor device having a transistor portion and a diode portion, there is known a structure in which an electrode is connected to a semiconductor substrate via a trench-shaped contact portion (for example, see Patent Documents 1 and 2).

[0003] Patent Document 1: WO2018 / 056233 Patent Document 2: Japanese Patent Application Publication No. 2021-150483 Summary of the invention Technical issues It is preferable to improve the trade-off between the reverse recovery loss and the forward voltage of the diode portion.

[0004] Technical Solution In a first aspect of the present invention, a semiconductor device is provided, which comprises: a transistor portion; a diode portion; a plurality of groove portions, which are arranged on the front surface of a semiconductor substrate; a drift region of a first conductivity type, which is arranged on the semiconductor substrate; a base region of a second conductivity type, which is arranged above the drift region in the transistor portion; an emitter region of a first conductivity type and a contact region of a second conductivity type, both of which are arranged on the front surface of the semiconductor substrate in the transistor portion, and the doping concentration of the emitter region is higher than the doping concentration of the drift region, and the doping concentration of the contact region is higher than the doping concentration of the base region; an anode region of a second conductivity type, which is arranged above the drift region in the diode portion; a mesa portion of the semiconductor substrate, which is arranged between the plurality of groove portions; an interlayer insulating film, which is arranged above the semiconductor substrate; a front electrode, which is arranged above the semiconductor substrate; a trench contact portion, which connects the front electrode to the mesa portion in the transistor portion; and a front contact portion, which connects the front electrode to the mesa portion in the diode portion, the lower end of the front contact portion being arranged at a position higher than the lower end of the trench contact portion.

[0005] A width of the front contact portion in the trench arrangement direction may be greater than a width of the trench contact portion in the trench arrangement direction.

[0006] The front electrode may include an emitter electrode.

[0007] The front electrode may include a contact plug portion provided in a contact hole of the interlayer insulating film and connecting the emitter electrode with the semiconductor substrate.

[0008] The doping concentration of the anode region may be lower than the doping concentration of the base region.

[0009] The doping concentration of the anode region may be the same as the doping concentration of the base region.

[0010] The doping concentration of the anode region may be higher than the doping concentration of the base region.

[0011] The diode portion may include a lifetime control region provided at a position closer to the front surface side than a center of the semiconductor substrate in a depth direction of the semiconductor substrate.

[0012] The semiconductor device may include: a first plug region of the second conductivity type, which is arranged at the lower end of the trench contact portion and has a doping concentration higher than the doping concentration of the contact region; and a second plug region of the second conductivity type, which is arranged in contact with the lower end of the front contact portion and has a doping concentration higher than the doping concentration of the contact region.

[0013] The first plug region may be disposed discontinuously in the extending direction of the trench.

[0014] The second plug region may be provided to extend in the trench extension direction.

[0015] The semiconductor device may include an accumulation region of the first conductivity type in the transistor portion, the accumulation region being provided above the drift region and having a doping concentration higher than that of the drift region.

[0016] The semiconductor device may include a boundary region arranged between the transistor portion and the diode portion, wherein, when viewed from above, a ratio of an area of ​​the emitter region in a mesa portion of the boundary region is smaller than a ratio of an area of ​​the emitter region in a mesa portion of the transistor portion, and the front contact portion is arranged in the mesa portion of the boundary region.

[0017] A width of the boundary region in the trench arrangement direction may be greater than or equal to 20 μm and less than or equal to 250 μm.

[0018] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 1 is a plan view showing an example of the semiconductor device 100 .

[0020] Figure 2 yes Figure 1 Magnified view of area D in FIG.

[0021] Figure 3A It is shown Figure 2 A diagram showing an example of an ee cross section in .

[0022] Figure 3Byes Figure 3A An enlarged view of the vicinity of the second land portion 62 and the third land portion 63 is shown.

[0023] Figure 4A It is shown Figure 2 A diagram showing an example of the ff cross section.

[0024] Figure 4B yes Figure 4A An enlarged view of the vicinity of the second stage surface portion 62 and the third stage surface portion 63 is shown.

[0025] Figure 5 1 is a diagram showing an example of the P-type doping concentration distribution of the anode region 84 and the second plug region 222 in the vicinity of the front surface of the third mesa portion 63 .

[0026] Figure 6 It is shown Figure 2 A top view of another example of .

[0027] Fig. 7A It is shown Figure 6 A diagram showing an example of the gg cross section in FIG.

[0028] Figure 7B It is shown Figure 6 A diagram of an example of an hh cross section in .

[0029] Figure 8 It is shown Figure 2 A top view of another example of .

[0030] Fig.9A It is shown Figure 8 A diagram of an example of the jj cross section in FIG.

[0031] Fig. 9B It is shown Figure 8 A diagram of an example of the kk cross section in FIG.

[0032] Explanation of symbols 10…semiconductor substrate, 11…well region, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 17…trench contact portion, 18…drift region, 20…buffer region, 21…front surface, 22…collector region, 23…back surface, 24…collector electrode, 29…straight portion, 30…dummy trench portion, 31…front end portion, 32…dummy insulating film, 34…dummy conductive portion, 38…interlayer insulating film, 39…straight portion, 40…gate trench portion, 41…front end portion, 42…gate insulating film, 44…gate conductive portion, 52…emitter electrode, 54…contact hole, 60…terasa portion, 61…firstterasa portion, 62…secondterasa portion, 63…third terrace portion, 64…fourth terrace portion, 70…transistor portion, 80…diode portion, 81…extension region, 82…cathode region, 84…anode region, 87…front contact portion, 90…edge termination structure portion, 100…semiconductor device, 130…peripheral gate wiring, 131…active side gate wiring, 160…active portion, 162…end edge, 164…gate pad, 200…boundary region, 201…adjustment region, 202…non-adjustment region, 204…lattice defect, 206…lifetime adjustment region, 221…first plug region, 222…second plug region, 250…contact plug portion, 251…plug, 252…barrier metal portion DETAILED DESCRIPTION Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0033] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as the front surface, and the other is referred to as the back surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is actually installed.

[0034] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis, and Z-axis are used to explain technical matters. The rectangular coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is recorded without recording the positive or negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0035] In this specification, the orthogonal axes parallel to the front and back sides of the semiconductor substrate are referred to as the X-axis and the Y-axis. In addition, the axis perpendicular to the front and back sides of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. In addition, in this specification, the direction including the X-axis and the Y-axis and parallel to the front and back sides of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0036] The area from the center in the depth direction of the semiconductor substrate to the front surface of the semiconductor substrate is sometimes referred to as the front side. Similarly, the area from the center in the depth direction of the semiconductor substrate to the back surface of the semiconductor substrate is sometimes referred to as the back side.

[0037] In this specification, when it is said that they are "same" or "equal", it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0038] In this specification, the conductivity type of the doped region doped with impurities is set to P type or N type for description. In this specification, impurities sometimes specifically refer to one of N type donors and P type acceptors, and sometimes are described as dopants. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting N type conductivity or a semiconductor exhibiting P type conductivity.

[0039] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the actual concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. For example, if the donor concentration is N D , and the acceptor concentration is set to N A , then the net doping concentration at any position becomes N D -N A In this specification, the net doping concentration may be described simply as the doping concentration.

[0040] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of taking electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, a VOH defect formed by bonding a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor functions as an electron donor. A hydrogen donor may be a donor formed by bonding at least a vacancy (V) and hydrogen (H). Alternatively, interstitial Si-H formed by bonding interstitial silicon (Si-i) and hydrogen in a silicon semiconductor also functions as an electron donor. In this specification, VOH defects or interstitial Si-H are sometimes referred to as hydrogen donors.

[0041] In this specification, the semiconductor substrate is distributed with N-type body donors throughout. Body donors are donors formed by dopants that are roughly uniformly contained in the ingot when manufacturing the ingot that serves as the basis of the semiconductor substrate. The body donor in this example is an element other than hydrogen. The dopant of the body donor is, for example, phosphorus, antimony, arsenic, selenium or sulfur, but is not limited to this. The body donor in this example is phosphorus. Body donors are also contained in the P-type region. The semiconductor substrate can be a wafer cut from a semiconductor ingot or a chip formed by singulating the wafer. The semiconductor ingot can be manufactured by any of the CZ method, the magnetron crystal pulling method (MCZ method), and the zone melting method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 When the oxygen concentration is high, hydrogen donors tend to be generated easily. The body donor concentration can be the chemical concentration of body donors distributed throughout the semiconductor substrate, or a value between 90% and 100% of the chemical concentration. In addition, the semiconductor substrate can also be an undoped substrate that does not contain dopants such as phosphorus. In this case, the body donor concentration (D0) of the undoped substrate is, for example, 1×10 10 / cm 3 Above and 5×10 12 / cm 3 The bulk donor concentration (D0) of the undoped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the undoped substrate is preferably 5×10 12 / cm 3 Hereinafter, each concentration in the present invention may be a value at room temperature. As an example, the value at room temperature may be a value at 300K (Kelvin) (about 26.9° C.).

[0042] In the case of being recorded as P+ type or N+ type in this specification, it means that the doping concentration is higher than the doping concentration of P type or N type, and in the case of being recorded as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type. In addition, in the case of being recorded as P++ type or N++ type in this specification, it means that the doping concentration is higher than the doping concentration of P+ type or N+ type. Unless otherwise specified, the unit system in this specification is the SI unit system. Although the unit of length is sometimes expressed in cm, each calculation can be performed after conversion to meters (m).

[0043] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the state of electrical activation. Chemical concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). The above net doping concentration can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by the extended resistance measurement method (SR method) can be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method can be used as a value in thermal equilibrium. In addition, in the N-type region, the donor concentration is much greater than the acceptor concentration, so the carrier concentration in the region can also be set to the donor concentration. Similarly, in the P-type region, the carrier concentration in the region can also be set to the acceptor concentration. In this specification, the doping concentration of the N-type region is sometimes referred to as the donor concentration, and the doping concentration of the P-type region is sometimes referred to as the acceptor concentration.

[0044] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor or net doping in the region. In the case where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region can also be used as the concentration of the donor, acceptor or net doping. In this specification, atoms / cm is used to express the concentration per unit volume. 3 or / cm 3 This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms symbol can also be omitted.

[0045] The carrier concentration measured by the SR method can be lower than the concentration of the donor or acceptor. In the range of current flow when measuring the spreading resistance, the carrier mobility of the semiconductor substrate is sometimes lower than the value of the carrier mobility in the crystalline state. The disorder (disorder) of the crystal structure caused by lattice defects, etc., scatters the carriers, resulting in a decrease in carrier mobility.

[0046] The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. For example, the donor concentration of phosphorus or arsenic, which is a donor, or the acceptor concentration of boron, which is an acceptor, in a silicon semiconductor is about 99% of their chemical concentrations. On the other hand, the donor concentration of hydrogen, which is a donor, in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.

[0047] Figure 1 FIG. 1 is a top view showing an example of the semiconductor device 100. Figure 1 , the positions of the components projected onto the front surface of the semiconductor substrate 10 are shown. Figure 1 , only a part of the components of the semiconductor device 100 is shown, and other components are omitted.

[0048] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an edge 162 when viewed from above. In this specification, the condition referred to as the condition viewed from above refers to the condition observed from the front side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of edge 162 that are opposite to each other when viewed from above. Figure 1 In the embodiment, the X-axis and the Y-axis are parallel to one of the end sides 162. In addition, the Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0049] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region where a main current flows between the front and back surfaces of the semiconductor substrate 10 in the depth direction when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but Figure 1 The active portion 160 may refer to a region that overlaps with the emitting electrode in a plan view. In addition, a region sandwiched by the active portion 160 in a plan view may also be included in the active portion 160.

[0050] The active portion 160 includes a transistor portion 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor) and a diode portion 80 including a diode element such as a freewheeling diode (FWD). Figure 1 In the example of FIG. 1 , the transistor section 70 and the diode section 80 are alternately arranged along a predetermined first direction (in this example, the X-axis direction) on the front surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT). In the X-axis direction, a boundary region is arranged between the transistor section 70 and the diode section 80, but Figure 1 Omitted in .

[0051] exist Figure 1 In the figure, the region where the transistor portion 70 is arranged is marked with a symbol "I", and the region where the diode portion 80 is arranged is marked with a symbol "F". In this specification, a direction different from the first direction in a plan view is sometimes referred to as a second direction (in Figure 1 The second direction may be a direction perpendicular to the first direction. The transistor portion 70 and the diode portion 80 may each have a length in the second direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The second direction of the transistor portion 70 and the diode portion 80 may be the same as the length direction of each groove portion and the length direction of the mesa portion described later.

[0052] The diode portion 80 has an N+ type cathode region in a region in contact with the back side of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is a region overlapping with the cathode region when viewed from above. On the back side of the semiconductor substrate 10, a P+ type collector region may be provided in a region other than the cathode region. In this specification, an extension region 81 in which the diode portion 80 is sometimes extended in the Y-axis direction to the gate wiring described later is also included in the diode portion 80. A collector region is provided on the back side of the extension region 81. The diode portion 80 has a P- type anode region on the front side of the semiconductor substrate 10.

[0053] The transistor portion 70 has a P+ type collector region in a region in contact with the back surface of the semiconductor substrate 10. In addition, the transistor portion 70 is periodically configured with an N+ type emitter region, a P+ type contact region, a P- type base region, and a gate structure having a gate conductive portion and a gate insulating film on the front side of the semiconductor substrate 10.

[0054] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged near the end 162. The vicinity of the end 162 refers to the area between the end 162 and the emitter electrode when viewed from above. When the semiconductor device 100 is actually installed, each pad can be connected to an external circuit via wiring such as a wire.

[0055] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 to the gate trench portion. Figure 1 In FIG. 1 , the gate wiring is marked with oblique hatching.

[0056] The gate wiring of this example has a peripheral gate wiring 130. The peripheral gate wiring 130 is arranged between the active portion 160 and the end 162 of the semiconductor substrate 10 when viewed from above. The peripheral gate wiring 130 of this example surrounds the active portion 160 when viewed from above. The area surrounded by the peripheral gate wiring 130 when viewed from above can also be set as the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the concentration of the base region described later, and is formed from the front surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region when viewed from above can also be set as the active portion 160.

[0057] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0058] The semiconductor device 100 of this example further includes an active-side gate wiring 131. The active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, the variation in wiring length from the gate pad 164 can be reduced in each region of the semiconductor substrate 10.

[0059] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate groove portion of the active portion 160. The peripheral gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0060] The active-side gate wiring 131 may be connected to the peripheral gate wiring 130. The active-side gate wiring 131 of this example extends along the X-axis direction from the peripheral gate wiring 130 on one side sandwiching the active portion 160 to the peripheral gate wiring 130 on the other side so as to cross the active portion 160 at approximately the center in the Y-axis direction. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 may be alternately arranged along the X-axis direction in each divided region.

[0061] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160 .

[0062] In a plan view, the semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the edge 162. The edge termination structure portion 90 of this example is arranged between the peripheral gate wiring 130 and the edge 162. The edge termination structure portion 90 alleviates the electric field concentration on the front side of the semiconductor substrate 10. The edge termination structure portion 90 may include at least one of a guard ring, a field plate, and a surface electric field reduction portion that surrounds the active portion 160 and is provided in an annular shape.

[0063] Figure 2 yes Figure 1 1 is an enlarged view of region D in FIG. Region D is a region including transistor portion 70, diode portion 80, and active-side gate wiring 131. Figure 1Although omitted in the figure, a boundary region 200 is arranged between the transistor portion 70 and the diode portion 80 in the X-axis direction. The boundary region 200 is a region having a P+ type collector region in the region in contact with the back surface of the semiconductor substrate 10. The area ratio of the emitter region 12 of the boundary region 200 is smaller than the area ratio of the emitter region 12 of the transistor portion 70. The boundary region 200 of this example does not have an emitter region on the front surface of the semiconductor substrate 10. The width of the boundary region 200 in the X-axis direction of this example is greater than 20 μm and less than 250 μm.

[0064] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, a contact region 15, and an anode region 84 provided inside the front side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131 provided above the front side of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0065] An interlayer insulating film is provided between the emitter electrode 52 and the front surface of the semiconductor substrate 10 and between the active-side gate wiring 131 and the front surface of the semiconductor substrate 10. Figure 2 The interlayer insulating film of this example is provided with a contact hole 54 so as to penetrate the interlayer insulating film. Figure 2 In FIG. 1 , each contact hole 54 is indicated by an oblique hatching line.

[0066] The emitter electrode 52 is disposed above the gate groove portion 40, the dummy groove portion 30, the well region 11, the emitter region 12, the base region 14, the contact region 15, and the anode region 84. The emitter electrode 52 is connected to the emitter region 12, the contact region 15, and the base region 14 on the front surface of the semiconductor substrate 10 through the contact hole 54. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the dummy groove portion 30 through the contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy groove portion 30 at the front end in the Y-axis direction of the dummy groove portion 30. The dummy conductive portion of the dummy groove portion 30 may not be connected to the emitter electrode 52 and the gate conductive portion, or may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0067] The active side gate wiring 131 is connected to the gate groove portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 can be connected to the gate conductive portion of the gate groove portion 40 at the front end portion 41 in the Y-axis direction of the gate groove portion 40. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy groove portion 30.

[0068] The emitter electrode 52 is formed of a material containing metal. The emitter electrode 52 is an example of a front electrode. Figure 2 , the range in which the emitter electrode 52 is provided is shown. For example, at least a part of the emitter electrode 52 is formed of aluminum or an alloy having aluminum as a main component, such as a metal alloy such as Al-Si, Al-Si-Cu, etc. The emitter electrode 52 may have a barrier metal. In addition, the front electrode may have a contact plug portion in the contact hole, the contact plug portion having a barrier metal formed of titanium and a titanium compound, etc. on the side of the contact hole, and a plug formed by burying tungsten, etc. in a manner that is in contact with the barrier metal and the emitter electrode 52. The contact plug portion connects the emitter electrode 52 to the semiconductor substrate 10.

[0069] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend with a predetermined width within a range not overlapping with the active side gate wiring 131. The well region 11 of this example is provided so as to be separated from one end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131 side. The well region 11 is a region of the second conductivity type having a higher doping concentration than the doping concentration of the base region 14. The base region 14 of this example is of P- type, and the well region 11 is of P+ type.

[0070] The transistor section 70, the diode section 80 and the boundary region 200 each have a plurality of groove sections arranged along the first direction. In the transistor section 70 of this example, one or more gate groove sections 40 and one or more dummy groove sections 30 are alternately arranged along the first direction. In the diode section 80 of this example, a plurality of dummy groove sections 30 are arranged along the first direction. In the diode section 80 of this example, no gate groove section 40 is arranged. In the boundary region 200 of this example, a plurality of dummy groove sections 30 are arranged along the first direction. In the boundary region 200 of this example, no gate groove section 40 is arranged.

[0071] The gate trench portion 40 of this example may include two straight line portions 39 extending in a second direction perpendicular to the first direction (portions forming a straight line groove along the second direction), and a front end portion 41 connecting the two straight line portions 39 . Figure 2 The second direction is the Y-axis direction.

[0072] Preferably, at least a portion of the tip portion 41 is curved in a plan view. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby alleviating electric field concentration at the ends of the straight portions 39 .

[0073] In the transistor portion 70, the dummy groove portion 30 is provided between each straight portion 39 of the gate groove portion 40. One dummy groove portion 30 may be provided between each straight portion 39, or a plurality of dummy groove portions 30 may be provided. In the transistor portion 70 of this example, two dummy groove portions 30 are provided between each straight portion 39. The dummy groove portion 30 may have a straight line shape extending in the second direction, or may have a straight line portion 29 and a front end portion 31 similarly to the gate groove portion 40. Figure 2 The semiconductor device 100 shown includes only the dummy trench portion 30 having the front end portion 31 , but may include both a linear dummy trench portion 30 without the front end portion 31 and a dummy trench portion 30 having the front end portion 31 .

[0074] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in a plan view. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. Thus, the electric field concentration at the bottom of each trench portion can be alleviated.

[0075] A mesa portion 60 is provided between adjacent groove portions in the first direction. The mesa portion 60 refers to an area clamped by the groove portion inside the semiconductor substrate 10. The front of the mesa portion 60 in this example is the front of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the groove portion. The mesa portion 60 in this example is provided on the front of the semiconductor substrate 10 along the groove extending in the second direction (Y-axis direction). The mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200 may have different structures. In the present specification, when referred to as the mesa portion 60 for short, it refers to the mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200, respectively.

[0076] The base region 14 is provided in the mesa portion 60 of the transistor portion 70, and the anode region 84 is provided in the mesa portion 60 of the diode portion 80 and the boundary region 200. Figure 2 In the figure, although the base region 14 is shown to be arranged at the end of one side in the second direction of each mesa portion, the base region 14 is also arranged at the end of the other side of each mesa portion. In the mesa portion 60 of the transistor portion 70, at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type can be arranged in the area sandwiched by the base region 14 when viewed from above. The emitter region 12 of this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 can be arranged between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction.

[0077] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0078] The contact regions 15 and emitter regions 12 in the mesa portion 60 are respectively arranged from one groove portion in the X-axis direction to the other groove portion. As an example, the contact regions 15 and emitter regions 12 of the mesa portion 60 are alternately arranged along the second direction (Y-axis direction) of the groove portion.

[0079] In other examples, the contact area 15 and the emitter area 12 of the mesa portion 60 can be arranged in a strip shape along the second direction (Y-axis direction) of the groove portion. For example, the emitter area 12 is arranged in the area connected to the groove portion, and the contact area 15 is arranged in the area sandwiched by the emitter area 12.

[0080] In the present example, the emitter region 12 is not provided in the mesa portion 60 of the diode portion 80. The area ratio of the emitter region 12 in the mesa portion 60 of the boundary region 200 is smaller than the area ratio of the emitter region 12 in the mesa portion 60 of the transistor portion 70. In the present example, the emitter region 12 is not provided in the mesa portion 60 of the boundary region 200.

[0081] An anode region 84 may be provided on the front surface of the mesa portion 60 of the diode portion 80 and the boundary region 200. The doping concentration of the anode region 84 may be the same as or different from the doping concentration of the base region 14. In this example, the doping concentration of the anode region 84 is lower than the doping concentration of the base region 14. In this example, the base region 14 is of P-type, and the anode region 84 is of P--type.

[0082] The mesa portion 60 of the boundary region 200 of this example may have the same anode region 84 as the mesa portion 60 of the diode portion 80. It should be noted that the mesa portion 60 of the boundary region 200 may also have a structure different from the anode region 84, and may also have a P-type impurity region with a doping concentration lower than that of the base region 14. By providing a P-type impurity region with a low doping concentration in the mesa portion 60 of the boundary region 200, the injection of holes from the mesa portion 60 of the boundary region 200 can be suppressed, thereby reducing the reverse recovery loss.

[0083] In addition, in the mesa portion 60 of the boundary region 200, an N-type impurity region having the same doping concentration as the emitter region 12 or a lower doping concentration than the emitter region 12 can be provided instead of the anode region 84. However, in this case, the gate groove portion 40 is not provided in the boundary region 200. In addition, the groove portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy groove portion 30. In the mesa portion 60 of the boundary region 200, the N-type impurity region is not connected to the gate groove portion 40, so the N-type impurity region does not form an inversion layer and is turned on. As a result, the injection of holes from the mesa portion 60 of the boundary region 200 can be suppressed, and the reverse recovery loss can be reduced.

[0084] In addition, the base region 14 may be provided in the boundary region 200 and the mesa portion 60 of the diode portion 80. In addition, the contact region 15 may be provided on the front side of the base region 14, and the contact region 15 may be sandwiched by the base region 14 in the Y-axis direction. That is, the area ratio of the contact region 15 in the mesa portion 60 of the boundary region 200 may be larger than the area ratio of the contact region 15 in the mesa portion 60 of the diode portion 80. In this case, holes in the semiconductor substrate 10 are easily extracted to the emitter electrode 52 via the mesa portion 60 of the boundary region 200.

[0085] A contact hole 54 is provided above each mesa portion 60. The contact hole 54 is arranged in a region sandwiched by the base region 14 or the anode region 84. The contact hole 54 of this example is provided above each region of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the base region 14 and the well region 11. The contact hole 54 may be arranged at the center of the mesa portion 60 in the first direction (X-axis direction).

[0086] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate 10. On the back surface of the semiconductor substrate 10, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the back surface 23 of the semiconductor substrate 10 and the buffer region 20. Figure 2 In FIG. 8 , the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0087] The cathode region 82 is arranged to be separated from the well region 11 in the Y-axis direction. Thus, the distance between the P-type region (well region 11) formed to a deep position with a relatively high doping concentration and the cathode region 82 can be ensured, thereby improving the withstand voltage. The end of the cathode region 82 in the Y-axis direction of this example is arranged to be farther away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction can be arranged between the well region 11 and the contact hole 54.

[0088] Figure 3A It is shown Figure 2ee cross section in FIG. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in this cross section.

[0089] The interlayer insulating film 38 is provided on the front surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. Figure 2 The contact hole 54 described in FIG.

[0090] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is an example of a front electrode. The emitter electrode 52 may be in contact with the semiconductor substrate 10 through a contact hole 54 of the interlayer insulating film 38. Alternatively, a contact plug portion may be provided in the contact hole 54 and connect the emitter electrode 52 to the semiconductor substrate 10. The contact plug portion may include a plug formed of tungsten or the like, and a barrier metal containing titanium provided in a portion in contact with the semiconductor substrate 10. The barrier metal may include a titanium nitride layer, or may include a stacked structure of a titanium nitride layer and a titanium layer.

[0091] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0092] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is disposed in the transistor portion 70, the diode portion 80 and the boundary region 200 respectively.

[0093] In this example, the plurality of mesa portions 60 include a second mesa portion 62, a third mesa portion 63, and a fourth mesa portion 64. The second mesa portion 62 is provided in the transistor portion 70, the third mesa portion 63 is provided in the diode portion 80, and the fourth mesa portion 64 is provided in the boundary region 200.

[0094] In the second mesa portion 62 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in order from the front surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the second mesa portion 62. The accumulation region 16 is arranged between the base region 14 and the drift region 18.

[0095] The emitter region 12 is exposed on the front surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0096] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the groove portions on both sides of the second mesa portion 62.

[0097] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. That is, the donor concentration of the accumulation region 16 is higher than the donor concentration of the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be improved and the on-state voltage can be reduced. The accumulation region 16 can be provided to cover the entire back surface of the base region 14 in the second terrace portion 62.

[0098] In the third terrace portion 63 of the diode portion 80, an anode region 84 is provided in contact with the front surface 21 of the semiconductor substrate 10. The doping concentration of the anode region 84 may be the same as the doping concentration of the base region 14, or may be lower than the doping concentration of the base region 14. The doping concentration of the anode region 84 in this example is lower than the doping concentration of the base region 14. The base region 14 in this example is of P-type, and the anode region 84 is of P--type. A drift region 18 is provided below the anode region 84. An accumulation region 16 may be provided below the anode region 84.

[0099] In the fourth terrace portion 64 of the boundary region 200 of this example, a P-type anode region 84 is provided in contact with the front surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the anode region 84. In the fourth terrace portion 64, an accumulation region 16 may be provided below the anode region 84.

[0100] In the transistor portion 70, the diode portion 80, and the boundary region 200, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak having a higher doping concentration than the doping concentration of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the top of the concentration peak. In addition, the doping concentration of the drift region 18 may use the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0101] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be set at the same depth position as, for example, a chemical concentration peak of hydrogen (protons) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0102] In the transistor portion 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14 or may contain an acceptor different from the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0103] In the diode portion 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements that become the donors and acceptors of each region are not limited to the above examples.

[0104] In the boundary region 200, a collector region 22 of a P+ type is provided below the buffer region 20. That is, the boundary region 200 can be regarded as a part of the transistor portion 70. The collector region 22 of the boundary region 200 can have the same doping concentration as the boundary region 200 of the transistor portion 70. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 can be set as the boundary position in the X-axis direction between the diode portion 80 and the boundary region 200.

[0105] In other examples, a part or all of the collector region 22 may be replaced with the cathode region 82 in the boundary region 200. In the case where the cathode region 82 is provided on the back side of the boundary region 200, the region where the contact region 15 and the anode region 84 are alternately arranged in the region sandwiched by the anode region 84 may be set as the diode portion 80, and the region where the contact region 15 is arranged in the entire region sandwiched by the anode region 84 may be set as the boundary region 200. In the case where the cathode region 82 is provided on the back side of the boundary region 200, the boundary region 200 may also be regarded as a part of the diode portion 80.

[0106] The groove portion on the diode portion 80 side of the two groove portions connected to the emitter region 12 arranged closest to the diode portion 80 in the X-axis direction may be a dummy groove portion 30. The dummy groove portion 30 in this case may be set as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80). The center position in the X-axis direction of the dummy groove portion 30 may be set as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80).

[0107] The emitter region 12 may be provided in the boundary region 200. However, in this case, the gate groove portion 40 is not provided in the boundary region 200. In addition, the groove portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy groove portion 30. That is, the transistor operation does not occur in the boundary region 200. The gate groove portion 40 may also be provided in the boundary region 200. However, in this case, the emitter region 12 is not provided in the boundary region 200. That is, the transistor operation does not occur in the boundary region 200.

[0108] The collector region 22 and the cathode region 82 are exposed on the back surface 23 of the semiconductor substrate 10 and connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0109] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the front side 21 of the semiconductor substrate 10. Each groove portion penetrates the base region 14 or the anode region 84 from the front side 21 of the semiconductor substrate 10 and is provided below the base region 14 and the anode region 84. In the region where at least any one of the emitter region 12, the contact region 15 and the storage region 16 is provided, each groove portion also penetrates these doped regions. The method of manufacturing in which the groove portion penetrates the doped region is not limited to the order of forming the groove portion after the doped region is formed. The method of forming the doped region between the groove portions after the groove portion is formed is also included in the method of the groove portion penetrating the doped region.

[0110] As described above, the gate trench portion 40 and the dummy trench portion 30 are provided in the transistor portion 70. In this example, the dummy trench portion 30 is provided in the diode portion 80 and the boundary region 200, and the gate trench portion 40 is not provided. However, the boundary between the boundary region 200 and the transistor portion 70 may be provided with the gate trench portion 40 or the dummy trench portion 30.

[0111] It should be noted that the boundary region 200 is a buffer structure for arranging two different structures, the transistor portion 70 and the diode portion 80, in parallel. Therefore, the width of the boundary region 200 in the X-axis direction may be very short. For example, the boundary region 200 may be provided to cover one or more degrees of the width of the fourth stage portion 64, or may not be provided.

[0112] The boundary region 200 may be provided widely in the X-axis direction over a plurality of fourth terrace portions 64. Thus, the influence of the transistor portion 70 on the characteristics of the diode portion 80 can be suppressed, for example, the influence of the operation of the gate trench portion 40 and the discharge or injection of holes in the contact region 15 on the forward voltage and reverse recovery characteristics can be suppressed.

[0113] The gate trench portion 40 includes a gate trench provided on the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided in a manner covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position further inside than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0114] The gate conductive portion 44 can be set longer than the base region 14 in the depth direction. The gate groove portion 40 in the cross section is covered by the interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is connected to the gate groove portion 40.

[0115] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy groove provided on the front surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and is provided at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0116] The gate trench 40 and the dummy trench 30 of this example are covered by the interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may be curved surfaces convex downward (curved in cross section).

[0117] The second mesa portion 62 of this example is provided with a trench contact portion 17. The trench contact portion 17 is a portion where the front electrode (i.e., the emitter electrode 52 or the contact plug portion) is provided inside the mesa portion. The trench contact portion 17 can be formed by forming a groove in the front surface 21 of the semiconductor substrate 10 exposed by the contact hole 54 and filling the front electrode inside the groove. In the second mesa portion 62, the region of the trench contact portion 17 where the second mesa portion 62 is connected to the front electrode corresponds to the contact portion.

[0118] The third terrace portion 63 of this example is provided with a front contact portion 87 in which the front electrode is in contact with the front surface of the third terrace portion 63. The lower end of the front contact portion 87 is arranged at a position higher than the lower end of the groove contact portion 17. The fourth terrace portion 64 of this example may be provided with a groove contact portion 17 or a front contact portion 87. Alternatively, the groove contact portion 17 may be provided on a part of the fourth terrace portion 64, and the front contact portion 87 may be provided on the other fourth terrace portions 64.

[0119] In this example, each contact portion refers to an interface where the front electrode and the mesa portion 60 are in contact. The contact portion may include a surface of the front electrode and a surface of the mesa portion 60. Here, in the case of the front contact portion 87, the surface of the mesa portion 60 refers to the front surface of the mesa portion 60, that is, the front surface 21 of the semiconductor substrate 10. In the case of the trench contact portion 17, the surface of the mesa portion 60 refers to the bottom surface of the contact hole 54 provided inside the mesa portion 60. The width Wpcn of the front contact portion 87 in the X-axis direction in this example may be the same as the width Wtcn of the trench contact portion 17 in the X-axis direction, may be different from the width Wtcn, or may be larger than the width Wtcn.

[0120] In addition, when a metal silicide layer is formed at the interface between the front electrode and the mesa portion 60, the metal silicide layer may be included in the front electrode. In other words, the interface between the metal silicide layer and the mesa portion 60 may be set as a contact portion.

[0121] A plug region may be provided in at least a portion of the mesa portion 60 in a region connected to the lower end of the contact portion. The plug region is a P++ type region having a doping concentration higher than that of the contact region 15. Figure 3A In the example of FIG. 8 , a second plug region 222 is provided in contact with the front contact portion 87 .

[0122] In this example, the trench contact portion 17 is provided in the transistor portion 70, thereby facilitating extraction of minority carriers (eg, holes) in the base region 14. This can improve breakdown resistance such as latch-up resistance due to minority carriers. Figure 3A The trench contact 17 shown is provided to a depth reaching the middle of the emitter region 12, and the first plug region 221 is not provided on the bottom. In other examples, the trench contact 17 may be provided to a depth reaching the base region 14, and the first plug region 221 may be provided on the bottom of the trench contact 17.

[0123] In addition, the diode portion 80 of this example is provided with a front contact portion 87 instead of the trench contact portion 17. When the trench contact portion 17 is provided, since the region with a high doping concentration near the front surface 21 of the semiconductor substrate 10 is removed in the anode region 84, the trench contact portion 17 is in contact with the region with a low doping concentration in the anode region 84. Therefore, by providing the front contact portion 87 in the third terrace portion 63 of the diode portion 80, the forward voltage of the diode portion 80 can be reduced.

[0124] The width Wpcn of the front contact portion 87 in the X-axis direction of this example is larger than the width Wtcn of the trench contact portion 17 in the X-axis direction. This can further reduce the contact resistance of the front contact portion 87 and further reduce the forward voltage of the diode portion 80.

[0125] The reverse recovery loss and forward voltage of the diode unit 80 are in a trade-off relationship. If the hole injection is increased when the diode unit 80 is turned on, the forward voltage is reduced, but the reverse recovery loss increases. On the other hand, if the extraction of holes is promoted, the reverse recovery loss is reduced, but the forward voltage of the diode unit 80 increases. In this example, by providing a trench contact portion 17 in the transistor unit 70 and providing a front contact portion 87 in the diode unit 80, the trade-off between the reverse recovery loss and the forward voltage of the diode unit 80 can be improved.

[0126] Figure 3B yes Figure 3A The second table portion 62 and the third table portion 63 are shown in an enlarged view. Figure 3B In the figure, a second stage portion 62 and a third stage portion 63 are respectively shown, and the area between the stage portions is omitted.

[0127] The emitter electrode 52 of this example is arranged on the front surface of the interlayer insulating film 38. The contact plug portion 250 includes a plug 251 and a barrier metal portion 252. The plug 251 of this example contains tungsten. The barrier metal portion 252 is arranged above the front surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is arranged at least on the bottom surface of the contact hole 54. The barrier metal portion 252 can be arranged at the lower end of each contact portion. The barrier metal portion 252 can be in contact with the semiconductor substrate 10. The barrier metal portion 252 can also be arranged on the side of the contact hole 54. The plug 251 is buried in the contact hole 54 via the barrier metal portion 252. The plug 251 and the barrier metal portion 252 can also be arranged on the front surface of the interlayer insulating film 38, or they can also be arranged on the front surface of the interlayer insulating film 38.

[0128] The barrier metal portion 252 is formed of a material having a higher hydrogen absorption property than the emitter electrode 52. Thus, hydrogen ions are suppressed from invading the semiconductor substrate 10. The barrier metal portion 252 of this example contains titanium. The barrier metal portion 252 may include a titanium nitride layer. The barrier metal portion 252 may also be a stacked film of a titanium layer and a titanium nitride layer.

[0129] The emitter electrode 52 is provided above the barrier metal portion 252. The emitter electrode 52 is also provided above the interlayer insulating film 38. The emitter electrode 52 is formed of a material different from that of the barrier metal portion 252. As an example, the emitter electrode 52 contains aluminum. The emitter electrode 52 may be an alloy of aluminum and silicon.

[0130] The width Wpcn of the front contact portion 87 in the X-axis direction of this example is larger than the width Wtcn of the trench contact portion 17 in the X-axis direction. This can reduce the contact resistance of the front contact portion 87 and reduce the forward voltage of the diode portion 80.

[0131] The third mesa portion 63 is provided in contact with the lower end of the front contact portion 87, and may include a P++ type second plug region 222 having a doping concentration higher than that of the anode region 84. The doping concentration of the second plug region 222 may be higher than that of the contact region 15. The doping concentration of the anode region 84 of the third mesa portion 63 may be lower than that of the base region 14 of the transistor portion 70. In this case, it is possible to suppress the injection of holes from the third mesa portion 63 into the drift region 18. The second plug region 222 of this example may be provided to extend along the Y-axis direction, or may be provided intermittently.

[0132] Figure 3B The depth position Z1 of the trench contact portion 17 in the Z-axis direction and the depth position Z2 of the front contact portion 87 in the Z-axis direction are shown. The depth position of the trench contact portion 17 and the front contact portion 87 refers to the deepest position at the interface where the semiconductor substrate 10 and the metal electrode (e.g., the barrier metal portion 252, the emitter electrode 52, etc.) are connected on the bottom surface of the contact hole 54. The depth position can be the distance from the front surface 21 of the semiconductor substrate 10 in the depth direction (-Z-axis direction). The depth position Z2 is configured at a shallower position than the depth position Z1.

[0133] The depth position Z2 of this example is at the same depth position as the front surface 21 of the semiconductor substrate 10. In addition, the depth position Z1 of this example is arranged at a position deeper than the front surface 21 of the semiconductor substrate 10. That is, the depth position Z1 is arranged at a position farther from the front surface 21 of the semiconductor substrate 10 than the depth position Z2.

[0134] In another example, the depth position Z2 may be a position between the depth position Z1 and the front surface 21 of the semiconductor substrate 10. In this case, with the front surface 21 of the semiconductor substrate 10 as a reference, the depth position Z2 may be a depth less than half of the depth position Z1, or may be a depth less than 1 / 4 of the depth position Z1.

[0135] Figure 4A It is shown Figure 2 FIG. ff is an example of a cross section in FIG. ff is an XZ plane passing through the contact region 15 and the cathode region 82. In the cross section ff, the contact region 15 is arranged instead of Figure 3A The emitter region 12 in the ee section is shown. The other structures are the same as those in the ee section. The structures of the trench contact 17 and the front contact 87 in the ff section are also the same as those in the ee section.

[0136] The second mesa portion 62 of this example is provided in contact with the lower end of the trench contact portion 17, and has a P++ type first plug region 221 with a doping concentration higher than that of the contact region 15. At least a portion of the first plug region 221 is provided so as to overlap with the contact region 15 when viewed from above. That is, the first plug region 221 is provided in any XZ cross section passing through the contact region 15. The first plug region 221 may be provided in an XZ cross section passing through the center of the contact region 15 in the Z-axis direction. The first plug region 221 may not be provided in any XZ cross section passing through the emitter region 12. For example, the first plug region 221 is not provided in an XZ cross section passing through the center of the emitter region 12 in the Z-axis direction. The entire first plug region 221 may also be provided so as to overlap with the contact region 15. In this case, the first plug region 221 does not overlap with the emitter region 12 when viewed from above, and the first plug region 221 is provided intermittently in the Y-axis direction. By providing each plug region, holes can be easily extracted from each land portion, thereby suppressing a decrease in tolerance.

[0137] Figure 4B yes Figure 4A The second table portion 62 and the third table portion 63 are shown in an enlarged view. Figure 4B In the figure, a second platform portion 62 and a third platform portion 63 are shown respectively, and the area between the platform portions is omitted. The structure of the third platform portion 63 is similar to Figure 3B The third terrace portion 63 shown is identical.

[0138] Relative to Figure 3B In the structure shown in FIG. 1 , the second mesa portion 62 has a contact region 15 instead of the emitter region 12 and has a first plug region 221 in contact with the lower end of the trench contact portion 17. Figure 3B Same as the example.

[0139] Figure 5 The diagram shows an example of the P-type doping concentration distribution of the anode region 84 and the second plug region 222 near the front surface of the third mesa portion 63. The vertical axis represents the doping concentration distribution in the third mesa portion 63, and the horizontal axis represents the depth position based on the front surface of the third mesa portion 63.

[0140] Figure 5 The solid line shows the P-type doping concentration distribution of this example. The depth position Z2 of this example is at the same depth position as the front surface 21. The P-type doping concentration distribution of this example is composed of the anode region 84 formed by diffusing P-type impurities from the front surface 21, and the second plug region 222 formed by ion implantation into the bottom surface of the contact hole 54.

[0141] Figure 5The doping concentration distribution of the P type in the comparative example is shown by the one-dot chain line. The comparative example is a doping concentration distribution when the third mesa portion 63 of the diode portion 80 is provided with the trench contact portion 17 as in the transistor portion 70 .

[0142] In the comparative example, since the trench contact portion 17 is provided, the high doping concentration region near the front surface 21 of the semiconductor substrate 10 is removed in the anode region 84. The P-type doping concentration distribution of the comparative example is composed of the second plug region 222, which is a region formed by ion implantation into the bottom surface of the contact hole 54 formed to the depth position Z1 in the anode region 84.

[0143] The trench contact 17 is in contact with a region of the anode region 84 having a lower doping concentration than the front contact 87. Therefore, hole injection is reduced and the forward voltage increases. Therefore, by providing the front contact 87 in the third mesa portion 63 of the diode portion 80, the forward voltage of the diode portion 80 can be reduced.

[0144] Figure 6 It is shown Figure 2 This example is a top view of another example. Figure 2 The difference is that the boundary region 200 includes a mesa portion 60, and has a base region 14 on the front side, and a contact region 15 is provided on the front side of the base region 14. In addition, the doping concentration of the anode region 84 in this example can be higher than Figure 2 The doping concentration of the anode region 84 is high and the same as the doping concentration of the base region 14. The anode region 84 of this example is of P-type.

[0145] In addition, on the front side of the mesa portion 60 of the diode portion 80, the base region 14 is provided in the Y-axis direction to sandwich the anode region 84, and the contact region 15 is provided between the anode region 84 and the base region 14. The contact region 15 may be provided to cover the end of the contact hole 54 in a plan view.

[0146] Fig. 7A It is shown Figure 6 The gg cross section is an example of a cross section in FIG. The gg cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in this cross section.

[0147] The semiconductor device 100 of this example has a lifetime adjustment region 206, which includes a lifetime inhibitor for adjusting the lifetime of carriers. The lifetime adjustment region 206 of this example is a region where the lifetime of charge carriers is locally short. Charge carriers are electrons or holes. Charge carriers are sometimes simply referred to as carriers. The lifetime adjustment region 206 of this example is formed by injecting charged particles such as helium from the front side 21 of the semiconductor substrate 10. In this example, the concentration distribution of charged particles such as helium in the depth direction of the semiconductor substrate 10 can have a shape that leads from the lifetime adjustment region 206 to the front side 21 of the semiconductor substrate 10. That is, the concentration ( / cm 3 ) may decrease monotonically from the lifetime adjustment zone 206 to the front side 21. The concentration of charged particles such as helium in the front side 21 may be greater than 0. On the other hand, in the direction from the lifetime adjustment zone 206 toward the back side 23, the concentration of charged particles such as helium may have a shape such as a trailing lead. However, the concentration of charged particles such as helium in the trailing direction toward the back side 23 decreases more sharply than the concentration of charged particles such as helium in the trailing direction toward the front side 21. The concentration of charged particles such as helium in the back side 23 is lower than the concentration of charged particles such as helium in the front side 21. The concentration of charged particles such as helium in the front side 21 may be below the measurement limit or may be 0. The lifetime adjustment zone 206 may also be formed by injecting charged particles such as helium from the back side 23 of the semiconductor substrate 10.

[0148] By injecting charged particles such as helium into the semiconductor substrate 10, lattice defects 204 such as vacancies are formed near the injection position. The lattice defects 204 generate recombination centers. The lattice defects 204 can be mainly composed of vacancies such as single atomic vacancies (V) and polyatomic vacancies (VV), which can be dislocations, interstitial atoms, or transition metals. For example, atoms adjacent to the vacancies have dangling bonds. In a broad sense, the lattice defects 204 can also include donors and acceptors, but in this specification, the lattice defects 204 mainly composed of vacancies are sometimes referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, the lattice defects 204 are sometimes referred to as recombination centers that contribute to the recombination of carriers and are simply referred to as recombination centers or lifetime inhibitors. The lifetime inhibitor can be formed by injecting helium ions into the semiconductor substrate 10. The helium chemical concentration can be set to the density of the lattice defects 204. It should be noted that the depth position of the density peak of the lifetime inhibitor may not coincide with the depth position of the helium chemical concentration peak because the lifetime inhibitor formed by helium injection is sometimes terminated by hydrogen present in the buffer region 20. In addition, when hydrogen ions are implanted into the semiconductor substrate 10, the lifetime inhibitor may be formed in a hydrogen ion passage region that is closer to the implantation surface than the range of the hydrogen ions.

[0149] Lattice defects 204 are an example of lifetime inhibitors. Fig. 7AIn the figure, the lattice defects 204 at the injection position of the charged particles are schematically shown by the × mark. In the region where a large number of lattice defects 204 remain, the carriers are captured by the lattice defects 204, so the carrier lifetime becomes short. By adjusting the carrier lifetime, the reverse recovery time, reverse recovery loss and other characteristics of the diode portion 80 can be adjusted. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime presents a minimum value can be set as the depth position of the lifetime adjustment region 206.

[0150] The lifetime adjustment zone 206 is arranged on the front side 21 of the semiconductor substrate 10. The front side 21 refers to the area from the central position in the depth direction of the semiconductor substrate 10 to the front side 21 of the semiconductor substrate 10. The lifetime adjustment zone 206 of this example is arranged at a position lower than the lower end of the groove portion. In addition, in the case where the lifetime adjustment zone 206 is formed by irradiation with a particle beam with strong transmission power such as an electron beam, lattice defects are formed approximately uniformly from the front side 21 to the back side 23 of the semiconductor substrate 10, but in this case, it can also be regarded that the depth position of the lifetime adjustment zone 206 is arranged on the front side 21 of the semiconductor substrate 10.

[0151] The lifetime adjustment region 206 may be provided in at least one of the transistor portion 70 and the diode portion 80. In the case where the semiconductor device 100 has the boundary region 200, the lifetime adjustment region 206 may also be provided in the boundary region 200. The lifetime adjustment region 206 may be provided in the entire region in the X-axis direction of the diode portion 80. The lifetime adjustment region 206 may also be provided in the entire boundary region 200. In other examples, the lifetime adjustment region 206 may also be provided in a portion of the boundary region 200.

[0152] The lifetime adjustment zone 206 of the diode section 80 of this example is extended to a portion of the transistor section 70 in the X-axis direction. The lifetime adjustment zone 206 of the diode section 80 and the lifetime adjustment zone 206 of the transistor section 70 are set at the same depth position. In the transistor section 70, the area where the lifetime adjustment zone 206 is set is set as the adjustment zone 201, and the area where the lifetime adjustment zone 206 is not set is set as the non-adjustment zone 202. The non-adjustment zone 202 is a region where the carrier lifetime at the same depth position as the lifetime adjustment zone 206 is shorter than the carrier lifetime of the lifetime adjustment zone 206 of the diode section 80. The non-adjustment zone 202 may also be a region where charged particles such as helium are not injected to form lifetime inhibitors such as lattice defects 204. The chemical concentration ( / cm 3 ) can be the same as the chemical concentration at the center of the drift region 18 of the charged particle in the Z-axis direction.

[0153] The adjustment region 201 of this example has a first terrace portion 61 and a groove contact portion 17 connected to the emitter electrode 52. The groove contact portion 17 may be provided for a portion of the first terrace portion 61, or for all of the first terrace portions 61. Alternatively, the front contact portion 87 may be provided for all of the first terrace portions 61. The second terrace portion 62 of the non-adjustment region 202 has the same Figure 3A The structure of the second mesa portion 62 described in the above is the same as that of the second mesa portion 62 described in the above description, so the description is omitted. It should be noted that the lifetime adjustment region 206 may not be extended to the transistor portion 70 without providing the adjustment region 201. Alternatively, the lifetime adjustment region 206 may be extended to the entire surface of the transistor portion 70 without providing the non-adjustment region 202.

[0154] The doping concentration of the anode region 84 may be the same as the doping concentration of the base region 14, or may be lower than the doping concentration of the base region 14. Alternatively, the doping concentration of the anode region 84 may be higher than the doping concentration of the base region 14. The semiconductor device 100 of this example has the lifetime adjustment region 206 to reduce the reverse recovery loss of the diode portion 80, so the doping concentration of the anode region 84 can be made relatively high.

[0155] The boundary region 200 of this example has a base region 14 provided in one mesa portion 60 (fourth mesa portion 64), and a contact region 15 provided on the front side of the base region 14. The ends of the contact region 15 in the Y-axis direction are sandwiched by the base region 14. As a result, holes in the semiconductor substrate 10 are easily extracted to the emitter electrode 52 via the mesa portion 60 (fourth mesa portion 64) of the boundary region 200 during the turn-off operation. In addition, the lifetime adjustment region 206 is extended to the transistor portion 70 to provide the adjustment region 201, so that the injection of holes from the contact region 15 can be suppressed. Therefore, in the X-axis direction, the boundary region 200 may not be extended over a plurality of mesa portions 60, or the boundary region 200 may not be provided.

[0156] It should be noted that, as another example, in addition to providing the lifetime adjustment region 206, a wide boundary region whose width in the X-axis direction covers a plurality of mesa portions 60 is provided, thereby further suppressing the injection of holes from the mesa portions 60 (the first mesa portion 61, the second mesa portion 62, and the fourth mesa portion 64), and reducing the loss during the reverse recovery action.

[0157] Figure 7B is included Figure 6 The hh cross section includes the contact region 15 in the cathode region 82. The hh cross section is the XZ plane passing through the contact region 15 and the cathode region 82. In the hh cross section, the contact region 15 is configured to replace Fig. 7AThe emitter region 12 in the gg cross section is shown. The other structures are the same as those in the gg cross section. In the hh cross section, the structures of the trench contact 17 and the front contact 87 are also the same as those in the gg cross section.

[0158] Figure 8 It is shown Figure 2 This example is a top view of another example. Figure 2 The difference is that the boundary region 200 is not provided. The semiconductor device 100 of this example is mainly used for a resonance circuit and is used under the condition that a reverse recovery operation is not performed.

[0159] Fig.9A It is shown Figure 8 FIG. 1 is a diagram showing an example of a jj cross section in FIG. The jj cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section.

[0160] The doping concentration of the anode region 84 in this example can be the same as the doping concentration of the base region 14, or higher than the doping concentration of the base region 14. The anode region 84 in this example is a P-type. In addition, the anode region 84 can also be formed simultaneously by ion implantation of the base region 14, the contact region 15 or the well region 11.

[0161] The second mesa portion 62 of the transistor portion 70 of the present example is provided with the trench contact portion 17. The third mesa portion 63 of the diode portion 80 of the present example is provided with the front contact portion 87.

[0162] It should be noted that the boundary region 200 is not provided in this example, but it may be provided in other examples. In this case, since the reverse recovery operation is not performed, it is not necessary to provide the boundary region 200 over a plurality of mesa portions 60 in the X-axis direction in order to suppress hole injection from the contact region 15 of the transistor portion 70, and the boundary region 200 may be formed with a narrow width. For example, the boundary region 200 may have a Fig. 7A A fourth land portion 64 of the same front contact portion 87 .

[0163] Fig. 9B It is shown Figure 8 FIG. 1 is a diagram showing an example of a kk cross section in FIG. The kk cross section is an XZ plane passing through the contact region 15 and the cathode region 82. In the kk cross section, the contact region 15 is arranged instead of Fig.9AThe emitter region 12 in the jj cross section shown. The other structures are the same as those in the jj cross section. The structures of the trench contact portion 17 and the front contact portion 87 in the kk cross section are also the same as those in the jj cross section. It should be noted that in the diode portion 80, the base region 14 can be provided in the third terrace portion 63, and the contact region 15 can be provided on the front side of the base region 14.

[0164] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0165] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the apparatus, system, program and method shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated "before...", "in advance", etc., and the result of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: Transistor Department; Diode Department; A plurality of groove portions are disposed on the front surface of the semiconductor substrate; A drift region of a first conductivity type, which is disposed on the semiconductor substrate; a base region of a second conductivity type, which is disposed above the drift region in the transistor portion; An emitter region of a first conductivity type and a contact region of a second conductivity type, both of which are arranged on the front surface of the semiconductor substrate in the transistor portion, and the doping concentration of the emitter region is higher than the doping concentration of the drift region, and the doping concentration of the contact region is higher than the doping concentration of the base region; an anode region of a second conductivity type, which is disposed above the drift region in the diode portion; A mesa portion of the semiconductor substrate, which is disposed between the plurality of groove portions; an interlayer insulating film disposed above the semiconductor substrate; A front electrode, which is disposed above the semiconductor substrate; a trench contact portion connecting the front electrode and the mesa portion in the transistor portion; and a front contact portion connecting the front electrode and the mesa portion in the diode portion, The lower end of the front contact portion is arranged above the lower end of the trench contact portion.

2. The semiconductor device according to claim 1, wherein: The width of the front contact portion in the trench arrangement direction is greater than the width of the trench contact portion in the trench arrangement direction.

3. The semiconductor device according to claim 1, wherein: The front electrode includes an emitter electrode.

4. The semiconductor device according to claim 3, wherein: The front electrode includes a contact plug portion, which is provided in a contact hole of the interlayer insulating film and connects the emitter electrode to the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein: The doping concentration of the anode region is lower than the doping concentration of the base region.

6. The semiconductor device according to claim 1, wherein: The doping concentration of the anode region is the same as the doping concentration of the base region.

7. The semiconductor device according to claim 1, wherein: The doping concentration of the anode region is higher than the doping concentration of the base region.

8. The semiconductor device according to claim 6 or 7, characterized in that: The diode portion includes a lifetime control region provided at a position closer to the front surface side than a center of the semiconductor substrate in a depth direction of the semiconductor substrate.

9. The semiconductor device according to claim 1, wherein: The semiconductor device comprises: A first plug region of the second conductivity type, which is disposed at a lower end of the trench contact portion and has a doping concentration higher than that of the contact region; and The second plug region of the second conductivity type is disposed in contact with the lower end of the front contact portion and has a doping concentration higher than that of the contact region.

10. The semiconductor device according to claim 9, wherein: The first plug region is disposed discontinuously in the extending direction of the trench.

11. The semiconductor device according to claim 9, wherein: The second plug region is arranged to extend in the trench extending direction.

12. The semiconductor device according to claim 1, wherein: The transistor portion includes an accumulation region of the first conductivity type, the accumulation region being provided above the drift region and having a doping concentration higher than that of the drift region.

13. The semiconductor device according to claim 1, wherein: The semiconductor device includes a boundary region provided between the transistor portion and the diode portion. In a plan view, an area ratio of the emitter region in the mesa portion of the boundary region is smaller than an area ratio of the emitter region in the mesa portion of the transistor portion. The front contact portion is disposed on the terrace portion of the boundary region.

14. The semiconductor device according to claim 13, wherein: A width of the boundary region in the trench arrangement direction is greater than or equal to 20 μm and less than or equal to 250 μm.

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