IGBT (Insulated Gate Bipolar Translator) structure with floating P-type and N-type buried layers

Abstract

The invention relates to an IGBT (Insulated Gate Bipolar Translator) structure with floating P and N type buried layers. A collector, a P type substrate, an n type buffer region and an n type drift region are sequentially arranged from bottom to top; the first floating P region, the first gate, the P body region, the second gate and the second floating P region are electrically contacted with the upper surface of the n-type drift region in sequence from left to right; the n-type carrier buried layer is buried in the P body region; the first N + source region and the second N + source region are respectively arranged between the first grid electrode and the second grid electrode; the lower surface of the gate oxide layer is electrically contacted with the upper surfaces of the floating P region and the gate respectively; and the lower surface of the emitter is electrically contacted with the upper surfaces of the first gate oxide layer, the first N + source region, the second N + source region, the lug boss of the P body region, the second N + source region and the second gate oxide layer respectively. According to the invention, the voltage endurance capability can be improved, and the conduction loss and the switching loss are reduced, thereby improving the reliability and prolonging the service life.

Description

Technical Field

[0001] The invention relates to the field of IGBT, and in particular to an IGBT structure with floating P and N type buried layers. Background Art

[0002] With the rapid development of power electronics technology, IGBT, as an important power semiconductor device, has been widely used in power conversion, motor drive, renewable energy and other fields; however, the traditional IGBT structure has certain limitations in current density, switching speed and loss, and it is difficult to meet the growing demand for high efficiency and high reliability. For example:

[0003] Current density is generally limited by physical structure and manufacturing process. Although IGBT has the characteristics of high current density, the traditional IGBT structure is often limited by chip design, material selection and packaging technology, which limits the improvement of current density. As the current density increases, the heating problem of IGBT will become more serious, thus affecting its reliability and service life.

[0004] The switching speed often determines the application scope of IGBT in high-frequency circuits. The switching speed of traditional IGBT is affected by the internal carrier movement speed and circuit structure, and is usually lower than that of high-speed switching devices such as MOSFET. Slow switching speed will lead to higher switching losses, increase the energy consumption and heat generation of the system, and also limit the application of IGBT in high-frequency circuits, especially in situations that require fast response and precise control.

[0005] Losses generally directly affect the efficiency and heat generation of the system. The losses of traditional IGBTs mainly include conduction losses and switching losses. Conduction losses are due to the presence of a saturation voltage Vcesat when the IGBT is in the on state, which causes energy loss when current passes through. Switching losses are generated during the IGBT switching process, including turn-on losses Eon and turn-off losses Eoff, which will reduce the efficiency of the system, increase heat generation, and may even cause overheating and damage to the IGBT.

[0006] Therefore, it is urgent to develop a new IGBT structure to solve the above technical problems. Summary of the invention

[0007] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide an IGBT structure with floating P and N type buried layers, which can improve the withstand voltage and switching speed, reduce the conduction loss and switching loss, thereby improving the reliability and service life.

[0008] In order to solve the above technical problems, the technical solution of the present invention is: an IGBT structure with floating P and N type buried layers, comprising:

[0009] The collector, the P-type substrate, the n-type buffer region and the n-type drift region are arranged in sequence from bottom to top;

[0010] A first floating P region, a first gate, a P body region, a second gate, and a second floating P region are electrically contacted with the upper surface of the n-type drift region from left to right, the filling depth of the first floating P region is greater than the filling depth of the first gate, and the filling depth of the second floating P region is greater than the filling depth of the second gate;

[0011] An n-type carrier buried layer, buried in the P body region;

[0012] A first N+ source region and a second N+ source region are respectively arranged between the first gate and the second gate and separated by a protruding portion of the P body region protruding upward, the first N+ source region is close to the first gate, and the second N+ source region is close to the second gate;

[0013] A first gate oxide layer, the lower surface of which is electrically in contact with the upper surfaces of the first floating P region and the first gate respectively;

[0014] A second gate oxide layer, the lower surface of which is electrically in contact with the upper surfaces of the second floating P region and the second gate respectively;

[0015] The emitter has a lower surface that is electrically in contact with the first gate oxide layer, the first N+ source region, the second N+ source region, the raised portion of the P body region, the second N+ source region, and the upper surface of the second gate oxide layer.

[0016] Furthermore, the n-type drift region has an embedded portion protruding upward to be embedded between the first gate and the second gate, and the lower surface of the P body region is in electrical contact with the embedded portion.

[0017] Furthermore, the first gate oxide layer, the second gate oxide layer, the first gate and the second gate are all filled in a gate trench; wherein,

[0018] The first gate oxide layer and the second gate oxide layer are symmetrical about the embedded portion;

[0019] The first gate and the second gate are symmetrical about the embedded portion.

[0020] Further, the first floating P region and the second floating P region are symmetrical about the embedded part.

[0021] In order to further lower the electric field lines near the gate to prevent electron aggregation, the first floating P region and the second floating P region are formed by ion implantation, and the implantation depth is greater than the gate trench.

[0022] In order to better ensure the voltage resistance of the device, the depth of the first floating P region and the second floating P region is 11 μm.

[0023] In order to further improve the breakdown voltage, the doping concentration of the n-type drift region is 2e12cm -3 The thickness of the P body region is 4 μm and the doping concentration is 1.5e15 cm -3 The doping concentration of the first N+ source region and the second N+ source region is 7e14cm -3 .

[0024] After adopting the above technical scheme, the present invention optimizes the layout of the floating P region and the N-type buried layer, and sets the floating P region, which can improve the voltage resistance performance of the device. The filling depth of the floating P region is greater than the filling depth of the gate, which helps to reduce the electric field lines near the gate by adjusting the carrier concentration, and prevent the bottom of the gate from being broken down due to electron accumulation, thereby further improving the breakdown voltage of the device; the n-type carrier buried layer is embedded in the p-body region to form a double-peak hole barrier. During the forward conduction process, this layer is embedded in the p-body region, which can separate the hole barrier from the drift region, prevent the breakdown voltage from being reduced due to high n-doping, and can reduce the on-state voltage drop and conduction loss without affecting the voltage resistance of the device. In addition, the on-state resistance is smaller, thereby reducing the switching loss and increasing the switching speed; the symmetrical design of the gate, gate oxide layer, floating P region and N+ source region improves the uniformity and switching speed of the device, reduces the stress concentration inside the device, improves the reliability and service life of the device, and is suitable for high-power and high-frequency application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of an IGBT structure with floating P and N type buried layers of the present invention;

[0026] Figure 2 The present invention is a flow chart for preparing an IGBT structure with floating P and N type buried layers;

[0027] Figure 3 A comparison diagram of the conduction characteristic curves of the embodiment and the conventional planar gate type IGBT;

[0028] Figure 4 1 is an energy band diagram of an embodiment and a comparative example;

[0029] Figure 5 It is a comparison diagram of the on-resistance of the embodiment and the comparative example;

[0030] Figure 6 1 is a graph showing the corresponding withstand voltage values ​​of the embodiment and the floating P regions with different thicknesses;

[0031] Figure 7 It is a diagram of withstand voltage values ​​under the optimal parameters of the embodiment;

[0032] In the figure, 1, collector; 2, P-type substrate; 3, n-type buffer; 4, n-type drift region; 5, first floating P region; 6, first gate; 7, P body region; 8, second gate; 9, second floating P region; 10, n-type carrier buried layer; 11, first N+ source region; 12, second N+ source region; 13, first gate oxide layer; 14, second gate oxide layer; 15, emitter;

[0033] Figure 3 In the figure, (a) is a graph showing the conduction characteristic of a conventional planar gate IGBT at different gate voltages; (b) is a graph showing the conduction characteristic of an embodiment at different gate voltages; (c) is Figure 3 (b) Enlarged image of the gray area;

[0034] Figure 4 In the figure, (a) is the energy band diagram of the comparative example; (b) is the energy band diagram of the embodiment.

[0035] Figure 6 In the figure, (a) is the collector voltage-current diagram of the device corresponding to the floating P region with different thicknesses; Figure 6 (b) is the withstand voltage value of the device corresponding to the floating P region with different thickness. DETAILED DESCRIPTION

[0036] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments in conjunction with the accompanying drawings.

[0037] like Figure 1 As shown, an IGBT structure with floating P and N type buried layers comprises:

[0038] The collector 1, the P-type substrate 2, the n-type buffer region 3 and the n-type drift region 4 are arranged in sequence from bottom to top;

[0039] The first floating P region 5, the first gate 6, the P body region 7, the second gate 8, and the second floating P region 9 are electrically contacted with the upper surface of the n-type drift region 4 from left to right, the filling depth of the first floating P region 5 is greater than the filling depth of the first gate 6, and the filling depth of the second floating P region 9 is greater than the filling depth of the second gate 8;

[0040] An n-type carrier buried layer 10, buried in the P body region 7;

[0041] The first N+ source region 11 and the second N+ source region 12 are respectively arranged between the first gate 6 and the second gate 8 and separated by the upwardly protruding portion of the P body region 7. The first N+ source region 11 is close to the first gate 6, and the second N+ source region 12 is close to the second gate 8;

[0042] A first gate oxide layer 13, the lower surface of which is electrically in contact with the upper surfaces of the first floating P region 5 and the first gate 6 respectively;

[0043] A second gate oxide layer 14, the lower surface of which is electrically in contact with the upper surface of the second floating P region 9 and the second gate 8 respectively;

[0044] The emitter 15 has a lower surface which is in electrical contact with the first gate oxide layer 13 , the first N+ source region 11 , the second N+ source region 12 , the raised portion of the P body region 7 , the second N+ source region 12 and the upper surface of the second gate oxide layer 14 .

[0045] Among them, the size of the n-type drift region 4 determines the withstand voltage capability of the device. The depth of the n-type drift region 4 is preferably 85μm, and the doping concentration is generally set to 1e10-1e15A / cm3. The on-state voltage drop and withstand voltage capability corresponding to different doping concentrations are different and need to be compromised.

[0046] In one embodiment, Figure 1 As shown, the n-type drift region 4 has an embedded portion (a table width W) protruding upward to be embedded between the first gate 6 and the second gate 8. Ncs ), the lower surface of the P body region 7 is in electrical contact with the embedded portion.

[0047] In one embodiment, Figure 1 As shown, the first gate oxide layer 13, the second gate oxide layer 14, the first gate 6 and the second gate 8 are all filled in a gate trench; wherein,

[0048] The first gate oxide layer 13 and the second gate oxide layer 14 are symmetrical about the embedded portion;

[0049] The first gate 6 and the second gate 8 are symmetrical with respect to the embedded portion.

[0050] The gate trench etching depth is 8.05um, the thickness of the first gate oxide layer 13 and the second gate oxide layer 14 is 0.05um, the thickness of the first gate 6 and the second gate 8 is 8um, and the first gate 6 and the second gate 8 respectively include a gate and an oxide layer wrapping the gate. The left side of the first N+ source region 11 and the left side of the n-type carrier buried layer 10 and the P body region 7 are also electrically connected to the oxide layer of the first gate 6, and the right side of the second N+ source region 12 and the right side of the n-type carrier buried layer 10 and the P body region 7 are also electrically connected to the oxide layer of the second gate 8.

[0051] In one embodiment, Figure 1 As shown, the first floating P region 5 and the second floating P region 9 are symmetrical about the embedded portion.

[0052] In one embodiment, Figure 1As shown, the first floating P region 5 and the second floating P region 9 are formed by ion implantation, and the implantation depth is greater than the gate trench, which helps to lower the electric field lines near the gate and prevent electrons from gathering.

[0053] In one embodiment, Figure 1 As shown, the ion concentration of the first floating P region 5 and the second floating P region 9 is 2e20-2e22 A / cm3, and the depth (thickness) is preferably 11 μm.

[0054] In one embodiment, the doping concentration of the n-type drift region 4 is 2e12cm -3 , the thickness of P body region 7 is 4μm, and the doping concentration is 1.5e15cm -3 The doping concentration of the first N+ source region 11 and the second N+ source region 12 is 7e14cm -3 .

[0055] The method for preparing the IGBT structure with floating P and N type buried layers involved in the above embodiment may be but is not limited to the following: Figure 2 As shown, including:

[0056] Step 0: First, a pattern structure is depicted by coating, exposure and development, and then an n-type drift region 4 is formed by an epitaxial method. This region should have good conductivity and withstand voltage;

[0057] Step 1: Thin the silicon wafer (n-type drift region 4) and perform ion implantation to form a P-type substrate 2, ensuring that it has sufficient resistivity and crystal quality;

[0058] Step 2: forming an n-type buffer layer 3 on the P-type substrate 2 by ion implantation or epitaxial growth technology, and the n-type buffer layer is used to optimize the withstand voltage characteristics of the device;

[0059] Step 3: forming a P body region 7 and an n-type carrier buried layer 10 in sequence on the n-type drift region 4 by ion implantation or epitaxial growth technology, wherein the n-type carrier buried layer 10 is embedded in the P body region 7 to ensure that a good interface is formed between the P body region 7 and the n-type carrier buried layer 10;

[0060] Step 4: Use photolithography and etching techniques to etch a mesa on the P body region 7 to prepare for the subsequent definition of the gate and other regions;

[0061] Step 5: Use photolithography and dry etching techniques to form a gate trench on the mesa, which will be used to fill the polysilicon gate later;

[0062] Step 6: Using LPCVD low pressure chemical vapor deposition process, grow an oxide layer on the bottom and sidewall of the gate trench to isolate the polysilicon gate;

[0063] Step 7: Fill the polysilicon gate on the oxide layer and etch it so that the lower surface of the polysilicon is highly smooth and uniform, forming the first gate 6 and the second gate 82, and making the first gate 6 and the second gate 8 symmetrical about the embedded part (i.e., the part between the first gate 6 and the second gate 8 of the n-type drift region);

[0064] Step 8: forming a first floating P region 5 and a second floating P region 9 above the n-type drift region 4 by ion implantation technology. In the embodiment of the present invention, the implantation depth of the floating P region is deeper than the depth of the gate trench, and the first floating P region 5 and the second floating P region 9 are symmetrical about the embedded portion.

[0065] Step 9: forming a first N+ source region 11 connected to the first gate 6 and a second N+ source region 12 connected to the second gate 8 above the n-type drift region 4 and between the first floating P region 5 and the second floating P region 9 by ion implantation or epitaxial growth technology, and making the first N+ source region 11 and the second N+ source region 12 symmetrical about the embedded portion;

[0066] Step 10: depositing a metal layer on the oxide layer, and forming an emitter 15 by photolithography and etching techniques, and making the emitter 15 contact with the upper surface of the oxide layer;

[0067] Step 11: forming a collector electrode 1 on the lower surface of the P-type substrate 2 by a metallization process, and making the P-type substrate 2 form a good ohmic contact with the collector electrode 1;

[0068] Step 12: Perform packaging process, including bonding wires and packaging shell, to complete the manufacture of IGBT devices.

[0069] The above embodiment ( Figure 1 The beneficial effects of the scheme involved in the present invention are introduced in detail.

[0070] A. The above embodiment has a smaller on-state voltage drop and lower power consumption.

[0071] Figure 3 The above embodiment and the conventional planar gate IGBT are the conduction characteristic curves. The simulation process is as follows:

[0072] The voltage bias of all electrodes is 0V, the gate voltage is increased from 0.1 to 2V, and the collector voltage is scanned from 0, 1V to 20V in a certain step length to obtain the conduction characteristic curve; Figure 3 The on-state characteristic curves under different gate voltages are shown. When the drain current reaches 1e-6A / μm, the corresponding on-state voltage drop is 1.5V, which meets the design requirements. The on-state voltage drop Von of the IGBT structure is:

[0073] V on =vp+N +V MOS +V FS

[0074] Among them, v p+N is the voltage drop of the PN junction between the collector 1 and the N-type buffer 3, V FS is the voltage drop of N-type buffer 3, V MOS It is the voltage drop of the MOSFET structure in the IGBT structure.

[0075] Figure 3 (a) is the conduction characteristic curve of the traditional planar gate IGBT under different gate voltages. When the gate voltage reaches 5V, the device is turned off. As the gate voltage increases, the current density in the collector after the device is turned on is about 1e-4A / μm, and the corresponding on-state voltage drop is about 2.5V.

[0076] Figure 3 (b) is a graph showing the conduction characteristics of the above embodiment at different gate voltages. Figure 3 (c) Figure 3 (b) is an enlarged view of the gray area. Figure 3 (b) and Figure 3 (c) It can be seen that the on-state voltage drop corresponding to the above embodiment when the collector on-state current density is 1e-6A / um is about 1.5V, which is lower than that of the traditional planar gate IGBT. The lower the on-state voltage drop, the lower the loss.

[0077] Figure 4 (a) is an energy band diagram of a comparative example (compared with the above embodiment, there is no n-type carrier burying layer 10), Figure 4 (b) is the energy band diagram of this embodiment. The comparison results show that:

[0078] In the comparative example, the high n-doping concentration at the junction of the P-body region 7 and the n-type drift region 4 partially blocks the flow of holes and restricts the holes from entering the P-body region 7. This causes the holes to gather between the P-body region 7 and the n-type drift region 4, increasing the carrier concentration of the n-type drift region 4 and reducing the on-state voltage drop of the device. However, the N-type barrier doping concentration affects the internal electric field distribution of the device, which also leads to a decrease in the breakdown voltage and affects the voltage resistance of the device.

[0079] In this embodiment, an n-type carrier buried layer 10 is introduced into the p-body region 7. As can be seen from the energy band diagram of this region, a double-peak hole barrier is formed. In the forward conduction process, the layer is embedded in the p-body region 7 to separate the hole barrier from the drift region, thereby preventing the breakdown voltage from being reduced due to high n-doping. That is, this embodiment can reduce the on-state voltage drop without affecting the withstand voltage of the device.

[0080] B. The above embodiment has smaller on-state resistance and lower switching loss at the same gate voltage.

[0081] Figure 5 The on-resistance diagram of the embodiment and the comparative example (compared with the above embodiment, there is no n-type carrier buried layer 10), the rise time is set to 1ms, the gate voltage is 6V, the drain current corresponding to the traditional IGBT is about 1E-6A / μm, and the on-resistance is calculated to be about 6000Ω. The corresponding drain current of the device made in this embodiment is about 1.4E-6A / μm, and the on-resistance is calculated to be 4285Ω. Compared with the comparative example, the on-resistance is reduced by 1715Ω, and the on-voltage drop is reduced by about 1V. This is because in the on-state, the p-body region of the traditional structure extracts holes from the n-drift region, thereby reducing the carrier concentration in the n-drift region, reducing the leakage current, and increasing the on-resistance. After the introduction of the n-type carrier buried layer, the movement trajectory of some carriers can be suppressed under high n-doping, so that they are stored between the n-drift region and the p-body region, thereby increasing the concentration of carriers in the drift region, reducing the on-state resistance of the device, increasing the leakage current, lowering the switching loss, and reducing the conduction loss, making the device easier to turn on.

[0082] C. The above embodiment has higher pressure resistance

[0083] Figure 6 This is a graph showing the device's withstand voltage and the floating P region's thickness. Figure 6 (a) is the collector voltage-current diagram of the device corresponding to the floating P region with different thicknesses; Figure 6 (b) is the withstand voltage value of the device corresponding to the floating P region with different thickness.

[0084] from Figure 6 It can be seen that when the floating P region structure (0um) is not added, the device withstand voltage is as low as 324V (the traditional IGBT is a structure without adding a floating P region). Due to the concentration of electrons, breakdown is most likely to occur at the bottom corner of the gate oxide layer. After the floating P region structure is introduced, the concentration of electrons and holes at the bottom of the gate oxide layer is improved, and the equipotential lines are lowered, thereby increasing the withstand voltage of the device (862V). The deeper the floating p structure (11 microns), the lower the equipotential lines, and the higher the withstand voltage of the device (862V). It can be seen that the addition of a floating P region in this embodiment can limit the increase in the withstand voltage of the IGBT device.

[0085] In addition, the voltage resistance of the device is also affected by the doping concentration of the n-type drift region 4. As the doping concentration of the drift region decreases, the thicker the depletion layer (J2) formed, the higher the voltage resistance of the device. However, IGBT needs to make a trade-off between breakdown voltage and on-state voltage drop. As the doping concentration of the drift region decreases, the J2 junction becomes thicker, thereby increasing the on-state voltage drop. Therefore, simply reducing the doping concentration of the epitaxial layer is not possible without limitations. The voltage resistance of IGBT (insulated gate bipolar transistor) is affected by the P body region 7 and the N+ source region, which are mainly related to the electric field distribution inside the device and the formation of the PN junction.

[0086] The size, doping concentration and electric field distribution of the P-body region 7 have a great influence on the formation and performance of the PN junction. The larger and higher the doping concentration of the P-body region 7, the better the withstand voltage of the device is generally. After all, they can reduce the electric field concentration, thereby reducing the breakdown at the PN junction. Since J2 plays an important role in withstand voltage, increasing the doping concentration of the P-type region also helps to increase the thickness of J2, thereby increasing the withstand voltage value. However, compared with the n-type drift region 4, the size of the p-body region 7 is too small, so increasing the doping concentration has little effect on the withstand voltage value of the device.

[0087] By controlling the doping concentration of the N+ source region, the electric field distribution inside the device can be made more uniform and the electric field concentration near the PN junction can be reduced, thereby improving the voltage resistance of the device.

[0088] After simulation experiments, the optimal parameters were determined: when the floating P region depth is 11 μm, the doping concentration of the n-type drift region 4 is 2e12 cm -3 , P body thickness is 4 μm, doping concentration is 1.5e15 cm -3 , N source doping concentration is 7e14 cm -3 The resulting device breakdown voltage reaches 1300-1400V (specifically Figure 7 The on-state voltage drop is only 1.5V.

[0089] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. An IGBT structure with floating P and N type buried layers, characterized in that: include: A collector (1), a P-type substrate (2), an n-type buffer region (3) and an n-type drift region (4) are arranged in sequence from bottom to top; A first floating P region (5), a first gate (6), a P body region (7), a second gate (8), and a second floating P region (9) are electrically contacted with the upper surface of the n-type drift region (4) in sequence from left to right, the filling depth of the first floating P region (5) being greater than the filling depth of the first gate (6), and the filling depth of the second floating P region (9) being greater than the filling depth of the second gate (8); An n-type carrier buried layer (10), buried in the P body region (7); A first N+ source region (11) and a second N+ source region (12) are respectively arranged between the first gate (6) and the second gate (8), and are separated by a protruding portion of the P body region (7) protruding upward, the first N+ source region (11) being close to the first gate (6), and the second N+ source region (12) being close to the second gate (8); A first gate oxide layer (13), the lower surface of which is in electrical contact with the upper surfaces of the first floating P region (5) and the first gate (6); A second gate oxide layer (14), the lower surface of which is in electrical contact with the upper surfaces of the second floating P region (9) and the second gate (8) respectively; An emitter (15), the lower surface of which is respectively in electrical contact with the first gate oxide layer (13), the first N+ source region (11), the second N+ source region (12), the raised portion of the P body region (7), the second N+ source region (12) and the upper surface of the second gate oxide layer (14).

2. The IGBT structure with floating P and N type buried layers according to claim 1, characterized in that: The n-type drift region (4) has an embedded portion protruding upward to be embedded between the first gate (6) and the second gate (8), and the lower surface of the P body region (7) is in electrical contact with the embedded portion.

3. The IGBT structure with floating P and N type buried layers according to claim 2, characterized in that: The first gate oxide layer (13), the second gate oxide layer (14), the first gate (6) and the second gate (8) are all filled in a gate trench; wherein: The first gate oxide layer (13) and the second gate oxide layer (14) are symmetrical about the embedded portion; The first grid (6) and the second grid (8) are symmetrical about the embedded portion.

4. The IGBT structure with floating P and N type buried layers according to claim 3, characterized in that: The first floating P region (5) and the second floating P region (9) are symmetrical about the embedded portion.

5. The IGBT structure with floating P and N type buried layers according to claim 3, characterized in that: The first floating P region (5) and the second floating P region (9) are formed by ion implantation, and the implantation depth is greater than that of the gate trench.

6. The IGBT structure with floating P and N type buried layers according to claim 5, characterized in that: The depth of the first floating P region (5) and the second floating P region (9) is 11 μm.

7. The IGBT structure with floating P and N type buried layers according to claim 1 or 6, characterized in that: The doping concentration of the n-type drift region (4) is 2e12cm -3 The thickness of the P body region (7) is 4 μm, and the doping concentration is 1.5e15 cm -3 The doping concentration of the first N+ source region (11) and the second N+ source region (12) is 7e14cm -3 .

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