Wide bandgap semiconductor trench IGBT device structure and manufacturing method thereof

Abstract

The invention provides a wide bandgap semiconductor trench IGBT device structure and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The IGBT device comprises a collector electrode, a collector region, a buffer layer, an epitaxial layer and an emitter electrode located on the epitaxial layer, wherein the collector electrode, the collector region, the buffer layer and the epitaxial layer are stacked in sequence. A buried layer and a well region are arranged in the epitaxial layer; and at least one trench gate structure penetrating through the well region is also arranged. The bottom of the trench gate structure is provided with a second doped region in direct contact with the trench gate structure, and the top of the trench gate structure is covered with an interlayer dielectric layer. The two sides of the trench gate structure are provided with emitter trenches surrounded by the first doped region. The first doped region is in direct contact with the buried layer. An emitter dielectric layer is deposited along the wall of the emitter trench, and the emitter dielectric layer is filled with a semiconductor material. A conductive layer is disposed in a portion of the buried layer below the trench gate structure. The collector region, the buried layer, the well region, the first doped region and the second doped region have the same doping type, and are different from the buffer layer, the epitaxial layer and the conductive layer in doping type.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a wide bandgap semiconductor trench IGBT device structure and a manufacturing method thereof. Background Art

[0002] As a fully controlled power semiconductor device, the insulated gate bipolar transistor (IGBT) has the characteristics of both field effect transistor and bipolar transistor. It has the advantages of high operating frequency, high input impedance, low switching loss, low on-state voltage, and high current density. It is widely used in new energy vehicles, rail transit, smart grid and other technical fields.

[0003] Compared with traditional semiconductor (such as Si) IGBT, wide bandgap semiconductor (such as SiC) IGBT has the characteristics of high withstand voltage and high power. However, it has also encountered major technical challenges in the development process, such as poor conduction characteristics, weak conductivity modulation, slow turn-off speed, etc. Wide bandgap semiconductor IGBT also includes trench IGBT and planar IGBT. Planar IGBT is easier to realize in terms of process, but has a higher conduction voltage drop than trench IGBT.

[0004] However, the following problems still exist in the development of trench IGBT: (1) Since the trench IGBT reduces the JFET (Junction Field-Effect Transistor) area in the planar IGBT device, although it can significantly reduce the on-state voltage drop without increasing the device turn-off loss, the high electric field in the blocking state causes the electric field on the gate dielectric layer to increase, and the electric field intensifies at the groove corner of the gate groove, causing the gate dielectric layer to be quickly broken down under high drain voltage. Therefore, the device ultimately has poor tolerance to the electrostatic effects of harsh environments and high-voltage spikes in the circuit, and the risk of device failure is doubled, affecting the long-term reliability of the device. (2) The compromise relationship between the on-state voltage drop and the turn-off loss of the trench IGBT device has not yet reached the ideal state and still needs to be further improved. Therefore, it is necessary to optimize the device structure of the trench IGBT to protect the gate dielectric layer, especially the bottom and groove corner of the gate groove. The optimized device structure must also achieve the purpose of improving the contradictory relationship between the on-state voltage drop and the turn-off loss. Summary of the invention

[0005] Based on the above technical problems, the present invention provides a wide bandgap semiconductor trench IGBT device structure, which has the characteristics of reducing the trench corner electric field of the trench gate structure, balancing the compromise relationship between the gate oxide electric field and the conduction characteristics of the device, and reducing the device turn-off loss.

[0006] Specifically, in order to achieve the above purpose, the present invention adopts the following technical effects: A wide bandgap semiconductor trench IGBT device structure, comprising a collector, a collector region, a buffer layer and an epitaxial layer stacked in sequence, and an emitter located on the epitaxial layer; a buried layer and a well region located on the buried layer are provided in the epitaxial layer; at least one trench gate structure penetrating the well region is provided in the epitaxial layer; a second doped region directly in contact with the trench gate structure is provided at the bottom, and the top is covered by an interlayer dielectric layer located on the lower surface of the emitter; emitter trenches penetrating the well region are provided on both sides of the trench gate structure; the emitter trench is surrounded by a first doped region; The first doped region is in direct contact with the buried layer; an emitter dielectric layer is deposited along the wall of the emitter trench, and a semiconductor material is filled inside the emitter trench; along the first direction, a conductive layer is arranged in a portion of the buried layer below the trench gate structure; the conductive layer is a multi-layer structure; the first direction refers to a direction perpendicular to the direction from the collector to the emitter and perpendicular to the direction from the emitter trench to the gate trench; the doping types of the collector region, the buried layer, the well region, the first doped region, and the second doped region are of the first type; the doping types of the buffer layer, the epitaxial layer, and the conductive layer are of the second type.

[0007] In a preferred solution, a third doping region of the second doping type is disposed on the upper surface of the well region; and an ohmic metal layer is disposed on the upper surface of the third doping region.

[0008] In a preferred embodiment, along the first direction, above the buried layer where the conductive layer is not provided, a fourth doping region is provided which is in direct contact with both the first doping region and the second doping region; the doping type of the fourth doping region is the first type.

[0009] In a preferred embodiment, along the first direction, above the buried layer where the conductive layer is provided, a fifth doping region is provided which is in direct contact with both the first doping region and the second doping region; the doping type of the fifth doping region is the second type.

[0010] In a preferred solution, the dimensions of each layer of the conductive layer in the direction from the emitter trench to the trench gate structure are different, and the doping concentration of each layer is different.

[0011] In a preferred solution, the emitter trench is a multi-level structure.

[0012] The present invention also provides a method for preparing the wide bandgap semiconductor trench IGBT device structure, comprising the following steps: S1. forming a buffer layer, an epitaxial layer and a buried layer on the collector region; S2, forming a well region on the upper layer of the epitaxial layer; S3, etching a gate trench and an emitter trench in the epitaxial layer; S4, forming a first doping region around the emitter trench; forming a second doping region at the bottom of the gate trench; S5, forming a conductive layer in a portion of the buried layer below the second doped region; S6, forming a gate dielectric layer on the inner wall of the gate trench, and then growing a gate; forming an emitter dielectric layer on the inner wall of the emitter trench, and then depositing a semiconductor material; S7, depositing an interlayer dielectric material on the structure obtained in step S6, and etching to retain the interlayer dielectric material on the gate and the upper surface of the gate dielectric layer to obtain an interlayer dielectric layer; S8. Fabricate an emitter on the upper surface of the structure obtained in step S7, and fabricate a collector on the surface of the collector region away from the buffer layer.

[0013] In a preferred embodiment, step S2 further includes the following steps: forming a third doped region in the upper layer of the well region; and step S8 further includes the following steps before manufacturing the emitter: depositing an ohmic contact metal on the upper surface of the third doped region to form an ohmic metal layer.

[0014] In a preferred solution, step S5 further includes the following steps: forming a fourth doping region around the second doping region above the buried layer where the conductive layer is not provided.

[0015] In a preferred solution, step S5 further includes the following steps: forming a fifth doping region around the second doping region above the conductive layer.

[0016] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) In the present invention, by controlling the doping depth and concentration of the first doping region around the emitter trench, the protection effect of the trench gate structure can be regulated. The first doping region is in direct contact with the buried layer, which can ensure that the buried layer is always in a grounded state, and can also achieve the purpose of well protecting the trench angle of the trench gate structure. If there is a part of the electric field passing through the buried layer through the conductive layer, the second doping region located at the bottom of the trench gate structure can further protect the trench angle. Therefore, the deep masking structure formed by the first doping region, the buried layer and the second doping region can better protect the trench angle of the trench gate structure, reduce the electric field at the trench angle, and improve the gate oxide reliability of the device.

[0017] (2) By controlling the doping width and doping concentration of each layer of the multilayer conductive layer, the conduction characteristics of the IGBT device can be controlled. A larger doping width and a higher doping concentration can further reduce the conduction voltage drop of the device and improve the conduction characteristics of the device.

[0018] (3) The buried layer set in the epitaxial layer can effectively extract holes in the drift region during the device shutdown process. By controlling the doping width of the conductive layer, the doping width of the buried layer can be controlled, thereby further controlling the speed of hole extraction during the device shutdown process. A buried layer with a larger doping area can increase the device shutdown speed and reduce the device shutdown loss.

[0019] (4) The fourth doped region located below the trench gate structure and in direct contact with the second doped region can ensure that the second doped region is in a grounded state, thereby enhancing the protective effect of the second doped region on the gate, thereby better improving the dynamic reliability of the device.

[0020] (5) The fifth doping region located below the trench gate structure and in direct contact with the second doping region serves as a current enhancement region. By controlling its doping area and doping concentration, the conduction characteristics of the device can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the three-dimensional structure of a wide bandgap semiconductor trench IGBT device provided in Example 1 of the present invention; and also a schematic diagram of the structure of the IGBT device prepared in Example 2; Figure 2 for Figure 1 A cross-sectional view of the upper section A; Figure 3 for Figure 1 A cross-sectional view of the upper section B; Figure 4~Figure 14 A schematic diagram of the process of preparing an IGBT device structure in Example 2; Fig.15 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram; Fig.16 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram; Fig.17 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram; Fig.18 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram; Fig.19 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram; Fig. 20 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section B (reference Figure 1 ) schematic diagram; Fig.21 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section B (reference Figure 1 ) schematic diagram; Fig. 22 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram.

[0022] In the figure: 1, collector region; 2, buffer layer; 3, epitaxial layer; 301, first epitaxial layer; 302, second epitaxial layer; 4, buried layer; 5, well region; 6, trench gate structure; 601, gate trench; 602, gate dielectric layer; 603, gate; 701, emitter trench; 702, emitter dielectric layer; 703, semiconductor material; 8, first doped region; 9, second doped region; 10, conductive layer; 11, collector; 12, emitter; 13, interlayer dielectric layer; 14, third doped region; 15, ohmic metal layer; 16, fourth doped region; 17, fifth doped region. DETAILED DESCRIPTION

[0023] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present application so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following implementation modes by those of ordinary skill in the art without creative work belongs to the protection scope of the present application.

[0024] Directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., indicate directions or positional relationships based on directions or positional relationships in the drawings of the specification, or directions or positional relationships in which the products of this application are usually placed when in use, and are only for the convenience of describing and understanding the product structure of this application. Therefore, directional terms cannot be understood as limiting this application. In this application, unless otherwise clearly defined, expressions such as "upper", "above", "above", and "upper surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. Expressions such as "lower", "below", "below", and "lower surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is lower in level than the second feature. Ordinal numbers used in this application, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0025] Example 1 Reference Figures 1 to 3 , a wide bandgap semiconductor trench IGBT device structure, comprising a collector 11, a collector region 1, a buffer layer 2 and an epitaxial layer 3 stacked in sequence, and an emitter 12 located on the epitaxial layer 3. A buried layer 4 and a well region 5 are provided in the epitaxial layer 3. In the direction from the collector 11 to the emitter 12, the buried layer 4 is located below the well region 5. At least one trench gate structure 6 is provided in the epitaxial layer 3. The trench gate structure 6 includes a gate trench 601 (refer to Figure 6-10 ), a gate dielectric layer 602 deposited along the inner wall of the gate trench, and a gate 603 filled in the gate trench. The trench gate structure 6 penetrates the well region 5, and its bottom is located above the buried layer 4 and does not contact the buried layer 4. A second doped region 9 is provided at the bottom of the trench gate structure 6 in direct contact with it. The top of the trench gate structure 6 is covered by an interlayer dielectric layer 13. On both sides of the trench gate structure 6, an emitter trench 701 is provided that penetrates the well region 5 (refer to Figure 6-10). The emitter trench 701 is surrounded by the first doped region 8 (including the outside of the sidewalls and the outside of the bottom of the emitter trench). The first doped region 8 is in direct contact with the buried layer 4. An emitter dielectric layer 702 is deposited along the inner wall of the emitter trench 701. The emitter trench 701 is filled with a semiconductor material 703. The direction perpendicular to the direction from the collector to the emitter and perpendicular to the direction from the emitter trench to the gate trench is defined as the first direction. Along the first direction, below the trench gate structure 6 (or below the second doped region 9), a conductive layer 10 is provided in a portion of the buried layer 4. In the direction from the emitter 12 to the collector 11, the conductive layer 10 is divided into multiple layers. Among them, the doping type of the collector region 1, the buried layer 4, the well region 5, the first doped region 8, and the second doped region 9 is the first type; the doping type of the buffer layer 2, the epitaxial layer 3, and the conductive layer 10 is the second type.

[0026] By controlling the depth (the dimension in the direction from the emitter 12 to the collector 11) and the doping concentration of the first doping region 8, the protection effect of the trench gate structure 6 can be adjusted. The first doping region 8 is in direct contact with the buried layer 4, which can ensure that the buried layer 4 is always in a grounded state, and can also play a good role in protecting the groove angle of the trench gate structure 6. If there is a part of the electric field passing through the buried layer 4 through the conductive layer 10, the second doping region 9 can further protect the groove angle of the trench gate structure 6. Therefore, the deep masking structure formed by the first doping region 8, the buried layer 4 and the second doping region 9 can better protect the groove angle of the trench gate structure 6, reduce the electric field of the groove angle, and improve the reliability of the gate dielectric layer 602.

[0027] The conduction characteristics of the IGBT device can be controlled by controlling the width (the dimension in the direction from the emitter trench to the gate trench) and doping concentration of each layer of the conductive layer 10. When the width of the conductive layer 10 is larger and the doping concentration is higher, it is more conducive to reducing the conduction voltage drop of the device, thereby improving the conduction characteristics of the device.

[0028] The buried layer 4 can extract holes in the drift region (i.e., the first epitaxial layer 301) well during the shutdown process of the IGBT device. The width of the buried layer 4 (the size of the buried layer 4 in the direction from the emitter trench to the gate trench) can be controlled by controlling the width of the conductive layer 10, thereby controlling the extraction speed of the device during the shutdown process. The larger the area of ​​the buried layer 4, the more conducive it is to improving the shutdown speed of the device, thereby reducing the shutdown loss of the device and improving the shutdown characteristics of the device.

[0029] In a further preferred embodiment, a third doping region 14 of the second doping type is disposed on the upper surface of the well region 5. An ohmic metal layer 15 is disposed on the upper surface of the third doping region 14. Both the first doping region 8 and the third doping region 14 form ohmic contacts with the emitter 12 through the ohmic metal layer 15.

[0030] In a further preferred embodiment, along the first direction, above the buried layer 4 where the conductive layer 10 is not provided, a fourth doping region 16 is provided, which is in direct contact with both the first doping region 8 and the second doping region 9. The fourth doping region 16 has the first doping type.

[0031] The fourth doping region 16 is used to ensure that the second doping region 9 is in a grounded state, further enhance the protection effect of the second doping region 9 on the trench gate structure 6, and better improve the dynamic reliability of the device.

[0032] In a further preferred embodiment, along the first direction, above the buried layer 4 provided with the conductive layer 10, a fifth doping region 17 is provided, which is in direct contact with both the first doping region 8 and the second doping region 9. The doping type of the fifth doping region 17 is the second type.

[0033] The fifth doping region 17 serves as a current enhancement region. By controlling the doping area and concentration of the fifth doping region 17 , the conduction characteristics of the device can be further improved.

[0034] As an example, the collector region 1, the buried layer 4, the first doped region 8, the second doped region 9, and the fourth doped region 16 are doped with P+ type, and the well region 5 is doped with P type; the buffer layer 2 and the epitaxial layer 3 are doped with N-type, and the conductive layer 10, the third doped region 14, and the fifth doped region 17 are doped with N+ type. Alternatively, the collector region 1, the buried layer 4, the first doped region 8, the second doped region 9, and the fourth doped region 16 are doped with N+ type, and the well region 5 is doped with N type; the buffer layer 2 and the epitaxial layer 3 are doped with P-type, and the conductive layer 10, the third doped region 14, and the fifth doped region 17 are doped with P+ type.

[0035] As an example, the epitaxial layer 3 is separated into a first epitaxial layer 301 and a second epitaxial layer 302 by the buried layer 4. The doping concentration of the second epitaxial layer 302 is higher than that of the first epitaxial layer 301.

[0036] As an example, the depth of the first doped region 8 is controlled so that the bottom of the first doped region 8 is flush with the bottom of the buried layer 4 (eg Figure 2 as shown). Or Fig.15 As shown, the depth of the first doped region 8 is controlled so that the first doped region 8 penetrates the buried layer 4, and its bottom extends in the epitaxial layer 3 toward the buffer layer 2 (not in contact with the buffer layer 2). At this time, a super junction structure is formed in the device structure, and increasing the doping concentration of the first doped region 8 can attract the electric field to a greater extent, so that less electric field is gathered toward the trench gate structure 6, thereby further reducing the trench corner electric field of the trench gate structure 6 and improving the gate reliability of the device.

[0037] As an example, the width and concentration of each layer of the conductive layer 10 are different. For example, the conductive layer 10 is a three-layer structure, and the width of each layer (the dimension along the direction from the emitter trench to the gate trench) gradually decreases in the direction from the collector 11 to the emitter 12 (e.g. Figure 2 Alternatively, the conductive layer 10 is a three-layer structure, and the width of each layer gradually increases along the direction from the collector 11 to the emitter 12 (as shown in FIG. Fig.16 Alternatively, the conductive layer 10 is a three-layer structure, and along the direction from the collector 11 to the emitter 12, the widths of the upper and lower layers are greater than the width of the middle layer (as shown in FIG. Fig.17 Alternatively, the conductive layer 10 is a three-layer structure, and along the direction from the collector 11 to the emitter 12, the widths of the upper and lower layers are both smaller than the width of the middle layer (as shown in FIG. Fig.18 In some other embodiments, the width of each layer of the conductive layer 10 is the same, or / and the doping concentration of each layer is the same. By controlling the width and doping concentration of each layer of the conductive layer 10, the trade-off relationship between the gate oxide electric field and the conduction characteristics of the IGBT device can be balanced.

[0038] As an example, the emitter trench is a multi-level structure. Figure 2 The secondary grooves shown, or Fig.19 The three-level trench shown, or a trench with more levels. The role of the emitter trench is to assist the ion implantation method to prepare the first doping region 8. When the doping depth of the first doping region 8 is deeper, the high-energy ion implantation step can be saved to the maximum extent, reducing the manufacturing cost of the device. When the number of levels of the emitter trench is ≥3, the deeper implantation depth of the first doping region 8 can form a super junction, thereby modulating the electric field and improving the overall characteristics of the device.

[0039] As an example, the doping area of ​​the fourth doping region 16 can be adjusted according to actual needs. For example, along the direction from the emitter trench to the gate trench, the fourth doping region 16 can be located on both sides of the second doping region 9 (such as Figure 3 ) or only on one side of the second doping region 9 (as shown Fig. 20 and Fig.21 as shown).

[0040] As an example, the fifth doped region 17 is not in direct contact with the well region 5 (eg Figures 1 to 3 or the fifth doped region 17 is in direct contact with the well region 5 (as shown); Fig. 22 as shown).

[0041] As an example, the material of the collector region 1 is a wide bandgap semiconductor material, for example, at least one of SiC, GaN, Ga2O3, AlN, and diamond.

[0042] As an example, the material of the gate 603 is polysilicon.

[0043] As an example, the semiconductor material 703 is polysilicon.

[0044] Example 2 Reference Figure 1 to Figure 14 , a method for preparing a wide bandgap semiconductor trench IGBT device structure, comprising the following steps: S1, (cross section A & B) buffer layer, epitaxial layer and buried layer are formed on the collector region (refer to Figure 4 ). The epitaxial layer and the buried layer are formed in one of the following two ways: (1) epitaxially growing a first epitaxial layer, a buried layer, and a second epitaxial layer on the upper surface of the buffer layer in sequence. (2) epitaxially growing an epitaxial layer on the upper surface of the buffer layer, and then forming a buried layer in the epitaxial layer by ion implantation.

[0045] S2, (cross section A & B) a well region is formed in the upper layer of the epitaxial layer (refer to Figure 5 ). The method of forming the well region is any one of an ion implantation method, a secondary epitaxial method or a method of growing oxide.

[0046] S3, (cross section A & B) etch the gate trench and emitter trench through the well region in the epitaxial layer (refer to Figure 6 ). The etching method is dry etching.

[0047] S4, (cross section A & B) A first doping region is formed around the emitter trench by ion implantation. A second doping region is formed at the bottom of the gate trench by ion implantation (refer to Figure 7 ).

[0048] S5, (cross section A) in a portion of the buried layer below the second doped region, a conductive layer is formed by ion implantation (refer to Figure 8 ).

[0049] S6, (cross section A & B) Form a gate dielectric layer on the inner wall of the gate trench, and then grow the gate. Form an emitter dielectric layer on the inner wall of the emitter trench, and then deposit semiconductor material (refer to Fig.11 and Fig.12 ).

[0050] S7, (cross section A & B) depositing an interlayer dielectric material on the structure obtained in step S6, and etching, retaining the interlayer dielectric material on the upper surface of the trench gate structure, to obtain an interlayer dielectric layer (refer to Fig.13 and Fig.14 ).

[0051] S8, (cross section A & B) an emitter is fabricated on the upper surface of the structure obtained in step S7, and a collector is fabricated on the surface of the collector region away from the buffer layer (refer to Figure 2 and Figure 3 ).

[0052] In a further preferred embodiment, step S2 further includes the following steps: forming a third doped region (see Figure 5 ). Step S8 also includes the following steps before making the emitter: depositing an ohmic contact metal on the upper surface of the third doped region to form an ohmic metal layer (refer to Figure 2 and Figure 3 ).

[0053] In a further preferred embodiment, step S5 further includes the following steps: forming a fourth doped region (refer to Fig.10 ).

[0054] In a further preferred embodiment, step S5 further includes the following steps: forming a fifth doping region (see Fig. 9 ).

[0055] The above-described embodiments are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various changes and modifications. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A wide bandgap semiconductor trench IGBT device structure, characterized in that: The invention comprises a collector, a collector region, a buffer layer and an epitaxial layer stacked in sequence, and an emitter located on the epitaxial layer; a buried layer and a well region located on the buried layer are arranged in the epitaxial layer; at least one trench gate structure penetrating the well region is arranged in the epitaxial layer; a second doped region directly in contact with the trench gate structure is arranged at the bottom, and the top is covered by an interlayer dielectric layer located on the lower surface of the emitter; emitter trenches penetrating the well region are arranged on both sides of the trench gate structure; the emitter trench is surrounded by a first doped region; the first doped region and the The buried layer is in direct contact with the emitter trench; an emitter dielectric layer is deposited along the wall of the emitter trench, and the interior of the emitter trench is filled with semiconductor material; along the first direction, a conductive layer is arranged in a portion of the buried layer below the trench gate structure; the conductive layer is a multi-layer structure; the first direction refers to a direction perpendicular to the direction from the collector to the emitter and perpendicular to the direction from the emitter trench to the gate trench; the doping type of the collector region, the buried layer, the well region, the first doped region, and the second doped region is the first type; the doping type of the buffer layer, the epitaxial layer, and the conductive layer is the second type.

2. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: A third doping region of the second doping type is disposed on the upper surface of the well region; and an ohmic metal layer is disposed on the upper surface of the third doping region.

3. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: Along the first direction, above the buried layer where the conductive layer is not provided, a fourth doping region is provided which is in direct contact with both the first doping region and the second doping region; the doping type of the fourth doping region is the first type.

4. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: Along the first direction, above the buried layer where the conductive layer is provided, a fifth doping region is provided which is in direct contact with both the first doping region and the second doping region; the doping type of the fifth doping region is the second type.

5. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: The sizes of each layer of the conductive layer in the direction from the emitter trench to the trench gate structure are different, and the doping concentration of each layer is different.

6. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: The emitter trench is a multi-level structure.

7. The method for preparing a wide bandgap semiconductor trench IGBT device structure according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1. forming a buffer layer, an epitaxial layer and a buried layer on the collector region; S2, forming a well region on the upper layer of the epitaxial layer; S3, etching a gate trench and an emitter trench in the epitaxial layer; S4, forming a first doping region around the emitter trench; forming a second doping region at the bottom of the gate trench; S5, forming a conductive layer in a portion of the buried layer below the second doped region; S6, forming a gate dielectric layer on the inner wall of the gate trench, and then growing a gate; forming an emitter dielectric layer on the inner wall of the emitter trench, and then depositing a semiconductor material; S7, depositing an interlayer dielectric material on the structure obtained in step S6, and etching to retain the interlayer dielectric material on the gate and the upper surface of the gate dielectric layer to obtain an interlayer dielectric layer; S8. Fabricate an emitter on the upper surface of the structure obtained in step S7, and fabricate a collector on the surface of the collector region away from the buffer layer.

8. The preparation method according to claim 7, characterized in that: Step S2 also includes the following steps: forming a third doped region on the upper layer of the well region; step S8 also includes the following steps before manufacturing the emitter: depositing an ohmic contact metal on the upper surface of the third doped region to form an ohmic metal layer.

9. The preparation method according to claim 7, characterized in that: Step S5 also includes the following steps: forming a fourth doping region around the second doping region above the buried layer where the conductive layer is not provided.

10. The preparation method according to claim 7, characterized in that: Step S5 also includes the following steps: forming a fifth doping region around the second doping region above the conductive layer.

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