A wide bandgap semiconductor trench IGBT device structure and manufacturing method thereof

Abstract

The present invention provides a wide bandgap semiconductor trench IGBT device structure and a method for manufacturing the same, belonging to the field of semiconductor device technology. The IGBT device includes a collector, a collector region, a buffer layer, and an epitaxial layer stacked in sequence, and an emitter located above the epitaxial layer. A buried layer and a well region are provided in the epitaxial layer; at least one trench gate structure is also provided that penetrates the well region. A second doped region is provided at the bottom of the trench gate structure, directly contacting the second doped region, and an interlayer dielectric layer covers the top. Emitter trenches are provided on both sides of the trench gate structure, each surrounded by a first doped region. The first doped region is in direct contact with the buried layer. An emitter dielectric layer is deposited along the wall of the emitter trench, and the interior of the emitter trench is filled with a semiconductor material. A conductive layer is provided in a portion of the buried layer below the trench gate structure. The collector region, buried layer, well region, first doped region, and second doped region all have the same doping type, and are different from the doping types of the buffer layer, epitaxial layer, and conductive layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a wide bandgap semiconductor trench IGBT device structure and a manufacturing method thereof. Background Art

[0002] As a fully controlled power semiconductor device, the insulated gate bipolar transistor (IGBT) combines the characteristics of a field-effect transistor and a bipolar transistor. It has the advantages of high operating frequency, high input impedance, low switching loss, low on-state voltage, and high current density. It is widely used in technical fields such as new energy vehicles, rail transit, and smart grids.

[0003] Wide-bandgap semiconductor (e.g., SiC) IGBTs offer higher voltage resistance and higher power compared to traditional semiconductor (e.g., Si) IGBTs. However, their development has also encountered significant technical challenges, such as poor on-state characteristics, weak conductivity modulation, and slow turn-off speed. Wide-bandgap semiconductor IGBTs include both trench IGBTs and planar IGBTs. Planar IGBTs are easier to implement in terms of process, but have a higher on-state voltage drop than trench IGBTs.

[0004] However, the following problems still exist in the development of trench IGBTs: (1) Since trench IGBTs reduce the JFET (Junction Field-Effect Transistor) area in planar IGBT devices, although they can significantly reduce the on-state voltage drop without increasing the device's turn-off loss, the high electric field in the blocking state causes the electric field on the gate dielectric layer to increase, and the electric field intensifies at the groove corners of the gate trench, causing the gate dielectric layer to be quickly broken down under high drain voltages. Therefore, the device's tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit is poor, the risk of device failure is doubled, and the long-term reliability of the device is affected. (2) The compromise between the on-state voltage drop and the turn-off loss of trench IGBT devices has not yet reached an ideal state and still needs further improvement. Therefore, it is necessary to optimize the device structure of the trench IGBT to protect the gate dielectric layer, especially the bottom and groove corners of the gate trench. The optimized device structure must also achieve the purpose of improving the contradictory relationship between the on-state voltage drop and the turn-off loss. Summary of the Invention

[0005] Based on the above technical problems, the present invention provides a wide bandgap semiconductor trench IGBT device structure that reduces the trench gate structure's corner electric field, balances the trade-off between the device's gate oxide electric field and on-state characteristics, and reduces device turn-off losses.

[0006] Specifically, in order to achieve the above-mentioned purpose, the present invention adopts the following technical effects:

[0007] A wide bandgap semiconductor trench IGBT device structure, comprising a collector, a collector region, a buffer layer and an epitaxial layer stacked in sequence, and an emitter located above the epitaxial layer; a buried layer and a well region located above the buried layer are provided in the epitaxial layer; at least one trench gate structure penetrating the well region is provided in the epitaxial layer; a second doped region directly in contact with the bottom of the trench gate structure is provided, and the top is covered by an interlayer dielectric layer located on the lower surface of the emitter; emitter trenches penetrating the well region are provided on both sides of the trench gate structure; the emitter trench is surrounded by a first doped region; The first doped region is in direct contact with the buried layer; an emitter dielectric layer is deposited along the wall of the emitter trench, and the interior of the emitter dielectric layer is filled with semiconductor material; along the first direction, a conductive layer is provided in a portion of the buried layer below the trench gate structure; the conductive layer is a multi-layer structure; the first direction refers to a direction perpendicular to the direction from the collector to the emitter and perpendicular to the direction from the emitter trench to the gate trench; the doping type of the collector region, the buried layer, the well region, the first doped region, and the second doped region is the first type; the doping type of the buffer layer, the epitaxial layer, and the conductive layer is the second type.

[0008] In a preferred solution, a third doping region of the second doping type is provided on the upper surface of the well region; and an ohmic metal layer is provided on the upper surface of the third doping region.

[0009] In a preferred embodiment, along the first direction, above the buried layer where the conductive layer is not provided, a fourth doping region is provided that is in direct contact with both the first doping region and the second doping region; the doping type of the fourth doping region is the first type.

[0010] In a preferred solution, along the first direction, above the buried layer where the conductive layer is provided, a fifth doping region is provided that is in direct contact with both the first doping region and the second doping region; the doping type of the fifth doping region is the second type.

[0011] In a preferred solution, the dimensions of each layer of the conductive layer in the direction from the emitter trench to the trench gate structure are different, and the doping concentration of each layer is different.

[0012] In a preferred solution, the emitter trench is a multi-level structure.

[0013] The present invention also provides a method for preparing the wide bandgap semiconductor trench IGBT device structure, comprising the following steps:

[0014] S1. forming a buffer layer, an epitaxial layer and a buried layer on the collector region;

[0015] S2, forming a well region on the upper layer of the epitaxial layer;

[0016] S3, etching a gate trench and an emitter trench in the epitaxial layer;

[0017] S4, forming a first doping region around the emitter trench; forming a second doping region at the bottom of the gate trench;

[0018] S5, forming a conductive layer in a portion of the buried layer below the second doped region;

[0019] S6, forming a gate dielectric layer on the inner wall of the gate trench, and then growing a gate; forming an emitter dielectric layer on the inner wall of the emitter trench, and then depositing a semiconductor material;

[0020] S7, depositing an interlayer dielectric material on the structure obtained in step S6, and etching to retain the interlayer dielectric material on the gate and the upper surface of the gate dielectric layer to obtain an interlayer dielectric layer;

[0021] S8. Fabricate an emitter on the upper surface of the structure obtained in step S7, and fabricate a collector on the surface of the collector region facing away from the buffer layer.

[0022] In a preferred embodiment, step S2 further includes the following steps: forming a third doped region on the upper layer of the well region; and step S8 further includes the following steps before forming the emitter: depositing an ohmic contact metal on the upper surface of the third doped region to form an ohmic metal layer.

[0023] In a preferred solution, step S5 further includes the following steps: forming a fourth doping region around the second doping region above the buried layer where the conductive layer is not provided.

[0024] In a preferred solution, step S5 further includes the following steps: forming a fifth doping region around the second doping region above the conductive layer.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] (1) In the present invention, by controlling the doping depth and concentration of the first doping region around the emitter trench, the protection effect of the trench gate structure can be regulated. The first doping region is in direct contact with the buried layer, which can ensure that the buried layer is always in a grounded state, and can also achieve the purpose of well protecting the trench corner of the trench gate structure. If there is a part of the electric field passing through the buried layer through the conductive layer, the second doping region located at the bottom of the trench gate structure can further protect the trench corner. Therefore, the deep masking structure formed by the first doping region, the buried layer and the second doping region can better protect the trench corner of the trench gate structure, reduce the electric field at the trench corner, and improve the gate oxide reliability of the device.

[0027] (2) By controlling the doping width and doping concentration of each layer of the multilayer conductive layer, the conduction characteristics of the IGBT device can be controlled. A larger doping width and a higher doping concentration can further reduce the device's conduction voltage drop and improve the device's conduction characteristics.

[0028] (3) The buried layer in the epitaxial layer can effectively extract holes from the drift region during the device shutdown process. By controlling the doping width of the conductive layer, the doping width of the buried layer can be controlled, thereby further controlling the speed of hole extraction during the device shutdown process. A larger doping area of ​​the buried layer can increase the device shutdown speed and reduce the device shutdown loss.

[0029] (4) The fourth doped region located below the trench gate structure and in direct contact with the second doped region can ensure that the second doped region is in a grounded state, thereby enhancing the protective effect of the second doped region on the gate and further improving the dynamic reliability of the device.

[0030] (5) The fifth doping region located below the trench gate structure and in direct contact with the second doping region serves as a current enhancement region. By controlling its doping area and doping concentration, the conduction characteristics of the device can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of the three-dimensional structure of a wide bandgap semiconductor trench IGBT device provided in Example 1 of the present invention; it is also a schematic diagram of the IGBT device structure prepared in Example 2;

[0032] Figure 2 for Figure 1 a cross-sectional view of the upper section A;

[0033] Figure 3 for Figure 1 a cross-sectional view of the upper section B;

[0034] Figures 4 to 14 This is a schematic diagram of the process of preparing the IGBT device structure in Example 2;

[0035] Figure 15 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram;

[0036] Figure 16 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram;

[0037] Figure 17 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram;

[0038] Figure 18 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram;

[0039] Figure 19 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram;

[0040] Figure 20 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section B (reference Figure 1 ) schematic diagram;

[0041] Figure 21 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section B (reference Figure 1 ) schematic diagram;

[0042] Figure 22 Another wide bandgap semiconductor trench IGBT device provided by the present invention is in section A (reference Figure 1 ) schematic diagram.

[0043] In the figure: 1. Collector region; 2. Buffer layer; 3. Epitaxial layer; 301. First epitaxial layer; 302. Second epitaxial layer; 4. Buried layer; 5. Well region; 6. Trench gate structure; 601. Gate trench; 602. Gate dielectric layer; 603. Gate; 701. Emitter trench; 702. Emitter dielectric layer; 703. Semiconductor material; 8. First doped region; 9. Second doped region; 10. Conductive layer; 11. Collector; 12. Emitter; 13. Interlayer dielectric layer; 14. Third doped region; 15. Ohmic metal layer; 16. Fourth doped region; 17. Fifth doped region. DETAILED DESCRIPTION

[0044] The following content clearly and completely describes the technical solution of the present application in conjunction with the embodiments so that those skilled in the art can fully understand the present application. Obviously, the embodiments described are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made by those of ordinary skill in the art to the following embodiments without creative work falls within the scope of protection of the present application.

[0045] Directional terms used in this application, such as "upper," "lower," "inner," "outer," "bottom," and "upper surface," indicate positions or locations based on the figures in the specification or the positions or locations in which the product of this application is typically placed when in use. These terms are intended solely to facilitate description and understanding of the product structure of this application. Therefore, these directional terms should not be construed as limiting this application. In this application, unless otherwise expressly defined, expressions such as "upper," "above," "above," and "upper surface" of a first feature relative to a second feature indicate that the first and second features may be in direct contact or indirect contact through an intermediary; that the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is at a higher level than the second feature. Expressions such as "lower," "below," "below," and "lower surface" of a first feature relative to a second feature indicate that the first and second features may be in direct contact or indirect contact through an intermediary; that the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is at a lower level than the second feature. The ordinal numbers used in this application, such as "first" and "second," are used solely for descriptive purposes to distinguish similar objects and are not to be construed as indicating or implying relative importance or implicitly indicating the quantity of the technical features indicated. Methods not described in detail in the following examples are conventional methods well known to those skilled in the art.

[0046] Example 1

[0047] Reference Figures 1-3 A wide bandgap semiconductor trench IGBT device structure includes a collector 11, a collector region 1, a buffer layer 2, and an epitaxial layer 3 stacked in sequence, and an emitter 12 located on the epitaxial layer 3. A buried layer 4 and a well region 5 are provided in the epitaxial layer 3. In the direction from the collector 11 to the emitter 12, the buried layer 4 is located below the well region 5. At least one trench gate structure 6 is provided in the epitaxial layer 3. The trench gate structure 6 includes a gate trench 601 (refer to Figure 6-10), a gate dielectric layer 602 deposited along the inner wall of the gate trench, and a gate 603 filled in the gate trench. The trench gate structure 6 penetrates the well region 5, and its bottom is located above the buried layer 4 and does not contact the buried layer 4. A second doped region 9 is provided at the bottom of the trench gate structure 6 in direct contact with it. The top of the trench gate structure 6 is covered by an interlayer dielectric layer 13. On both sides of the trench gate structure 6, an emitter trench 701 is provided that penetrates the well region 5 (refer to Figure 6-10 ). The emitter trench 701 is surrounded by a first doped region 8 (including the outside of the emitter trench sidewalls and the outside of the bottom). The first doped region 8 is in direct contact with the buried layer 4. An emitter dielectric layer 702 is deposited along the inner wall of the emitter trench 701. The emitter trench 701 is filled with a semiconductor material 703. The direction perpendicular to the direction from the collector to the emitter and perpendicular to the direction from the emitter trench to the gate trench is defined as the first direction. Along the first direction, below the trench gate structure 6 (or below the second doped region 9), a conductive layer 10 is provided in a portion of the buried layer 4. Along the direction from the emitter 12 to the collector 11, the conductive layer 10 is divided into multiple layers. Among them, the doping type of the collector region 1, the buried layer 4, the well region 5, the first doped region 8, and the second doped region 9 is the first type; the doping type of the buffer layer 2, the epitaxial layer 3, and the conductive layer 10 is the second type.

[0048] By controlling the depth (the dimension in the direction from the emitter 12 to the collector 11) and doping concentration of the first doped region 8, the protective effect of the trench gate structure 6 can be controlled. The first doped region 8 is in direct contact with the buried layer 4, which can ensure that the buried layer 4 is always in a grounded state, and can also effectively protect the trench corner of the trench gate structure 6. If part of the electric field passes through the buried layer 4 through the conductive layer 10, the second doped region 9 can further protect the trench corner of the trench gate structure 6. Therefore, the deep masking structure formed by the first doped region 8, the buried layer 4 and the second doped region 9 can effectively protect the trench corner of the trench gate structure 6, reduce the electric field at the trench corner, and improve the reliability of the gate dielectric layer 602.

[0049] By controlling the width (the dimension along the direction from the emitter trench to the gate trench) and doping concentration of each layer of conductive layer 10, the on-state characteristics of the IGBT device can be controlled. A wider conductive layer 10 and a higher doping concentration are more conducive to reducing the device's on-state voltage drop, thereby improving the device's on-state characteristics.

[0050] During the IGBT's shutdown process, the buried layer 4 effectively extracts holes from the drift region (i.e., the first epitaxial layer 301). By controlling the width of the conductive layer 10, the width of the buried layer 4 (the dimension of the buried layer 4 in the direction from the emitter trench to the gate trench) can be controlled, thereby controlling the extraction speed during the device's shutdown process. A larger buried layer 4 area improves the device's shutdown speed, thereby reducing turn-off losses and enhancing the device's turn-off characteristics.

[0051] In a further preferred embodiment, a third doping region 14 of the second doping type is provided on the upper surface of the well region 5. An ohmic metal layer 15 is provided on the upper surface of the third doping region 14. Both the first doping region 8 and the third doping region 14 form ohmic contacts with the emitter 12 via the ohmic metal layer 15.

[0052] In a further preferred embodiment, along the first direction, above the buried layer 4 where the conductive layer 10 is not provided, a fourth doping region 16 is provided, directly contacting both the first doping region 8 and the second doping region 9. The fourth doping region 16 has the first doping type.

[0053] The function of the fourth doping region 16 is to ensure that the second doping region 9 is in a grounded state, further enhance the protection effect of the second doping region 9 on the trench gate structure 6, and better improve the dynamic reliability of the device.

[0054] In a further preferred embodiment, along the first direction, above the buried layer 4 provided with the conductive layer 10, a fifth doping region 17 is provided, directly contacting both the first doping region 8 and the second doping region 9. The doping type of the fifth doping region 17 is the second type.

[0055] The fifth doping region 17 serves as a current enhancement region. By controlling the doping area and concentration of the fifth doping region 17 , the conduction characteristics of the device can be further improved.

[0056] As an example, the collector region 1, the buried layer 4, the first doped region 8, the second doped region 9, and the fourth doped region 16 are doped with P+ type, and the well region 5 is doped with P type; the buffer layer 2 and the epitaxial layer 3 are doped with N- type, and the conductive layer 10, the third doped region 14, and the fifth doped region 17 are doped with N+ type. Alternatively, the collector region 1, the buried layer 4, the first doped region 8, the second doped region 9, and the fourth doped region 16 are doped with N+ type, and the well region 5 is doped with N type; the buffer layer 2 and the epitaxial layer 3 are doped with P- type, and the conductive layer 10, the third doped region 14, and the fifth doped region 17 are doped with P+ type.

[0057] As an example, the epitaxial layer 3 is separated into a first epitaxial layer 301 and a second epitaxial layer 302 by the buried layer 4. The doping concentration of the second epitaxial layer 302 is higher than that of the first epitaxial layer 301.

[0058] As an example, the depth of the first doped region 8 is controlled so that the bottom of the first doped region 8 is flush with the bottom of the buried layer 4 (eg Figure 2 as shown). Or Figure 15 As shown, the depth of the first doped region 8 is controlled so that the first doped region 8 penetrates the buried layer 4, and its bottom extends in the epitaxial layer 3 toward the buffer layer 2 (without contacting the buffer layer 2). In this case, a superjunction structure is formed in the device structure. Increasing the doping concentration of the first doped region 8 can attract the electric field to a greater extent, causing less electric field to be concentrated toward the trench gate structure 6. This can further reduce the trench corner electric field of the trench gate structure 6 and improve the gate reliability of the device.

[0059] As an example, the width and concentration of each layer of the conductive layer 10 are different. For example, the conductive layer 10 is a three-layer structure, and the width of each layer (the dimension along the direction from the emitter trench to the gate trench) gradually decreases in the direction from the collector 11 to the emitter 12 (e.g. Figure 2 Alternatively, the conductive layer 10 is a three-layer structure, and the width of each layer gradually increases along the direction from the collector 11 to the emitter 12 (as shown). Figure 16 Alternatively, the conductive layer 10 is a three-layer structure, and along the direction from the collector 11 to the emitter 12, the widths of the upper and lower layers are both greater than the width of the middle layer (as shown in FIG. Figure 17 Alternatively, the conductive layer 10 is a three-layer structure, and along the direction from the collector 11 to the emitter 12, the widths of the upper and lower layers are both smaller than the width of the middle layer (as shown in FIG. Figure 18 In some other embodiments, each layer of the conductive layer 10 has the same width and / or the same doping concentration. By controlling the width and doping concentration of each layer of the conductive layer 10, the trade-off between the gate oxide electric field and the conduction characteristics of the IGBT device can be balanced.

[0060] As an example, the emitter trench is a multi-level structure. Figure 2 Secondary grooves as shown, or as Figure 19 The emitter trenches are shown as three levels, or may have more levels. The emitter trenches assist in the ion implantation process for forming the first doped region 8. A deeper doping depth in the first doped region 8 can minimize the need for high-energy ion implantation steps, reducing device manufacturing costs. When the number of emitter trenches is ≥3, the deeper implantation depth in the first doped region 8 can form a superjunction, thereby modulating the electric field and improving the overall device characteristics.

[0061] As an example, the doping area of ​​the fourth doping region 16 can be adjusted according to actual needs. For example, along the direction from the emitter trench to the gate trench, the fourth doping region 16 can be located on both sides of the second doping region 9 (such as Figure 3) or only on one side of the second doping region 9 (as shown Figure 20 and Figure 21 shown).

[0062] As an example, the fifth doping region 17 is not in direct contact with the well region 5 (eg Figures 1-3 or the fifth doped region 17 is in direct contact with the well region 5 (as shown); Figure 22 shown).

[0063] As an example, the material of the collector region 1 is a wide bandgap semiconductor material, for example, at least one of SiC, GaN, Ga2O3, AlN, and diamond.

[0064] As an example, the material of the gate 603 is polysilicon.

[0065] As an example, the semiconductor material 703 is polysilicon.

[0066] Example 2

[0067] Reference Figures 1 to 14 A method for preparing a wide bandgap semiconductor trench IGBT device structure comprises the following steps:

[0068] S1, (cross section A & B) forming a buffer layer, epitaxial layer and buried layer on the collector region (refer to Figure 4 The epitaxial layer and the buried layer are formed by one of the following two methods: (1) epitaxially growing a first epitaxial layer, a buried layer, and a second epitaxial layer on the upper surface of the buffer layer. (2) epitaxially growing an epitaxial layer on the upper surface of the buffer layer, and then forming a buried layer in the epitaxial layer by ion implantation.

[0069] S2, (cross section A & B) a well region is formed in the upper layer of the epitaxial layer (refer to Figure 5 The well region is formed by ion implantation, secondary epitaxy, or oxide growth.

[0070] S3, (cross section A & B) etch the gate trench and emitter trench through the well region in the epitaxial layer (refer to Figure 6 ). The etching method is dry etching.

[0071] S4, (cross section A & B) A first doping region is formed around the emitter trench by ion implantation. A second doping region is formed at the bottom of the gate trench by ion implantation (refer to Figure 7 ).

[0072] S5, (cross section A) in a portion of the buried layer below the second doped region, a conductive layer is formed by ion implantation (refer to Figure 8 ).

[0073] S6, (cross section A & B) a gate dielectric layer is formed on the inner wall of the gate trench, and then a gate is grown. An emitter dielectric layer is formed on the inner wall of the emitter trench, and then a semiconductor material is deposited (refer to Figure 11 and Figure 12 ).

[0074] S7, (cross section A & B) depositing an interlayer dielectric material on the structure obtained in step S6, and etching to retain the interlayer dielectric material on the upper surface of the trench gate structure to obtain an interlayer dielectric layer (refer to Figure 13 and Figure 14 ).

[0075] S8, (cross section A & B) an emitter is fabricated on the surface of the structure obtained in step S7, and a collector is fabricated on the surface of the collector region away from the buffer layer (refer to Figure 2 and Figure 3 ).

[0076] In a further preferred embodiment, step S2 further includes the following steps: forming a third doped region (refer to Figure 5 Step S8 also includes the following steps before making the emitter: depositing an ohmic contact metal on the upper surface of the third doped region to form an ohmic metal layer (refer to Figure 2 and Figure 3 ).

[0077] In a further preferred embodiment, step S5 further includes the following steps: forming a fourth doping region (refer to Figure 10 ).

[0078] In a further preferred embodiment, step S5 further includes the following steps: forming a fifth doping region (refer to Figure 9 ).

[0079] The embodiments described above are merely preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various modifications and variations. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A wide bandgap semiconductor trench IGBT device structure, characterized in that: The present invention comprises a collector, a collector region, a buffer layer and an epitaxial layer stacked in sequence, and an emitter located above the epitaxial layer; the epitaxial layer is provided with a buried layer and a well region located above the buried layer; the epitaxial layer is provided with at least one trench gate structure penetrating the well region; the bottom of the trench gate structure is provided with a second doped region directly in contact with it, and the top is covered by an interlayer dielectric layer located on the lower surface of the emitter; emitter trenches penetrating the well region are provided on both sides of the trench gate structure; the emitter trench is surrounded by a first doped region; the first doped region is in direct contact with the buried layer; the emitter trench has an emitter dielectric layer deposited along the wall, and the interior of the emitter trench is filled with semiconductor material; Along the first direction, below the trench gate structure, a conductive layer is provided in a portion of the buried layer; the conductive layer is a multi-layer structure, and each layer of the conductive layer has different dimensions in the direction from the emitter trench to the trench gate structure, and the doping concentration of each layer is different; the first direction refers to a direction perpendicular to the direction from the collector to the emitter and perpendicular to the direction from the emitter trench to the gate trench; the doping type of the collector region, the buried layer, the well region, the first doping region, and the second doping region is of the first type; the doping type of the buffer layer, the epitaxial layer, and the conductive layer is of the second type.

2. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: A third doping region of the second doping type is provided on the upper surface of the well region; and an ohmic metal layer is provided on the upper surface of the third doping region.

3. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: Along the first direction, above the buried layer where the conductive layer is not provided, a fourth doping region is provided, which is in direct contact with both the first doping region and the second doping region; the doping type of the fourth doping region is the first type.

4. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: Along the first direction, above the buried layer where the conductive layer is provided, a fifth doping region is provided, which is in direct contact with both the first doping region and the second doping region; the doping type of the fifth doping region is the second type.

5. The wide bandgap semiconductor trench IGBT device structure according to claim 1, characterized in that: The emitter trench is a multi-level structure.

6. The method for preparing a wide bandgap semiconductor trench IGBT device structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1. forming a buffer layer, an epitaxial layer and a buried layer on the collector region; S2, forming a well region on the upper layer of the epitaxial layer; S3, etching a gate trench and an emitter trench in the epitaxial layer; S4, forming a first doping region around the emitter trench; forming a second doping region at the bottom of the gate trench; S5, forming a conductive layer in a portion of the buried layer below the second doped region; S6, forming a gate dielectric layer on the inner wall of the gate trench, and then growing a gate; forming an emitter dielectric layer on the inner wall of the emitter trench, and then depositing a semiconductor material; S7, depositing an interlayer dielectric material on the structure obtained in step S6, and etching to retain the interlayer dielectric material on the gate and the upper surface of the gate dielectric layer to obtain an interlayer dielectric layer; S8. Fabricate an emitter on the upper surface of the structure obtained in step S7, and fabricate a collector on the surface of the collector region facing away from the buffer layer.

7. The preparation method according to claim 6, characterized in that Step S2 further includes the following steps: forming a third doped region on the upper layer of the well region; step S8 further includes the following steps before forming the emitter: depositing an ohmic contact metal on the upper surface of the third doped region to form an ohmic metal layer.

8. The preparation method according to claim 6, characterized in that Step S5 further includes the following steps: forming a fourth doping region around the second doping region above the buried layer where the conductive layer is not provided.

9. The preparation method according to claim 6, characterized in that Step S5 further includes the following steps: forming a fifth doping region around the second doping region above the conductive layer.

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