Semiconductor element and manufacturing method thereof
By forming an asymmetric gate dielectric layer structure in the semiconductor element, the reduction in performance caused by boron penetration and hollow effects of traditional polysilicon gates, as well as the problems of GIDL in medium voltage components, and more efficient component driving capabilities are achieved.
Patent Information
- Application Number
- CN202311154296.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-24
- Filing Date
- 2023-09-08
- Publication Date
- 2025-02-28
AI Technical Summary
In the existing metal oxide semiconductor (MOS) transistors, the component performance of the traditional polysilicon gate is reduced due to boron penetration effect and hollow-out effect. In the medium voltage component, the gate structure and doping region are too close to each other, causing problems such as the gate to cause drain leakage current (GIDL).
By forming an asymmetric gate dielectric layer structure on the substrate, the specific steps include forming the first and second gap walls on the gate structure and removing it by etching and removing by patterning masks to form an asymmetric gate dielectric layer and gap wall structure.
It effectively reduces the occurrence probability of GIDL, improves the driving capability and efficiency of semiconductor components, and solves the performance problem of traditional polysilicon gates.
Smart Images
Figure CN119545831A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for manufacturing a semiconductor element, and in particular to a method for forming an asymmetric gate dielectric layer. Background Art
[0002] In the existing semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as a standard gate filling material. However, as the size of MOS transistors continues to shrink, the traditional polysilicon gate has problems such as the boron penetration effect, which leads to reduced device performance, and the unavoidable depletion effect, which increases the equivalent gate dielectric thickness and reduces the gate capacitance, leading to the decline of device driving ability. Therefore, the semiconductor industry has tried to use new gate filling materials, such as using work function metals to replace traditional polysilicon gates as control electrodes that match high-k gate dielectric layers.
[0003] However, in the current metal gate transistor manufacturing process, especially in the preparation of medium voltage devices, the gate structure and the doped regions on both sides, such as the lightly doped drain or source / drain regions, are too close, which causes the so-called gate-induced-drain-leakage (GIDL) and other problems. Therefore, how to improve the current metal gate manufacturing process to solve this problem is an important issue today. Summary of the invention
[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor element, which mainly forms a gate structure on a substrate, then forms a first spacer on the gate structure, forms a patterned mask on the gate structure and one side of the gate structure, removes a portion of the first spacer on the other side of the gate structure, and then forms a source / drain region on both sides of the gate structure.
[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a gate structure disposed on a substrate, a first spacer disposed next to the gate structure, and a second spacer disposed next to the first spacer. The gate structure further includes a gate electrode disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate electrode, wherein the gate dielectric layer on one side of the gate electrode and the gate dielectric layer on the other side of the gate electrode are asymmetric. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figures 1 to 7 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0007] Figure 8 FIG. 4 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention.
[0008] Explanation of symbols
[0009] 12: Base
[0010] 14: Gate structure
[0011] 16: Gate dielectric layer
[0012] 18: Gate material layer
[0013] 20: Hard mask
[0014] 22: Hard Mask
[0015] 24: Hard Mask
[0016] 26: Gate electrode
[0017] 28: First spacer
[0018] 30: Second spacer
[0019] 32: Sacrificial layer
[0020] 34: Patterned Mask
[0021] 36: The third gap wall
[0022] 38: Source / Drain Region
[0023] 40: Contact hole etching stop layer
[0024] 42: Interlayer dielectric layer
[0025] 44:Metal Gate
[0026] 50: High dielectric constant dielectric layer
[0027] 52: Work function metal layer
[0028] 54: Low impedance metal layer
[0029] 56: Hard mask
[0030] 58: Contact plug DETAILED DESCRIPTION
[0031] Please refer to Figures 1 to 8 , Figures 1 to 8 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1As shown, first, a substrate 12 is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which a transistor region for preparing a medium voltage device can be defined, and the transistor region can include a PMOS transistor region or an NMOS transistor region in detail. It should be noted that although this embodiment takes the manufacture of a general planar field effect transistor as an example, in other variant embodiments, the semiconductor manufacturing process of the present invention can also be applied to non-planar field effect transistors (non-planar) such as fin-structured field effect transistors. At this time, Figure 1 The indicated substrate 12 corresponds to the fin structure formed on the substrate 12 .
[0032] According to one embodiment of the present invention, the fin structure is preferably obtained by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then the desired patterned structure, such as a strip-shaped patterned fin structure, is obtained by a fin structure cutting process (fin cut).
[0033] In addition, the formation method of the fin structure may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure. In addition, the formation method of the fin structure may also include first forming a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed from the patterned hard mask layer, and this semiconductor layer can serve as the corresponding fin structure. These embodiments of forming the fin structure are all within the scope of the present invention.
[0034] Then, at least one gate structure 14 or a dummy gate may be formed on the substrate 12. In the present embodiment, the gate structure 14 may be fabricated by a gate first fabrication process, a gate last fabrication process of a high-k first fabrication process, or a gate last fabrication process of a high-k last fabrication process according to the fabrication process requirements. Taking the post-high-k dielectric layer manufacturing process of the present embodiment as an example, a gate dielectric layer 16 or dielectric layer, a gate material layer 18 composed of polysilicon, and a selective hard mask 20 may be sequentially formed on the substrate 12, and a patterned photoresist (not shown) may be used as a mask to perform a pattern transfer manufacturing process, and a portion of the hard mask 20 and a portion of the gate material layer 18 may be removed by a single etching or successive etching steps, and then the patterned photoresist may be stripped to form a gate structure 14 composed of the patterned gate material layer 18 and the patterned hard mask 20 on the substrate 12. In the present embodiment, the gate material layer 18 may be used as a gate electrode 26, and the hard mask 20 preferably comprises a double-layer structure, wherein the lower hard mask 22 preferably comprises silicon nitride and the upper hard mask 24 preferably comprises silicon oxide, but the present invention is not limited thereto.
[0035] Subsequently, a first spacer 28 is formed on the gate structure 14 including the top surface of the gate structure 14, the sidewalls of the gate structure 14 and the surface of the gate dielectric layer 16 on both sides of the gate structure 14, and then a second spacer 30 is formed on the first spacer 28. In the present embodiment, the first spacer 28 and the second spacer 30 are preferably made of silicon oxycarbon nitride (SiOCN), but according to other embodiments of the present invention, the first spacer 28 and the second spacer 30 can be made of the same or different materials according to the manufacturing process requirements, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride, and this variation is also within the scope of the present invention.
[0036] like Figure 2 As shown, a sacrificial layer 32 is then formed on the second spacer 30 , wherein the sacrificial layer 32 preferably comprises silicon nitride, but is not limited thereto.
[0037] like Figure 3 to Figure 4 As shown, a photolithography and etching process is then performed to remove the sacrificial layer 32, the second spacer 30 and the first spacer 28 on one side of the gate structure 14. More specifically, the photolithography and etching process is as follows: Figure 3 As shown, a patterned mask 34 such as a patterned photoresist may be formed directly above the gate structure 14 and on one side of the gate structure 14 such as the right side, wherein the patterned mask 34 preferably exposes the other side of the gate structure 14 such as most of the sacrificial layer 32 on the left side and a small part of the sacrificial layer 32 on the right side.
[0038] Then as Figure 4 As shown, a portion of the sacrificial layer 32, a portion of the second spacer 30, a portion of the first spacer 28, and a portion of the gate dielectric layer 16 on the left and right sides of the gate structure 14 are removed by etching using a patterned mask 34 as a mask, so that the gate dielectric layer 16, the first spacer 28, the second spacer 30, and the sacrificial layer 32 on the left and right sides of the gate structure 14 form an asymmetric structure. More specifically, in this stage, after all the vertical and horizontal portions of the sacrificial layer 32 on the left side of the gate structure 14, a portion of the vertical and horizontal portions of the second spacer 30, a portion of the horizontal portion of the first spacer 28, and a portion of the gate dielectric layer 16 are removed by etching, the sidewalls of the sacrificial layer 32 remaining are preferably aligned with the vertical sidewalls of the second spacer 30, the horizontal sidewalls of the first spacer 28, and the sidewalls of the gate dielectric layer 16 below.
[0039] Compared with the vertical portions of the sacrificial layer 32 and the second spacer 30 on the left side of the gate structure 14 being removed, only part of the horizontal portions of the sacrificial layer 32, the second spacer 30 and the first spacer 28 on the right side of the gate structure 14 are removed, wherein the width of the remaining sacrificial layer 32 on the left side of the gate structure 14 is preferably smaller than the width of the sacrificial layer 32 on the right side of the gate structure 14, the width of the remaining second spacer 30 on the left side of the gate structure 14 is preferably smaller than the width of the second spacer 30 on the right side of the gate structure 14, the width of the remaining first spacer 28 on the left side of the gate structure 14 is preferably smaller than the width of the first spacer 28 on the right side of the gate structure 14, and the width of the gate dielectric layer 16 on the left side of the gate structure 14 is preferably smaller than the width of the gate dielectric layer 16 on the right side of the gate structure 14.
[0040] According to an embodiment of the present invention, the width of each spacer or material layer mentioned above may include the maximum distance extending from the outer sidewall of each spacer or material layer along the horizontal or X direction to the inner sidewall thereof or the sidewall of the gate structure 14. For example, the width of the sacrificial layer 32 remaining on the left side of the gate structure 14 may include the width extending from the left sidewall of the sacrificial layer 32 to the left sidewall of the gate structure 14, the width of the second spacer 30 remaining on the left side of the gate structure 14 may include the width extending from the left sidewall of the second spacer 30 to the right sidewall thereof, the width of the first spacer 28 remaining on the left side of the gate structure 14 may include the width extending from the left sidewall of the first spacer 28 that is aligned with the sidewall of the second spacer 30 to the right sidewall thereof, and the width of the gate dielectric layer 16 remaining on the left side of the gate structure 14 may include the width extending from the left sidewall of the gate dielectric layer 16 that is aligned with the sidewall of the second spacer 30 to the left sidewall of the gate structure 14.
[0041] like Figure 5As shown, an etching process is then performed to remove the sacrificial layer 32, and then a third spacer 36 is formed on the second spacer 30, wherein the third spacer 36 is preferably disposed on the top and sidewalls of the second spacer 20, the sidewalls of the first spacer 28, and the surface of the gate dielectric layer on both sides of the gate structure 14. In the present embodiment, the third spacer 36 preferably comprises silicon oxide, but is not limited thereto. According to other embodiments of the present invention, the aforementioned first spacer 28, the second spacer 30, the sacrificial layer 32, and the third spacer 36 can all be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride according to the manufacturing process requirements, and this variation is within the scope of the present invention.
[0042] Then Figure 6 As shown, an ion implantation process is performed to implant N-type or P-type dopants into the substrate 12 on both sides of the gate structure 14 to form source / drain regions 38, wherein the source / drain region 38 on the left side of the gate structure 14 is preferably a source region and the source / drain region 38 on the right side of the gate structure 14 is a drain region. Then, a contact hole etching stop layer 40 can be selectively formed to cover the surface of the third spacer 36, and then an interlayer dielectric layer 42 is formed on the contact hole etching stop layer 52. Then, a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 42, part of the contact hole etching stop layer 40, part of the third spacer 36, part of the second spacer 30, part of the first spacer 28 and all the hard masks 20 and expose the gate material layer 18 composed of polysilicon material, so that the upper surface of the gate material layer 18 is flush with the upper surface of the interlayer dielectric layer 42.
[0043] like Figure 7 As shown, a metal gate replacement (RMG) process is then performed to convert the gate structure 14 into a metal gate 44. For example, a selective dry etching or wet etching process may be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 18 in the gate structure 14 to form a groove in the interlayer dielectric layer 42 (not shown).
[0044] Then, a selective dielectric layer (not shown), a high-k dielectric layer 50, a work function metal layer 52, and a low-resistance metal layer 54 are sequentially formed in the groove, and then a planarization process is performed, such as using CMP to remove part of the low-resistance metal layer 54, part of the work function metal layer 52, and part of the high-k dielectric layer 50 to form the metal gate 44. Taking the gate structure manufactured by the post-high-k dielectric layer manufacturing process in this embodiment as an example, the gate electrode 26 in each of the formed metal gates 44 preferably includes a U-shaped high-k dielectric layer 50, a U-shaped work function metal layer 52, and a low-resistance metal layer 54.
[0045] In the present embodiment, the high-k dielectric layer 50 comprises a dielectric material having a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.
[0046] The work function metal layer 52 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 52 and the low resistance metal layer 54, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and other materials. The low resistance metal layer 54 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) and other materials or combinations thereof. Subsequently, a portion of the low resistance metal layer 54, a portion of the work function metal layer 52 and a portion of the high dielectric constant dielectric layer 50 may be removed to form grooves (not shown), and then a hard mask 56 is filled in each groove and a planarization process is performed to make the top surface of the hard mask 56 flush with the top surface of the interlayer dielectric layer 42. In the present embodiment, the hard mask 56 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride.
[0047] Afterwards, a pattern transfer process may be performed, for example, a pattern mask may be used to remove a portion of the interlayer dielectric layer 42, a portion of the contact hole etching stop layer 40, a portion of the third spacer 36, and a portion of the gate dielectric layer 16 next to the gate structure 14 to form a plurality of contact holes (not shown) and expose the source / drain region 38. Then, the required metal material is filled in each contact hole, for example, a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof. Afterwards, a planarization process is performed, for example, chemical mechanical polishing is used to remove a portion of the metal material to form contact plugs 58 in each contact hole to electrically connect the source / drain region 42. At this point, the fabrication of the semiconductor device of the preferred embodiment of the present invention is completed.
[0048] Please refer to Figure 7 , Figure 7 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. Figure 7 As shown, the semiconductor device mainly includes a gate structure 14 disposed on a substrate 12, a first spacer 28 disposed next to the gate structure 14, a second spacer 30 disposed next to the first spacer 28, a third spacer 36 disposed next to the second spacer 30, and a source / drain region 38 disposed in the substrate 12 on both sides of the gate structure 14.
[0049] In addition, in the present embodiment, the gate structure 14 further comprises a gate electrode 26 disposed on the substrate 12 and a gate dielectric layer 16 disposed between the substrate 12 and the gate electrode 26, wherein the gate dielectric layer 16 on one side of the gate electrode 26 is asymmetric with the gate dielectric layer 16 on the other side of the gate electrode 26, and the spacer on one side of the gate electrode 26 is also asymmetric with the spacer on the other side of the gate electrode 26, for example, the second spacer 30 on the left side of the gate electrode 26 is I-shaped and the second spacer 30 on the right side of the gate electrode 26 is L-shaped.
[0050] From a detailed view, the width of the second spacer 30 on the left side of the gate electrode 26 is preferably smaller than the width of the second spacer 30 on the right side of the gate electrode 26, the width of the first spacer 28 on the left side of the gate electrode 26 is preferably smaller than the width of the first spacer 28 on the right side of the gate electrode 26, and the width of the gate dielectric layer 16 on the left side of the gate electrode 26 that is aligned with the second spacer 30 is preferably smaller than the width of the gate dielectric layer 16 on the right side of the gate electrode 26 that is aligned with the second spacer 30. According to an embodiment of the present invention, the width of the first spacer 28 on the right side of the gate electrode 26 is preferably more than twice the width of the first spacer 28 on the left side of the gate electrode 26, including three times, four times, five times, six times, or even seven times or more, and the width of the second spacer 30 on the right side of the gate electrode 26 is preferably more than twice the width of the second spacer 30 on the left side of the gate electrode 26, including three times, four times, five times, six times, or even seven times or more.
[0051] In addition, the distance S1 extending from the left side of the gate electrode 26 from the source / drain region 38 or the edge of the source region to the edge of the gate electrode 26 is also preferably shorter than the distance D1 extending from the right side of the gate electrode 26 from the edge of the source / drain region 38 or the edge of the drain region to the edge of the gate electrode 26. According to an embodiment of the present invention, the distance D1 extending from the right side of the gate electrode 26 from the edge of the source / drain region 38 or the edge of the drain region to the edge of the gate electrode 26 is preferably more than twice, including three times, four times, five times, six times, or even seven times or more, the distance S1 extending from the left side of the gate electrode 26 from the edge of the source / drain region 38 or the edge of the source region to the edge of the gate electrode 26.
[0052] Please refer to Figure 8 , Figure 8 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is disclosed. Figure 8 As shown, compared to Figure 7The gate dielectric layer 16 in the embodiment extends from directly below the gate electrode 26 to the surface of the substrate 12 on both sides of the gate electrode 26. Figure 4 When removing a portion of the sacrificial layer 32, a portion of the second spacer 30, a portion of the first spacer 28, and a portion of the gate dielectric layer 16 by asymmetric etching, the gate dielectric layer 16 on both sides of the first spacer 28 is completely removed and the surface of the substrate 12 is exposed. Figures 5 to 7 The manufacturing process completes the manufacturing of the metal gate 44 and the contact plug 58. In this case, the leftmost edge of the gate dielectric layer 16 of the gate electrode 26 will be aligned with the first spacer 28 and the second spacer 30 above, and the rightmost edge of the gate dielectric layer 16 of the gate electrode 26 will also be aligned with the first spacer 28 and the second spacer 30 above. This variation is also within the scope of the present invention.
[0053] Generally speaking, the medium voltage components widely used today have problems such as gate-induced-drain-leakage (GIDL) due to the gate structure being too close to the doped regions on both sides, such as the lightly doped drain or source / drain regions. In order to improve this phenomenon, the present invention mainly forms a spacer next to the gate structure, then forms a patterned mask directly above the gate structure and most of the area on the other side of the gate structure, and then performs an etching process to remove most of the spacer and part of the gate dielectric layer on the other side of the gate structure, so that the spacers and gate dielectric layers on both sides of the gate structure form an asymmetric structure with different widths and / or shapes. According to the preferred embodiment of the present invention, the medium voltage component prepared in this way can effectively reduce the probability of GIDL and improve the performance of the component.
[0054] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: Include: forming a gate structure on the substrate; forming a first spacer on the gate structure; forming a patterned mask on the gate structure and one side of the gate structure; removing a portion of the first spacer on the other side of the gate structure; as well as Source / drain regions are formed on both sides of the gate structure.
2. The method of claim 1, further comprising: forming a gate dielectric layer on the substrate; forming a gate material layer on the gate dielectric layer; patterning the gate material layer to form the gate structure; forming the first spacer on the gate structure; forming a second spacer on the first spacer; forming a sacrificial layer on the second spacer; removing the sacrificial layer, the second spacer and the first spacer on the other side of the gate structure; forming a third spacer on the second spacer; as well as The source / drain regions are formed. 3 . The method of claim 2 , further comprising completely removing the sacrificial layer before forming the third spacer. 4 . The method of claim 2 , further comprising simultaneously removing the sacrificial layer, the second spacer, the first spacer, and the gate dielectric layer. 5 . The method of claim 2 , wherein the gate dielectric layer on one side of the gate structure and the gate dielectric layer on another side of the gate structure are asymmetric. 6 . The method of claim 2 , wherein a width of the gate dielectric layer on one side of the gate structure is different from a width of the gate dielectric layer on another side of the gate structure. 7 . The method of claim 2 , wherein a width of the second spacer on one side of the gate structure is different from a width of the second spacer on another side of the gate structure.
8. The method of claim 1, further comprising: forming an interlayer dielectric layer surrounding the gate structure; and A metal gate replacement process is performed to convert the gate structure into a metal gate.
9. A semiconductor element, characterized in that: Include: A gate structure is disposed on a substrate, wherein the gate structure comprises: a gate electrode disposed on the substrate; and A gate dielectric layer is disposed between the substrate and the gate electrode, wherein the gate dielectric layer on one side of the gate electrode and the gate dielectric layer on the other side of the gate electrode are asymmetric; A first spacer is disposed beside the gate structure; and The second spacer is arranged beside the first spacer. 10 . The semiconductor device as claimed in claim 9 , wherein a width of the gate dielectric layer on one side of the gate structure is different from a width of the gate dielectric layer on another side of the gate structure. 11 . The semiconductor device as claimed in claim 9 , wherein the first spacer on one side of the gate structure and the first spacer on the other side of the gate structure are asymmetric. 12 . The semiconductor device as claimed in claim 9 , wherein a width of the first spacer on one side of the gate structure is different from a width of the first spacer on another side of the gate structure. 13 . The semiconductor device as claimed in claim 9 , wherein the second spacer on one side of the gate structure and the second spacer on the other side of the gate structure are asymmetric. 14 . The semiconductor device as claimed in claim 9 , wherein a width of the second spacer on one side of the gate structure is different from a width of the second spacer on another side of the gate structure.
15. The semiconductor device as claimed in claim 9, wherein the gate electrode comprises a metal gate.
16. The semiconductor device as claimed in claim 9, wherein the gate electrode comprises: A high-k dielectric layer is disposed on the gate dielectric layer; a work function metal layer disposed on the high dielectric constant dielectric layer; and The low-resistance metal layer is disposed on the work function metal layer.