Semiconductor device, method for manufacturing semiconductor device, and power conversion device

Abstract

The invention provides a semiconductor device capable of preventing insulation breakdown of an insulating film facing a gate electrode near a boundary between an active region and an inactive region. The second trench (TR2) is provided in the non-active region (RI), is in contact with the active region (RA), and has a second side wall (SW2) and a second bottom (BT2), the second side wall (SW2) having a length portion (SW2a) and a width portion (SW2b). A second bottom diffusion layer (17) of the second conductivity type is provided on at least a portion of the second bottom portion (BT2). A second side wall diffusion layer (16b) of the second conductivity type is provided in at least one of the length portion (SW2a) and the width portion (SW2b). The gate electrode (18) includes gate embedded portions (18b) respectively embedded in the plurality of first trenches (TR1), and gate wiring portions (18w) extending from the gate embedded portions (18b) into the second trenches (TR2). A second bottom portion diffusion layer (17) is disposed in at least a portion of the second bottom portion (BT2) where the gate wiring portion (18w) is disposed in plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Power semiconductor devices (more simply referred to as power devices) are used in switching elements for controlling the supply of power to loads such as motors. Power devices are required to be small, lightweight, and have low losses. Low losses are one of the biggest requirements, and are also related to the impact of reduced energy consumption on the global environment. In addition, the above requirements must be achieved at the lowest possible cost.

[0003] As the above-mentioned semiconductor device, a semiconductor device with an insulating gate such as IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is widely used. In particular, a method of reducing losses by increasing the channel density by setting the insulating gate as a vertical trench gate is widely used. In addition, in recent years, the application of wide-bandgap semiconductors such as silicon carbide (SiC) has been proposed to improve the performance of semiconductor devices. Trench-type MOSFETs that can use SiC as a semiconductor material are disclosed, for example, in Patent Documents 1 to 3.

[0004] Patent Document 1: International Publication No. 2017 / 138215

[0005] Patent Document 2: Japanese Patent Application Publication No. 2015-126086

[0006] Patent Document 3: Japanese Patent Application Publication No. 2010-147222

[0007] When the trench gate type switching element is switched, the destruction of the gate insulating film formed by the oxide film or the like, or the insulating film such as the field insulating film directly under the gate pad, becomes a problem. In particular, when SiC is used as the semiconductor material, high withstand voltage and high-speed operation can be expected compared to Si, but these can easily lead to difficulties in ensuring the reliability of the insulating film. Specifically, in the switching element required to have a high withstand voltage, the electric field strength applied to the insulating film also becomes higher. In addition, in high-speed operation, dV / dt also becomes higher, so a voltage increase caused by displacement current also occurs.

[0008] In particular, the gate electrode of the trench gate type switching element has: a portion buried in the trench formed in the active region, and a portion extending from the portion to the inactive region (in other words, the region outside the active region). If the gate electrode faces the drift layer via the gate insulating film at the bottom or side wall of the trench near the boundary of the above portion, the gate electrode is easily affected by the potential of the drift layer. As a result, the above-mentioned insulating film is easily destroyed. In order to prevent this situation, although it is considered to form an impurity diffusion layer of a conductivity type opposite to that of the drift layer at the bottom and side wall of the trench, there has been no sufficient research so far on such a trench structure with a diffusion layer that is fully considered. Summary of the invention

[0009] The present disclosure has been made to solve the above-mentioned problems, and one object thereof is to provide a semiconductor device capable of preventing dielectric breakdown of an insulating film facing a gate electrode near a boundary between an active region and an inactive region.

[0010] A semiconductor device according to one embodiment of the present disclosure has an active region and an inactive region when viewed from above, wherein the inactive region includes a withstand voltage holding region and a gate wiring region in contact with the active region. The semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first electrode disposed on the first main surface of the semiconductor substrate; a second electrode disposed on the second main surface of the semiconductor substrate; an insulating film disposed on the first main surface of the semiconductor substrate; and a gate electrode disposed on the first main surface via the insulating film.

[0011] The semiconductor substrate includes: a drift layer of a first conductivity type, which is arranged in the active region and the inactive region; a base region of a second conductivity type different from the first conductivity type, which is arranged in the active region and disposed between the drift layer and the first main surface; a first semiconductor region of the first conductivity type, which is arranged in the active region, disposed on the base region and in contact with the first electrode; a plurality of first trenches, which are arranged in the first main surface within the active region and have: a first bottom and a first side wall in contact with the first semiconductor region and the base region, each of the plurality of first trenches extending along a length direction and arranged in a width direction intersecting the length direction; a first bottom diffusion layer of the second conductivity type, which is arranged at the first bottom of each of the plurality of first trenches; a first sidewall diffusion layer of the second conductivity type, which is arranged at the first bottom of each of the plurality of first trenches; The first side wall of each trench is provided, and is in contact with the first bottom diffusion layer and the base region; a second semiconductor region of the first conductivity type or the second conductivity type is provided at least in the active region, is arranged between the drift layer and the second main surface, and is in contact with the second electrode; a second trench is provided on the first main surface in the inactive region, is in contact with the active region, has a second side wall and a second bottom, and the second side wall has: a length portion along the length direction, and a width portion along the width direction; a second bottom diffusion layer of the second conductivity type is provided in at least a portion of the second bottom of the second trench; and a second sidewall diffusion layer of the second conductivity type is provided in at least one of the length portion and the width portion of the second sidewall of the second trench, and is in contact with the second bottom diffusion layer and the base region. The gate electrode includes: a gate buried portion, which is buried in the multiple first grooves of the semiconductor substrate respectively via the insulating film; and a gate wiring portion, which extends from the gate buried portion into the second groove, and the second bottom diffusion layer is arranged in the second bottom of the second groove, at least in the portion where the gate wiring portion is arranged when viewed from above.

[0012] According to one embodiment of the present disclosure, the second sidewall diffusion layer provided on the second sidewall of the second trench is in contact with the second bottom diffusion layer provided on at least a portion of the second bottom of the second trench and the base region having the potential of the first electrode. Thus, the second sidewall in contact with the active region and the second bottom extending from the second sidewall to the inactive region are electrically connected to the potential of the first electrode, thereby avoiding excessive potential rise. Therefore, insulation breakdown of the insulating film facing the gate electrode near the boundary between the active region and the inactive region can be prevented.

[0013] The objects, features, methods and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a plan view schematically showing the layout of the semiconductor device according to the first embodiment when viewed from above.

[0015] Figure 2 The structure of the semiconductor device according to the first embodiment is schematically shown. Figure 1 A partial top view of the field of view of the dashed area II.

[0016] Figure 3 The structure of the semiconductor device according to the first embodiment is schematically shown. Figure 2 A partial cross-sectional view along line III-III.

[0017] Figure 4 The structure of the semiconductor device according to the first embodiment is schematically shown. Figure 2 A partial cross-sectional view along line IV-IV.

[0018] Figure 5 The structure of the semiconductor device according to the first embodiment is schematically shown. Figure 2 A partial cross-sectional view along line VV.

[0019] Figure 6 The structure of the semiconductor device according to the first embodiment is schematically shown. Figure 2 A partial cross-sectional view along line VI-VI.

[0020] Figure 7 The first step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 3 Corresponding partial cross-sectional view in the field of view.

[0021] Figure 8 The first step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 5 Corresponding partial cross-sectional view in the field of view.

[0022] Fig. 9 The second step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 3 Corresponding partial cross-sectional view in the field of view.

[0023] Fig.10 The second step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 5 Corresponding partial cross-sectional view in the field of view.

[0024] Fig.11 The third step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 3 Corresponding partial cross-sectional view in the field of view.

[0025] Fig.12 The third step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 5 Corresponding partial cross-sectional view in the field of view.

[0026] Fig.13 The fourth step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 3 Corresponding partial cross-sectional view in the field of view.

[0027] Fig.14 The fourth step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 5 Corresponding partial cross-sectional view in the field of view.

[0028] Fig.15 The fifth step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 3 Corresponding partial cross-sectional view in the field of view.

[0029] Fig.16 The fifth step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 5 Corresponding partial cross-sectional view in the field of view.

[0030] Fig.17 The sixth step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 3 Corresponding partial cross-sectional view in the field of view.

[0031] Fig.18 The sixth step of the method for manufacturing a semiconductor device according to the first embodiment is schematically shown. Figure 5 Corresponding partial cross-sectional view in the field of view.

[0032] Fig.19 This is a plan view schematically showing the layout of the semiconductor device according to the second embodiment when viewed from above.

[0033] Fig. 20 FIG. 2 schematically shows the structure of a semiconductor device according to Embodiment 2. Fig.19 A partial top view of the field of view of the dotted area XX.

[0034] Fig.21 The structure of the semiconductor device according to the second embodiment is schematically shown along the Fig. 20 A partial cross-sectional view along line XXI-XXI.

[0035] Fig. 22 The structure of the semiconductor device according to the second embodiment is schematically shown along the Fig. 20 A partial cross-sectional view along line XXII-XXII.

[0036] Fig.23 The structure of the semiconductor device according to the second embodiment is schematically shown along the Fig. 20 A partial cross-sectional view along line XXIII-XXIII.

[0037] Fig.24 The structure of the semiconductor device according to the second embodiment is schematically shown along the Fig. 20 A partial cross-sectional view along line XXIV-XXIV.

[0038] Fig.25 This is a plan view schematically showing the layout of the semiconductor device according to the third embodiment when viewed from above.

[0039] Fig.26 FIG. 2 schematically shows the structure of a semiconductor device according to Embodiment 3. Fig.25 Partial top view of the field of view of the dashed area XXVI.

[0040] Fig. 27 The structure of the semiconductor device according to the third embodiment is schematically shown. Fig.26 A partial cross-sectional view along line XXVII-XXVII.

[0041] Fig.28 The structure of the semiconductor device according to the third embodiment is schematically shown. Fig.26 A partial cross-sectional view along line XXVIII-XXVIII.

[0042] Fig.29 The structure of the semiconductor device according to the third embodiment is schematically shown. Fig.26 A partial cross-sectional view along line XXIX-XXIX.

[0043] Fig.30 The structure of the semiconductor device according to the third embodiment is schematically shown. Fig.26 A partial cross-sectional view of line XXX-XXX.

[0044] Fig.31 This is a plan view schematically showing the layout of the semiconductor device according to the fourth embodiment when viewed from above.

[0045] Fig.32 The structure of the semiconductor device according to the fourth embodiment is schematically shown. Fig.31 Partial top view of the field of view of the dashed area XXXII.

[0046] Fig.33 The structure of the semiconductor device according to the fourth embodiment is schematically shown along the Fig.32 A partial cross-sectional view along line XXXIII-XXXIII.

[0047] Fig.34 The structure of the semiconductor device according to the fourth embodiment is schematically shown along the Fig.32 A partial cross-sectional view along line XXXIV-XXXIV.

[0048] Fig.35 The structure of the semiconductor device according to the fourth embodiment is schematically shown along the Fig.32 A partial cross-sectional view along line XXXV-XXXV.

[0049] Fig.36 The structure of the semiconductor device according to the fourth embodiment is schematically shown along the Fig.32 A partial cross-sectional view along line XXXVI-XXXVI.

[0050] Fig.37 This is a block diagram schematically showing the configuration of a power conversion system including a power conversion device according to the fifth embodiment.

[0051] Explanation of the reference numerals: 7…gate insulating film; 11…source electrode (first electrode); 12…drain electrode (second electrode); 14…first bottom diffusion layer; 16a…first sidewall diffusion layer; 16b…second sidewall diffusion layer; 17…second bottom diffusion layer; 18…gate electrode; 18b…gate buried portion; 18w…gate wiring portion; 20…field insulating film; 501~504…semiconductor device; 1201…power conversion device; RA…active region; RIg…gate wiring region; RI…inactive region; RIv…voltage-withstand holding region; SF1…upper surface (first main surface); SF2…lower surface (second main surface); SB…semiconductor substrate; SW1…first sidewall; SW2…second sidewall; SW2a…length portion; SW2b…width portion; TR1…first trench; TR2…second trench. DETAILED DESCRIPTION

[0052] Hereinafter, the embodiment will be described based on the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and their description will not be repeated.

[0053] <Implementation method 1>

[0054] Figure 1 This is a plan view schematically showing the layout of the semiconductor device 501 according to the first embodiment when viewed from above. Figure 2 The structure of the semiconductor device 501 is schematically shown. Figure 1 A partial top view of the field of view of the dashed area II. Figure 3 The structure of the semiconductor device 501 is schematically shown along Figure 2 A partial cross-sectional view along line III-III. Figure 4 The structure of the semiconductor device 501 is schematically shown along Figure 2 A partial cross-sectional view along line IV-IV. Figure 5 The structure of the semiconductor device 501 is schematically shown along Figure 2 A partial cross-sectional view along line VV. Figure 6 The structure of the semiconductor device 501 is schematically shown along Figure 2 A partial cross-sectional view of line VI-VI. In addition, Figure 1 The dotted pattern in φ represents an example of the pattern of all the surface electrodes on the upper surface SF1 of the semiconductor substrate SB. Figure 2 The dotted pattern in represents the pattern of the gate embedded portion 18b and the internal wiring 18ew which are part of the gate electrode 18 (typically, the pattern of the polysilicon layer). Figure 2 In order to facilitate observation of the internal structure of the semiconductor device 501, only the edges of the gate surface electrode 18pw of the gate electrode 18 and the source electrode 11 are represented by double-dotted lines. In addition, the interlayer insulating film 9 is omitted from illustration and the contact portion CTs and the contact portion CTg penetrating therethrough are represented by rectangles marked with Xs.

[0055] The semiconductor device 501 has a semiconductor substrate SB. When the semiconductor substrate SB is viewed from above, the semiconductor device 501 has an active area RA and an inactive area RI. On the semiconductor substrate SB, the active area RA is a portion where actual elements are made, and the inactive area RI is a portion where actual elements are not made. The active area RA can be formed by arranging a plurality of unit structures having substantially the same structure approximately periodically. The inactive area RI has: a withstand voltage maintaining area RIv, and a gate wiring area RIg in contact with the active area RA. The gate wiring area RIg can have a pad area RIgp and an internal wiring area RIgw. The inactive area RI can also have a source wiring area RIs. The withstand voltage maintaining area RIv is a region for ensuring the withstand voltage of the semiconductor device 501, and therefore preferably surrounds the active area RA. In the withstand voltage maintaining area RIv, it is preferred that a region for ensuring the withstand voltage is formed on the upper surface SF1 by adding impurities, for example, forming a reference to the later-described embodiment 2. Fig.23 and Fig.24 The FLR27 (Field Limiting Ring: Field Limiting RIng) shown in FIG. － The conductivity type of the drift layer 3 is different from that of the gate wiring region RIg. The gate wiring region RIg is a region for arranging a gate wiring portion 18w described later. The source wiring region RIs is a region for arranging a source wiring portion 29 (see the following description) which is a part of the source electrode 11. Fig.23 and Fig.24 ) area.

[0056] The semiconductor substrate SB has an upper surface SF1 (first main surface) and a lower surface SF2 (a second main surface opposite to the first main surface). The upper surface SF1 of the semiconductor substrate SB has: a substantially flat portion, and a portion that is lower than the flat portion, namely, a plurality of grooves, specifically, a plurality of first grooves TR1 and at least one second groove TR2. The material of the semiconductor substrate SB is not particularly limited, and may be Si or SiC, for example. In addition to the semiconductor substrate SB, the semiconductor device 501 also has a source electrode 11 (first electrode), a drain electrode 12 (second electrode), a gate electrode 18, a gate insulating film 7, a field insulating film 20, and an interlayer insulating film 9. The semiconductor device 501 of the present embodiment 1 is a vertical MOSFET that switches the main current flowing between the source electrode 11 on the upper surface SF1 and the drain electrode 12 on the lower surface SF2, and has a trench gate structure controlled by the potential of the gate electrode 18. The trench gate structure is composed of n + Source layer 5, p-channel doped layer 4, n － The drift layer 3 , the gate insulating film 7 , and the gate buried portion 18 b of the gate electrode 18 are constituted.

[0057] The source electrode 11 is provided on the upper surface SF1 of the semiconductor substrate SB. The source electrode 11 may include a silicide layer 11b in contact with the semiconductor substrate SB and a non-silicide layer 11a stacked thereon. The drain electrode 12 is provided on the lower surface SF2 of the semiconductor substrate SB. The drain electrode 12 may include a silicide layer 12b (barrier metal layer) in contact with the semiconductor substrate SB and a surface metal layer 12a stacked thereon. The non-silicide layer 11a and the surface metal layer 12a may be made of an electrode material containing aluminum, for example.

[0058] The gate insulating film 7, the field insulating film 20 and the interlayer insulating film 9 are provided on the upper surface SF1 of the semiconductor substrate SB. The interlayer insulating film 9 has a thickness direction ( Figure 3 to Figure 6 The source electrode 11 and the gate electrode 18 are separated in the longitudinal direction (in the longitudinal direction). The gate electrode 18 is provided on the upper surface SF1 via any one of the gate insulating film 7 and the field insulating film 20. The thickness of the field insulating film 20 may be greater than that of the gate insulating film 7.

[0059] The semiconductor substrate SB has an n-type (first conductivity type) n － drift layer 3, p-type (second conductivity type different from the first conductivity type) p-channel doped layer 4 (base region), first conductivity type n + Source layer 5 (first semiconductor region), p-type p + The contact layer 6 (contact region), the p-type first bottom diffusion layer 14, the p-type first side wall diffusion layer 16a, the n-type n +The semiconductor substrate SB may also be formed on the n-type substrate 1 (second semiconductor region), a p-type second bottom diffusion layer 17, and a p-type second sidewall diffusion layer 16b. + Substrate 1 and n － There is n-type n between the drift layers 3 + Buffer layer 2 In addition, the semiconductor substrate SB may further include an n-type sidewall diffusion layer 15 .

[0060] n － The drift layer 3 is provided in the active region RA and the inactive region RI. + The substrate 1 is provided at least in the active region RA and is arranged at n － Between the drift layer 3 and the lower surface SF2. + The substrate 1 is in contact with the drain electrode 12 .

[0061] The p-channel doped layer 4 is provided in the active region RA and is arranged between the n － Between the drift layer 3 and the upper surface SF1.

[0062] n + The source layer 5 is provided in the active region RA and is disposed on the p-channel doped layer 4. + The source layer 5 is in contact with the source electrode 11 .

[0063] The plurality of first trenches TR1 are provided on the upper surface SF1 in the active region RA. The plurality of first trenches TR1 have: + The source layer 5 and the p-channel doping layer 4 contact the first side wall SW1 and the first bottom BT1. The plurality of first trenches TR1 are respectively formed along the length direction ( Figure 2 The plurality of first trenches TR1 are arranged in a width direction intersecting the length direction. The width direction may be orthogonal to the length direction.

[0064] The first bottom diffusion layer 14 is provided at the first bottom BT1 of each of the plurality of first trenches TR1. The first sidewall diffusion layer 16a is provided at a portion of the first sidewall SW1 of each of the plurality of first trenches TR1. The first sidewall diffusion layer 16a is in contact with the first bottom diffusion layer 14 and the p-channel doped layer 4. A first sidewall diffusion layer 16a may be provided at a portion of the first sidewall SW1 where the p-type first sidewall diffusion layer 16a is not provided. － The drift layer 3 is in contact with an n-type sidewall diffusion layer 15 .

[0065] The second trench TR2 is provided on the upper surface SF1 in the inactive region RI and contacts the active region RA. The second trench TR2 has a second side wall SW2 and a second bottom BT2. The second side wall SW2 has a length portion SW2a along the length direction and a width portion SW2b along the width direction. Figure 2In the partial top view of the semiconductor device 501, the second trench TR2 extends in an L shape. When the semiconductor device 501 is viewed from above, the second trench TR2 can surround the active area RA. The plurality of first trenches TR1 can be directly connected to the second trench TR2. Figure 2 In the embodiment, the left end of each first trench TR1 is directly connected to the second trench TR2. The width of the second trench TR2 may be greater than the width of the first trench TR1 ( Figure 3 or Figure 4 (width) in the horizontal dimension.

[0066] The second bottom diffusion layer 17 is provided at least in a portion of the second bottom BT2 of the second trench TR2 .

[0067] The second side wall diffusion layer 16b is provided on at least one of the length portion SW2a and the width portion SW2b of the second side wall SW2 of the second trench TR2. Figure 2 to Figure 6 As shown, the second side wall diffusion layer 16b may be provided on both the length portion SW2a and the width portion SW2b of the second side wall SW2 of the second trench TR2. The second side wall diffusion layer 16b may also be provided on the entire length portion SW2a of the second side wall SW2 of the second trench TR2. The second side wall diffusion layer 16b may also be provided on the entire width portion SW2b of the second side wall SW2 of the second trench TR2. The second side wall diffusion layer 16b is in contact with the second bottom diffusion layer 17 and the p-channel doping layer 4.

[0068] In a top view, the second sidewall diffusion layer 16b may surround the active region RA. Figure 2 As shown, the second side wall SW2 of the second trench TR2 and the end surface ( Figure 2 In the case where the second side wall diffusion layer 16b is connected to the left end of the first trench TR1 in the plan view, if the second side wall diffusion layer 16b surrounds the active region RA via the end surface in a plan view, the second side wall diffusion layer 16b is regarded as surrounding the active region RA in a plan view.

[0069] The source electrode 11 has at least one contact portion CTs in contact with the upper surface SF1 of the semiconductor substrate SB outside the second trench TR2. Figure 2 In the figure, in the upper right part of the field of view (outside the second trench TR2 extending in an L shape on the left and lower sides of the field of view), a plurality of contact portions CTs (rectangles with X marks) extending in the length direction are arranged in the width direction (vertical direction in the figure). The source electrode 11 may have a contact portion CTs between the trench closest to the second trench TR2 in the width direction among the plurality of first trenches TR1 and the second trench TR2. The contact portion CTs corresponds to the contact portion CTs between the second trench TR2 and the first trench TR1. Figure 2 The contact part CTs is arranged at the bottom in the field of view.

[0070] p + The contact layer 6 is in contact with the contact portion CTs of the source electrode 11, specifically, in contact with the silicide layer 11b of the source electrode 11. + The contact layer 6 is in contact with the p-channel doped layer 4. + The contact layer 6 may also be in contact with the second side wall diffusion layer 16b. In this case, the contact portion CTs and the second side wall diffusion layer 16b are connected by p + The contact layers 6 are electrically connected to each other.

[0071] The gate electrode 18 includes a gate embedded portion 18b and a gate wiring portion 18w. The gate embedded portion 18b is embedded in each of the plurality of first trenches TR1 of the semiconductor substrate SB via the gate insulating film 7. The gate embedded portion 18b is made of, for example, polysilicon. The gate wiring portion 18w extends from the gate embedded portion 18b into the second trench TR2. A second bottom diffusion layer 17 is disposed in a portion of the second bottom BT2 of the second trench TR2 where the gate wiring portion 18w is disposed when viewed from above.

[0072] The gate wiring portion 18w may include an internal wiring 18ew and a gate surface electrode 18pw. The internal wiring 18ew is directly connected to the gate embedded portion 18b. The internal wiring 18ew and the gate embedded portion 18b may be made of the same material, for example, polysilicon. Figure 1 The gate surface electrode 18pw in the semiconductor device 501 can be used as a component connected to a wiring (e.g., a bonding wire) for applying a gate potential to the semiconductor device 501. The gate surface electrode 18pw has a contact portion CTg that contacts the internal wiring 18ew. The second bottom diffusion layer 17 or p may be disposed on the portion of the upper surface SF1 of the semiconductor substrate SB that overlaps with the gate surface electrode 18pw when viewed from above. + The contact layer 6 is a p-type diffusion layer. In the portion overlapping with the gate surface electrode 18pw in a plan view, the internal wiring 18ew can be separated from the semiconductor substrate SB by being arranged on the field insulating film 20 .

[0073] Next, regarding the method for manufacturing the semiconductor device 501, the following particularly refers to Figure 7 to Figure 18 , the process of forming the first trench TR1 having the inner surface formed with the first bottom diffusion layer 14 and the first sidewall diffusion layer 16a and the second trench TR2 having the inner surface formed with the second bottom diffusion layer 17 and the second sidewall diffusion layer 16b will be described.

[0074] Figure 7 and Figure 8 Each of them schematically shows the first step of the method for manufacturing the semiconductor device 501. Figure 3 and Figure 5First, prepare a local cross-sectional view with n + The substrate 1 and the n layers stacked thereon + Buffer layer 2 and n － Semiconductor substrate SB of drift layer 3. Next, etching mask material 23 is formed on upper surface SF1 of semiconductor substrate SB using, for example, general photolithography technology. Etching mask material 23 may include, for example, a photoresist film or a plasma insulating film formed using the photoresist film.

[0075] Fig. 9 and Fig.10 Each of them schematically shows the second step of the method for manufacturing the semiconductor device 501. Figure 3 and Figure 5 Partial cross-sectional view in the corresponding field of view In this step, etching is performed using the etching mask material 23. Thus, the first trench TR1 and the second trench TR2 are formed.

[0076] Fig.11 and Fig.12 Each of them schematically shows the third step of the method for manufacturing the semiconductor device 501. Figure 3 and Figure 5 First, for example, using a general photolithography technique, an injection mask material 23A is formed on the upper surface SF1 of the semiconductor substrate SB. Alternatively, instead of re-forming all the injection mask materials 23A, an etching mask material 23 ( Fig. 9 and Fig.10 ) as a part or all of the injection mask material 23A. Next, by performing ion implantation using the injection mask material 23A, an impurity implantation region 26 is formed. In order to effectively perform the ion implantation with respect to the first bottom BT1 of the first trench TR1 and the second bottom BT2 of the second trench TR2, and to substantially have no effect on the first side wall SW1 of the first trench TR1 and the second side wall SW2 of the second trench TR2, the ion implantation is performed almost vertically with respect to the semiconductor substrate SB. In addition, as a modified example, the third step may also be performed after the fourth and fifth steps described later.

[0077] Next, ion implantation is performed on the first side wall SW1 of the first trench TR1 and the second side wall SW2 of the second trench TR2 from a direction inclined with respect to the semiconductor substrate SB to form a first side wall diffusion layer 16a ( Figure 3 ) and the second side wall diffusion layer 16b ( Figure 5 ) is an impurity implantation region. Figure 13 to Figure 16 This process will be described.

[0078] Fig.13 and Fig.14 Each of them schematically shows the fourth step of the method for manufacturing the semiconductor device 501. Figure 3 and Figure 5 Local cross-sectional view in the corresponding field of view. First, an injection mask material 23B is formed on the upper surface SF1 of the semiconductor substrate SB, for example, using a general photolithography technique. In addition, instead of reforming all of the injection mask material 23B, an etching mask material 23 or an injection mask material 23A may be used as part or all of the injection mask material 23B. Next, an impurity injection region 26 is formed by performing ion implantation using the injection mask material 23B. In this process, the direction of the ion implantation is set so that it is effectively performed with respect to the length portion SW2a of the first side wall SW1 of the first trench TR1 and the second side wall SW2 of the second trench TR2, and has substantially no effect on the width portion SW2b of the second side wall SW2 of the second trench TR2. Specifically, the direction of the ion implantation is set so that the ion beam is effectively incident with respect to the length portion SW2a of the first side wall SW1 of the first trench TR1 and the second side wall SW2 of the second trench TR2 (refer to Fig.13 ), and the ion beam is not substantially incident on the width portion SW2b of the second side wall SW2 of the second trench TR2 (refer to Fig.14 ). Therefore, in this process, ion implantation is performed on the length portion SW2a of the second side wall SW2 of the second trench TR2, and ion implantation is substantially not performed on the width portion SW2b of the second side wall SW2 of the second trench TR2. In addition, as a modified example, the ion implantation in the fourth process may also be performed after the ion implantation in the fifth process described later.

[0079] Fig.15 and Fig.16 Each of them schematically shows the fifth step of the method for manufacturing the semiconductor device 501. Figure 3 and Figure 5 A partial cross-sectional view in the corresponding field of view. By performing ion implantation using the implantation mask material 23B, the impurity implantation region 26 is formed. In this process, the direction of ion implantation is set so that the ion implantation is effectively performed with respect to the width portion SW2b of the second side wall SW2 of the second trench TR2, and has substantially no effect on the first side wall SW1 of the first trench TR1 and the length portion SW2a of the second side wall SW2 of the second trench TR2. Specifically, the direction of ion implantation is set so that the ion beam is effectively incident with respect to the width portion SW2b of the second side wall SW2 of the second trench TR2 (refer to Fig.16 ), and the ion beam is substantially not incident on the length portion SW2a of the first side wall SW1 of the first trench TR1 and the second side wall SW2 of the second trench TR2 (refer to Fig.15). Therefore, in this process, ions are implanted into the width portion SW2b of the second side wall SW2 of the second trench TR2, and ions are not substantially implanted into the length portion SW2a of the second side wall SW2 of the second trench TR2.

[0080] Fig.17 and Fig.18 Each of them schematically shows the sixth step of the method for manufacturing the semiconductor device 501. Figure 3 and Figure 5 The local cross-sectional view in the corresponding field of view. In this process, the impurity injection region 26 ( Fig.15 and Fig.16 ) is annealed. Thus, the first bottom diffusion layer 14, the first side wall diffusion layer 16a, the second bottom diffusion layer 17 and the second side wall diffusion layer 16b are formed by activating the injected impurities. As described above, the fourth step ( Fig.13 and Fig.14 ) and the fifth step ( Fig.15 and Fig.16 ). Therefore, in order to form the second side wall diffusion layer 16b on the second side wall SW2 of the second trench TR2, a plurality of ion implantation processes with different ion implantation directions are performed. In addition, in each of the above-mentioned ion implantation processes, aluminum ions are used as impurity ions, for example. In addition, the implantation energy of each ion implantation is set so that the diffusion expansion in the depth direction and the in-plane direction of the p-type impurity diffusion layer formed by the ion implantation is sufficient to prevent the electric field from concentrating on the gate insulating film 7 of the semiconductor device 501, and the influence on the main withstand voltage and on-resistance is also taken into consideration.

[0081] In addition, the p-channel doped layer 4 and n-channel doped layer 5 in the semiconductor substrate SB of the semiconductor device 501 are + The source layer 5 and p + The contact layer 6 can be formed using the above-mentioned photolithography technology, ion implantation technology and annealing technology. They can be formed in the fourth step ( Fig.13 and Fig.14 ) before. In addition, in the sixth step ( Fig.17 and Fig.18 ) before performing ion implantation for forming them, the sixth step can also serve as annealing for forming them. The subsequent steps can be implemented using general semiconductor manufacturing technology, so their description is omitted. In addition, the manufacturing method of semiconductor devices 502 to 504 of embodiments 2 to 4 described later can be performed by deforming the processing pattern in the manufacturing method of the semiconductor device 501 of the first embodiment described above, so its description is omitted.

[0082] Next, the operation of the semiconductor device 501 will be described below. As described above, the semiconductor device 501 has n + Source layer 5, p-channel doped layer 4, n － The MOSFET structure is composed of the drift layer 3, the gate insulating film 7, and the gate embedded portion 18b of the gate electrode 18. When a positive voltage higher than the threshold voltage of the MOSFET structure is applied to the gate electrode 18, the MOSFET structure is turned on. As a result, the drain voltage drops, and the main current flows between the source electrode 11 and the drain electrode 12. On the contrary, when a positive voltage lower than the threshold voltage of the MOSFET structure or a negative voltage is applied to the gate electrode 18, the MOSFET structure is turned off. As a result, the drain voltage rises, and the source electrode 11 and the drain electrode 12 are electrically disconnected.

[0083] Next, the following describes the problems that may occur in a general MOSFET. When the drain voltage rises due to the switching action described above, the － The voltage shared by the gate insulating film 7 in contact with the drift layer 3 also rises, so the electric field strength applied to the gate insulating film 7 becomes higher. Generally, the vicinity of the trench formed at the boundary between the withstand voltage holding region RIv and the active region RA receives the electric field in the thickness direction of the semiconductor substrate SB and the electric field in the in-plane direction, and is therefore greatly affected by this. In addition, when the potential of the p-type diffusion layer provided at the bottom of the trench rises as the drain voltage rises, the electric field applied to the gate insulating film at the bottom of the trench becomes stronger.

[0084] According to the structure of the semiconductor device 501 of the present embodiment, the second side wall diffusion layer 16b provided on the second side wall SW2 of the second trench TR2 is in contact with each of the second bottom diffusion layer 17 provided on at least a portion of the second bottom BT2 of the second trench TR2 and the p-channel doped layer 4 having a source potential (more generally, the potential of the source electrode 11). Thus, the second side wall SW2 in contact with the active region RA and the second bottom BT2 extending therefrom to the inactive region RI are electrically connected to the source potential (more generally, the potential of the source electrode 11), thereby being able to avoid excessive potential rise. Therefore, it is possible to prevent insulation breakdown of the insulating film (specifically, the gate insulating film 7 or the field insulating film 20) facing the gate electrode 18 near the boundary between the active region RA and the inactive region RI. In addition, by preventing the above-mentioned excessive potential rise, erroneous operation of the semiconductor device can be avoided.

[0085] The second side wall diffusion layer 16b may be provided in both the length portion SW2a and the width portion SW2b of the second side wall SW2 of the second trench TR2. Thus, both the length portion SW2a and the width portion SW2b of the second side wall SW2 can avoid excessive potential rise.

[0086] The second trench TR2 may surround the active region RA in a plan view, thereby providing a region that can avoid an excessive potential rise so as to surround the active region RA.

[0087] p-type + The contact layer 6 is in contact with the contact portion CTs and the second side wall diffusion layer 16b. Thus, the second side wall diffusion layer 16b can be connected to the source potential (more generally, the potential of the source electrode 11) by p + The short electrical path of the contact layer 6 is electrically connected. Therefore, an excessive potential rise of the second side wall diffusion layer 16b can be avoided more reliably.

[0088] The plurality of first trenches TR1 may be directly connected to the second trench TR2. Thus, any one or each of the first bottom diffusion layer 14 and the first sidewall diffusion layer 16a of the first trench TR1 may continuously form a second trench TR2 or a further trench (for example, the third trench TR3 (see Fig.32 , Fig.35 as well as Fig.36 (Embodiment 4 described later)) p-type diffusion layer.

[0089] The ratio of the area of ​​the second sidewall diffusion layer 16b to the total area of ​​the second sidewall SW2 of the second trench TR2 may be greater than the ratio of the area of ​​the first sidewall diffusion layer 16a to the total area of ​​the first sidewall SW1 of the first trench TR1. Thus, the effect of the second sidewall diffusion layer 16b can be more sufficient. This aspect will be described below.

[0090] Reference Figure 2 , length L1, length Lp1, length L2 and length Lp2 represent the following contents,

[0091] L1: Pitch of the repeated pattern in the active region RA when viewed from above

[0092] Lp1: pattern length of the first side wall diffusion layer 16 a in the repeated pattern of the active region RA in a plan view

[0093] L2: Pitch of the repeated pattern of the second trench TR2 in a plan view

[0094] Lp2: pattern length of the second side wall diffusion layer 16 b in the repeated pattern of the second trench TR2 in a plan view.

[0095] Here, it can be considered that a case similar to the case where the first trench TR1 has a substantially uniform depth and the second trench TR2 also has a substantially uniform depth is allowed. Therefore, when the ratio of the area of ​​the first side wall diffusion layer 16a to the total area of ​​the first side wall SW1 of the first trench TR1 is defined as R1, and the ratio of the area of ​​the second side wall diffusion layer 16b to the total area of ​​the length portion SW2a of the second side wall SW2 of the second trench TR2 is defined as R2, the following relationship can be obtained:

[0096] R1=Lp1 / L1

[0097] R2=Lp2 / L2.

[0098] When the ratio R1 and the ratio R2 satisfy the relationship R2>R1, the potential around the length portion SW2a of the second side wall SW2 is stably grounded to the source potential. Here, only the length portion SW2a of the second side wall SW2 is described in detail, but even if R2 is calculated with attention paid to the entire second side wall SW2, it can be said that it is almost the same.

[0099] As described above, since the ratio R1 proportional to the ratio of the first side wall diffusion layer 16a formed can be relatively small, the n side wall diffusion layer formed can be + The source layer 5 is relatively large in proportion to the first side wall diffusion layer 16a. + The source layer 5 is thus formed by + The source layer 5 has a relatively large proportion, and a sufficiently low on-resistance can be obtained. Therefore, according to this embodiment, the above-mentioned effects can prevent the insulation breakdown of the semiconductor device 501 and obtain a sufficiently low on-resistance.

[0100] According to the manufacturing method of the semiconductor device 501 of the present embodiment, a process of forming the first side wall diffusion layer 16a and the second side wall diffusion layer 16b by ion implantation from an oblique direction relative to the first side wall SW1 of the first trench TR1 and the second side wall SW2 of the second trench TR2 is performed. Thus, the desired impurity diffusion layer can be formed only by ion implantation from the inner surface of the first trench TR1 and the second trench TR2 to a relatively shallow area. Therefore, it is not necessary to perform ion implantation with high energy. Thus, first, it is not necessary to use a high-energy ion implanter. Second, it is not necessary to form a thick implantation mask that can withstand high-energy ion implantation. Third, it is possible to prevent the generation of crystal defects of the semiconductor caused by high energy.

[0101] The steps of implanting ions into the length portion SW2a of the second side wall SW2 of the second trench TR2 and the steps of implanting ions into the width portion SW2b of the second side wall SW2 of the second trench TR2 can be performed separately. Thus, the second side wall diffusion layer 16b can be stably formed in each of the length portion SW2a and the width portion SW2b.

[0102] The steps of forming the first trench TR1 and the second trench TR2 in the semiconductor substrate SB may be performed simultaneously, and ion implantation may be performed from an oblique direction with respect to the first side wall SW1 of the first trench TR1 and the second side wall SW2 of the second trench TR2, thereby simultaneously performing the steps of forming the first side wall diffusion layer 16a and the second side wall diffusion layer 16b. Thus, it is possible to suppress an increase in manufacturing cost for adding the second trench TR2 and the second side wall diffusion layer 16b to a typical semiconductor device having the first trench TR1 and the first side wall diffusion layer 16a.

[0103] In the above-mentioned first embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type is described. As a modified example, the first conductivity type may be p-type and the second conductivity type may be n-type. This modified example may also be applied to other embodiments.

[0104] In the semiconductor device 501 of the first embodiment described above, in order to form a MOSFET (more generally, a MISFET (Metal Insulator Semiconductor Field Effect Transistor)), the second semiconductor region (n in this embodiment) + The substrate 1) has a first conductivity type. As a modification of this, the second semiconductor region may also have a second conductivity type. In this case, an IGBT as a semiconductor device can be obtained. This modification can also be applied to other embodiments.

[0105] <Implementation method 2>

[0106] Fig.19 This is a plan view schematically showing the layout of the semiconductor device 502 according to the second embodiment when viewed from above. Fig. 20 The structure of the semiconductor device 502 is schematically shown. Fig.19 A partial top view of the field of view of the dotted area XX. Fig.21 The structure of the semiconductor device 502 is schematically shown along Fig. 20 A partial cross-sectional view along line XXI-XXI. Fig. 22 The structure of the semiconductor device 502 is schematically shown along Fig. 20 A partial cross-sectional view along line XXII-XXII. Fig.23The structure of the semiconductor device 502 is schematically shown along Fig. 20 A partial cross-sectional view along line XXIII-XXIII. Fig.24 The structure of the semiconductor device 502 is schematically shown along Fig. 20 A partial cross-sectional view of line XXIV-XXIV. In addition, Fig.19 The dotted pattern in φ represents an example of an electrode pattern on the upper surface SF1 of the semiconductor substrate SB. Fig. 20 The dotted pattern in represents the pattern of the gate embedded portion 18b and the internal wiring 18ew which are part of the gate electrode 18 (typically, the pattern of the polysilicon layer). Fig. 20 In order to facilitate observation of the internal structure of the semiconductor device 502, only the edges of the gate surface electrode 18pw of the gate electrode 18 and the source electrode 11 are indicated by double-dotted lines, and the interlayer insulating film 9 is omitted from illustration and the contact portion CTs, the contact portion CTg, and the contact portion CTsb penetrating the interlayer insulating film 9 are indicated by rectangles marked with Xs.

[0107] In the semiconductor device 502, the withstand voltage holding region RIv, the source wiring region RIs, and the internal wiring region RIgw ( Fig.19 ) are each arranged in the second trench TR2. In the withstand voltage holding region RIv, it is preferable to form a region for ensuring withstand voltage by adding impurities on the upper surface SF1. For example, Fig.23 and Fig.24 As shown, a p-type FLR 27 and an n-type channel stopper layer 28 are provided on the upper surface SF1. Figure 1 ) of the source wiring portion 29 ( Fig.23 and Fig.24 ) is a part of the source electrode 11 and extends from the portion of the source electrode 11 arranged in the active region RA. The source wiring portion 29 may include a silicide layer 29b in contact with the semiconductor substrate SB and a non-silicide layer 29a stacked thereon. The source wiring portion 29 of the source electrode 11 may also include a contact portion CTsb in contact with the second bottom diffusion layer 17.

[0108] In addition, since the structure other than the above is almost the same as the structure of the above-mentioned Embodiment 1, the description thereof will not be repeated.

[0109] According to the present embodiment, the withstand voltage maintaining region RIv, the source wiring region RIs, and the internal wiring region RIgw ( Fig.19) are each arranged in the second trench TR2. Thus, the second trench TR2 can be utilized to make it difficult for each of them to generate electric field concentration. Therefore, the semiconductor device 502 can prevent the insulation breakdown of the insulating film facing the gate electrode 18 and stably ensure the main withstand voltage (the withstand voltage between the source electrode 11 and the drain electrode 12).

[0110] <Implementation method 3>

[0111] Fig.25 This is a plan view schematically showing the layout of the semiconductor device 503 according to the third embodiment when viewed from above. Fig.26 The structure of the semiconductor device 503 is schematically shown. Fig.25 Partial top view of the field of view of the dashed area XXVI. Fig. 27 The structure of the semiconductor device 503 is schematically shown along Fig.26 A partial cross-sectional view along line XXVII-XXVII. Fig.28 The structure of the semiconductor device 503 is schematically shown along Fig.26 A partial cross-sectional view along line XXVIII-XXVIII. Fig.29 The structure of the semiconductor device 503 is schematically shown along Fig.26 A partial cross-sectional view along line XXIX-XXIX. Fig.30 The structure of the semiconductor device 503 is schematically shown along Fig.26 A partial cross-sectional view of line XXX-XXX. In addition, Fig.25 The dotted pattern in φ represents an example of an electrode pattern on the upper surface SF1 of the semiconductor substrate SB. Fig.26 The dotted pattern in represents the pattern of the gate embedded portion 18b and the internal wiring 18ew which are part of the gate electrode 18 (typically, the pattern of the polysilicon layer). Fig.26 In order to facilitate observation of the internal structure of the semiconductor device 503, only the edges of the gate surface electrode 18pw of the gate electrode 18 and the source electrode 11 are represented by double-dotted lines. In addition, the interlayer insulating film 9 is omitted from the illustration and the contact portion CTs and the contact portion CTg penetrating therethrough are represented by rectangles marked with Xs.

[0112] In the semiconductor device 503, the source electrode 11 has a contact portion CTsb that contacts the second bottom diffusion layer 17 of the semiconductor substrate SB. Fig.29 In the cross-sectional view, on the upper surface SF1 (in other words, in a plan view), a contact portion CTsb is arranged between the gate electrode 18 and the second side wall SW2 of the second trench TR2. Fig.23Unlike (Embodiment 2), on the upper surface SF1 (in other words, when viewed from above), the gate electrode 18 is not interposed between the contact portion CTsb and the second side wall SW2 of the second trench TR2. Therefore, in this embodiment, the contact portion CTsb can be arranged near the second side wall diffusion layer 16b. The following describes the preferred arrangement of the contact portion CTsb near the second side wall diffusion layer 16b.

[0113] On the upper surface SF1 of the semiconductor substrate SB, a plurality of first trenches TR1 are arranged at intervals in the width direction. Fig. 27 To explain, the one interval is the dimension between the right end of the opening of the left first trench TR1 on the upper surface SF1 and the left end of the opening of the center first trench TR1. In other words, the one interval is the width dimension of the mesa portion of the semiconductor substrate SB between the first trenches TR1 adjacent to each other on the upper surface SF1. When viewed from above, the interval between the contact portion CTsb and the second side wall SW2 provided with the second side wall diffusion layer 16b is preferably smaller than the one interval.

[0114] In addition, since the structure other than the above is almost the same as the structure of the above-mentioned Embodiment 1, the description thereof will not be repeated.

[0115] According to the present embodiment, the second bottom diffusion layer 17 can be directly connected to the source electrode 11 having the source potential (more generally, the potential of the source electrode 11) through the contact portion CTsb. Therefore, it is possible to more reliably avoid an excessive potential rise of the second bottom diffusion layer 17. Here, the interval between the contact portion CTsb of the source electrode 11 and the second side wall SW2 provided with the second side wall diffusion layer 16b can also be smaller than the above-mentioned one interval. Thus, the second side wall diffusion layer 16b can be electrically connected to the source electrode 11 having the source potential (more generally, the potential of the source electrode 11) through a short electrical path. Therefore, it is possible to more reliably avoid an excessive potential rise of the second side wall diffusion layer 16b.

[0116] <Implementation method 4>

[0117] Fig.31 FIG. 1 is a plan view schematically showing the layout of the semiconductor device 504 according to the fourth embodiment when viewed from above. Fig.32 The structure of the semiconductor device 504 is schematically shown. Fig.31 Partial top view of the field of view of the dashed area XXXII. Fig.33 The structure of the semiconductor device 504 is schematically shown along Fig.32 A partial cross-sectional view along line XXXIII-XXXIII. Fig.34 The structure of the semiconductor device 504 is schematically shown along Fig.32 A partial cross-sectional view along line XXXIV-XXXIV. Fig.35 The structure of the semiconductor device 504 is schematically shown along Fig.32 A partial cross-sectional view along line XXXV-XXXV. Fig.36 The structure of the semiconductor device 504 is schematically shown along Fig.32 A partial cross-sectional view of line XXXVI-XXXVI. In addition, Fig.31 The dotted pattern in φ represents an example of an electrode pattern on the upper surface SF1 of the semiconductor substrate SB. Fig.32 The dotted pattern in the figure represents the pattern of the gate buried portion 18b and the internal wiring 18ew as part of the gate electrode 18 (typically the pattern of the polysilicon layer). The structure of the source electrode 11 of the semiconductor device 504 is similar to that of the second embodiment. Fig. 20 The structures shown are almost identical, so Fig.32 The illustration is omitted. Fig.32 In the figure, only the edges of the gate surface electrode 18pw of the gate electrode 18 are indicated by double-dashed lines, and the interlayer insulating film 9 is omitted and the contact portions CTg and CTsb penetrating therethrough are indicated by rectangles marked with Xs.

[0118] As described in the third embodiment, on the upper surface SF1 of the semiconductor substrate SB, a plurality of first trenches TR1 are arranged with one interval in the width direction. The semiconductor substrate SB has a third trench TR3 on the upper surface SF1 in the inactive region RI. The third trench TR3 has a third bottom BT3. The third trench TR3 is separated from the second trench TR2 in such a manner that a mesa portion MS of the semiconductor substrate SB is formed between the third trench TR3 and the second trench TR2. The third trench TR3 is separated from the second trench TR2 by an amount equal to or greater than the above-mentioned one interval. The use of the mesa portion MS is not particularly limited, but in the present embodiment, it is used as a place for configuring the internal wiring 18ew of the gate electrode 18.

[0119] In the present embodiment, the withstand voltage holding region RIv is arranged at the third bottom portion BT3 of the third trench TR3. Specifically, the p-type FLR 27 and the n-type channel stopper layer 28 described in the second embodiment are formed at the third bottom portion BT3.

[0120] In addition, since the structure other than the above is almost the same as the structure of the above-mentioned embodiment 1 or 2, the description thereof will not be repeated.

[0121] According to the present embodiment, the third trench TR3 is separated from the second trench TR2 by an amount equal to or greater than the above-mentioned one interval of the first trench TR1. Thus, the mesa portion MS has at least a mechanical strength substantially equal to the mechanical strength of the mesa portion between the first trenches TR1. Therefore, the mesa portion MS can be prevented from being damaged by thermal stress or the like.

[0122] <Implementation method 5>

[0123] The fifth embodiment is a component in which any one of the semiconductor devices 501 to 504 of the first to fourth embodiments is applied to a power conversion device. This application is not limited to a specific power conversion device, and the following describes a case in which any one of the semiconductor devices 501 to 504 of the first to fourth embodiments is applied to a three-phase inverter as the fifth embodiment.

[0124] Fig.37 This is a block diagram showing the configuration of a power conversion system to which the power conversion device 1200 according to the fifth embodiment is applied.

[0125] Fig.37 The power conversion system shown is composed of a power supply 1100, a power conversion device 1200, and a load 1300. The power supply 1100 is a DC power supply, and supplies DC power to the power conversion device 1200. The power supply 1100 can be composed of various components, for example, it can be composed of a DC system, a solar cell, a storage battery, or a rectifier circuit connected to an AC system, and an AC / DC converter. In addition, the power supply 1100 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a specified power.

[0126] The power conversion device 1200 is a three-phase inverter connected between the power source 1100 and the load 1300, converts the DC power supplied from the power source 1100 into AC power, and supplies the AC power to the load 1300. Fig.37 As shown, the power conversion device 1200 includes: a main conversion circuit 1201, which converts the input DC power into AC power and outputs it; a drive circuit 1202, which outputs a drive signal for driving each switching element of the main conversion circuit 1201; and a control circuit 1203, which outputs a control signal of the drive circuit 1202 to the drive circuit 1202.

[0127] The load 1300 is not limited to a specific use, but in the fifth embodiment, it is a three-phase motor driven by the AC power supplied from the power conversion device 1200. The motor can be mounted on various electrical devices, for example, hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0128] The following describes the details of the power conversion device 1200. The main conversion circuit 1201 includes a switching element and a return diode (not shown). The DC power supplied from the power supply 1100 is converted into AC power by switching by the switching element, and the AC power is supplied to the load 1300. Although there are many specific circuit structures of the main conversion circuit 1201, the main conversion circuit 1201 of the fifth embodiment is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six return diodes connected in reverse parallel to each switching element. Any of the semiconductor devices 501 to 504 of the above-mentioned embodiments 1 to 4 is applied to each switching element of the main conversion circuit 1201. The six switching elements are used as three pairs of switching elements. The two switching elements of each pair are connected in series to form an upper and lower branch. Therefore, the three pairs of switching elements constitute the three upper and lower branches for the three phases (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower branch, that is, the three output terminals of the main conversion circuit 1201, are connected to the load 1300.

[0129] The drive circuit 1202 generates a drive signal for driving the switch element of the main conversion circuit 1201, and supplies it to the control electrode of the switch element of the main conversion circuit 1201. Specifically, according to the control signal from the control circuit 1203 described later, a drive signal for turning the switch element on and a drive signal for turning the switch element off are output to the control electrode of each switch element. When the switch element is maintained in the on state, the drive signal is a voltage signal (on signal) above the threshold voltage of the switch element, and when the switch element is maintained in the off state, the drive signal is a voltage signal (off signal) less than the threshold voltage of the switch element.

[0130] The control circuit 1203 controls the switch elements of the main conversion circuit 1201 so as to supply the desired power to the load 1300. Specifically, the control circuit 1203 calculates the time (on time) when each switch element of the main conversion circuit 1201 should be in the on state based on the power to be supplied to the load 1300. For example, the main conversion circuit 1201 can be controlled by PWM control that modulates the on time of the switch element according to the voltage to be output. Then, the control circuit 1203 outputs a control instruction (control signal) to the drive circuit 1202 in a manner that outputs an on signal to the switch element that should be in the on state and an off signal to the switch element that should be in the off state at each moment. The drive circuit 1202 outputs an on signal or an off signal as a drive signal to the control electrode of each switch element according to the control signal.

[0131] In the power conversion device of the fifth embodiment, any one of the semiconductor devices 501 to 504 of the first to fourth embodiments is applied as a switching element of the main conversion circuit 1201 , thereby improving reliability.

[0132] In this embodiment 5, any one of the semiconductor devices 501 to 504 of embodiments 1 to 4 is applied to a two-level three-phase inverter, but this application is not limited to a specific power conversion device and can also be applied to various power conversion devices. The power conversion device can also be a multi-level power conversion device with more than three levels, for example, instead of a two-level power conversion device. In addition, when power is supplied to a single-phase load, the power conversion device can be a single-phase inverter. In addition, when power is supplied to a DC load, etc., any one of the semiconductor devices 501 to 504 of embodiments 1 to 4 can also be applied to a DC / DC converter or an AC / DC converter.

[0133] In addition, the load to which the power conversion device supplies power is not limited to the motor, and may be, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system. In addition, the power conversion device may also be used as a power conditioner for a solar power generation system or a power storage system.

[0134] Furthermore, the various embodiments may be freely combined, or the various embodiments may be appropriately modified or omitted.

[0135] <Note>

[0136] Hereinafter, each aspect of the present disclosure will be collectively described as a supplementary note.

[0137] (Note 1)

[0138] A semiconductor device (501-504) comprises an active region (RA) and an inactive region (RI) when viewed from above, wherein the inactive region (RI) comprises: a withstand voltage holding region (RIv) and a gate wiring region (RIg) in contact with the active region (RA), wherein:

[0139] A semiconductor substrate (SB) having: a first main surface (SF1) and a second main surface (SF2) opposite to the first main surface (SF1);

[0140] a first electrode (11) provided on the first main surface (SF1) of the semiconductor substrate (SB);

[0141] a second electrode (12) provided on the second main surface (SF2) of the semiconductor substrate (SB);

[0142] an insulating film provided on the first main surface (SF1) of the semiconductor substrate (SB); and

[0143] a gate electrode (18) provided on the first main surface (SF1) via the insulating film,

[0144] The semiconductor substrate (SB) comprises:

[0145] A drift layer (3) of a first conductivity type, which is arranged in the active region (RA) and the inactive region (RI);

[0146] a base region (4) of a second conductivity type different from the first conductivity type, which is provided in the active region (RA) and arranged between the drift layer (3) and the first main surface (SF1);

[0147] The first semiconductor region (5) of the first conductivity type is provided in the active region (RA), is arranged on the base region (4) and is in contact with the first electrode (11);

[0148] a plurality of first trenches (TR1) provided on the first main surface (SF1) in the active region (RA), having a first bottom portion (BT1) and a first side wall (SW1) in contact with the first semiconductor region (5) and the base region (4), wherein the plurality of first trenches (TR1) each extend along a length direction and are arranged in a width direction intersecting the length direction;

[0149] The second conductivity type first bottom diffusion layer (14), which is arranged at the first bottom (BT1) of each of the plurality of first trenches (TR1);

[0150] The second conductive type first sidewall diffusion layer (16a) is disposed on the first sidewall (SW1) of each of the plurality of first trenches (TR1) and is in contact with the first bottom diffusion layer (14) and the base region (4);

[0151] The second semiconductor region (1) of the first conductivity type or the second conductivity type is at least provided in the active region (RA), arranged between the drift layer (3) and the second main surface (SF2) and in contact with the second electrode (12);

[0152] a second trench (TR2) provided on the first main surface (SF1) in the inactive region (RI), contacting the active region (RA) and having a second side wall (SW2) and a second bottom (BT2), wherein the second side wall (SW2) has a length portion (SW2a) along the length direction and a width portion (SW2b) along the width direction;

[0153] The second conductivity type second bottom diffusion layer (17) is provided at least in a portion of the second bottom (BT2) of the second trench (TR2); and

[0154] The second conductive type second sidewall diffusion layer (16b) is provided on at least one of the length portion (SW2a) and the width portion (SW2b) of the second sidewall (SW2) of the second trench (TR2) and is in contact with the second bottom diffusion layer (17) and the base region (4).

[0155] The gate electrode (18) comprises:

[0156] a gate buried portion (18b) buried in each of the plurality of first trenches (TR1) of the semiconductor substrate (SB) via the insulating film; and

[0157] a gate wiring portion (18w) extending from the gate embedded portion (18b) into the second trench (TR2),

[0158] The second bottom diffusion layer (17) is arranged at least in a portion of the second bottom (BT2) of the second trench (TR2) where the gate wiring portion (18w) is arranged in the plan view.

[0159] (Note 2)

[0160] According to the semiconductor device (501-504) described in Supplementary Note 1,

[0161] The second side wall diffusion layer (16b) is provided on both the length portion (SW2a) and the width portion (SW2b) of the second side wall (SW2) of the second trench (TR2).

[0162] (Note 3)

[0163] The semiconductor device according to Supplement 1 or 2,

[0164] In the plan view, the second trench (TR2) surrounds the active area (RA).

[0165] (Note 4)

[0166] The semiconductor device according to any one of appendices 1 to 3,

[0167] The first electrode (11) has a contact portion (CTs) between a groove closest to the second groove (TR2) in the width direction among the plurality of first grooves (TR1) and the second groove (TR2), the contact portion (CTs) being in contact with the first main surface (SF1) of the semiconductor substrate (SB) outside the second groove (TR2),

[0168] The semiconductor substrate (SB) includes a contact region (6) of the second conductivity type in contact with the contact portion (CTs) and the second sidewall diffusion layer (16b).

[0169] (Note 5)

[0170] The semiconductor device (503) according to any one of Supplementary Notes 1 to 4,

[0171] The first electrode (11) has a contact portion (CTsb) in contact with the second bottom diffusion layer (17) of the semiconductor substrate (SB).

[0172] (Note 6)

[0173] The semiconductor device according to Supplementary Note 5,

[0174] In the first main surface (SF1) of the semiconductor substrate (SB), the plurality of first trenches (TR1) are arranged at intervals in the width direction.

[0175] In the plan view, the interval between the contact portion of the first electrode (11) and the second side wall (SW2) of the second trench (TR2) is smaller than the one interval.

[0176] (Note 7)

[0177] The semiconductor device according to any one of Supplementary Notes 1 to 6,

[0178] The ratio of the area of ​​the second sidewall diffusion layer (16b) to the total area of ​​the second sidewall (SW2) of the second trench (TR2) is greater than the ratio of the area of ​​the first sidewall diffusion layer (16a) to the total area of ​​the first sidewall (SW1) of the first trench (TR1).

[0179] (Note 8)

[0180] The semiconductor device (501-503) according to any one of Supplementary Notes 1 to 7,

[0181] The plurality of first trenches (TR1) are directly connected to the second trenches (TR2).

[0182] (Note 9)

[0183] The semiconductor device (504) according to any one of Supplementary Notes 1 to 8,

[0184] In the first main surface (SF1) of the semiconductor substrate (SB), the plurality of first trenches (TR1) are arranged at intervals in the width direction.

[0185] The semiconductor substrate (SB) includes a third trench (TR3) provided on the first main surface (SF1) in the inactive region (RI), separated from the second trench (TR2) in such a manner that a mesa portion (MS) of the semiconductor substrate (SB) is formed between the third trench and the second trench (TR2), and having a third bottom portion (BT3).

[0186] The third groove (TR3) is separated from the second groove (TR2) by an amount equal to or greater than the one interval.

[0187] (Note 10)

[0188] A method for manufacturing a semiconductor device (501-504), for manufacturing the semiconductor device according to any one of Supplementary Notes 1-9, comprising the following steps:

[0189] a) forming the first trench (TR1) and the second trench (TR2) in the semiconductor substrate (SB); and

[0190] b) forming the first side wall diffusion layer (16a) and the second side wall diffusion layer (16b) by performing ion implantation from an oblique direction into the first side wall (SW1) of the first trench (TR1) and the second side wall (SW2) of the second trench (TR2).

[0191] (Note 11)

[0192] According to the method for manufacturing a semiconductor device (501 to 504) as described in Supplementary Note 10,

[0193] Described b) comprises the following steps:

[0194] b1) a step of implanting ions into the length portion (SW2a) of the second side wall (SW2) of the second trench (TR2); and

[0195] b2) a step of implanting ions into the width portion (SW2b) of the second side wall (SW2) of the second trench (TR2),

[0196] The b1) and b2) are performed separately.

[0197] (Note 12)

[0198] A power conversion device (1200), comprising:

[0199] A main conversion circuit (1201) comprising a semiconductor device (501-504) as described in any one of Supplementary Notes 1-9, converting input power and outputting the converted power;

[0200] A driving circuit (1202) that outputs a driving signal for driving the semiconductor device (501-504) to the semiconductor device (501-504); and

[0201] A control circuit (1203) outputs a control signal for controlling the drive circuit (1202) to the drive circuit (1202).

Claims

1. A semiconductor device having an active region and an inactive region when viewed from above, wherein the inactive region comprises: The withstand voltage holding region and the gate wiring region in contact with the active region are characterized by comprising: A semiconductor substrate having: a first main surface and a second main surface opposite to the first main surface; a first electrode disposed on the first main surface of the semiconductor substrate; a second electrode disposed on the second main surface of the semiconductor substrate; an insulating film provided on the first main surface of the semiconductor substrate; and a gate electrode provided on the first main surface via the insulating film, The semiconductor substrate comprises: A drift layer of the first conductivity type, which is disposed in the active region and the inactive region; a base region of a second conductivity type different from the first conductivity type, which is provided in the active region and arranged between the drift layer and the first main surface; The first semiconductor region of the first conductivity type is provided in the active region, is arranged on the base region and is in contact with the first electrode; a plurality of first trenches, which are provided on the first main surface in the active region and have a first bottom portion and a first side wall in contact with the first semiconductor region and the base region, wherein the plurality of first trenches each extend along a length direction and are arranged in a width direction intersecting the length direction; The second conductive type first bottom diffusion layer is disposed at the first bottom of each of the plurality of first trenches; The second conductive type first sidewall diffusion layer is disposed on the first sidewall of each of the plurality of first trenches and is in contact with the first bottom diffusion layer and the base region; The second semiconductor region of the first conductivity type or the second conductivity type is provided at least in the active region, is arranged between the drift layer and the second main surface and is in contact with the second electrode; A second trench, which is provided on the first main surface in the inactive region, contacts the active region and has a second sidewall and a second bottom, wherein the second sidewall has a length portion along the length direction and a width portion along the width direction; A second bottom diffusion layer of the second conductivity type, disposed at at least a portion of the second bottom of the second trench; and The second conductive type second sidewall diffusion layer is provided on at least one of the length portion and the width portion of the second sidewall of the second trench and is in contact with the second bottom diffusion layer and the base region. The gate electrode comprises: a gate embedding portion that is embedded in the plurality of first trenches of the semiconductor substrate through the insulating film, respectively; and a gate wiring portion extending from the gate embedded portion into the second trench, The second bottom diffusion layer is arranged at least in a portion of the second bottom portion of the second trench where the gate wiring portion is arranged in the plan view.

2. The semiconductor device according to claim 1, wherein: The second sidewall diffusion layer is provided on both the length portion and the width portion of the second sidewall of the second trench.

3. The semiconductor device according to claim 1 or 2, characterized in that: In the plan view, the second trench surrounds the active area.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The first electrode has a contact portion between a groove closest to the second groove in the width direction among the plurality of first grooves and the second groove, the contact portion being in contact with the first main surface of the semiconductor substrate outside the second groove, The semiconductor substrate includes a contact region of the second conductivity type in contact with the contact portion and the second sidewall diffusion layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The first electrode has a contact portion that contacts the second bottom diffusion layer of the semiconductor substrate.

6. The semiconductor device according to claim 5, wherein: In the first main surface of the semiconductor substrate, the plurality of first trenches are arranged at intervals in the width direction. In the plan view, the interval between the contact portion of the first electrode and the second sidewall of the second trench is smaller than the one interval.

7. The semiconductor device according to any one of claims 1 to 6, wherein: A ratio of an area of ​​the second sidewall diffusion layer to a total area of ​​the second sidewall of the second trench is greater than a ratio of an area of ​​the first sidewall diffusion layer to a total area of ​​the first sidewall of the first trench.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The plurality of first trenches are directly connected to the plurality of second trenches.

9. The semiconductor device according to any one of claims 1 to 8, wherein: In the first main surface of the semiconductor substrate, the plurality of first trenches are arranged at intervals in the width direction. The semiconductor substrate includes a third trench provided on the first main surface in the inactive region, separated from the second trench in such a manner that a mesa portion of the semiconductor substrate is formed between the third trench and the second trench, and having a third bottom portion. The third trench is separated from the second trench by an amount equal to or greater than the one spacing.

10. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of claims 1 to 9, characterized in that: The following processes are available: a) forming the first trench and the second trench in the semiconductor substrate; and b) forming the first sidewall diffusion layer and the second sidewall diffusion layer by performing ion implantation from an oblique direction into the first sidewall of the first trench and the second sidewall of the second trench.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Described b) comprises the following steps: b1) a step of performing ion implantation on the length portion of the second sidewall of the second trench; and b2) a step of implanting ions into the width portion of the second sidewall of the second trench, The b1) and b2) are performed separately.

12. A power conversion device, characterized in that: have: A main conversion circuit, comprising the semiconductor device according to any one of claims 1 to 9, which converts input power and outputs the power; a driving circuit that outputs a driving signal for driving the semiconductor device to the semiconductor device; as well as A control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

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