An integrated-capacitance VDMOS device and its manufacturing method

Abstract

The present invention discloses an integrated-capacitance VDMOS device and a manufacturing method thereof, relating to the field of microelectronics technology, including: a drain, a substrate, and a drift region stacked in sequence; a first gate oxide layer located on the upper surface of the drift region, and in a direction perpendicular to the substrate, the orthographic projection of the first gate oxide layer is within the orthographic projection of the substrate; a gate located on the upper surface of the first gate oxide layer, and the orthographic projection of the gate is within the orthographic projection of the first gate oxide layer; a second gate oxide layer covering the upper surface and the side surface of the gate, and the orthographic projection of the second gate oxide layer overlaps with the orthographic projection of the first gate oxide layer; a source located on the side surface of the gate oxide layer composed of the first gate oxide layer and the second gate oxide layer, and the height of the source is greater than the height of the gate oxide layer; an insulating layer located on the upper surface of the source; a metal layer located on the upper surface of the insulating layer, and the metal layer is connected to the gate through a conductive via. The present invention can reduce the switching speed of the VDMOS device.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and particularly relates to an integrated-capacitor VDMOS device and a preparation method thereof. Background Art

[0002] Electromagnetic interference (EMI) refers to the phenomenon of mutual interference between an electromagnetic field and a circuit, or between different circuits. This interference can be generated through electromagnetic radiation, electromagnetic induction, electromagnetic coupling, etc. Its negative impacts include degraded device performance, signal distortion, communication interruption, etc. In severe cases, it may even lead to device damage or safety accidents.

[0003] The propagation of electromagnetic interference mainly has two forms: conducted interference and radiated interference. As a commonly used switch in a circuit system, a power device is one of the main sources of electromagnetic interference. The noise interference generated by its continuous turn-on and turn-off usually propagates to the back end of the circuit in the form of conducted interference. Currently, to address electromagnetic interference, it mainly starts from three aspects: the interference source, the propagation path, and the sensitive device. Generally, at the circuit level, measures such as adding LC filters, optimizing circuit design and layout, using decoupling capacitors and protection circuits are taken to optimize from the propagation path; and measures such as reducing the signal generation frequency and selecting low-noise components are taken to suppress from the interference source. However, these measures are likely to increase the size and cost of the system, and the high-frequency attenuation effect is not obvious. Especially in circuit design and capacitor selection, rich knowledge and experience and the best layout scheme are required, otherwise the expected effect cannot be achieved.

[0004] Therefore, how to improve the problem of electromagnetic interference from the device structure level has become an urgent problem to be solved currently. Summary of the Invention

[0005] To solve the above problems existing in the prior art, the present invention provides an integrated-capacitor VDMOS device and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] In a first aspect, the present invention provides an integrated-capacitor VDMOS device, comprising:

[0007] A drain, a substrate, and a drift region stacked in sequence;

[0008] A first gate oxide layer, located on the upper surface of the drift region. Along the direction perpendicular to the substrate, the orthographic projection of the first gate oxide layer is within the orthographic projection of the substrate;

[0009] A gate, located on the upper surface of the first gate oxide layer. Along the direction perpendicular to the substrate, the orthographic projection of the gate is within the orthographic projection of the first gate oxide layer;

[0010] A second gate oxide layer covers the upper surface and the side surfaces of the gate electrode. Along the direction perpendicular to the substrate, the orthographic projection of the second gate oxide layer overlaps with the orthographic projection of the first gate oxide layer.

[0011] A source electrode is located on the side surface of the gate oxide layer composed of the first gate oxide layer and the second gate oxide layer. Along the direction perpendicular to the substrate, the height of the source electrode is greater than the height of the gate oxide layer.

[0012] An insulating layer is located on the upper surface of the source electrode.

[0013] A metal layer is located on the upper surface of the insulating layer, and the metal layer is connected to the gate electrode through a conductive via.

[0014] In a second aspect, the present invention further provides a method for manufacturing an integrated-capacitance VDMOS device for manufacturing the integrated-capacitance VDMOS device provided above in the present invention, including:

[0015] Providing a substrate;

[0016] Epitaxially growing a drift region on the substrate;

[0017] Depositing a first gate oxide layer on the drift region, depositing a gate electrode on the first gate oxide layer, and depositing a second gate oxide layer on the upper surface and the side surfaces of the gate electrode. The first gate oxide layer and the second gate oxide layer form the gate oxide layer.

[0018] Depositing a source electrode around the gate oxide layer and on the drift region;

[0019] Depositing an insulating layer on the source electrode;

[0020] Depositing a metal layer on the insulating layer, and connecting the metal layer to the gate electrode through a conductive via.

[0021] Advantages of the present invention:

[0022] An integrated-capacitance VDMOS device and a manufacturing method thereof provided by the present invention include a drain electrode, a substrate, and a drift region stacked in sequence, which is a vertical-structured device. A first gate oxide layer and a source electrode are disposed on the upper surface of the drift region, and the source electrode is located on the periphery of the first gate oxide layer. A gate electrode is disposed on the upper surface of the first gate oxide layer, and a second gate oxide layer covers the upper surface and the side surface of the gate electrode. The first gate oxide layer and the second gate oxide layer together form a gate oxide layer. Along the direction perpendicular to the substrate, the height of the source electrode is greater than that of the gate oxide layer, and the source electrode surrounds the gate oxide layer to form a groove. An insulating layer is disposed on the upper surface of the source electrode, and a metal layer is disposed on the upper surface of the insulating layer. On the one hand, a capacitance is formed between the source electrode and the gate electrode. On the other hand, another capacitance is formed between the metal layer and the source electrode, and the metal layer is electrically connected to the gate electrode through a conductive hole, which is equivalent to two capacitances connected in parallel, further increasing the parasitic capacitance between the gate electrode and the source electrode to reduce the switching speed of the VDMOS device, thereby optimizing the electromagnetic interference performance of the VDMOS device and improving the performance of the VDMOS device.

[0023] The following will further describe the present invention in detail with reference to the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of an integrated-capacitance VDMOS device provided by an embodiment of the present invention;

[0025] Figure 2 is a top view of an integrated-capacitance VDMOS device provided by an embodiment of the present invention;

[0026] Figure 3 is a flowchart of a manufacturing method of an integrated-capacitance VDMOS device provided by an embodiment of the present invention;

[0027] Figures 4a to 4k is a schematic diagram of a manufacturing method of an integrated-capacitance VDMOS device provided by an embodiment of the present invention;

[0028] Figure 5 is a schematic diagram of a comparison of the turn-off current characteristics between the device provided by an embodiment of the present invention and an existing device;

[0029] Figure 6 is a schematic diagram of a comparison of the turn-off voltage characteristics between the device provided by an embodiment of the present invention and an existing device;

[0030] Figure 7 is a schematic diagram of a comparison of the static characteristics between the device provided by an embodiment of the present invention and an existing device. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0032] At present, dealing with electromagnetic interference mainly starts from three aspects: the interference source, the propagation path, and the sensitive device. Generally, from the circuit level, by adding LC filters, optimizing circuit design and layout, using decoupling capacitors and protection circuits, etc., to optimize from the propagation path; there is also to suppress from the interference source by reducing the signal generation frequency and selecting low-noise components; in addition, there is also to optimize from the device level, generally by increasing the doping concentration of the JFET region, changing the gate length and the thickness of the gate oxide layer to reduce the switching speed of the device.

[0033] These measures at the existing circuit optimization level will increase the size and cost of the system, and the high-frequency attenuation effect is not obvious. Especially in circuit design and capacitor selection, rich knowledge and experience and the best layout scheme are required, otherwise the expected effect cannot be achieved; these measures at the device optimization level will also increase the process manufacturing cost, and will have an adverse impact on the original static characteristics of the device, and even make it unqualified.

[0034] In view of this, a VDMOS device integrated with a capacitor and a preparation method thereof provided by the present invention further optimize the problem of electromagnetic interference by integrating a capacitor inside the VDMOS device; and when optimizing the problem of electromagnetic interference, it does not affect the static characteristics of the VDMOS device itself.

[0035] Please refer to Figure 1 , Figure 1 which is a schematic diagram of a VDMOS device integrated with a capacitor provided by an embodiment of the present invention, Figure 2 and Figure 2 is a top view of a VDMOS device integrated with a capacitor provided by an embodiment of the present invention. A VDMOS device integrated with a capacitor provided by the present invention includes:

[0036] A drain 10, a substrate 20, and a drift region 30 stacked in sequence;

[0037] A first gate oxide layer 41, located on the upper surface of the drift region 30. Along the direction D1 perpendicular to the substrate, the orthographic projection of the first gate oxide layer 41 is within the orthographic projection of the substrate 20;

[0038] A gate 50, located on the upper surface of the first gate oxide layer 41. Along the direction D1 perpendicular to the substrate, the orthographic projection of the gate 50 is within the orthographic projection of the first gate oxide layer 41;

[0039] A second gate oxide layer 42, covering the upper surface and the side surface of the gate 50. Along the direction D1 perpendicular to the substrate, the orthographic projection of the second gate oxide layer 42 overlaps with the orthographic projection of the first gate oxide layer 41;

[0040] The source electrode 60 is located on the side of the gate oxide layer composed of the first gate oxide layer 41 and the second gate oxide layer 42, and along the direction D1 perpendicular to the substrate, the height of the source electrode 60 is greater than the height of the gate oxide layer;

[0041] The insulating layer 70 is located on the upper surface of the source electrode 60;

[0042] The metal layer 80 is located on the upper surface of the insulating layer 70, and the metal layer 80 is connected to the gate electrode 50 through a conductive via.

[0043] Specifically, please continue to refer to Figure 1 and Figure 2 , a VDMOS device with an integrated capacitor provided by the present invention includes a drain electrode 10, a substrate 20, and a drift region 30 stacked in sequence, which is a vertical structure device. The upper surface of the drift region 30 is provided with a first gate oxide layer 41 and a source electrode 60. The source electrode 60 is located around the first gate oxide layer 41. The upper surface of the first gate oxide layer 41 is provided with a gate electrode 50, and the upper surface and side surfaces of the gate electrode 50 are covered with a second gate oxide layer 42. The first gate oxide layer 41 and the second gate oxide layer 42 together form a gate oxide layer. Along the direction D1 perpendicular to the substrate, the height of the source electrode 60 is greater than the height of the gate oxide layer, as Figure 1 shown, and in combination with Figure 2 , the source electrode 60 surrounds the gate oxide layer to form a groove. The upper surface of the source electrode 60 is provided with an insulating layer 70, and the upper surface of the insulating layer 70 is provided with a metal layer 80; on the one hand, the source electrode 60 and the gate electrode 50 form a capacitor, and on the other hand, the metal layer 80 and the source electrode 60 form another capacitor, and the metal layer 80 is electrically connected to the gate electrode 50 through a conductive via, which is equivalent to two capacitors in parallel, further increasing the parasitic capacitance between the gate electrode 50 and the source electrode 60, reducing the switching speed of the VDMOS device, and then optimizing the electromagnetic interference performance of the VDMOS device and improving the performance of the VDMOS device.

[0044] In an optional embodiment of the present invention, a capacitor is formed between the source electrode 60 and the metal layer 80 , a capacitor is formed between the source electrode 60 and the gate electrode 50 , the metal layer 80 is connected to the gate electrode 50 through a conductive via, so that the capacitor and the capacitor are in parallel to form a parallel capacitor;

[0045] The relationship between the parallel capacitor and the switching voltage slope of the VDMOS device is:

[0046] ;

[0047] The relationship between the parallel capacitor and the switching current slope of the VDMOS device is:

[0048] ;

[0049] Among them, represents the switching voltage of the VDMOS device, represents the switching current of the VDMOS device, represents the maximum value of the drain 10 current during the switching process, and the capacitor is inversely proportional, represents the gate 50 voltage, represents the capacitance formed between the gate 50 and the source 60, represents the voltage between the drain 10 and the source 60 of the MOSFET device, represents the continuous current of the drain 10, represents the capacitance formed between the source 60 and the metal layer 80, represents the flat-band voltage of the VDMOS device, represents the threshold voltage for the VDMOS device to turn on.

[0050] In an alternative embodiment of the present invention, the switching voltage slope of the VDMOS device is inversely proportional to the capacitance and the switching current slope of the VDMOS device is inversely proportional to the capacitance is inversely proportional.

[0051] In this embodiment, the switching current slope of the VDMOS device and the switching voltage slope of the VDMOS device decrease as the capacitance increases. The smaller the switching current slope of the VDMOS device and the switching voltage slope of the VDMOS device, the smaller the switching rate of the VDMOS device, thereby optimizing the electromagnetic interference performance of the VDMOS device and improving the performance of the VDMOS device; it can also be understood that the larger the capacitance value of the capacitance , the more advantageous it is.

[0052] In an alternative embodiment of the present invention, the expression of the capacitance is:

[0053] ;

[0054] Among them, represents the relative permittivity of the insulating layer 70, represents the thickness of the insulating layer 70, represents the overlapping area between the source 60 and the metal layer 80.

[0055] It should be noted that in this embodiment, from the above formula, it can be seen that the capacitance value that needs to be increased for the VDMOS device can be adjusted according to the type and thickness of the insulating layer 70.

[0056] In an alternative embodiment of the present invention, the material of the insulating layer 70 is silicon dioxide or silicon nitride.

[0057] Optionally, the material of the insulating layer 70 is silicon dioxide (SiO2), with a relative dielectric constant of 3.9. Along the direction D1 perpendicular to the substrate, the thickness of the insulating layer 70 is 0.1 μm, and the value of the integrated capacitance is about 600 pf.

[0058] In an alternative embodiment of the present invention, along the direction D1 perpendicular to the substrate, the thickness of the insulating layer 70 is 0.1 - 0.3 μm.

[0059] It should be noted that the thickness of the insulating layer 70 is not fixed and can be calculated based on the capacitance to be implanted and the dielectric constant of the insulating layer 70.

[0060] In an alternative embodiment of the present invention, along the direction D1 perpendicular to the substrate, the thickness of the metal layer 80 is 4 - 5 μm.

[0061] Optionally, the material of the metal layer 80 can be Al.

[0062] In an alternative embodiment of the present invention, the metal layer 80 is connected to the gate 50 through a conductive via. Among them, along the direction D1 perpendicular to the substrate, the conductive via penetrates the gate oxide layer.

[0063] Specifically, in this embodiment, a conductive via is opened in the gate oxide layer, and the electrical connection between the gate 50 and the metal layer 80 is realized through the conductive via.

[0064] It should be noted that, as Figure 1 shown, the source electrode 60 is located around the gate oxide layer. Along the direction D1 perpendicular to the substrate, the source electrode 60 does not overlap with the gate oxide layer. The insulating layer 70 is located on the upper surface of the source electrode 60, and the metal layer 80 is located on the upper surface of the insulating layer 70. That is, the orthographic projections of the insulating layer 70 and the metal layer 80 do not overlap with the orthographic projection of the gate oxide layer. It can also be understood that the top of the device directly exposes the gate oxide layer. By opening a conductive via in the gate oxide layer, the electrical connection between the gate 50 and the metal layer 80 can be realized.

[0065] Based on the same inventive concept, please refer to Figure 3 , Figure 3 which is a flowchart of a method for manufacturing an integrated-capacitance VDMOS device provided by an embodiment of the present invention. The present invention also provides a method for manufacturing an integrated-capacitance VDMOS device for manufacturing the integrated-capacitance VDMOS device provided by the above embodiments of the present invention. For the embodiments of the device, please refer to the above, and details will not be repeated here; the manufacturing method includes:

[0066] S101. Provide a substrate 20;

[0067] S102. Epitaxially grow a drift region 30 on a substrate 20;

[0068] S103. Deposit a first gate oxide layer 41 on the drift region 30, deposit a gate electrode 50 on the first gate oxide layer 41, and deposit a second gate oxide layer 42 on the upper surface and side surfaces of the gate electrode 50. The first gate oxide layer 41 and the second gate oxide layer 42 form a gate oxide layer;

[0069] S104. Deposit a source electrode 60 around the gate oxide layer and on the drift region 30;

[0070] S105. Deposit an insulating layer 70 on the source electrode 60;

[0071] S106. Deposit a metal layer 80 on the insulating layer 70. The metal layer 80 is connected to the gate electrode 50 through a conductive via;

[0072] S107. Deposit a drain electrode 10 on the side of the substrate 20 facing away from the drift region 30.

[0073] In an alternative embodiment of the present invention, before depositing the first gate oxide layer 41 on the drift region 30, it further includes:

[0074] Form P-type well regions 90 by ion implantation on both sides of the drift region 30;

[0075] Form N-type source regions 100 by ion implantation within the P-type well regions 90.

[0076] In an alternative embodiment of the present invention, an integrated capacitor VDMOS device is prepared through the following process, specifically:

[0077] S1. Provide an N+-type substrate 20, as Figure 4a shown.

[0078] Specifically, the N+-type substrate 20 is heavily doped, and the doping concentration is 1×10 18 ~6×10 20 cm 2 .

[0079] S2. Epitaxially grow an N-drift region 30 on the N+-type substrate 20, as Figure 4b shown.

[0080] Specifically, the N-drift region 30 is lightly doped, and the doping concentration is 1×10 14 ~1×10 16 cm 2 .

[0081] S3. Perform ion implantation on both sides of the N-drift region 30 to form P-type well regions 90, as Figure 4c shown.

[0082] Specifically, using a mask plate, ion implantation is performed on both sides of the N-drift region 30, B ions are implanted, and a P-type well region 90 is formed on each side of the N-drift region 30.

[0083] Among them, the P-type well region 90 is lightly doped, and the doping concentration is 8×10 15 ~1×10 18 cm 2 .

[0084] S4. Ion implantation is performed in the P-type well region 90 to form an N-type source region 100, as Figure 4d shown.

[0085] Specifically, using a mask plate, ion implantation is performed in the P-type well region 90, As ions are implanted, an N-type source region 100 is formed, and an N-type source region 100 is formed in each of the two P-type well regions 90.

[0086] Among them, the N+-type source region 100 is heavily doped, and the doping concentration is 1×10 18 ~1×10 20 cm 2 .

[0087] S5. Oxide is deposited on the upper surface of the N-drift region 30 to form a first gate oxide layer 41, as Figure 4e shown.

[0088] Specifically, on the surface of silicon carbide, oxide is grown by a thermal oxidation process to form a first gate oxide layer 41, and the thickness of the first gate oxide layer 41 is about 0.1 μm.

[0089] S6. A gate electrode 50 is deposited on the upper surface of the first gate oxide layer 41, as Figure 4f shown.

[0090] Specifically, using a deposition process, polysilicon is deposited on the upper surface of the first gate oxide layer 41 to form a gate electrode 50.

[0091] S7. A second gate oxide layer 42 is deposited on the upper surface and the side surface of the gate electrode 50, as Figure 4g shown.

[0092] Specifically, using a deposition process, a second gate oxide layer 42 is deposited on the upper surface and the side surface of the gate electrode 50, and a conductive hole (not shown in the figure) is formed through an etching process and a deposition process. The first gate oxide layer 41 and the second gate oxide layer 42 form a gate oxide layer.

[0093] Among them, the thickness of the second gate oxide layer 42 is about 1 μm.

[0094] S8. Deposit the source electrode 60 on the upper surfaces of the partial N-type source region 100 and the partial P-type well region 90, as well as around the gate oxide layer, as Figure 4h shown.

[0095] Specifically, use a deposition process to deposit metal on the upper surfaces of the partial N-type source region 100 and the partial P-type well region 90 to form the source electrode 60.

[0096] S9. Use a deposition process to deposit an insulating layer 70 on the upper surface of the source electrode 60, as Figure 4i shown.

[0097] Specifically, the material of the insulating layer 70 is silicon dioxide, and the thickness is about 0.1 μm. The thickness can be adjusted based on the required implanted capacitance and the dielectric constant of the insulating layer 70.

[0098] S10. Use a deposition process to deposit a metal layer 80 on the upper surface of the insulating layer 70, as Figure 4j shown.

[0099] Specifically, the material of the metal layer 80 is Al, and the thickness is 4 - 5 μm.

[0100] S11. Use a deposition process to deposit a drain electrode 10 on the side of the substrate 20 away from the drift region 30, as Figure 4k shown.

[0101] In an alternative embodiment of the present invention, the structure of the integrated-capacitance VDMOS device provided in the above embodiment is verified through a simulation experiment. Specifically:

[0102] I. Simulation Content and Result Analysis

[0103] Please refer to Figure 5 and Figure 6 . Figure 5 FIG. is a schematic diagram of the comparison of the turn-off current characteristics between the device provided in the embodiment of the present invention and the existing device, Figure 6 FIG. is a schematic diagram of the comparison of the turn-off voltage characteristics between the device provided in the embodiment of the present invention and the existing device. Figure 5 In Figure 6 and, Origin represents the existing device without integrated capacitance, and New represents the device provided by the present invention. It can be seen from the figure that after integrating a capacitor of about 600 pf between the gate and the source of the VDMOS device provided by the present invention, the turn-off current voltage rate decreases significantly. Through calculation, the turn-off current slope decreases by about 43%, and the turn-off voltage slope decreases by about 39%. Moreover, the amplitude of the slope decrease will increase as the integrated capacitance value increases.

[0104] Please refer to Figure 7 . Figure 7It is a schematic diagram for comparing the static characteristics between the device provided by the embodiment of the present invention and the existing device. Figure 7 In it, Origin represents the existing device without integrated capacitance, and New represents the device provided by the present invention. The threshold voltage, breakdown voltage, and on-resistance of the existing device and the VDMOS device provided by the present invention are simulated. It can be seen from the figure that there is no significant difference in the threshold voltage, breakdown voltage, and on-resistance between the two, indicating that integrating a capacitance inside the VDMOS device has no impact on the static characteristics of the device.

[0105] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant is intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the article or device including the said element. Terms such as "connected" or "coupled" do not necessarily refer to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present invention.

[0106] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0107] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A VDMOS device with integrated capacitor, characterized in that: include: A drain electrode, a substrate and a drift region are stacked in sequence; A first gate oxide layer is located on an upper surface of the drift region, and along a direction perpendicular to the substrate, an orthographic projection of the first gate oxide layer is located within a range of an orthographic projection of the substrate; A gate is located on an upper surface of the first gate oxide layer, and along a direction perpendicular to the substrate, an orthographic projection of the gate is located within a range of an orthographic projection of the first gate oxide layer; A second gate oxide layer covers the upper surface and side surfaces of the gate, and an orthographic projection of the second gate oxide layer overlaps with an orthographic projection of the first gate oxide layer in a direction perpendicular to the substrate; A source electrode is located on an upper surface and a side surface of a gate oxide layer composed of the first gate oxide layer and the second gate oxide layer, and along a direction perpendicular to the substrate, a height of the source electrode is greater than a height of the gate oxide layer; an insulating layer, located on an upper surface of the source electrode; A metal layer, located on the upper surface of the insulating layer, and the metal layer is connected to the gate through a conductive hole; A capacitor is formed between the source electrode and the metal layer , a capacitor is formed between the source and the gate The metal layer is connected to the gate through a conductive hole so that the capacitor With the capacitor Connected in parallel, a parallel capacitor is formed.

2. The VDMOS device with integrated capacitor according to claim 1, characterized in that: The capacitor The expression is: ； in, represents the relative dielectric constant of the insulating layer, Indicates the thickness of the insulation layer, Represents the overlapping area between the source and the metal layer.

3. The VDMOS device with integrated capacitor according to claim 1, characterized in that: The insulating layer is made of silicon dioxide or silicon nitride.

4. The VDMOS device with integrated capacitor according to claim 1, characterized in that: Along the direction perpendicular to the substrate, the thickness of the insulating layer is 0.1-0.3 μm.

5. The VDMOS device with integrated capacitor according to claim 1, characterized in that: Along the direction perpendicular to the substrate, the thickness of the metal layer is 4-5 μm.

6. The VDMOS device with integrated capacitor according to claim 1, characterized in that: The metal layer is connected to the gate via a conductive hole, wherein the conductive hole penetrates the gate oxide layer along a direction perpendicular to the substrate.

7. A method for preparing a VDMOS device with integrated capacitor, for preparing the VDMOS device with integrated capacitor as claimed in any one of claims 1 to 6, characterized in that: include: providing a substrate; epitaxially growing a drift region on the substrate; Depositing a first gate oxide layer on the drift region, depositing a gate on the first gate oxide layer, and depositing a second gate oxide layer on the upper surface and side surfaces of the gate, wherein the first gate oxide layer and the second gate oxide layer form a gate oxide layer; Depositing a source electrode around the gate oxide layer and on the drift region; depositing an insulating layer on the source electrode; Depositing a metal layer on the insulating layer, wherein the metal layer is connected to the gate via a conductive hole; A drain is deposited on a side of the substrate facing away from the drift region.

8. The method for preparing a VDMOS device with integrated capacitor according to claim 7, characterized in that: Before depositing the first gate oxide layer on the drift region, the method further comprises: forming a P-type well region on both sides of the drift region by ion implantation; An N-type source region is formed in the P-type well region by ion implantation.

Images