A short channel field effect transistor, a method for manufacturing the same, and an electronic device

Abstract

The application provides a short channel field effect transistor, a preparation method thereof and an electronic device, and the transistor comprises a substrate, a first insulating layer in a stepped structure, a first part and a second part arranged in sequence, the top surface of the second part is higher than that of the first part, a gate located above the second part, a second insulating layer in a stepped structure, the top surface of the second insulating layer on the gate is higher than that of the second insulating layer on the second part not covered by the gate, a third insulating layer covering the second insulating layer and the first part, the third insulating layer is formed by an atomic layer deposition process, a source and a drain respectively located on the two sides of the gate, a semiconductor layer electrically connected with the source and the drain, the semiconductor layer is formed by an atomic layer deposition process, and the stepped structure between the first insulating layer, the gate and the second insulating layer is formed by an etching process. The application can realize large-area and low-cost preparation of the short channel field effect transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a short channel field effect transistor, a preparation method thereof and an electronic device. BACKGROUND

[0002] The phased array antenna array has the advantages of strong directivity, high gain and good reconfigurability, and is the mainstream antenna array at present. In general, in order to obtain higher gain, narrower main lobe, stronger plasticity, beamforming capability and multi-beam generation capability, the phased array antenna is generally composed of an array of many antenna units, and the feed parameters of each unit are controlled through active phased array technology. The amplifier is an important component, and the currently mainly applied monolithic integrated radio frequency integrated circuit materials, such as GaAs, Si and GaN, can realize amplification function at X-band or even higher frequency band, but have the disadvantages of complex process, high cost, high requirements for materials and equipment and inability to meet the large-area preparation required by the phased array antenna.

[0003] Therefore, how to prepare a large-area short channel field effect transistor for application in a phased array antenna array in a large area and at a low cost is a technical problem to be solved at present. SUMMARY

[0004] In view of the defects in the prior art, the purpose of the present application is to provide a short channel field effect transistor, a preparation method thereof and an electronic device.

[0005] According to a first aspect of the present application, a short channel field effect transistor is provided, which comprises:

[0006] a substrate;

[0007] a first insulating layer located above the substrate, the first insulating layer being in a stepped structure and comprising a first part and a second part arranged in sequence, the top surface of the second part being higher than the top surface of the first part;

[0008] a gate located above the second part, the gate being arranged at an end of the second part close to the first part;

[0009] a second insulating layer located above the gate and the second part not covered by the gate, the second insulating layer being in a stepped structure, the top surface of the second insulating layer on the gate being higher than the top surface of the second insulating layer on the second part not covered by the gate;

[0010] a third insulating layer covering the second insulating layer and the first part, and the side walls formed by the second part, the gate and the second insulating layer respectively; the third insulating layer is formed by an atomic layer deposition process;

[0011] a source electrode and a drain electrode, located above the third insulating layer, and the source electrode and the drain electrode are located on two sides of the gate electrode respectively;

[0012] a semiconductor layer, located above the third insulating layer, two ends of the semiconductor layer are electrically connected with the source electrode and the drain electrode respectively, and the semiconductor layer exposes the gate electrode, the source electrode and the drain electrode; the semiconductor layer is formed by an atomic layer deposition process;

[0013] a stepped structure is formed between the first insulating layer, the gate electrode and the second insulating layer, and the stepped structure is formed by an etching process.

[0014] Optionally, the semiconductor layer comprises:

[0015] a first part of the semiconductor layer, located above the gate electrode, the first part of the semiconductor layer covers the third insulating layer between the source electrode and the drain electrode;

[0016] a second part of the semiconductor layer, the second part of the semiconductor layer covers part of the source electrode;

[0017] a third part of the semiconductor layer, the third part of the semiconductor layer covers part of the drain electrode;

[0018] the channel width of the semiconductor is the distance between the source electrode and the drain electrode, the channel length of the semiconductor is the distance between two edges of the semiconductor layer perpendicular to the channel width direction, the length of the gate electrode is the distance between two edges perpendicular to the channel width direction, and the channel length is smaller than the length of the gate electrode.

[0019] Optionally, the source electrode and the drain electrode partially overlap or do not overlap the gate electrode in the direction of the normal line of the substrate.

[0020] Optionally, the transistor has one or more of the following options:

[0021] a source electrode plate is provided on the third insulating layer, and the source electrode plate is electrically connected with the source electrode;

[0022] a drain electrode plate is provided on the third insulating layer, and the drain electrode plate is electrically connected with the drain electrode;

[0023] a gate electrode plate is provided on the first insulating layer, and the gate electrode plate is electrically connected with the gate electrode.

[0024] Optionally, a protective layer is provided above the semiconductor layer, the protective layer covers the semiconductor layer, and the protective layer is provided with a first through hole exposing the gate electrode, a second through hole exposing the source electrode and a third through hole exposing the drain electrode.

[0025] Optionally, the first insulating layer, the second insulating layer and the third insulating layer are formed by using the same material.

[0026] Optionally, the semiconductor layer is formed by using metal oxide material.

[0027] Optionally, the gate, the source and the drain each have a three-layer material structure formed by titanium, gold and nickel from bottom to top.

[0028] According to a second aspect of the present application, a preparation method of the short channel field effect transistor is provided, and the method comprises:

[0029] providing a substrate;

[0030] forming a first insulating layer covering the substrate above the substrate, etching the first insulating layer to form a first part and a second part in a stepped shape, and forming a gate on the second part;

[0031] forming a second insulating layer above the gate and the second part not covered by the gate, etching the second insulating layer to form a stepped shape, and exposing the side surface of the gate electrode by the step sidewall parallel to the normal direction of the substrate;

[0032] atomically depositing and growing a third insulating layer as a gate oxide layer on the second insulating layer and the first part;

[0033] forming a source and a drain above the third insulating layer, and the source and the drain are respectively located on the two sides of the gate;

[0034] atomically depositing and growing a semiconductor layer above the source and the drain, the semiconductor layer is electrically connected to the gate and the drain, and is patterned;

[0035] etching to expose the through hole of the gate, the source and the drain.

[0036] According to a third aspect of the present application, an electronic device is provided, and the electronic device comprises the short channel field effect transistor.

[0037] Compared with the prior art, the present application has at least one of the following beneficial effects:

[0038] The present application utilizes a larger size lithography process to realize the structure and preparation method of the short channel field effect transistor. The vertical channel makes the channel length of the device only determined by the thickness of the gate, and is not dependent on the lithography precision. Therefore, the short channel field effect transistor can be prepared in a large area by using a larger size process, and can be widely applied in the field of integrated circuit technology, and provides a good technical path for realizing a large-area radio frequency amplification circuit. BRIEF DESCRIPTION OF DRAWINGS

[0039] Other features, objects, and advantages of the application will become more apparent from the following detailed description when read in conjunction with the accompanying drawings:

[0040] Figure 1 is a cross-sectional schematic view of a short channel field effect transistor structure in an embodiment of the present application;

[0041] Figure 2 is a cross-sectional schematic view corresponding to step S1 and step S2 of a method for manufacturing a short channel field effect transistor structure in an embodiment of the present application;

[0042] Figure 3 is a cross-sectional schematic view corresponding to step S2 of a method for manufacturing a short channel field effect transistor structure in an embodiment of the present application;

[0043] Figure 4 is a cross-sectional schematic view corresponding to step S3-step S7 of a method for manufacturing a short channel field effect transistor structure in an embodiment of the present application;

[0044] Figure 5 is a cross-sectional schematic view corresponding to step S8 of a method for manufacturing a short channel field effect transistor structure in an embodiment of the present application.

[0045] In the figure: 100 is a substrate, 110 is a first insulating layer, 111 is a first part, 112 is a second part, 121 is a gate, 122 is a gate plate, 130 is a second insulating layer, 140 is a third insulating layer, 151 is a drain, 152 is a source, 153 is a source plate, 154 is a drain plate, 160 is a semiconductor layer, 161 is a first part of the semiconductor layer, 162 is a second part of the semiconductor layer, 163 is a third part of the semiconductor layer, 170 is a protective layer, and PR represents a photoresist pattern layer. DETAILED DESCRIPTION

[0046] The application will be described in further detail below with specific embodiments. The following embodiments will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These are within the scope of protection of the present application.

[0047] It should be noted that the terms "first", "second" and the like in the description and in the claims are used for descriptive purposes only and do not necessarily connote an ordering of elements or numbering of elements. Thus, a feature specified as the "first" feature can implicitly or explicitly include one or more of the same feature, and the like. Also, the terms "first", "second" and the like are used merely as identifiers that identify a difference between two elements that have a difference, but do not connote an order or a priority or a ranking of the elements. It is to be understood that the data used herein can be interchanged, where appropriate, to enable the embodiments of the application described herein to be carried out in other than the order depicted or described herein.

[0048] With reference to Figures 1-5 In one embodiment, the short channel field effect transistor comprises a substrate 100, a first insulating layer 110, a gate 121, a second insulating layer 130, a third insulating layer 140, a source 152 and a drain 151, and a semiconductor layer 160. The first insulating layer 110 is located above the substrate 100. The first insulating layer 110 has a stepped structure and comprises a first portion 111 and a second portion 112 arranged in sequence. The top surface of the second portion 112 is higher than the top surface of the first portion 111. The gate 121 is located above the second portion 112. The area of the gate 121 is smaller than the area of the second portion 112. The gate 121 is arranged at the end of the second portion 112 close to the first portion 111. The second insulating layer 130 is located above the gate 121 and the second portion 112 not covered by the gate 121. The second insulating layer has a stepped structure. The top surface of the second insulating layer 130 on the gate 121 is higher than the top surface of the second insulating layer 130 on the second portion 112 not covered by the gate 121. The third insulating layer 140 covers the second insulating layer 130 and the first portion 111, and the sidewalls of the second portion 112, the gate 121 and the second insulating layer 130, thereby enabling the formation of a uniform thin film on a non-flat area such as a sidewall. The third insulating layer 140 is formed by an atomic layer deposition process and has good coverage on the sidewalls of the stepped structure formed by the first insulating layer 110, the gate 121 and the second insulating layer 130. The source 152 and the drain 151 are located above the third insulating layer 140 and are respectively located on the two sides of the gate 121. The semiconductor layer 160 is located above the third insulating layer. The semiconductor layer 160 covers the third insulating layer 140 between the source 152 and the drain 151, and part of the source 152 and part of the drain 151. The two ends of the semiconductor layer 160 are respectively electrically connected to the source 152 and the drain 151. The semiconductor layer 160 exposes the gate 121, the source 152 and the drain 151. The semiconductor layer 160 is formed by an atomic layer deposition process and has good coverage on the sidewalls of the stepped structure formed by the third insulating layer 140. A stepped structure is formed between the first insulating layer 110, the gate 121 and the second insulating layer 130. The stepped structure is formed by an etching process.

[0049] The short-channel field-effect transistor in this embodiment of the invention can be, but is not limited to, a bottom-gate bottom-contact structure. A stepped structure is formed by etching the first insulating layer 110, the second insulating layer 130, and the gate 121, exposing the sidewalls of the gate 121. A third insulating layer 140 (gate insulating layer) and a semiconductor layer 160 are formed using the good step coverage of atomic layer deposition. The gate 121 is located in the normal direction of the substrate 100. Figures 1-3 The thickness along the direction indicated by ND in the diagram represents the length of the gate 121 of the field-effect transistor. By controlling the switching of the channel, the length of the gate 121 modulating semiconductor is no longer determined by the precision of the photolithography process, but entirely by the thickness deposited during the fabrication of the gate 121. This allows for the fabrication of a short-channel field-effect transistor under large-scale photolithography conditions. Furthermore, the semiconductor layer 160 and the third insulating layer 140 are formed by atomic layer deposition, which is beneficial for improving device performance. Existing conventional high-frequency devices such as silicon-based, silicon nitride, and gallium arsenide suffer from drawbacks such as high cost and inability to be fabricated on a large scale. The short-channel field-effect transistor provided in this invention can utilize display panel fabrication processes to achieve low-cost fabrication of large-area short-channel devices of 100 inches and above.

[0050] In the above embodiments, a first insulating layer 110 covers and overlaps the substrate 100; a first portion 111 extends along the surface of the substrate 100 and directly contacts the substrate 100; a second portion 112 extends along the surface of the substrate 100 and directly contacts the substrate 100. A gate 121 extends along the surface of the second portion 112 of the first insulating layer 110. A second insulating layer 130 covers the gate 121 and part or all of the first insulating layer 110. A third insulating layer 140 covers the second insulating layer 130, the first portion 111 of the first insulating layer 110, and the sidewalls formed by the second portion 112 of the first insulating layer 110, the gate 121, and the second insulating layer 130.

[0051] In some embodiments, the semiconductor layer 160 includes a first semiconductor layer portion 161, a second semiconductor layer portion 162, and a third semiconductor layer portion 163, wherein: the first semiconductor layer portion 161 is located above the gate 121, and covers a third insulating layer 140 between the source 152 and the drain 151; the second semiconductor layer portion 162 covers a portion of the source 152; and the third semiconductor layer portion 163 covers a portion of the drain 151. (Refer to...) Figure 4, the channel width direction of the semiconductor is perpendicular to the normal direction of the substrate 100, the channel width of the semiconductor is the distance between the source 152 and the drain 151, and the width of the gate 121 can be greater than or less than the channel width; the channel length of the semiconductor is the distance between the two edges of the semiconductor layer 160 perpendicular to the channel width direction (i.e., along the normal direction of the substrate), the length of the gate 121 is the distance between the two edges perpendicular to the channel width direction (i.e., along the normal direction of the substrate), and the channel length of the semiconductor is less than the length of the gate 121, so that the gate 121 can fully regulate the semiconductor layer 160.

[0052] In some embodiments, the source 152 and the drain 151 partially overlap or do not overlap the gate 121 in the normal direction of the substrate 100.

[0053] In the above embodiment, the first insulating layer 110 is provided with a gate plate 122, and the gate plate 122 is electrically connected with the gate 121. The third insulating layer 140 is provided with a source plate 153, and the source plate 153 is electrically connected with the source 152. The third insulating layer 140 is provided with a drain plate 154, and the drain plate 154 is electrically connected with the drain 151.

[0054] In some embodiments, a protective layer 170 is arranged above the semiconductor layer 160, the protective layer 170 covers the semiconductor layer 160, and the protective layer 170 is provided with a first through hole exposing the gate 121, a second through hole exposing the source 152, and a third through hole exposing the drain 151.

[0055] The materials of the first insulating layer 110, the second insulating layer 130, and the third insulating layer 140 include high-performance inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, and aluminum oxide. Preferably, the first insulating layer 110, the second insulating layer 130, and the third insulating layer 140 are formed by using the same material to simplify the manufacturing process and further reduce the cost.

[0056] The material of the semiconductor layer 160 is a metal oxide material prepared by an atomic layer deposition process, including any one of indium oxide, zinc oxide, gallium oxide, and tin oxide, or a combination of two or more thereof or other semiconductor materials.

[0057] The gate 121, the source 152, and the drain 151 are single-layer or multi-layer structures, and the materials thereof include, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys thereof, metal oxides thereof, metal nitrides thereof, or combinations thereof or other conductive materials. Preferably, the gate 121, the source 152, and the drain 151 each have a three-layer material structure formed by titanium, gold, and nickel from bottom to top, so that the contact resistance can be reduced, the adhesion of the electrode can be improved, and the growth of the atomic layer deposition is suitable.

[0058] The material of the substrate 100 can be glass, quartz, organic polymer, or non-transparent / reflective material (e.g., conductive material, metal, wafer, ceramic, or other applicable material), or other applicable material. If a conductive material or metal is used, an insulating layer is coated on the substrate 100 to avoid short circuit. It is noted that the first insulating layer 110 can not be grown if the substrate 100 is sufficiently insulating.

[0059] Based on the same inventive concept, another embodiment of the present application provides a method for manufacturing the short channel field effect transistor as described above, referring to Figures 1-5 the method comprises the following steps:

[0060] S1, providing a substrate 100;

[0061] S2, forming a first insulating layer 110 on the substrate 100 to cover the substrate 100, etching the first insulating layer 110 to form a first part 111 and a second part 112 in a stepped shape, and forming a gate 121 on the second part 112;

[0062] S3, forming a second insulating layer 130 on the gate 121 and the second part 112 not covered by the gate 121, using a photoresist pattern layer PR as a mask, etching the second insulating layer 130 to form a stepped shape and expose the gate electrode side surface parallel to the normal direction of the substrate 100 to directly contact the third insulating layer 140, thereby regulating the semiconductor layer 160; the structure formed by etching is as shown in Figure 3 ;

[0063] S4, atomic layer deposition of a third insulating layer 140 as a gate oxide layer on the second insulating layer 130 and the first part 111 to isolate the gate 121 from the source 152 and the drain 151;

[0064] S5, preparing a source 152 and a drain 151 on the third insulating layer 140, the source 152 and the drain 151 being respectively located on both sides of the gate 121;

[0065] S6, atomic layer deposition of a semiconductor layer 160 on the source 152 and the drain 151, the semiconductor layer 160 being electrically connected to the source 152 and the drain 151, and being patterned to reduce the gate 121 leakage current, avoid crosstalk between adjacent devices, and reduce the overall power consumption of the circuit;

[0066] S7, etching to expose the through holes of the gate 121, the source 152, and the drain 151.

[0067] In the above method, in step S2, the second part 112 is further formed with a gate plate 122; in step S5, the third insulating layer 140 is further formed with a source plate 153 and a drain plate 154, and in step S7, the through holes of the gate plate 122, the source plate 153 and the drain plate 154 are exposed by etching correspondingly.

[0068] In some embodiments, after step S7, there is further a step S8: preparing a protective layer 170, and etching to expose the through holes of the gate 121, the source 152 and the drain 151, etc., as shown in Figure 5

[0069] Another embodiment of the present application also provides an electronic device comprising the above short channel field effect transistor, and the electronic device has the same technical effects as the short channel field effect transistor, which will not be repeated here.

[0070] The above embodiments of the present application utilize a large-size photolithography process to realize the structure and preparation method of the short channel field effect transistor, the vertical channel makes the channel length of the device only determined by the thickness of the gate, and is not dependent on the photolithography precision, so that the large-size process is used to realize the large-area preparation of the short channel field effect transistor, thereby solving the problem that the existing short channel device cannot be prepared in a large area at low cost. The embodiments of the present application can be applied to the field of large-area integrated circuit technology requiring short channel devices, for example, the preparation of a phased array antenna radio frequency amplification circuit, which provides a good technical path for realizing a large-area radio frequency amplification circuit.

[0071] The specific embodiments of the present application are described above. It should be understood that the present application is not limited to the above specific embodiments, and various modifications or changes can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application. The above preferred features can be used in combination as long as they are not in conflict with each other.​

Claims

1. A short-channel field-effect transistor, characterized in that, include: Substrate; A first insulating layer is located above the substrate. The first insulating layer has a stepped structure and includes a first part and a second part arranged sequentially. The top surface of the second part is higher than the top surface of the first part. A gate is located above the second portion, and the gate is disposed at the end of the second portion near the first portion; A second insulating layer is located above the gate and the second portion not covered by the gate. The second insulating layer has a stepped structure, and the top surface of the second insulating layer on the gate is higher than the top surface of the second insulating layer on the second portion not covered by the gate. A third insulating layer covers the second insulating layer and the first portion, as well as the sidewalls formed by the second portion, the gate, and the second insulating layer; the third insulating layer is formed using an atomic layer deposition process. The source and drain are located above the third insulating layer, and the source and drain are located on opposite sides of the gate, respectively. A semiconductor layer is located above the third insulating layer, with its two ends electrically connected to the source and the drain, respectively, and the semiconductor layer exposing the gate, the source, and the drain; the semiconductor layer is formed using an atomic layer deposition process. A stepped structure is formed between the first insulating layer, the gate, and the second insulating layer, and the stepped structure is formed by an etching process.

2. The short-channel field-effect transistor according to claim 1, characterized in that, The semiconductor layer includes: A first portion of the semiconductor layer is located above the gate, and the first portion of the semiconductor layer covers the third insulating layer between the source and the drain. A second portion of the semiconductor layer, the second portion of the semiconductor layer covering a portion of the source electrode; A third portion of the semiconductor layer, wherein the third portion of the semiconductor layer covers a portion of the drain electrode; The channel width of the semiconductor is the distance between the source and the drain, the channel length of the semiconductor is the distance between the two edges of the semiconductor layer perpendicular to the channel width direction, the gate length is the distance between the two edges perpendicular to the channel width direction, and the channel length is less than the gate length.

3. The short-channel field-effect transistor according to claim 1, characterized in that, The source and the drain may partially overlap or not overlap with the gate in the direction normal to the substrate.

4. The short-channel field-effect transistor according to claim 1, characterized in that, One or more of the following options are available: -A source electrode plate is provided on the third insulating layer, and the source electrode plate is electrically connected to the source electrode; - A drain plate is provided on the third insulating layer, and the drain plate is electrically connected to the drain. - A gate electrode is provided on the first insulating layer, and the gate electrode is electrically connected to the gate.

5. The short-channel field-effect transistor according to claim 1, characterized in that, A protective layer is provided above the semiconductor layer, the protective layer covers the semiconductor layer, and the protective layer has a first via exposing the gate, a second via exposing the source, and a third via exposing the drain.

6. The short-channel field-effect transistor according to claim 1, characterized in that, The first insulating layer, the second insulating layer, and the third insulating layer are formed of the same material.

7. The short-channel field-effect transistor according to claim 1, characterized in that, The semiconductor layer is formed using a metal oxide material.

8. The short-channel field-effect transistor according to claim 1, characterized in that, The gate, the source, and the drain all have a three-layer material structure formed from titanium, gold, and nickel in sequence from bottom to top.

9. A method for fabricating a short-channel field-effect transistor according to any one of claims 1-8, characterized in that, include: Provide substrate; A first insulating layer covering the substrate is formed above the substrate, the first insulating layer is etched to form a stepped first portion and a second portion, and a gate is formed on the second portion; A second insulating layer is formed above the gate and the second portion not covered by the gate. The second insulating layer is etched to form a stepped shape, and the gate electrode sidewalls parallel to the substrate normal direction are exposed. A third insulating layer is deposited and grown on the second insulating layer and the atomic layer of the first portion as a gate oxide layer; A source and a drain are fabricated on the third insulating layer, with the source and the drain located on opposite sides of the gate, respectively. A semiconductor layer is deposited and grown on the source and drain electrodes at atomic layers, the semiconductor layer being electrically connected to the gate and drain electrodes and patterned. Etching exposes the vias of the gate, the source, and the drain.

10. An electronic device, characterized in that, Includes the short-channel field-effect transistor according to any one of claims 1-8.

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