Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention discloses a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors. The at least one first metal gate structure is arranged on the substrate, and the first metal gate structure is a PMOS (P-channel Metal Oxide Semiconductor)-like metal gate structure or an NMOS (N-channel Metal Oxide Semiconductor)-like metal gate structure; the metal structure is arranged on the substrate; the first metal gate structure is attached to the metal structure, and an insulating layer of the first metal gate structure is clamped between a metal gate of the first metal gate structure and the metal structure; and the metal gate of the first metal gate structure and the metal structure form a capacitor as a pair of opposite polar plates. Based on the above mode, the capacitor volume in the semiconductor structure can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a process method for manufacturing the semiconductor device. Background Art

[0002] In the prior art, in the manufacturing process of semiconductor structures, for example, in a planar MOS structure, the capacitor is usually a planar structure MOSCAP (metal-oxide-semiconductor capacitor) or Varactor (variable capacitor), and MOSCAP and Varactor usually occupy a larger area of ​​the AA (active area) structure.

[0003] The defect of the prior art is that since MOSCAP and Varactor usually occupy a larger area of ​​the AA structure, the capacitor needs to occupy a lot of area in the semiconductor structure, which easily makes the semiconductor structure need to occupy more space, and then easily increases the cost of the semiconductor structure or causes other negative effects. In summary, the capacitor in the existing semiconductor structure is relatively large. Summary of the invention

[0004] The main technical problem solved by the present application is how to reduce the capacitor volume in the semiconductor structure.

[0005] In order to solve the above technical problems, the first technical solution adopted in the present application is: a semiconductor device, comprising: a substrate; at least one first metal gate structure, the first metal gate structure is arranged on the substrate, the first metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure; a metal structure, the metal structure is arranged on the substrate; the first metal gate structure is arranged in contact with the metal structure, and the insulating layer of the first metal gate structure is sandwiched between the metal gate of the first metal gate structure and the metal structure; the metal gate of the first metal gate structure and the metal structure serve as a pair of relative plates to form a capacitor.

[0006] Among them, the metal structure is a second metal gate structure; the insulating layer of the first metal gate structure and the insulating layer of the second metal gate structure are both sandwiched between the metal gate of the first metal gate structure and the metal gate of the second metal gate structure; the metal gate of the first metal gate structure and the metal gate of the second metal gate structure serve as a pair of relative plates to form a capacitor.

[0007] The first metal gate structure is a PMOS-like metal gate structure, and the second metal gate structure is an NMOS-like metal gate structure; or the first metal gate structure is an NMOS-like metal gate structure, and the second metal gate structure is a PMOS-like metal gate structure.

[0008] The substrate is a part of the active region in the semiconductor substrate, or the substrate is the top of the shallow trench isolation structure.

[0009] The insulating layer is a high-K dielectric layer, which is arranged between the bottom of the metal gate and the substrate and covers the side wall of the metal gate.

[0010] The first metal gate structure further comprises a spacer layer, which is located between the insulating layer and the substrate and covers the insulating layer on the side wall of the metal gate.

[0011] Among them, each first metal gate structure is led out through the corresponding contact window metal and connected to the first interconnection; the metal structure is led out through the corresponding contact window metal and connected to the second interconnection; the first interconnection serves as one plate of the capacitor, and the second interconnection serves as the other plate of the capacitor to form a capacitor.

[0012] The semiconductor device further comprises: a gate sidewall, which is arranged on the substrate and surrounds a capacitor region on the substrate. The first metal gate structure and the metal structure are both located in the capacitor region.

[0013] In order to solve the above technical problems, the second technical solution adopted in the present application is: a process method for a semiconductor device, comprising: providing a substrate, forming a capacitor area surrounded by a gate side wall on the substrate; forming a polysilicon layer in the capacitor area; etching the polysilicon layer to form at least one first accommodating cavity; forming a first metal gate structure in the first accommodating cavity; wherein the first metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure; etching the remaining polysilicon layer at least adjacent to the first metal gate structure in the capacitor area to form a second accommodating cavity; forming a metal structure in the second accommodating cavity so that the first metal gate structure is fitted with the metal structure, and the insulating layer of the first metal gate structure is sandwiched between the metal gate of the first metal gate structure and the metal structure; wherein the metal gate and the metal structure of the first metal gate structure serve as a pair of relative plates to form a capacitor.

[0014] The step of etching the remaining polysilicon layer in the capacitor region that is at least adjacent to the first metal gate structure to form a second accommodation cavity includes etching the entire remaining polysilicon layer in the capacitor region to form a second accommodation cavity.

[0015] The forming of the first metal gate structure in the first accommodating cavity includes: during the formation of the metal gate structure in the corresponding transistor manufacturing process, the first metal gate structure is simultaneously formed in the first accommodating cavity.

[0016] Wherein, a metal structure is formed in the second accommodating cavity, including: forming a second metal gate structure in the second accommodating cavity, so that the insulating layer of the first metal gate structure and the insulating layer of the second metal gate structure are both sandwiched between the metal gate of the first metal gate structure and the metal gate of the second metal gate structure; the metal gate of the first metal gate structure and the metal gate of the second metal gate structure serve as a pair of relative plates to form a capacitor.

[0017] The forming of the second metal gate structure in the second accommodating cavity includes: during the formation of the metal gate structure in the corresponding transistor manufacturing process, the second metal gate structure is synchronously formed in the second accommodating cavity.

[0018] Among them, forming a first metal gate structure in the first accommodating cavity includes: during the formation of the metal gate structure in the corresponding first transistor process, the first metal gate structure is synchronously formed in the first accommodating cavity; forming a second metal gate structure in the second accommodating cavity includes: during the formation of the metal gate structure in the corresponding second transistor process, the second metal gate structure is synchronously formed in the second accommodating cavity; in the metal gate structures of the transistors respectively prepared by the first transistor process and the second transistor process, the materials of the metal gates are different.

[0019] Different from the prior art, in the technical solution of the present application, at least one first metal gate structure and a metal structure are respectively formed on the substrate, the first metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure, and the metal structure is arranged in affixed manner with the first metal gate structure, so that the insulating layer on the first metal gate structure is sandwiched between the metal gate of the first metal gate structure and the metal structure, and the metal gate of the first metal gate structure and the metal structure are used as a stack of relative plates to form a capacitor. Based on the above manner, since the insulating layer in the metal gate structure is usually thin and has the characteristics of a high dielectric constant, therefore, by making the first metal gate structure and the metal structure in affixed manner so that the insulating layer is sandwiched between the two metal structures of the metal gate and the metal structure, the insulating layer can have a stronger ability to store charge with a smaller volume, thereby making the capacitor formed by the metal gate and the metal structure as relative plates and the sandwiched insulating layer have a higher capacitance value while being smaller as a whole, thereby reducing the capacitor volume in the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1is a schematic cross-sectional structure diagram of an embodiment of a semiconductor device of the present application;

[0022] Figure 2 It is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor device of the present application;

[0023] Figure 3 It is a schematic top view of a process state of an embodiment of a semiconductor device of the present application;

[0024] Figure 4 It is one of the cross-sectional schematic diagrams of the process state of an embodiment of the semiconductor device of the present application;

[0025] Figure 5 This is a second schematic cross-sectional view of a process state of an embodiment of the semiconductor device of the present application;

[0026] Figure 6 This is a third cross-sectional schematic diagram of a process state of an embodiment of the semiconductor device of the present application;

[0027] Figure 7 This is a fourth cross-sectional schematic diagram of a process state of an embodiment of the semiconductor device of the present application;

[0028] Figure 8 FIG5 is a fifth schematic cross-sectional diagram of a process state of an embodiment of a semiconductor device of the present application;

[0029] Fig. 9 This is the sixth schematic cross-sectional diagram of a process state of an embodiment of the semiconductor device of the present application;

[0030] Fig.10 This is the seventh schematic cross-sectional diagram of the process state of an embodiment of the semiconductor device of the present application.

[0031] Figure numerals: substrate 11, first metal gate structure 12, first metal gate 121, first insulating layer 122, first spacer 123, metal structure 13, second metal gate 131, second insulating layer 132, second spacer 133, gate sidewall 14, contact window metal 15, polysilicon layer 16, hard mask plate 17, photoresist layer 18. DETAILED DESCRIPTION

[0032] The present application is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present application, but are not intended to limit the scope of the present application. Similarly, the following examples are only some embodiments of the present application rather than all embodiments, and all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0033] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "install", "set", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or connected through an intermediate medium. For ordinary technicians in this field, the above-mentioned specific meanings belonging to this application can be connected according to specific circumstances.

[0035] In the prior art, in the manufacturing process of semiconductor structures, for example, in a planar MOS structure, the capacitor is usually a planar structure MOSCAP (metal-oxide-semiconductor capacitor) or Varactor (variable capacitor), and MOSCAP and Varactor usually occupy a larger area of ​​the AA (active area) structure.

[0036] The defect of the prior art is that since MOSCAP and Varactor usually occupy a larger area of ​​the AA structure, the capacitor needs to occupy a lot of area in the semiconductor structure, which easily makes the semiconductor structure need to occupy more space, and then easily increases the cost of the semiconductor structure or causes other negative effects. In summary, the capacitor in the existing semiconductor structure is relatively large.

[0037] For example, at the existing 2XLG semiconductor process technology node, the capacitor structure needs to occupy a large area on a single chip, which easily makes the single chip larger and increases the difficulty and cost of manufacturing all subsequent electronic products built based on the chip.

[0038] In the technical solution of the present application, a PMOS-like metal gate structure or an NMOS-like metal gate structure is adopted and arranged in conjunction with the corresponding metal structure, so that the metal gate in the PMOS-like metal gate structure or the NMOS-like metal gate structure, the insulating layer in the PMOS-like metal gate structure or the NMOS-like metal gate structure, and the metal structure are arranged in sequence, and the metal gate and the metal structure are separated by the insulating layer, so that the metal gate and the metal structure are used as relative plates to form a capacitor. In the capacitor formed in this way, since the insulating layer in the metal gate structure is usually a thin film deposited on the side wall of the metal gate, the volume of the film is small, and the film needs to have good insulation properties, which also makes it usually need to have a higher dielectric constant. Therefore, the insulating layer in the metal gate structure is used as the middle layer of a thinner and smaller capacitor, and the metal gate and the metal structure in the metal gate structure are used as relative plates on both sides of the middle layer, a capacitor with a smaller body but a higher capacitance value can be constructed, thereby reducing the capacitor volume in the semiconductor structure.

[0039] In addition, by reducing the size of the capacitor and increasing the capacitance density per unit area, the total area or volume of the chip made with the capacitor can be reduced, thereby reducing the cost of the chip and achieving other beneficial effects that can be achieved by reducing the total area or volume of the chip, which will not be elaborated here.

[0040] This application first proposes a semiconductor device, see Figure 1 , Figure 1 is a schematic cross-sectional structure diagram of an embodiment of the semiconductor device of the present application, such as Figure 1 As shown, the semiconductor device includes a substrate 11 , at least one first metal gate structure 12 and a metal structure 13 .

[0041] The first metal gate structure 12 is disposed on the substrate 11 , and the first metal gate structure 12 is a PMOS-like metal gate structure or an NMOS-like metal gate structure.

[0042] Among them, Figure 1 As shown, a substrate 11 may be constructed first. The substrate 11 may specifically be a part of an active area (AA) in a semiconductor substrate, or the top of a shallow trench isolation (STI), or other area in a semiconductor device that can be used to form a capacitor, which is not limited here.

[0043] An area for forming a capacitor can be divided on the substrate 11, recorded as the capacitor area, and a gate sidewall 14 is formed in the capacitor area. The gate sidewall 14 is located on the boundary of the capacitor area, and the area surrounded by the gate sidewall 14 is the capacitor area.

[0044] By depositing corresponding materials in the capacitor region and performing corresponding processing, a corresponding metal gate structure or metal structure can be constructed.

[0045] In one example, if Figure 1 As shown, at least one first metal gate structure 12 can be formed in the capacitor region. In this figure, only one first metal gate structure 12 is drawn for simplified representation. In other examples, 2, 5, 10, or other numbers of first metal gate structures 12 can also be seen in the cross-sectional structural schematic diagram of the semiconductor device, which is not limited here. Similarly, the number of metal structures 13 in the cross-sectional structural schematic diagram of the semiconductor device is the same as the first metal gate structure 12, which is not limited here.

[0046] The first metal gate structure 12 may specifically refer to a PMOS-like metal gate structure or an NMOS-like metal gate structure, which is not limited herein.

[0047] The PMOS-like metal gate structure is the same as the PMOS metal gate in the transistor structure, and is usually composed of an insulating layer wrapping the other surfaces of the P-type metal gate except the top surface. The difference between the PMOS-like metal gate structure and the transistor structure is that the PMOS-like metal gate structure does not include the parts of the transistor structure except the PMOS metal gate, such as the source and drain parts. Similarly, the NMOS-like metal gate structure is the same as the NMOS metal gate in the transistor structure, and is usually composed of an insulating layer wrapping the other surfaces of the N-type metal gate except the top surface. The difference between the NMOS-like metal gate structure and the transistor structure is that the NMOS-like metal gate structure does not include the parts of the transistor structure except the NMOS metal gate, such as the source and drain parts.

[0048] The metal structure 13 is disposed on the substrate 11 .

[0049] The metal structure 13 may be a metal structure with conductive capability or a metal gate structure, which is not limited here.

[0050] The first metal gate structure 12 is arranged in close contact with the metal structure 13, and the insulating layer of the first metal gate structure 12 is sandwiched between the metal gate of the first metal gate structure 12 and the metal structure 13. The metal gate of the first metal gate structure 12 and the metal structure 13 serve as a pair of opposite plates to form a capacitor.

[0051] As can be seen from the above description, the first metal gate structure 12 is a PMOS-like metal gate structure or an NMOS-like metal gate structure, that is, the first metal gate structure 12 is different from the transistor structure, so the first metal gate structure 12 can be arranged in contact with the metal structure 13 .

[0052] like Figure 1As shown, the metal gate of the first metal gate structure 12 can be recorded as the first metal gate 121, and the insulating layer of the first metal gate structure 12 can be recorded as the first insulating layer 122. Through the bonding arrangement, the first insulating layer 122 can be sandwiched between the first metal gate 121 and the metal structure 13. Since the first metal gate 121 and the metal structure 13 are both conductive materials, and the first insulating layer 122 separates the first metal gate 121 and the metal structure 13, the first metal gate 121 and the metal structure 13 can be made to form a capacitor as relative plates.

[0053] In addition, since the insulating layer in the first metal gate structure 12 is usually a thin film deposited on the side wall of the metal gate, the film has a small volume but a generally high dielectric constant, for example, it can be a high-K dielectric layer, so that the capacitor can have a smaller volume while having a better charge storage capacity.

[0054] In addition, since the first metal gate structure 12 is a PMOS-like metal gate structure or an NMOS-like metal gate structure, that is, the first metal gate structure 12 is the same as the PMOS metal gate or NMOS metal gate portion in the transistor structure, and the process required for its manufacturing process is also the same. Therefore, when a transistor structure is formed on a semiconductor substrate for forming a capacitor or other semiconductor substrate, the first metal gate structure 12 in the capacitor region can be formed simultaneously during the process of forming the PMOS metal gate or NMOS metal gate portion of the transistor structure. A single chip usually also includes a transistor structure and a capacitor structure. Based on this method, the formation efficiency of the capacitor can be effectively improved, and even the formation efficiency of the chip where the capacitor is located can be improved.

[0055] Different from the prior art, in the technical solution of the present application, at least one first metal gate structure and a metal structure are respectively formed on the substrate, the first metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure, and the metal structure is arranged in affixed manner with the first metal gate structure, so that the insulating layer on the first metal gate structure is sandwiched between the metal gate of the first metal gate structure and the metal structure, and the metal gate of the first metal gate structure and the metal structure are used as a stack of relative plates to form a capacitor. Based on the above manner, since the insulating layer in the metal gate structure is usually thin and has the characteristics of a high dielectric constant, therefore, by making the first metal gate structure and the metal structure in affixed manner so that the insulating layer is sandwiched between the two metal structures of the metal gate and the metal structure, the insulating layer can have a stronger ability to store charge with a smaller volume, thereby making the capacitor formed by the metal gate and the metal structure as relative plates and the sandwiched insulating layer have a higher capacitance value while being smaller as a whole, thereby reducing the capacitor volume in the semiconductor structure.

[0056] In one embodiment, if Figure 1 As shown, the metal structure 13 is a second metal gate structure.

[0057] The insulating layer of the first metal gate structure 12 and the insulating layer of the second metal gate structure are both sandwiched between the metal gate of the first metal gate structure 12 and the metal gate of the second metal gate structure.

[0058] The metal gate of the first metal gate structure 12 and the metal gate of the second metal gate structure serve as a pair of opposite plates to form a capacitor.

[0059] Specifically, the metal gate of the second metal gate structure may be referred to as the second metal gate 131 , and the insulating layer of the second metal gate structure may be referred to as the second insulating layer 132 .

[0060] The second metal gate structure may specifically refer to a PMOS-like metal gate structure or an NMOS-like metal gate structure, which is not limited here.

[0061] By bonding the first metal gate structure 12 and the metal structure 13, the first insulating layer 122 and the second insulating layer 132 can be sandwiched between the first metal gate 121 and the second metal gate 131. Since the first metal gate 121 and the second metal gate 131 are both conductive materials, and the first insulating layer 122 and the second insulating layer 132 jointly separate the first metal gate 121 and the second metal gate 131, the first metal gate 121 and the second metal gate 131 can be made to form a capacitor as relative plates.

[0062] Based on the above method, since the metal structure 13 is a second metal gate structure, and the second metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure, that is, the second metal gate structure is the same as the PMOS metal gate or NMOS metal gate part in the transistor structure, and the process required for its manufacturing process is also the same, so similarly to the first metal gate structure 12, when a transistor structure is formed on a semiconductor substrate used to form a capacitor or other semiconductor substrate, in the process of forming the PMOS metal gate or NMOS metal gate part of the transistor structure, the metal structure 13 in the capacitor area is formed synchronously, and a single chip usually also includes a transistor structure and a capacitor structure. Based on this method, the first metal gate structure 12 and the metal structure 13 in the semiconductor device can be synchronously constructed with the metal gate in the transistor structure, which can further effectively improve the formation efficiency of the capacitor, and even further improve the formation efficiency of the chip where the capacitor is located.

[0063] Alternatively, if Figure 1 As shown, the first metal gate structure 12 is a PMOS-like metal gate structure, and the second metal gate structure is an NMOS-like metal gate structure, or the first metal gate structure 12 is an NMOS-like metal gate structure, and the second metal gate structure is a PMOS-like metal gate structure.

[0064] Specifically, since the first metal gate structure 12 and the second metal gate structure in the semiconductor device need to be formed separately, that is, after the first metal gate structure 12 is formed, the first metal gate structure 12 needs to be bonded to form the second metal gate structure, so as to achieve a bonding arrangement of the two and form a smaller capacitor, the first metal gate structure 12 and the second metal gate structure require at least two metal gate formation steps to complete the construction.

[0065] Under the above premise, the first metal gate structure 12 and the second metal gate structure can be configured as different types of metal gate structures respectively, that is, the first metal gate structure 12 can be configured as one of a PMOS-like metal gate structure and an NMOS-like metal gate structure, and the second metal gate structure can be configured as the other of a PMOS-like metal gate structure and an NMOS-like metal gate structure.

[0066] Since transistors with PMOS metal gates, transistors with NMOS metal gates, and capacitors usually need to be formed on an entire semiconductor substrate or on a single chip, by configuring the capacitor in the above manner, when forming one of the transistor structures of the PMOS metal gate transistor and the NMOS metal gate transistor, in the process of forming the PMOS metal gate or NMOS metal gate portion of the transistor structure, the first metal gate structure 12 can be formed simultaneously, and when forming the other of the transistor structures of the PMOS metal gate transistor and the NMOS metal gate transistor, in the process of forming the PMOS metal gate or NMOS metal gate portion of the transistor structure, the second metal gate structure can be formed simultaneously. Based on the above manner, the construction of the capacitor can be completed while the PMOS metal gate transistor and the NMOS metal gate transistor are constructed, thereby further improving the formation efficiency of the capacitor.

[0067] In one embodiment, if Figure 1 As shown, the substrate 11 is a part of an active region in a semiconductor substrate, or the substrate 11 is a top portion of a shallow trench isolation structure.

[0068] Specifically, in one example, the substrate 11 can be part of the active area in the semiconductor substrate, and the above-mentioned capacitor can be directly constructed on the active area of ​​the semiconductor substrate. Since the capacitor has a small volume and a high capacitance density, it only occupies a smaller active area to complete the formation of the required capacitor.

[0069] In another example, the substrate 11 may be the top of a shallow trench isolation structure, wherein the shallow trench isolation structure may specifically be a structure formed by digging a groove on the substrate 11 and depositing oxide or other insulating materials on the groove, which will not be described in detail here.

[0070] Since the area at the top of the shallow trench isolation structure is relatively small, while the transistor or capacitor in the prior art requires a relatively large area to be formed, the prior art does not form a capacitor on the top of the shallow trench isolation structure, while the semiconductor device proposed in the present application is a capacitor with a relatively small volume. Therefore, the semiconductor device proposed in the present application can be formed on the top of the shallow trench isolation structure. By constructing a relatively small capacitor formed by sandwiching an insulating layer between a metal gate and a metal structure 13 on the top of the shallow trench isolation structure, it is possible to effectively utilize the top position of the shallow trench isolation structure that is usually idle, while achieving the formation of a capacitor with better performance. While ensuring better capacitor performance, it improves space utilization and reduces costs.

[0071] In one embodiment, the insulating layer is a high-K dielectric layer, which is disposed between the bottom of the metal gate and the substrate 11 and covers the sidewalls of the metal gate.

[0072] Specifically, the insulating layer of the first metal gate structure 12 can be a high-k dielectric layer, where the high-k dielectric is a dielectric having a dielectric constant greater than 3.9. In addition, when the metal structure 13 is the second metal gate structure described in the previous embodiment, the insulating layer of the second metal gate structure can also be a high-k dielectric layer.

[0073] The high-K dielectric layer separates the substrate 11 from the metal gate, and the high-K dielectric layer covers all surfaces of the metal gate except the top surface.

[0074] Based on the above method, a higher charge storage capability can be provided through the high-K dielectric layer to form a capacitor with better performance.

[0075] Alternatively, if Figure 1 As shown, the first metal gate structure 12 further has a spacer layer, which is located between the insulating layer and the substrate 11 and covers the insulating layer on the sidewall of the metal gate.

[0076] Specifically, the spacer layer of the first metal gate structure 12 may be referred to as a first spacer layer 123 . The first spacer layer 123 is located between the first insulating layer 122 and the substrate 11 described in the above embodiment and covers the insulating layer on the sidewall of the metal gate.

[0077] When the metal structure 13 is a second metal gate structure, the second metal gate structure may also have a spacer layer, which may be referred to as a second spacer layer 133 . The second spacer layer 133 is located between the second insulating layer 132 and the substrate 11 described in the above embodiment.

[0078] The first spacer layer 123 and the second spacer layer 133 can specifically be an oxide layer, or other types of spacer layers, which are not limited here. By setting the spacer layer, a relatively smooth contact surface for depositing and forming an insulating layer can be constructed based on the spacer layer, thereby making the formation of the insulating layer more reliable and efficient.

[0079] In one embodiment, each first metal gate structure 12 is led out through a corresponding contact metal 15 and connected to the first interconnection.

[0080] The metal structure 13 is led out through a corresponding contact metal 15 and connected to the second interconnection.

[0081] The first interconnection member serves as one plate of the capacitor, and the second interconnection member serves as the other plate of the capacitor, thereby forming a capacitor.

[0082] Specifically, the contact window metal may specifically refer to a CT (contact window) layer.

[0083] After the first metal gate structure 12 and the metal structure 13 are formed, contact window metal 15 can be deposited on the top of each other, and the contact window metal 15 corresponding to the first metal gate structure 12 is connected to each other through a first interconnection, and the contact window metal 15 corresponding to the metal structure 13 is connected to each other through a second interconnection. Subsequently, the first interconnection and the second interconnection are used as relative plates to form a capacitor for use.

[0084] In one embodiment, if Figure 1 As shown, the semiconductor device further includes a gate spacer 14 .

[0085] The gate spacer 14 is disposed on the substrate 11 . The gate spacer 14 encloses a capacitor region on the substrate 11 . The first metal gate structure 12 and the metal structure 13 are both located in the capacitor region.

[0086] Specifically, a region for forming a capacitor can be divided on the substrate 11, recorded as the capacitor region, and a gate sidewall 14 is formed in the capacitor region. The gate sidewall 14 is located on the boundary of the capacitor region, and the region enclosed by the gate sidewall 14 is the capacitor region.

[0087] By depositing corresponding materials in the capacitor region and performing corresponding processing, a corresponding metal gate structure or metal structure can be constructed.

[0088] Based on the above method, it is possible to form the first metal gate structure 12 and the metal structure 13 in a close relationship within the region enclosed by the gate sidewall 14, and avoid material overflow during the formation process, thereby improving the reliability of the semiconductor device formation process.

[0089] The present application also proposes a process method for manufacturing a semiconductor device, see Figure 2 , Figure 2 1 is a flow chart of an embodiment of a method for manufacturing a semiconductor device of the present application, wherein the method for manufacturing a semiconductor device is used to prepare a semiconductor device as described in any of the above embodiments, such as Figure 2 As shown, the process method of the semiconductor device includes:

[0090] Step S11 : providing a substrate 11 , and forming a capacitor region surrounded by a gate spacer 14 on the substrate 11 .

[0091] Step S12: forming a polysilicon layer in the capacitor region.

[0092] Step S13: etching the polysilicon layer to form at least one first accommodating cavity.

[0093] Step S14: forming a first metal gate structure 12 in the first accommodation cavity, wherein the first metal gate structure 12 is a PMOS-like metal gate structure or an NMOS-like metal gate structure.

[0094] Step S15: etching the remaining polysilicon layer in the capacitor region at least adjacent to the first metal gate structure 12 to form a second accommodation cavity.

[0095] Step S16: forming a metal structure 13 in the second accommodation cavity, so that the first metal gate structure 12 is arranged in close contact with the metal structure 13, and the insulating layer of the first metal gate structure 12 is sandwiched between the metal gate of the first metal gate structure 12 and the metal structure 13. The metal gate of the first metal gate structure 12 and the metal structure 13 serve as a pair of opposite plates to form a capacitor.

[0096] Specifically, see Figures 3 to 10 , Figure 3 is a top view schematically showing a process state of an embodiment of a semiconductor device of the present application, Figure 4 is one of the cross-sectional schematic diagrams of the process state of an embodiment of the semiconductor device of the present application, Figure 5 FIG. 2 is a second schematic cross-sectional diagram of a process state of an embodiment of a semiconductor device of the present application. Figure 6 FIG3 is a third schematic cross-sectional diagram of a process state of an embodiment of a semiconductor device of the present application. Figure 7 FIG4 is a fourth cross-sectional diagram of a process state of an embodiment of a semiconductor device of the present application. Figure 8 FIG5 is a fifth schematic cross-sectional diagram of a process state of an embodiment of a semiconductor device of the present application. Fig. 9 FIG6 is a sixth schematic cross-sectional diagram of a process state of an embodiment of a semiconductor device of the present application. Fig.10 This is the seventh schematic cross-sectional diagram of the process state of an embodiment of the semiconductor device of the present application.

[0097] like Figure 3 The figure shows a top view schematic diagram of the final formation of the semiconductor device. First, a gate sidewall 14 is formed on the substrate 11. A plurality of first metal gate structures 12 can be constructed in the capacitor region enclosed by the gate sidewall 14, and a metal structure 13 can be constructed in the portion of the capacitor region other than the first metal gate structure 12, so that the metal structure 13 can be respectively arranged in contact with each first metal gate structure 12, so that the corresponding insulating layer is sandwiched between the metal gate of the first metal gate structure 12 and the metal structure 13, and the contact window metal 15 deposited on the first metal gate structure 12 can be respectively connected to the first interconnect A, and the contact window metal 15 deposited on the metal structure 13 can be respectively connected to the second interconnect B, and a capacitor can be formed by using the first interconnect A and the second interconnect B as relative plates.

[0098] It should be noted that in the subsequent Figures 4 to 10 and Figure 1 In order to simplify the representation, only one first metal gate structure 12 and a corresponding metal structure 13 are drawn in the cross-sectional schematic diagram. However, in other examples, in the capacitor region surrounded by the gate sidewall 14, the capacitor region 12 and the corresponding metal structure 13 are actually Figure 3 As shown, a plurality of first metal gate structures 12 are provided, but this is not limited here.

[0099] In step S11, Figure 4 As shown, a gate spacer 14 may be formed on the substrate 11 , and the area enclosed by the gate spacer 14 is a capacitor area, which is used to form a subsequent first metal gate structure 12 and a metal structure 13 .

[0100] In step S12, Figure 5 As shown, a polysilicon layer 16 is filled in the capacitor region to be processed by etching.

[0101] In step S13, Figure 6 As shown, a hard mask plate 17 (HARDMASK, HM) and a photoresist layer 18 can be sequentially covered on the polysilicon layer 16, and subsequently etching processing can be performed based on the HM process. For example, the distribution position of the first metal gate structure 12 can be firstly engraved on the photoresist layer 18 to form a photoresist groove, and then the photoresist groove is dry-etched to form a hard mask groove, and finally the hard mask groove is dry-etched to form the polysilicon layer 16 to form a first accommodating cavity for forming the first metal gate structure 12.

[0102] In step S14, Figure 7 As shown, the spacer layer (first spacer layer 123) of the first metal gate structure 12, the insulating layer (first insulating layer 122) of the first metal gate structure 12, and the metal gate (first metal gate 121) of the first metal gate structure 12 can be deposited in sequence in the first accommodating cavity. Figure 8 As shown, a chemical-mechanical polishing (CMP) process is performed on the material at and above the layer where the hard mask plate 17 is located to form a first metal gate structure 12 .

[0103] In step S15, Fig. 9 As shown, the remaining polysilicon layer 16 adjacent to at least the first metal gate structure 12 in the capacitor region can be dry-etched to form a second accommodating cavity for forming the metal structure 13. Wherein, when executing step S15, in one example, only the remaining polysilicon layer 16 adjacent to the first metal gate structure 12 in the capacitor region can be etched, that is, the remaining part of the polysilicon layer in the capacitor region is etched to form the second accommodating cavity, and the part of the polysilicon layer is the polysilicon layer adjacent to the first metal gate structure 12 in the remaining entire polysilicon layer, and in another example, the entire polysilicon layer 16 remaining in the capacitor region can also be etched to form the second accommodating cavity, which can be determined according to needs and is not limited here. Based on this method, the metal structure 13 subsequently formed in the second accommodating cavity can be arranged adjacent to the first metal gate structure 12 that has been formed.

[0104] In step S16, if Fig.10 As shown, a metal structure 13 can be formed in the second accommodating cavity to form a capacitor with the metal gate of the first metal gate structure 12 and the metal structure 13 as relative plates. In one example, when the metal structure 13 is the second metal gate structure described in the above embodiment, a spacer layer (second spacer layer 133) of the second metal gate structure, an insulating layer (second insulating layer 132) of the second metal gate structure, and a metal gate (second metal gate 131) of the second metal gate structure can be deposited in sequence in the second accommodating cavity, and then the material above the first metal gate structure 12 is subjected to chemical grinding and polishing to form the second metal gate structure.

[0105] After completing the above steps S11-S16, step S17 may be further performed. Figure 1 As shown, corresponding contact window metals 15 are deposited on the first metal gate structure 12 and the metal structure 13, respectively, so that the contact window metals 15 corresponding to the first metal gate structure 12 are interconnected through a first interconnection, and the contact window metals 15 corresponding to the metal structure 13 are interconnected through a second interconnection. Subsequently, the first interconnection and the second interconnection are used as relative plates to form a capacitor for use.

[0106] Different from the prior art, in the technical solution of the present application, at least one first metal gate structure and a metal structure are respectively formed on the substrate, the first metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure, and the metal structure is arranged in affixed manner with the first metal gate structure, so that the insulating layer on the first metal gate structure is sandwiched between the metal gate of the first metal gate structure and the metal structure, and the metal gate of the first metal gate structure and the metal structure are used as a stack of relative plates to form a capacitor. Based on the above manner, since the insulating layer in the metal gate structure is usually thin and has the characteristics of a high dielectric constant, therefore, by making the first metal gate structure and the metal structure in affixed manner so that the insulating layer is sandwiched between the two metal structures of the metal gate and the metal structure, the insulating layer can have a stronger ability to store charge with a smaller volume, thereby making the capacitor formed by the metal gate and the metal structure as relative plates and the sandwiched insulating layer have a higher capacitance value while being smaller as a whole, thereby reducing the capacitor volume in the semiconductor structure.

[0107] In one embodiment, step S14 may specifically include:

[0108] During the formation of the metal gate structure in the corresponding transistor manufacturing process, the first metal gate structure 12 is simultaneously formed in the first accommodating cavity.

[0109] Specifically, since transistors and capacitors usually need to be constructed simultaneously on a semiconductor substrate or a single chip, and the corresponding metal gate structure also needs to be constructed in the transistor process, when the metal gate structure of the transistor is formed, the first metal gate structure 12 of the capacitor can be formed in the first accommodating cavity of the capacitor area simultaneously, thereby improving the formation efficiency of the entire semiconductor device.

[0110] In one embodiment, step S16 may specifically include:

[0111] A second metal gate structure is formed in the second accommodation cavity, so that the insulating layer of the first metal gate structure 12 and the insulating layer of the second metal gate structure are both sandwiched between the metal gate of the first metal gate structure 12 and the metal gate of the second metal gate structure. The metal gate of the first metal gate structure 12 and the metal gate of the second metal gate structure serve as a pair of opposite plates to form a capacitor.

[0112] Specifically, since the metal structure 13 is a second metal gate structure, and the second metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure, that is, the second metal gate structure is the same as the PMOS metal gate or NMOS metal gate portion in the transistor structure, and the process required for its manufacturing process is also the same, so similarly to the first metal gate structure 12, when a transistor structure is formed on a semiconductor substrate for forming a capacitor or other semiconductor substrate, in the process of forming the PMOS metal gate or NMOS metal gate portion of the transistor structure, the metal structure 13 in the capacitor region is formed simultaneously, and a single chip usually also includes a transistor structure and a capacitor structure. Based on this method, the first metal gate structure 12 and the metal structure 13 in the semiconductor device can be synchronously constructed with the metal gate in the transistor structure, which can further effectively improve the formation efficiency of the capacitor, and even further improve the formation efficiency of the chip where the capacitor is located.

[0113] Optionally, forming a second metal gate structure in the second accommodating cavity may specifically include:

[0114] During the formation of the metal gate structure in the corresponding transistor manufacturing process, a second metal gate structure is simultaneously formed in the second accommodating cavity.

[0115] Specifically, since transistors and capacitors usually need to be constructed simultaneously on a semiconductor substrate or a single chip, and the corresponding metal gate structure also needs to be constructed in the transistor process, when the metal gate structure of the transistor is formed, the first metal gate structure 12 of the capacitor can be formed in the first accommodating cavity of the capacitor area simultaneously, thereby improving the formation efficiency of the entire semiconductor device.

[0116] Optionally, forming the first metal gate structure 12 in the first accommodating cavity may specifically include:

[0117] During the formation of the metal gate structure in the corresponding first transistor manufacturing process, the first metal gate structure 12 is simultaneously formed in the first accommodating cavity.

[0118] A second metal gate structure is formed in the second accommodating cavity, comprising:

[0119] During the formation of the metal gate structure in the corresponding second transistor manufacturing process, a second metal gate structure is simultaneously formed in the second accommodating cavity.

[0120] In which, in the metal gate structures of the transistors respectively prepared by the first transistor process and the second transistor process, the materials of the metal gates are different.

[0121] Specifically, the metal gate of the metal gate structure of the transistor prepared by the first transistor process can be one of the PMOS metal gate and the NMOS metal gate, and the metal gate of the metal gate structure of the transistor prepared by the second transistor process can be the other of the PMOS metal gate and the NMOS metal gate.

[0122] Since transistors with PMOS metal gates, transistors with NMOS metal gates, and capacitors usually need to be formed on an entire semiconductor substrate or a single chip, by configuring the capacitor in the above manner, when forming one of the transistor structures of the PMOS metal gate transistor and the NMOS metal gate transistor, in the process of forming the PMOS metal gate or NMOS metal gate portion of the transistor structure, the first metal gate structure 12 can be formed simultaneously, and when forming the other of the transistor structures of the PMOS metal gate transistor and the NMOS metal gate transistor, in the process of forming the PMOS metal gate or NMOS metal gate portion of the transistor structure, the second metal gate structure can be formed simultaneously. Based on the above manner, the construction of the capacitor can be completed while the PMOS metal gate transistor and the NMOS metal gate transistor are constructed, thereby further improving the formation efficiency of the semiconductor device.

[0123] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other.

[0124] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0125] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0126] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (which can be a personal computer, server, network device or other system that can fetch instructions from the instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0127] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; at least one first metal gate structure, wherein the first metal gate structure is disposed on the substrate, and the first metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure; a metal structure, the metal structure being disposed on the substrate; The first metal gate structure is arranged in close contact with the metal structure, and the insulating layer of the first metal gate structure is sandwiched between the metal gate of the first metal gate structure and the metal structure; The metal gate of the first metal gate structure and the metal structure serve as a pair of opposite plates to form a capacitor.

2. The semiconductor device according to claim 1, wherein: The metal structure is a second metal gate structure; The insulating layer of the first metal gate structure and the insulating layer of the second metal gate structure are both sandwiched between the metal gate of the first metal gate structure and the metal gate of the second metal gate structure; The metal gate of the first metal gate structure and the metal gate of the second metal gate structure form a capacitor as a pair of opposite plates.

3. The semiconductor device according to claim 2, characterized in that The first metal gate structure is a PMOS-like metal gate structure, and the second metal gate structure is an NMOS-like metal gate structure. Alternatively, the first metal gate structure is an NMOS-like metal gate structure, and the second metal gate structure is a PMOS-like metal gate structure.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The substrate is a part of an active region in a semiconductor substrate, or the substrate is a top of a shallow trench isolation structure.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that: The insulating layer is a high-K dielectric layer, which is arranged between the bottom of the metal gate and the substrate and covers the sidewall of the metal gate.

6. The semiconductor device according to claim 5, characterized in that The first metal gate structure further has a spacer layer, which is located between the insulating layer and the substrate and covers the insulating layer on the side wall of the metal gate.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that: Each of the first metal gate structures is led out through a corresponding contact window metal and connected to a first interconnection member; The metal structure is led out through a corresponding contact window metal and connected to a second interconnection member; The first interconnection member serves as one plate of the capacitor, and the second interconnection member serves as the other plate of the capacitor, thereby forming the capacitor.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device further comprises: A gate sidewall is disposed on the substrate, the gate sidewall encloses a capacitor region on the substrate, and the first metal gate structure and the metal structure are both located in the capacitor region.

9. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, and forming a capacitor region surrounded by gate sidewalls on the substrate; forming a polysilicon layer in the capacitor region; Etching the polysilicon layer to form at least one first accommodating cavity; forming a first metal gate structure in the first accommodating cavity; wherein the first metal gate structure is a PMOS-like metal gate structure or an NMOS-like metal gate structure; Etching the remaining polysilicon layer in the capacitor region that is at least adjacent to the first metal gate structure to form a second accommodating cavity; A metal structure is formed in the second accommodating cavity so that the first metal gate structure is arranged in close contact with the metal structure, and the insulating layer of the first metal gate structure is sandwiched between the metal gate of the first metal gate structure and the metal structure; wherein the metal gate of the first metal gate structure and the metal structure serve as a pair of relative plates to form a capacitor.

10. The process method according to claim 9, characterized in that: The etching process is performed on the remaining polysilicon layer in the capacitor region at least adjacent to the first metal gate structure to form a second accommodating cavity, comprising: The entire polysilicon layer remaining in the capacitor region is etched to form a second accommodating cavity.

11. The process method according to claim 9 or 10, characterized in that: The forming of a first metal gate structure in the first accommodating cavity comprises: During the formation of the metal gate structure in the corresponding transistor manufacturing process, a first metal gate structure is simultaneously formed in the first accommodating cavity.

12. The process method according to claim 9 or 10, characterized in that: The forming of the metal structure in the second accommodating cavity comprises: A second metal gate structure is formed in the second accommodating cavity so that the insulating layer of the first metal gate structure and the insulating layer of the second metal gate structure are both sandwiched between the metal gate of the first metal gate structure and the metal gate of the second metal gate structure; wherein the metal gate of the first metal gate structure and the metal gate of the second metal gate structure serve as a pair of relative plates to form a capacitor.

13. The process method according to claim 12, characterized in that: The forming of a second metal gate structure in the second accommodating cavity comprises: During the formation of the metal gate structure in the corresponding transistor manufacturing process, a second metal gate structure is simultaneously formed in the second accommodation cavity.

14. The process method according to claim 12, characterized in that: The forming of a first metal gate structure in the first accommodating cavity comprises: During the formation of the metal gate structure in the corresponding first transistor process, a first metal gate structure is simultaneously formed in the first accommodation cavity; The forming of a second metal gate structure in the second accommodating cavity comprises: During the formation of the metal gate structure in the corresponding second transistor manufacturing process, a second metal gate structure is simultaneously formed in the second accommodation cavity; Among them, in the metal gate structures of the transistors respectively prepared by the first transistor process and the second transistor process, the materials of the metal gates are different.

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