Pixel array, display panel and manufacturing method of display panel

Abstract

The invention discloses a pixel array, a display panel and a manufacturing method of the display panel. The pixel array comprises a glass substrate and a plurality of pixel circuits arranged in an array mode, each pixel circuit comprises a first transistor and a second transistor, the second transistor is arranged on the first transistor, and the pixel array comprises a first polycrystalline silicon layer, a second polycrystalline silicon layer and a third amorphous silicon layer. The first polysilicon layer is disposed on the glass substrate and is configured as a channel region of the first transistor. The second polycrystalline silicon layer is arranged on the first transistor, the third amorphous silicon layer covers the second polycrystalline silicon layer, and the second polycrystalline silicon layer and the third amorphous silicon layer are configured to be a double-channel region of the second transistor. The third amorphous silicon layer covers the second polycrystalline silicon layer to form the double-channel region of the second transistor, so that the forbidden bandwidth of the double-channel region of the second transistor can be increased, the leakage current of the second transistor is further reduced, and the display effect of the display panel is prevented from being influenced by the leakage current.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and more specifically, to a pixel array, a display panel, and a method for manufacturing the display panel. Background Art

[0002] In the related art, a unit display area of ​​a high pixel density (PPI) display panel needs to include many pixel circuits, and a double-layer TFT structure may be used to set the transistors of the pixel circuits so that the pixel circuits are integrated.

[0003] However, in a double-layer TFT structure, the higher the layer, the more difficult it is to ensure uneven process and temperature conditions. The uneven process and temperature conditions of the TFTs set in the upper layer are difficult to ensure, resulting in a larger leakage current of the TFTs set in the upper layer, which in turn causes distortion of the image displayed by the display panel, affecting the display effect of the display panel. Summary of the invention

[0004] Embodiments of the present application provide a pixel array, a display panel, and a method for manufacturing the display panel.

[0005] The pixel array provided in the embodiment of the present application includes a glass substrate and a plurality of pixel circuits arranged in an array, each pixel circuit includes a first transistor and a second transistor, and the second transistor is arranged on the first transistor. The pixel array includes a first polysilicon layer, a second polysilicon layer and a third amorphous silicon layer. Among them, the first polysilicon layer is arranged on the glass substrate and is configured as a channel region of the first transistor. The second polysilicon layer is arranged on the first transistor, and the third amorphous silicon layer covers the second polysilicon layer, and the second polysilicon layer and the third amorphous silicon layer are configured as a double channel region of the second transistor.

[0006] The display panel provided in the embodiment of the present application can adopt a double-layer TFT structure to set the transistor of the pixel circuit, so that the pixel circuit is integrated and set, so that more pixel circuits can be set in a unit display area to meet the design requirements of a high pixel density (PPI) display panel. In the double-layer TFT structure, the third amorphous silicon layer covers the double channel region of the second transistor set on the second polysilicon layer to form an upper layer, which can increase the bandgap width of the double channel region of the second transistor, thereby reducing the leakage current of the second transistor, so that the display panel can meet the design requirements of a high pixel density (PPI) display panel while avoiding the display effect of the display panel being affected by the leakage current.

[0007] Excimer laser annealing (ELA) is used to make the polysilicon layer of the TFT in the pixel circuit. Specifically, when making the polysilicon layer, the laser used by ELA scans each pixel circuit along the row and column directions of the pixel array on a large-area glass substrate, and makes the polysilicon layer of the TFT to form the working channel region of the TFT. In excimer laser annealing (ELA), the laser beam can scan along the row direction of the pixel array or along the column direction, and the interval distance of each scan is the predetermined process parameter ELAPitch. The decimal part of the ratio of L and W to ELAPitch is 0.3 to 0.7, which can effectively reduce the vertical stripe Mura phenomenon caused by ELA and improve the display effect of the display panel.

[0008] In some embodiments, each of the pixel circuits includes a first switch, a second switch, a data voltage source, and a light-emitting device, the first transistor is configured as the first switch, the second transistor is configured as the second switch, the data voltage source is connected to the first switch and the light-emitting device, and the second switch is connected between the control electrode of the first switch and the light-emitting device.

[0009] In some embodiments, each of the pixel circuits includes a third switch and a reset voltage source, the second transistor is configured as the third switch, and the reset voltage source is connected to a control electrode of the first switch through the third switch.

[0010] In some embodiments, the pixel array may include a first dielectric layer, a second dielectric layer, a first metal layer, a second metal layer, and a third metal layer. The first dielectric layer is disposed in the same layer as the first polysilicon layer. The first metal layer is disposed on the second dielectric layer and is configured as a gate of the first transistor. The second dielectric layer is disposed in the same layer as the first metal layer. The second metal layer and the third metal layer. The second metal layer and the third metal layer are disposed on the second dielectric layer and are configured as a source and a drain of the first transistor.

[0011] In some embodiments, the pixel array may include a first planarization layer, a second planarization layer, a third planarization layer, a third dielectric layer, a fourth metal layer, a fifth metal layer, a sixth metal layer, a seventh metal layer, and an eighth metal layer. The first planarization layer is disposed in the same layer as the second metal layer and the third metal layer. The third dielectric layer is disposed on the first planarization layer and is disposed in the same layer as the second polysilicon layer. The fourth metal layer is disposed on the third dielectric layer and is configured as a gate of the second transistor. The second planarization layer is disposed in the same layer as the fourth metal layer. The fifth metal layer and the sixth metal layer are disposed on the second planarization layer and are configured as a source and a drain of the second transistor. The third planarization layer is disposed in the same layer as the fifth metal layer and the sixth metal layer. The seventh metal layer and the eighth metal layer are disposed on the third planarization layer and are configured as a source and a drain of the second transistor.

[0012] In some embodiments, the first polysilicon layer and the second polysilicon layer are manufactured by scanning the pixel array with a laser beam of an excimer laser annealing process, and the predetermined spacing distance of the laser beam scanning is a predetermined process parameter. Each of the pixel circuits is substantially rectangular, and the fractional part of the ratio of the length of each pixel circuit to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7, and the fractional part of the ratio of the width of each pixel circuit to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7.

[0013] In some embodiments, the pixel array includes a plurality of pixel groups arranged in an array, each of the pixel groups includes a plurality of the pixel circuits, each pixel group is substantially square, and the decimal part of the ratio of the side length of each pixel group to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7.

[0014] In some embodiments, the pixel group includes 2m+1 pixel circuits, and the side length of the pixel group is (2m+1)*n*ELA Pitch+0.5*(2m+1)*ELA Pitch, wherein m and n are positive integers, and ELA Pitch is the predetermined process parameter.

[0015] In some embodiments, the pixel group includes 2 pixel circuits, and the side length of the pixel group is 2n*ELA Pitch+(0.6-0.7)*ELA Pitch, or the side length of the pixel group is 2n*ELA Pitch+(1.3-1.4)*ELAPitch, wherein n is an integer greater than or equal to 0, and ELA Pitch is the predetermined process parameter.

[0016] The display panel provided in the embodiment of the present application includes the pixel array of the above embodiment.

[0017] In some embodiments, the pixel array is located in a display area of ​​a display panel, and the display panel includes a driving circuit located in a non-display area, wherein the driving circuit is configured to drive the pixel circuit to operate, and the driving circuit includes a third transistor, and the third transistor is arranged in the same layer as the first transistor.

[0018] The manufacturing method of the display panel provided in the embodiment of the present application includes: forming a first polysilicon layer on a glass substrate; using the first polysilicon layer as a channel region to form the first transistor; forming a second polysilicon layer and a third amorphous silicon layer in sequence on the first transistor, the third amorphous silicon layer covering the second polysilicon layer; using the second polysilicon layer and the third amorphous silicon layer as a double channel region to form the second transistor.

[0019] In some embodiments, the forming of the first polysilicon layer on the glass substrate includes: forming a first amorphous silicon layer on the glass substrate; scanning the first amorphous silicon layer with a laser beam of a laser annealing process to obtain the first polysilicon layer. The forming of the second polysilicon layer and the third amorphous silicon layer on the first transistor in sequence includes: forming a second amorphous silicon layer and a third amorphous silicon layer on the first transistor in sequence; scanning the second amorphous silicon layer with a laser beam of a laser annealing process to form a second polysilicon layer, and retaining the third amorphous silicon layer.

[0020] In some embodiments, the predetermined interval distance of the laser beam scanning is a predetermined process parameter, and the method includes: designing the size of the pixel array according to the predetermined process parameter, the pixel array includes a plurality of pixels arranged in an array, each of the pixels is substantially rectangular, the decimal part of the ratio of the length of each pixel circuit to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7, and the decimal part of the ratio of the width of each pixel circuit to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7.

[0021] The embodiment of the present application provides a pixel array, a display panel and a method for manufacturing a display panel. The pixel array includes a glass substrate and a plurality of pixel circuits arranged in an array, each pixel circuit includes a first transistor and a second transistor, and the second transistor is arranged on the first transistor. The pixel array includes a first polysilicon layer, a second polysilicon layer and a third amorphous silicon layer. Among them, the first polysilicon layer is arranged on the glass substrate and is configured as a channel region of the first transistor. The second polysilicon layer is arranged on the first transistor, and the third amorphous silicon layer covers the second polysilicon layer, and the second polysilicon layer and the third amorphous silicon layer are configured as a double channel region of the second transistor.

[0022] The display panel provided in the embodiment of the present application can adopt a double-layer TFT structure to set the transistor of the pixel circuit, so that the pixel circuit is integrated and set, so that more pixel circuits can be set in a unit display area to meet the design requirements of a high pixel density (PPI) display panel. In the double-layer TFT structure, the third amorphous silicon layer covers the double channel region of the second transistor set on the second polysilicon layer to form an upper layer, which can increase the bandgap width of the double channel region of the second transistor, thereby reducing the leakage current of the second transistor, so that the display panel can meet the design requirements of a high pixel density (PPI) display panel while avoiding the display effect of the display panel being affected by the leakage current.

[0023] Excimer laser annealing (ELA) is used to make the polysilicon layer of the TFT in the pixel circuit. Specifically, when making the polysilicon layer, the laser used by ELA scans each pixel circuit along the row and column directions of the pixel array on a large-area glass substrate, and makes the polysilicon layer of the TFT to form the working channel area of ​​the TFT. In excimer laser annealing (ELA), the laser beam can scan along the row direction of the pixel array or along the column direction, and the interval distance of each scan is the predetermined process parameter ELA Pitch. The decimal part of the ratio of L and W to ELA Pitch is 0.3 to 0.7, which can effectively reduce the vertical stripe Mura phenomenon caused by ELA and improve the display effect of the display panel.

[0024] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0026] Figure 1 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present application;

[0027] Figure 2 is a circuit diagram of a pixel circuit according to an embodiment of the present application;

[0028] Figure 3 is a signal timing diagram of a pixel circuit in some embodiments of the present application;

[0029] Figure 4 It is a schematic diagram of the pixel array arrangement of certain embodiments of the present application.

[0030] Description of main component symbols:

[0031] Pixel array 100, glass substrate 10, pixel circuit 20, first transistor 21, second transistor 22, first polysilicon layer 211, first metal layer 212, second metal layer 213, third metal layer 214, second polysilicon layer 221, third amorphous silicon layer 222, fourth metal layer 223, fifth metal layer 224, sixth metal layer 225, seventh metal layer 226, eighth metal layer 227, first dielectric layer 31, second dielectric layer 32, third dielectric layer 33, first planarization layer 41, second planarization layer 42, third planarization layer 43, polyimide layer 51, barrier layer 52, buffer layer 53, pixel group 60, display panel 1000, display area 1100, non-display area 1200, third transistor 1210. DETAILED DESCRIPTION

[0032] The embodiments of the present application are described in detail below, and the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0033] All directional indications (such as up, down, left, right, front, and back) in the embodiments of the present application are only used to explain the relative positional relationship, movement, etc. between the components under a certain posture (as shown in the drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0034] In the related art, a unit display area of ​​a high pixel density (PPI) display panel needs to include many pixel circuits, and a double-layer TFT structure may be used to set the transistors of the pixel circuits so that the pixel circuits are integrated.

[0035] However, in a double-layer TFT structure, the higher the layer, the more difficult it is to ensure uneven process and temperature conditions. The uneven process and temperature conditions of the TFTs set in the upper layer are difficult to ensure, resulting in a larger leakage current of the TFTs set in the upper layer, which in turn causes distortion of the image displayed by the display panel, affecting the display effect of the display panel.

[0036] Embodiments of the present application provide a pixel array 100 , a display panel 1000 , and a method for manufacturing the display panel 1000 .

[0037] The display panel 1000 provided in the embodiment of the present application may include the pixel array 100 provided in the embodiment of the present application. The pixel array 100 and the display panel 1000 provided in the embodiment of the present application may be manufactured by the manufacturing method provided in the embodiment of the present application.

[0038] Reference Figure 1 The pixel array 100 provided in the embodiment of the present application includes a glass substrate 10 and a plurality of pixel circuits 20 arranged in an array, each pixel circuit 20 includes a first transistor 21 and a second transistor 22, and the second transistor 22 is arranged on the first transistor 21. The pixel array 100 includes a first polysilicon layer 211, a second polysilicon layer 221 and a third amorphous silicon layer 222. Among them, the first polysilicon layer 211 is arranged on the glass substrate 10 and is configured as a channel region of the first transistor 21. The second polysilicon layer 221 is arranged on the first transistor 21, and the third amorphous silicon layer 222 covers the second polysilicon layer 221. The second polysilicon layer 221 and the third amorphous silicon layer 222 are configured as a double channel region of the second transistor 22.

[0039] In certain embodiments, the manufacturing method provided in the embodiments of the present application includes: forming a first polysilicon layer 211 on a glass substrate 10; using the first polysilicon layer 211 as a channel region to form a first transistor 21; sequentially forming a second polysilicon layer 221 and a third amorphous silicon layer 222 on the first transistor 21, and the third amorphous silicon layer 222 covers the second polysilicon layer 221; using the second polysilicon layer 221 and the third amorphous silicon layer 222 as a double channel region to form a second transistor 22.

[0040] Specifically, the display panel 1000 provided in the embodiment of the present application adopts a double-layer TFT structure to set the transistors of the pixel circuit 20 so that the pixel circuit 20 is integrated. In the double-layer TFT structure, the first transistor 21 can be a transistor set in the lower layer, and the second transistor 22 can be a transistor set in the upper layer.

[0041] The channel region of the first transistor 21 may be formed by the first polysilicon layer 211. Since the first polysilicon layer 211 has a higher carrier mobility (i.e., the speed at which electrons or holes move in the material), the response speed of the first transistor 21 is improved. In the first polysilicon layer 211, due to the presence of grains, current can pass more easily, which enhances the conductivity of the first transistor 21 and supports a display panel 1000 with a higher pixel density (PPI).

[0042] The channel region of the second transistor 22 is a double channel region, which may be composed of a second polysilicon layer 221 and a third amorphous silicon layer 222. The third amorphous silicon layer 222 is disposed on the second polysilicon layer 221, and the bandgap width of the double channel region of the second transistor 22 may be adjusted to reduce the thermally induced leakage effect of the double channel region and the leakage current of the second transistor 22.

[0043] In the second polysilicon layer 221, polysilicon is composed of many small grains, each of which has an orderly lattice structure, and electrons move relatively freely in these regions. The band gap of polysilicon is close to that of single crystal silicon, which is about 1.12 eV.

[0044] In the third amorphous silicon layer 222, the atomic arrangement of amorphous silicon is disordered. This disorder causes the movement of electrons to be more restricted and there are more localized states. These localized states make the bandgap width of amorphous silicon slightly larger than that of polycrystalline silicon, generally about 1.5 eV. Due to its disordered structure, amorphous silicon produces a large number of electron traps (trap states). These traps can limit the free movement of electrons, inhibit conductivity, and thus increase the bandgap width of the channel region.

[0045] The third amorphous silicon layer 222 is covered on the second polysilicon layer 221, and the disordered structure of amorphous silicon forms a layer of coverage on the surface, which changes the overall energy band structure. Due to the localized state and large bandgap width of amorphous silicon, the covering layer can increase the effective bandgap width of the overall channel region. Due to the large bandgap width of the second transistor 22, electrons are not easily thermally excited to cross the bandgap under high temperature conditions, which helps to suppress the thermally induced leakage effect. The large bandgap width of the second transistor 22 can also effectively reduce the thermal excitation of electrons and reduce the leakage current of the second transistor 22.

[0046] In this way, the display panel 1000 provided in the embodiment of the present application can adopt a double-layer TFT structure to set the transistors of the pixel circuit 20, so that the pixel circuit 20 is integrated, so that more pixel circuits 20 can be set in the unit display area 1100 to meet the design requirements of the high pixel density (PPI) display panel 1000.

[0047] In the double-layer TFT structure, the third amorphous silicon layer 222 covers the double channel region of the second transistor 22 formed on the second polysilicon layer 221, which can increase the bandgap width of the double channel region of the second transistor 22, thereby reducing the leakage current of the second transistor 22, so that the display panel 1000 can meet the design requirements of the high pixel density (PPI) display panel 1000 while avoiding the display effect of the display panel 1000 being affected by the leakage current.

[0048] Reference Figure 2 In some embodiments, each pixel circuit 20 includes a first switch, a second switch, a data voltage source, and a light-emitting device, the first transistor 21 is configured as the first switch, and the second transistor 22 is configured as the second switch. The data voltage source is connected to the first switch and the light-emitting device, and the second switch is connected between the control electrode of the first switch and the light-emitting device.

[0049] Specifically, the first switch may be switch T1, the second switch may be switch T2, the data voltage source may be voltage source Vdata, and the light emitting device may be light emitting diode D1. Voltage source Vdata may be coupled to the anode of light emitting diode D1 through switch T1, and switch T2 may be connected between the control electrode of switch T1 and the anode of light emitting diode D1.

[0050] The first transistor 21 can be used as the switch T1 in the pixel circuit 20, and the second transistor 22 can be used as the switch T2 in the pixel circuit 20. The switch T2 can be connected to the control electrode of the switch T1 at the node N1. The leakage current of the switch T1 is reduced, so that the potential of the node N1 can be prevented from being pulled down during the display phase of the pixel circuit 20, and the current flowing through the light-emitting diode D1 can be prevented from changing due to the change in the control electrode voltage of the switch T1, thereby preventing the pixel circuit 20 from displaying poorly.

[0051] Reference Figure 2 In some embodiments, each pixel circuit 20 includes a third switch and a reset voltage source, the second transistor 22 is configured as the third switch, and the reset voltage source is connected to the control electrode of the first switch through the third switch.

[0052] Specifically, the third switch may be a switch T3 , and the reset voltage source may be a voltage source Vinit. The voltage source Vinit may provide the switch T3 to be connected to the node N1 .

[0053] The second transistor 22 can be used as the switch T3 in the pixel circuit 20. The leakage current of the switch T3 is reduced, which can prevent the potential of the node N1 from being pulled down during the display stage of the pixel circuit 20, and prevent the control electrode voltage of the switch T3 from changing, causing the current flowing through the light-emitting diode D1 to change, thereby avoiding poor display of the pixel circuit 20.

[0054] In some embodiments, the pixel circuit 20 may further include a switch T4, a switch T5, a switch T6, a switch T7, a capacitor Cst, a voltage source VDD, and a voltage source VSS. The voltage source Vdata may be connected to the first pole of the switch T1 through the switch T4, and the voltage source VDD may be connected to the first pole of the switch T1 through the switch T5. The switch T6 may be connected between the second pole of the switch T1 and the anode of the light emitting diode D1, the switch T7 may be connected between the voltage source Vinit and the anode of the light emitting diode D1, and the cathode of the light emitting diode D1 may be connected to the voltage source VSS. The capacitor Cst is connected between the node N1 and the voltage source VDD.

[0055] The control electrodes of the switch T2 and the switch T4 may be connected to the Gate terminal, the control electrodes of the switch T3 and the switch T7 may be connected to the Re terminal, and the control electrodes of the switch T5 and the switch T6 may be connected to the EM terminal.

[0056] The voltage provided by the voltage source Vdata, the timing diagram of the voltage access to the Gate terminal, Re terminal and EM terminal can be referred to Figure 3 .

[0057] During period t1 , the pixel circuit 20 is in a reset stage, the switch T3 and the switch T7 are closed, the switch T2 , the switch T4 , the switch T5 and the switch T6 are opened, and the reset voltage provided by the voltage source Vinit is written into the node N1 .

[0058] During period t2 , the pixel circuit 20 is in the data voltage writing stage, switches T5 and T6 are closed, switches T2 , T3 , T4 and T7 are opened, and the data voltage provided by the voltage source Vdata is written into the first electrode of switch T1 .

[0059] During period t3, the pixel circuit 20 is in the display stage, switches T5 and T6 are closed, switches T2, T3, T4 and T7 are opened, and the voltage provided by the voltage source VDD is connected to the anode of the light-emitting diode D1 through switches T5, T1 and T6.

[0060] Reference Figure 1 , the pixel array 100 may include a polyimide layer 51, a barrier layer 52 and a buffer layer 53. The polyimide layer 51 may cover the glass substrate 10, and the polyimide layer 51 may be configured as a single-layer polyimide film layer or a double-layer polyimide film layer. The barrier layer 52 may cover the polyimide layer 51, and the buffer layer 53 may cover the barrier layer 52.

[0061] Reference Figure 1 In some embodiments, the pixel array 100 may include a first dielectric layer 31, a second dielectric layer 32, a first metal layer 212, a second metal layer 213, and a third metal layer 214. The first dielectric layer 31 is disposed in the same layer as the first polysilicon layer 211. The first metal layer 212 is disposed on the second dielectric layer 32 and is configured as a gate of the first transistor 21. The second dielectric layer 32 is disposed in the same layer as the first metal layer 212. The second metal layer 213 and the third metal layer 214. The second metal layer 213 and the third metal layer 214 are disposed on the second dielectric layer 32 and are configured as a source and a drain of the first transistor 21.

[0062] Specifically, the first dielectric layer 31 may cover the buffer layer 53 . The material of the first dielectric layer 31 may be silicon dioxide. The thickness of the first dielectric layer 31 is greater than that of the first polysilicon layer 211 .

[0063] The first metal layer 212 may cover the first dielectric layer 31 and serve as the gate of the first transistor 21. The orthographic projection of the first metal layer 212 on the first polysilicon layer 211 may be located in the middle of the first polysilicon layer 211. The second dielectric layer 32 may cover the first dielectric layer 31. The thickness of the first dielectric layer 31 is greater than that of the first metal layer 212. The second dielectric layer 32 may be an inter-layer dielectric (ILD) layer.

[0064] The second metal layer 213 and the third metal layer 214 may cover the second dielectric layer 32 and serve as the source and drain of the first transistor 21 , respectively. The orthographic projections of the second metal layer 213 and the third metal layer 214 on the first polysilicon layer 211 may be located on both sides of the first polysilicon layer 211 .

[0065] In some embodiments, the pixel array 100 may include a first planarization layer 41, a second planarization layer 42, a third planarization layer 43, a third dielectric layer 33, a fourth metal layer 223, a fifth metal layer 224, a sixth metal layer 225, a seventh metal layer 226, and an eighth metal layer 227. The first planarization layer 41 is disposed in the same layer as the second metal layer 213 and the third metal layer 214. The third dielectric layer 33 is disposed on the first planarization layer 41 and is disposed in the same layer as the second polysilicon layer 221. The fourth metal layer 223 is disposed on the third dielectric layer 33 and is configured as a gate of the second transistor 22. The second planarization layer 42 is disposed in the same layer as the fourth metal layer 223. The fifth metal layer 224 and the sixth metal layer 225 are disposed on the second planarization layer 42 and are configured as a source and a drain of the second transistor 22. The third planarization layer 43 is disposed in the same layer as the fifth metal layer 224 and the sixth metal layer 225. The seventh metal layer 226 and the eighth metal layer 227 are disposed on the third planarization layer 43 and configured as a source and a drain of the second transistor 22 .

[0066] Specifically, the first planarization layer 41 may cover the second dielectric layer 32 , and the thickness of the first planarization layer 41 may be greater than that of the second metal layer 213 and the third metal layer 214 .

[0067] The second polysilicon layer 221 may cover the first planarization layer 41 , and the third dielectric layer 33 may cover the buffer layer 53 . The material of the third dielectric layer 33 may be silicon dioxide, and the thickness of the third dielectric layer 33 is greater than the sum of the thicknesses of the second polysilicon layer 221 and the third amorphous silicon layer 222 .

[0068] The fourth metal layer 223 may cover the third dielectric layer 33 and serve as the gate of the second transistor 22, and the orthographic projection of the fourth metal layer 223 on the second polysilicon layer 221 may be located in the middle of the second polysilicon layer 221. The second planarization layer 42 may cover the third dielectric layer 33, and the thickness of the second planarization layer 42 is greater than that of the fourth metal layer 223.

[0069] The fifth metal layer 224 and the sixth metal layer 225 may cover the second planarization layer 42 and serve as the source and drain of the second transistor 22, respectively. The orthographic projections of the fifth metal layer 224 and the sixth metal layer 225 on the second polysilicon layer 221 may be located on both sides of the second polysilicon layer 221. The third planarization layer 43 may cover the second planarization layer 42, and the thickness of the third planarization layer 43 may be greater than that of the fifth metal layer 224 and the sixth metal layer 225.

[0070] The third planarization layer 43 may be a film layer located in the display area 1100. The seventh metal layer 226 and the eighth metal layer 227 may cover the third planarization layer 43 and serve as the source and drain of the second transistor 22, respectively. The orthographic projections of the seventh metal layer 226 and the eighth metal layer 227 on the second polysilicon layer 221 may be located on both sides of the second polysilicon layer 221.

[0071] Reference Figure 1 In some embodiments, the pixel array 100 is located in the display area 1100 of the display panel 1000, and the display panel 1000 includes a driving circuit located in the non-display area 1200, and the driving circuit is configured to drive the pixel circuit 20 to operate. The driving circuit includes a third transistor 1210, and the third transistor 1210 is arranged in the same layer as the first transistor 21.

[0072] Specifically, the driving circuit may be a gate driving circuit of the pixel circuit 20, and Figure 2 The third transistor 1210 may be a transistor in the gate driving circuit, and the third transistor 1210 may be disposed in the same layer as the first transistor 21 .

[0073] The display panel 1000 can use excimer laser annealing (ELA) to manufacture the polysilicon layer of the TFT in the pixel circuit 20. Specifically, when manufacturing the polysilicon layer, the laser used by ELA scans each pixel circuit 20 along the row and column direction of the pixel array 100 on the large-area glass substrate 10, and manufactures the polysilicon layer of the TFT to form a working channel region of the TFT.

[0074] In some embodiments, forming the first polysilicon layer 211 on the glass substrate 10 includes: forming a first amorphous silicon layer on the glass substrate 10 ; and scanning the first amorphous silicon layer with a laser beam of a laser annealing process to obtain the first polysilicon layer 211 .

[0075] In some embodiments, a second crystalline polysilicon layer and a third amorphous silicon layer 222 are sequentially formed on the first transistor 21, including: sequentially forming a second amorphous silicon layer and a third amorphous silicon layer 222 on the first transistor 21; scanning the second amorphous silicon layer with a laser beam using a laser annealing process to form the second polysilicon layer 221, and retaining the third amorphous silicon layer 222.

[0076] In the manufacturing process of the second-layer transistor in the manufacturing method of the embodiment of the present application, during the second laser beam scanning using the laser annealing process, the second amorphous silicon layer is scanned to form a second polycrystalline silicon layer 221, and the third amorphous silicon layer 222 is retained, so that the third amorphous silicon layer 222 covers the second polycrystalline silicon layer 221.

[0077] In the related art, in excimer laser annealing (ELA), due to the limitation of laser stability, there are differences in the working channel regions of TFTs in different pixel circuits 20, which leads to differences in electrical parameters of the pixel TFTs such as threshold voltage and mobility, which in turn translates into current differences and brightness differences in the display panel 1000, affecting the display effect, that is, ELA causes the vertical stripe Mura phenomenon.

[0078] The size of the pixel array 100 of the embodiment of the present application is compatible with the ELA process parameters, and can reduce or eliminate the ELA vertical Mura.

[0079] Reference Figure 4 In some embodiments, the first polysilicon layer 211 and the second polysilicon layer 221 are manufactured by laser beam scanning pixel array 100 by excimer laser annealing process, and the predetermined interval distance of laser beam scanning is the predetermined process parameter. Each pixel circuit 20 is substantially rectangular, and the decimal part of the ratio of the length of each pixel circuit 20 to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7, and the decimal part of the ratio of the width of each pixel circuit 20 to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7.

[0080] In some embodiments, the manufacturing method of the display panel 1000 includes: designing the size of the pixel array 100 according to predetermined process parameters, the pixel array 100 includes a plurality of pixels arranged in an array, each pixel is basically rectangular, the decimal part of the ratio of the length of each pixel circuit 20 to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7, and the decimal part of the ratio of the width of each pixel circuit 20 to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7.

[0081] Specifically, Figure 4 For example, the pixel circuit 20 is arranged substantially in a rectangular shape, the length of the pixel circuit 20 can be set to L, and the width can be set to W.

[0082] In excimer laser annealing (ELA), the laser beam can scan along the row direction or the column direction of the pixel array 100, and the interval distance of each scan is a predetermined process parameter ELA Pitch. The decimal part of the ratio of L and W to ELA Pitch is 0.3 to 0.7, which can effectively reduce the vertical stripe Mura phenomenon caused by ELA and improve the display effect of the display panel 1000.

[0083] In some embodiments, the pixel array 100 includes a plurality of pixel groups 60 arranged in an array, and each pixel group 60 includes a plurality of pixel circuits 20. Each pixel group 60 is substantially square, and the decimal part of the ratio of the side length of each pixel group 60 to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7.

[0084] Specifically, Figure 4 For example, a plurality of pixel circuits 20 arranged in an array can form a pixel group 60, and the pixel group 60 is in a square shape. For example, when L=3W, three pixel circuits 20 arranged along the row direction can form a pixel group 60, and the side length of the pixel group 60 is L. When L=2W, two pixel circuits 20 arranged along the row direction can form a pixel group 60, and the side length of the pixel group 60 is L.

[0085] In some embodiments, the pixel group 60 includes 2m+1 pixel circuits 20, and the side length of the pixel group 60 is (2m+1)*n*ELAPitch+0.5*(2m+1)*ELA Pitch, where m and n are positive integers, and ELA Pitch is a predetermined process parameter.

[0086] Specifically, m can be determined according to the number of pixel circuits 20 in the pixel group 60 , m can be any integer greater than 0, and n can be any integer greater than or equal to 0.

[0087] by Figure 4 For example, when L=3W, three pixel circuits 20 arranged along the row direction (for example, arranged in the order of R / G / B) can form a pixel group 60, and the side length of the pixel group 60 is L. At this time, 2m+1=3.

[0088] When 2m+1=3, the ELA Pich is 7 microns, and the side length of the pixel group 60 is 3*n*7+0.5*3*7. When n=3, the optimal pixel Pitch of 73.5 microns can be selected. As n changes (n ranges from any integer: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11...), as shown in Table 1 below, the optimal pixel design size appears every 21 microns.

[0089] In Table 1, Sub Pixel_pitch L is the side length of the pixel group 60 , which is substantially consistent with the length of the pixel circuit 20 , and Sub Pixel Pitch W is the width of the pixel circuit 20 .

[0090] It is a preferred embodiment when the decimal parts of Sub Pixel Pitch L / ELA Pitch and Sub Pixel Pitch W / ELA Pitch are both 0.3 to 0.7.

[0091] The most preferred implementation is: ELA Pitch = 7 microns, the side length of the pixel group 60 is 73.5 microns (Margin range: 72.5 to 75.5 microns), the length of the pixel circuit 20 is 74 microns (Margin range: 72.5 to 75.5 microns), and the width of the pixel circuit 20 is 24.5 microns (Margin range: 24.17 to 25.17).

[0092] ELA Pitch = 7 microns, side length of pixel group 60: 94.5 microns (Margin range: 93.5-96.5 microns), length of pixel circuit 20: 95 microns (Margin range: 93.5-96.5 microns), width of pixel circuit 20: 31.5 microns (Margin range: 31.17-32.17).

[0093] ELA Pitch = 7 microns, side length of pixel group 60: 115.5 microns (Margin range: 114.5-117.5 microns), length of pixel circuit 20: 115.5 microns (Margin range: 114.5-117.5 microns), width of pixel circuit 20: 38.5 microns (Margin range: 38.17-39.17).

[0094] Table 1

[0095]

[0096]

[0097]

[0098]

[0099]

[0100]

[0101]

[0102]

[0103]

[0104] In some embodiments, the pixel group 60 includes two pixel circuits 20, and the side length of the pixel group 60 is 2n*ELAPitch+(0.6-0.7)*ELA Pitch, or the side length of the pixel group 60 is 2m*n*ELA Pitch+(1.3-1.4)*ELAPitch, wherein n is an integer greater than or equal to 0, and ELA Pitch is a predetermined process parameter.

[0105] When L=2W, two pixel circuits 20 arranged along the row direction (eg, a GGRB pixel circuit 20 and an RGBG pixel circuit 20 arranged in sequence) can form a pixel group 60, and the side length of the pixel group 60 is L. At this time, 2m=2.

[0106] The ELA Pich is 6 microns, and the side length of the pixel group 60 can be 2*n*6+(1.3-1.4)*6, or 2*n*6+(0.6-0.7)*6, where n can be any integer in the value range.

[0107] The pixel size designed based on the above embodiment can effectively reduce the vertical stripe Mura phenomenon caused by ELA and improve the display effect of the display panel 1000.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0109] In addition, the term "connection" should be understood in a broad sense, for example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0110] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0111] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A pixel array, characterized in that: The pixel array includes a glass substrate and a plurality of pixel circuits arranged in an array, each of the pixel circuits includes a first transistor and a second transistor, the second transistor is arranged on the first transistor, and the pixel array includes: a first polysilicon layer, disposed on the glass substrate and configured as a channel region of the first transistor; A second polysilicon layer, disposed on the first transistor; A third amorphous silicon layer is formed, wherein the third amorphous silicon layer covers the second polysilicon layer, and the second polysilicon layer and the third amorphous silicon layer are configured to form a double channel region of the second transistor.

2. The pixel array according to claim 1, characterized in that: Each of the pixel circuits includes a first switch, a second switch, a data voltage source, and a light emitting device, the first transistor is configured as the first switch, and the second transistor is configured as the second switch; The data voltage source is connected to the light emitting device through the first switch, and the second switch is connected between the control electrode of the first switch and the light emitting device.

3. The pixel array according to claim 2, characterized in that: Each of the pixel circuits includes a third switch and a reset voltage source, the second transistor is configured as the third switch, and the reset voltage source is connected to a control electrode of the first switch through the third switch.

4. The pixel array according to claim 1, characterized in that: The pixel array comprises: A first dielectric layer, disposed on the same layer as the first polysilicon layer; A first metal layer, disposed on the dielectric layer and configured as a gate of the first transistor; A second dielectric layer is provided on the same layer as the first metal layer; A second metal layer and a third metal layer, wherein the second metal layer and the third metal layer are disposed on the second dielectric layer and are configured as a source and a drain of the first transistor.

5. The pixel array according to claim 4, characterized in that: The pixel array comprises: A first planarization layer, disposed on the same layer as the second metal layer and the third metal layer; A third dielectric layer is disposed on the first planarization layer and is disposed on the same layer as the second polysilicon layer; a fourth metal layer, disposed on the third dielectric layer and configured as a gate of the second transistor; A second planarization layer is disposed on the same layer as the fourth metal layer; a fifth metal layer and a sixth metal layer, wherein the fifth metal layer and the sixth metal layer are disposed on the second planarization layer and are configured as a source and a drain of the second transistor; A third planarization layer, disposed on the same layer as the fifth metal layer and the sixth metal layer; A seventh metal layer and an eighth metal layer, wherein the seventh metal layer and the eighth metal layer are disposed on the third planarization layer and configured as a source and a drain of the second transistor.

6. The pixel array according to claim 1, characterized in that: The first polysilicon layer and the second polysilicon layer are manufactured by scanning the pixel array with a laser beam in an excimer laser annealing process, and a predetermined interval distance of the laser beam scanning is a predetermined process parameter; Each of the pixel circuits is substantially rectangular, the decimal part of the ratio of the length of each pixel circuit to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7, and the decimal part of the ratio of the width of each pixel circuit to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.

7.

7. The pixel array according to claim 6, characterized in that: The pixel array includes a plurality of pixel groups arranged in an array, and each of the pixel groups includes a plurality of the pixel circuits; Each pixel group is substantially square, and a decimal part of a ratio of a side length of each pixel group to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.

7.

8. The pixel array according to claim 7, characterized in that: The pixel group includes 2m+1 pixel circuits, and the side length of the pixel group is (2m+1)*n*ELAPitch+0.5*(2m+1)*ELAPitch, wherein m is a positive integer, n is an integer greater than or equal to 0, and ELA Pitch is the predetermined process parameter.

9. The pixel array according to claim 7, characterized in that: The pixel group includes 2 pixel circuits, and the side length of the pixel group is 2n*ELAPitch+(0.6-0.7)*ELAPitch, or the side length of the pixel group is 2n*ELAPitch+(1.3-1.4)*ELAPitch, wherein n is an integer greater than or equal to 0, and ELAPitch is the predetermined process parameter.

10. A display panel, characterized in that: The display panel comprises the pixel array according to any one of claims 1 to 9, and the pixel array is located in a display area of ​​the display panel.

11. The display panel according to claim 10, characterized in that: The display panel includes a driving circuit located in a non-display area, the driving circuit is configured to drive the pixel circuit to operate, and the driving circuit includes a third transistor, and the third transistor is arranged in the same layer as the first transistor.

12. A method for manufacturing a display panel, characterized in that: The display panel includes a pixel array, the pixel array includes a plurality of pixel circuits arranged in an array, each of the pixel circuits includes a first transistor and a second transistor, the second transistor is arranged on the first transistor, and the method includes: forming a first polysilicon layer on a glass substrate; Using the first polysilicon layer as a channel region, forming the first transistor; forming a second polysilicon layer and a third amorphous silicon layer in sequence on the first transistor, wherein the third amorphous silicon layer covers the second polysilicon layer; The second transistor is formed by using the second polysilicon layer and the third amorphous silicon layer as a double channel region.

13. The method for manufacturing a display panel according to claim 12, characterized in that: The step of forming a first polysilicon layer on a glass substrate comprises: forming a first amorphous silicon layer on the glass substrate; Scanning the first amorphous silicon layer with a laser beam of a laser annealing process to obtain the first polycrystalline silicon layer; The step of sequentially forming a second crystalline polysilicon layer and a third amorphous silicon layer on the first transistor comprises: sequentially forming a second amorphous silicon layer and a third amorphous silicon layer on the first transistor; The second amorphous silicon layer is scanned with a laser beam using a laser annealing process to form a second polycrystalline silicon layer, and the third amorphous silicon layer is retained.

14. The method for manufacturing a display panel according to claim 13, characterized in that: The predetermined interval distance of the laser beam scanning is a predetermined process parameter, and the method comprises: The size of the pixel array is designed according to the predetermined process parameters, the pixel array includes a plurality of pixels arranged in an array, each of the pixels is substantially rectangular, the decimal part of the ratio of the length of each pixel circuit to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7, and the decimal part of the ratio of the width of each pixel circuit to the predetermined process parameter is greater than or equal to 0.3 and less than or equal to 0.7.

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