Positive and negative asymmetric voltage-resistant PNP structure electrostatic protection device
By designing the electrostatic protection device of PNP structure, using the bipolar transistor and metal silicide barrier layer composed of P-type heavily doped region/N well/P-type heavily doped region, the problems of the demand for forward and reverse asymmetric voltage withstand voltage and low area utilization in the prior art are solved, and efficient electrostatic discharge protection and good reliability are achieved.
Patent Information
- Application Number
- CN202411564792.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-02-28
AI Technical Summary
Existing CMOS architecture devices cannot meet the demand for forward and reverse asymmetric voltage withstand voltages. The cross-dressing solution leads to low area utilization and may cause parasitic problems, affecting chip reliability.
A PNP structure electrostatic protection device with positive and negative asymmetric voltage withstand voltage is designed, including forming a bipolar transistor composed of a P-type heavily doped region/N well/P-type heavily doped region on a P-type substrate, achieving asymmetric voltage withstand voltage by adjusting the lateral spacing, and forming a metal silicide barrier layer on an active region without injection to avoid short circuits.
The asymmetric positive and negative withstand voltage protection of single-stage devices is realized, and the positive and negative trigger voltage is adjustable, avoiding parasitic problems caused by cross-dressing, and improving area utilization and chip reliability.
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Figure CN119545911A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage. Background Art
[0002] In integrated circuits, CMOS architecture, such as GDPMOS, is often used as low-voltage ESD (electrostatic discharge) protection (such as Figure 1 With the development of automotive microelectronics, more and more customers are demanding positive and negative voltages. Existing CMOS architecture devices cannot meet these requirements. Due to different application scenarios, the forward and reverse voltage requirements may also be asymmetric.
[0003] The existing technical solution is to reverse the GDPMOS to achieve positive and negative asymmetric withstand voltage (such as Figure 2 The disadvantage of this solution is its low area utilization. Furthermore, reverse transmission may cause parasitic problems, affecting chip reliability.
[0004] In order to solve the above problems, it is necessary to propose a new type of PNP structure electrostatic protection device with positive and negative asymmetric voltage resistance. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a PNP structure electrostatic protection device with positive and negative asymmetric voltage resistance, which is used to solve the problem in the prior art that GDPMOS is reversed to achieve positive and negative asymmetric voltage resistance, resulting in low area utilization, and the reverse connection may cause parasitic problems, affecting the reliability of the chip.
[0006] To achieve the above-mentioned and other related purposes, the present invention provides a PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage, comprising:
[0007] A bipolar transistor consisting of a P-type heavily doped region / N-well / P-type heavily doped region is formed on a P-type substrate; wherein,
[0008] The active areas of the emitter, collector and base are isolated by shallow trench isolation;
[0009] The base of the bipolar transistor is formed by the N-well;
[0010] A P-type lightly doped drain is formed in the P-type heavily doped region;
[0011] An N-type heavily doped region is inserted between the two P-type heavily doped regions in the same active region, and the three serve as collectors or emitters;
[0012] The N-type heavily doped region and the P-type heavily doped region are connected via a non-implanted active region, and the base of the bipolar transistor is connected through the N-type heavily doped region and then floated, so as to achieve bidirectional electrostatic discharge protection;
[0013] There is a lateral distance between the N-type doped region and the P-type heavily doped region, and asymmetric withstand voltage is achieved by adjusting the lateral distance.
[0014] Preferably, the MOS device is a non-low-voltage device, and the depth of the P-type lightly doped drain is greater than the depth of the P-type doped region.
[0015] Preferably, the MOS device is a low-voltage device, and the depth of the P-type lightly doped drain is smaller than the depth of the P-type doped region.
[0016] Preferably, the device further includes forming a metal silicide blocking layer on the non-injected active area in the metal silicide process to prevent the N-type heavily doped area and the P-type heavily doped area from being short-circuited due to metal silicide.
[0017] Preferably, the metal silicide barrier layer is located between the N-type heavily doped region and the P-type heavily doped region.
[0018] Preferably, the metal silicide barrier layer spans over the N-type heavily doped region.
[0019] Preferably, the metal silicide barrier layer includes at least one of silicon-rich oxide, SiO2, SiON and Si3N4.
[0020] Preferably, the device further comprises forming a polysilicon layer on the non-implanted active area in the metal silicide process to avoid short circuit between the N-type heavily doped area and the P-type heavily doped area due to metal silicide.
[0021] Preferably, the polysilicon layer is located between the N-type heavily doped region and the P-type heavily doped region, and the polysilicon layer is floating.
[0022] Preferably, the device is used for electrostatic discharge protection of devices with a voltage range of 1.8V to 9V.
[0023] Preferably, the two outer P-type heavily doped regions and the N-type heavily doped region in the middle serve as collectors, and the P-type heavily doped region in the collector is connected to a high level; the two middle P-type heavily doped regions and the N-type heavily doped region in the middle serve as emitters, and the emitters are connected to a low level.
[0024] Preferably, the two outer P-type heavily doped regions and the N-type heavily doped region in the middle serve as emitters, and the P-type heavily doped region in the collector is connected to a low level; the two middle P-type heavily doped regions and the N-type heavily doped region in the middle serve as emitters, and the emitters are connected to a high level.
[0025] As described above, the PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage of the present invention has the following beneficial effects:
[0026] The present invention realizes asymmetric positive and negative withstand voltage protection through a single-stage device; the positive and negative trigger voltages are adjustable, which can be achieved only by structural changes, without changing or adding other processes or injections; compared with ESD ion implantation, this patent does not need to add any process to adjust the trigger voltage, and there is no hysteresis effect, which does not increase the risk of latch-up; it has good compatibility and is suitable for both P-type lightly doped drain-enclosing P-type heavily doped region structure and P-type heavily doped region-enclosing P-type lightly doped drain structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 Shown is a schematic diagram of an electrostatic protection device in the prior art;
[0028] Figure 2 Shown is a schematic diagram of the prior art GDPMOS reverse series to achieve positive and negative asymmetric withstand voltage;
[0029] Figure 3 Shown is a schematic structural diagram of an electrostatic protection device according to a first embodiment of the present invention;
[0030] Figure 4 Shown is a schematic structural diagram of an electrostatic protection device according to a second embodiment of the present invention;
[0031] Figure 5 Shown is a schematic structural diagram of an electrostatic protection device according to a third embodiment of the present invention;
[0032] Figure 6 Shown is a schematic structural diagram of an electrostatic protection device according to a fourth embodiment of the present invention;
[0033] Figure 7 Shown is a schematic structural diagram of an electrostatic protection device according to a fifth embodiment of the present invention;
[0034] Figure 8 Shown is a schematic structural diagram of an electrostatic protection device according to a sixth embodiment of the present invention;
[0035] Figure 9 Shown is a schematic diagram of a PNP structure used for positive and negative voltage protection according to an embodiment of the present invention;
[0036] Figure 10 It shows another embodiment of the present invention, in which PNP is used as a schematic diagram of a positive and negative voltage protection structure. DETAILED DESCRIPTION
[0037] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0038] See also Figure 3 The present invention provides a PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage, comprising:
[0039] A bipolar transistor consisting of a P-type heavily doped region 102 / N-well 101 / P-type heavily doped region 102 is formed on a P-type substrate. Specifically, three P-type heavily doped regions 102 / N-well 101 / P-type heavily doped regions 102 are formed on the P-type substrate to form two bipolar transistors; wherein,
[0040] The active areas of the emitter, collector and base are isolated by shallow trench isolation 105;
[0041] The base of the bipolar transistor is formed by the N-well 101;
[0042] The emitter and collector are both composed of a P-type heavily doped region 102;
[0043] A P-type lightly doped drain 104 is formed in the P-type heavily doped region 102;
[0044] In some embodiments, the MOS device is a non-low voltage device, and the depth of the P-type lightly doped drain 104 is greater than the depth of the P-type doped region.
[0045] In some embodiments, the MOS device is a low-voltage device, and the depth of the P-type lightly doped drain 104 is less than the depth of the P-type doped region.
[0046] In other words, the electrostatic protection device of the present invention has good compatibility, and is suitable for both the structure of a P-type lightly doped drain 104 enclosing a P-type heavily doped region 102 and the structure of a P-type heavily doped region 102 enclosing a P-type lightly doped drain 104 .
[0047] An N-type heavily doped region 103 is inserted between the two P-type heavily doped regions 102 in the same active region, and the three serve as collectors or emitters;
[0048] The N-type heavily doped region 103 and the P-type heavily doped region 102 are connected via a non-implanted active region. The base of the bipolar transistor is connected through the N-type heavily doped region 103 and then floated to achieve bidirectional electrostatic discharge protection.
[0049] A lateral spacing is provided between the N-type doped region and the heavily P-type doped region 102. This spacing is adjusted to achieve asymmetric withstand voltage. For example, by adjusting the distance between the heavily N-type doped region 103 and the heavily P-type doped region 102 at both ends from 0.20 μm to 0.4 μm, the threshold voltage is significantly reduced compared to the existing structure (Normal).
[0050] The structure of the present invention offers adjustable positive and negative trigger voltages, achieved solely through structural changes without requiring additional processes or implants. Compared to ESD ion implantation, this patent eliminates the need for any additional processes to adjust the trigger voltage, eliminates hysteresis, and increases the risk of latch-up.
[0051] This structure uses the size of a single-stage GDPMOS to provide the positive and negative voltage protection capabilities with the same effect as two-stage GDPMOS reverse series operation, has a higher area cost-effectiveness, and avoids the parasitic problems caused by reverse series operation.
[0052] To achieve high-impedance active area resistors, high-impedance polysilicon resistors, and high-performance ESD devices, it is necessary to form high-impedance non-metallic silicide regions. These high-impedance regions are generally referred to as non-salicide regions, and devices without metal silicide are called non-salicide devices. To form non-salicide devices, it is necessary to take advantage of the fact that metal only reacts with polysilicon and active area silicon, and not with the dielectric layer. Before the salicide process, a dielectric layer is deposited over the non-salicide regions to prevent salicide formation in these areas. This technology for forming non-salicide devices is called self-aligned silicide barrier (SAB), also known as resistive protection oxide (RPO). Materials for SAB films include silicon-rich oxide (SRO), SiO2, SiON, and Si3N4. SRO films have a higher silicon content than conventional silicon oxide films. The preparation of SRO is similar to conventional silicon oxide and can be deposited using PECVD, using source gases such as SiH4, O2, and Ar. The ratio of SiH4 to O2 is higher than that used in conventional silicon oxide formation. SiH4 can be replaced with Si2H6 and TEOS (tetraethylsilane), or O2 with N2O or O3. The source gases for depositing SiON are SiH4, N2O, and Ar, while those for depositing Si3N4 are SiH4, N3H, and Ar.
[0053] In some embodiments, the device further includes forming a metal silicide barrier layer 106 on the non-implanted active area during the metal silicide process to prevent the N-type heavily doped region 103 and the P-type heavily doped region 102 from short-circuiting due to the metal silicide.
[0054] In some embodiments, the metal silicide barrier layer 106 is located between the N-type heavily doped region 103 and the P-type heavily doped region 102, forming a Figure 4 or Figure 7 The structure shown.
[0055] In some embodiments, the metal silicide barrier layer 106 extends across the N-type heavily doped region 103 to form a Figure 5 The structure shown.
[0056] In some embodiments, the metal silicide blocking layer 106 includes at least one of silicon-rich oxide, SiO 2 , SiON, and Si 3 N 4 .
[0057] In some embodiments, the device further includes forming a polysilicon layer 107 on the non-implanted active region during the metal silicide process to prevent the N-type heavily doped region 103 and the P-type heavily doped region 102 from being short-circuited due to the metal silicide.
[0058] In some embodiments, the polysilicon layer 107 is located between the N-type heavily doped region 103 and the P-type heavily doped region 102, and the polysilicon layer 107 is floating, forming a Figure 6 or Figure 8 The structure shown.
[0059] In some embodiments, the device is used for electrostatic discharge protection of 1.8V to 9V devices.
[0060] In some embodiments, see Figure 9 The two outer P-type heavily doped regions 102 and the N-type heavily doped region 103 in the middle serve as collectors, and the P-type heavily doped region 102 in the collector is connected to a high level; the two middle P-type heavily doped regions 102 and the N-type heavily doped region 103 in the middle serve as emitters, and the emitter is connected to a low level.
[0061] In some embodiments, see Figure 10 The two outer P-type heavily doped regions 102 and the middle N-type heavily doped region 103 serve as emitters, and the P-type heavily doped region 102 in the collector is connected to a low level; the two middle P-type heavily doped regions 102 and the middle N-type heavily doped region 103 serve as emitters, and the emitter is connected to a high level.
[0062] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0063] In summary, the present invention achieves asymmetric positive and negative withstand voltage protection through a single-stage device. Adjustable positive and negative trigger voltages are achieved solely through structural changes, without the need for additional processes or implants. Compared to ESD ion implantation, this patented method achieves trigger voltage adjustment without any additional processes, exhibits no hysteresis, and does not increase the risk of latch-up. It also exhibits excellent compatibility, being suitable for both P-type lightly doped drain-enclosing P-type heavily doped region structures and P-type heavily doped region-enclosing P-type lightly doped drain structures. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.
[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage, characterized in that: include: A bipolar transistor consisting of a P-type heavily doped region / N-well / P-type heavily doped region is formed on a P-type substrate; wherein the active regions of the emitter, collector and base are isolated by shallow trench isolation; The base of the bipolar transistor is formed by the N-well; A P-type lightly doped drain is formed at the P-type heavily doped region; An N-type heavily doped region is inserted between the two P-type heavily doped regions in the same active region, and the three serve as collectors or emitters; The N-type heavily doped region and the P-type heavily doped region are connected via an active region without injection, and the base of the bipolar transistor is connected through the N-type heavily doped region and then floated, so as to achieve bidirectional electrostatic discharge protection; There is a lateral distance between the N-type doped region and the P-type heavily doped region, and the asymmetric withstand voltage is achieved by adjusting the lateral distance.
2. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 1, characterized in that: The MOS device is a non-low-voltage device, and the depth of the P-type lightly doped drain is greater than the depth of the P-type doped region.
3. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 1, characterized in that: The MOS device is a low voltage device, and the depth of the P-type lightly doped drain is less than the depth of the P-type doped region.
4. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 1, characterized in that: In the metal silicide process, the device further includes forming a metal silicide barrier layer on the non-implanted active area to prevent the N-type heavily doped area and the P-type heavily doped area from being short-circuited due to the metal silicide.
5. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 4, characterized in that: The metal silicide barrier layer is located between the N-type heavily doped region and the P-type heavily doped region.
6. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 4, characterized in that: The metal silicide barrier layer spans over the N-type heavily doped region.
7. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 4, characterized in that: The metal silicide barrier layer includes at least one of silicon-rich oxide, SiO2, SiON and Si3N4.
8. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 1, characterized in that: In the metal silicide process, the device further comprises forming a polysilicon layer on the non-implanted active area to prevent the N-type heavily doped area and the P-type heavily doped area from being short-circuited due to the metal silicide.
9. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 8, characterized in that: The polysilicon layer is located between the N-type heavily doped region and the P-type heavily doped region, and the polysilicon layer is floating.
10. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 1, characterized in that: The device is used for electrostatic discharge protection of devices ranging from 1.8V to 9V.
11. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 1, characterized in that: The two outer P-type heavily doped regions and the N-type heavily doped region in the middle serve as collectors, and the P-type heavily doped region in the collector is connected to a high level; the two middle P-type heavily doped regions and the N-type heavily doped region in the middle serve as emitters, and the emitters are connected to a low level.
12. The PNP structure electrostatic protection device with positive and negative asymmetric withstand voltage according to claim 1, characterized in that: The two outer P-type heavily doped regions and the N-type heavily doped region in the middle serve as emitters, and the P-type heavily doped region in the collector is connected to a low level; the two middle P-type heavily doped regions and the N-type heavily doped region in the middle serve as emitters, and the emitters are connected to a high level.