Structures with guard rings between terminals of single photon avalanche diode photodetectors and related methods

Abstract

Embodiments of the present disclosure provide structures with guard rings between terminals of a single photon avalanche diode photodetector (SPAD) and related methods. A structure according to the present disclosure includes a SPAD having an anode located within a doped well and a cathode located within the doped well. The guard ring includes a semiconductor material within the doped well. The semiconductor material and the doped well have opposite doping polarities.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuit (IC) structures. More specifically, various embodiments of the present disclosure provide structures having guard rings between terminals of a single photon avalanche diode (SPAD) photodetector and related methods. Background Art

[0002] It is widely recognized that fiber optic network links require greater bandwidth. Fiber optic communications have gained prominence in telecommunications, instrumentation, cable television, networking, and data transmission and distribution. Fiber optic communication systems or links include photodetector elements. The function of a photodetector in a fiber optic communication system is to convert optical power into voltage or current. The photodetector can be formed as a standard PIN diode structure (positive / intrinsic / negative conductivity) or an avalanche photodiode (APD). Although avalanche photodiodes require higher operating voltages that must be compensated for temperature excursions, the internal gain of avalanche photodiodes is much more sensitive to incident radiation. In addition, avalanche photodiodes generally provide a significantly increased receiver signal-to-noise ratio (SNR). A single-photon avalanche diode (SPAD) photodetector is an APD that is electrically biased significantly above its reverse bias breakdown voltage, which increases sensitivity to radiation and allows the photodiode to operate with less damage or noise than other APDs. In microelectronic circuits, the effectiveness of SPADs can be limited by edge breakdown (i.e., the electric field gradients at the edges of the avalanche junction are significantly higher and cause the diode structure to degrade at these edges). Summary of the invention

[0003] Some aspects of the present disclosure provide a structure including: a single-photon avalanche diode (SPAD) photodetector, which includes an anode located in a doped well and a cathode located in the doped well; and a guard ring located in the doped well and between the cathode and the anode, wherein the semiconductor material of the guard ring and the doped well have opposite doping types.

[0004] Another aspect of the present disclosure provides a structure comprising: a doped well located in a substrate; a single photon avalanche diode (SPAD) photodetector located in the substrate, the SPAD comprising: an anode located in a first portion of the doped well and having an anode contact thereto, a cathode located in a second portion of the doped well and having a cathode contact thereto, wherein the cathode is horizontally away from the anode in the doped well; and a guard ring comprising a semiconductor material located in the doped well and between the cathode and the anode, wherein the semiconductor material and the doped well have opposite doping types.

[0005] Another aspect of the present disclosure provides a method comprising: forming a single-photon avalanche diode (SPAD) photodetector comprising an anode located in a doped well and a cathode located in the doped well; and forming a guard ring in the doped well and between the cathode and the anode, wherein the semiconductor material of the guard ring and the doped well have opposite doping types. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other features of the present disclosure will be more readily understood through a detailed description of various aspects of the present disclosure taken in conjunction with the accompanying drawings which illustrate various embodiments of the present disclosure, in which:

[0007] Figure 1 A cross-sectional view of a structure including a single photon avalanche diode (SPAD) photodetector and a guard ring according to an embodiment of the present disclosure is provided.

[0008] Figure 2 A plan view of a structure including a single photon avalanche diode (SPAD) photodetector and a guard ring according to an embodiment of the present disclosure is provided.

[0009] Figure 3 A cross-sectional view of a structure according to the present disclosure during operation is shown, where shading indicates electric field strength.

[0010] Figure 4 A cross-sectional view of a structure including a SPAD and a plurality of guard ring regions according to an embodiment of the present disclosure is shown.

[0011] Figure 5-8 A cross-sectional view showing the formation of an anode region, a cathode region, and a guard ring in a doped well in a method according to an embodiment of the present disclosure is shown.

[0012] Fig. 9 and Fig.10 A cross-sectional view of forming a structure having multiple guard ring regions according to an embodiment of the present disclosure is shown.

[0013] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, the same reference numerals represent the same elements between the drawings. DETAILED DESCRIPTION

[0014] In the description herein, reference is made to the accompanying drawings forming a part thereof, in which specific exemplary embodiments in which the present teachings may be practiced are shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and may be changed within the scope of the present teachings. Therefore, the description herein is merely illustrative.

[0015] Embodiments of the present disclosure provide a structure having a guard ring between the terminals of a single photon avalanche diode (SPAD) photodetector and a related method. According to the structure of the present disclosure, a SPAD having an anode located in a doped well and a cathode located in the doped well is provided. The cathode and the anode are separated by a distance in the doped well. The guard ring is coupled to a semiconductor material located in the doped well and between the cathode and the anode. The semiconductor material and the doped well have opposite doping polarities. In this configuration, the guard ring can be electrically biased to partially offset and thereby reduce the electric field strength between the anode and the doped well. During the operation of the SPAD, the electrically biased guard ring can reduce or completely prevent premature (pre-mature) edge breakdown of the SPAD structure in addition to other benefits. In some embodiments, the structure may include differences in the height and / or position of the cathode, anode, and semiconductor material to further prevent high-intensity electric fields from accumulating in unwanted places.

[0016] The structure according to the present disclosure operates using a diode. A diode is a two-terminal element that behaves differently between two electrical contacts than a conducting or insulating material. Specifically, a diode provides high conductivity from one contact to another in one direction (i.e., the "forward" direction), but provides little conductivity in the opposite direction (i.e., the "reverse" direction). In the case of a PN junction, the forward and reverse orientations of the diode depend on the type and magnitude of the voltage applied to the material components of one or both terminals, which affects the size of the potential barrier. In the case of a junction between two semiconductor materials, the potential barrier will form along the interface between the two semiconductor materials.

[0017] An "avalanche junction", also known as an "avalanche diode", is a special type of diode structure used to bidirectionally control the flow of current through integrated circuit (IC) structures. An avalanche junction differs from a PN diode in having a much wider depletion region, i.e., a region of more lightly doped semiconductor material between the oppositely doped terminals of the diode. Applying a voltage across the wide depletion region can accelerate minority charge carriers in the insulating material to the point where ionization occurs in the crystal lattice. In turn, the accelerated minority charge carriers produce more charge carriers and more ionization. This effect is known as "avalanche breakdown". In this case, an electrical path can be formed in either direction from one terminal to the other, depending on whether the diode is forward biased or reverse biased. An avalanche diode differs from other diodes in that, for example, it provides a constant voltage drop across its two terminals that is independent of the amount of current passing through it.

[0018] refer to Figure 1, showing a cross-sectional view of a structure 100 according to an embodiment of the present disclosure. The structure 100 may be formed, for example, from a substrate 102 comprising one or more semiconductor materials. The substrate 102 may be formed, at least in part, from any currently known or later developed semiconductor material, which may include, but is not limited to, silicon, germanium, silicon germanium, and a semiconductor material having a chemical formula of Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 A substance composed of one or more III-V compound semiconductors of the defined composition, wherein X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions that are all greater than or equal to zero, and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 is the total relative molar amount). The substrate 102 can take the form of a bulk substrate, a semiconductor on insulator (SOI) substrate, and / or various other types of substrates. In the case of an SOI substrate, the semiconductor layer 102 of the SOI substrate can be located on a buried insulator layer 103 (shown in dotted lines) composed of any currently known or later developed insulator material (e.g., any one or more of the various oxides, nitrides, and / or other insulator materials discussed herein).

[0019] Portions of the substrate 102 may include dopants, thus providing a doped well 104 having a doping type opposite to that of the substrate 102. In the field of semiconductor processing, a "well" refers to a portion of a substrate that contains a specific type and concentration of impurities (dopants) to control its conductivity. According to one example, the substrate 102 may have a small amount of P-type doping. When referring to dopants, a P-type dopant refers to an element introduced into a semiconductor material to create free holes by "accepting" electrons from semiconductor atoms and thereby "releasing" holes. The acceptor atom must have one less valence electron than the host semiconductor. P-type dopants suitable for use in the substrate 102 may include, but are not limited to: boron (B), indium (In), and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Other alternatives include In and Ga. Ga has a high diffusivity in silicon dioxide (SiO2), so the oxide cannot be used as a mask during Ga diffusion. The doped well 104 may be formed in the substrate 102, for example, by vertical ion implantation, so that the upper surface of the doped well 104 is aligned with the upper surface of the substrate 102 and is therefore shared with the upper surface of the substrate 102. The doped well 104 may have a doping type opposite to that of the substrate 102, for example, in the case where the substrate 102 is doped to a p-type, the doped well 104 may be a lightly doped N-type (referred to as "n-doped"). N-type dopants suitable for use in the doped well 104 may include, but are not limited to: phosphorus (P), arsenic (Ar), antimony (Sb), bismuth (Bi), and lithium (L). Phosphorus and arsenic are the most common examples of n-type doping in integrated circuit technology. As is well known in the art, the doping type may be represented as "p" or "n", followed by a "plus sign" or a "minus sign", where the minus sign indicates a concentration lower than the baseline concentration and the plus sign indicates a concentration higher than the baseline concentration. Therefore, the doped well 104 may be distinguished from the substrate 102 at least in part based on its doping concentration, dopant material, etc. The substrate 102 may include other doped wells having the same or different doping types and is shown only for clarity. Figure 2 Such wells are omitted in .

[0020] Some portions of doped well 104 may include guard ring 106, or may be located below guard ring 106. As discussed in further detail herein, guard ring 106 is included within structure 100 to separate certain electrically active materials from one another. Guard ring 106 may take the form of semiconductor material that is oppositely doped relative to doped well 104 and / or other adjacent semiconductor material regions. The two portions of guard ring 106 are located at Figure 1 , but it should be understood that the two parts can be included in a single guard ring 106 surrounding the anode region 108, such as Figure 2 As shown and discussed elsewhere in this article.

[0021] An embodiment of the structure 100 includes an anode region 108 located within a doped well 104 and a cathode region 110 located within the doped well 104. A distance D separates the anode region 108 from the cathode region 110. The distance D and the size of the guard ring 106 can be selected to ensure that an avalanche junction will be formed within the depletion region defined by the doped well 104. The anode region 108 can be a region of semiconductor material within the doped well 104 that has an opposite polarity to the doped well 104, for example, it can be a P-type ("p++ doped") that is more highly doped than the guard ring 106 to form a strong PN junction between the anode region 108 and the underlying doped well 104. The cathode region 110 can have the same doping type as the doped well 104, but with a higher doping concentration. For example, where the doped well 104 has an "n-" doping, the cathode region 110 can have an "n+" doping. Radiation R entering the anode region 108 can create a current path within the structure 100. Although radiation R is shown as passing through and illuminating the upper side (i.e., the "back side") of structure 100, radiation propagating from the bottom side (i.e., the "front side") of structure 100 may also generate current. Anode region 108, doped well 104, and cathode region 110 collectively define a SPAD within structure 100. Guard ring 106 and its subcomponents are not considered part of the SPAD, but may interact with the SPAD components to affect their behavior, for example, by counteracting or preventing certain areas from having high electric field strengths, as discussed herein.

[0022] The SPAD in structure 100 (composed of an anode region 108, a cathode region 110, and a doped well 104 therebetween) works on the same principle as other diode junctions in integrated circuits. That is, the anode region 108 and the cathode region 110 provide two oppositely doped regions that allow current to flow easily from the anode region 108 to the cathode region 110, but prevent current from flowing in the opposite direction. SPAD is specifically configured to operate at a higher voltage than other types of diodes. In a normal diode, when the voltage applied thereto exceeds the inherent peak voltage of the diode, voltage and structural breakdown will occur. However, by forming an avalanche junction in the SPAD, the SPAD can continue to operate in the case of exceeding its breakdown voltage. The doped well 104 serves as a wider depletion region between the anode region 108 and the cathode region 110, enabling these portions of the structure 100 to exhibit "avalanche breakdown" higher than their breakdown voltage. Photons incident on the anode region 108 will therefore impart sufficient energy to induce a current from the anode region 108 to the cathode region 110, enabling the regions 104, 108, 110 to detect the incident radiation.

[0023] The presence of the guard ring 106, which is doped with the same polarity as the anode region 108 but at a lower concentration, will partially oppose the induced current through the doped well 104. During operation, an operator of the structure 100 can electrically bias the guard ring 106 to produce an electric field that more strongly opposes the current in the immediately adjacent portion of the doped well 104 without completely preventing avalanche breakdown. The electric field induced by the biasing of the guard ring 106 can have an opposite polarity to any electric field generated by illumination of the anode region 108, and can therefore prevent current from passing through locations physically close to the guard ring 106. Such locations typically include, for example, corners or vertical sidewalls of the anode region 108, which prevents "edge breakdown" near the anode region 108 or cathode region 110. An example of such an electric field is Figure 3 and discussed in further detail elsewhere in this document.

[0024] The guard ring 106 may include a semiconductor material 112 located between the anode region 108 and the cathode region 110 and having the same doping polarity as the anode region 108. The semiconductor material 112 may have the same doping type as the anode region 108, but at a lower concentration (e.g., where the anode region 108 has "p++ doping", the semiconductor material 112 may have "p+" doping). The presence of the semiconductor material 112 in the guard ring 106 defines a current path in the doped well 104 between the anode region 108 and the cathode region 110, which passes under the guard ring 106. Each region 108, 110, 112 may have a lower surface of a different depth within the doped well 104 (i.e., S1 represents the lower surface of the cathode region 110, S2 represents the lower surface of the semiconductor material 112, and S3 represents the lower surface of the anode region 108). The depth of the semiconductor material 112 within the doped well 104 may be greater than (i.e., deeper than) the depth of the anode region 108, but may be less than (i.e., shallower than) the depth of the cathode region 110. The varying depths of each region 108, 110, 112 within the doped well 104 may increase the physical distance between the anode region 108 and the cathode region 110, thereby increasing the effect of the electric field induced in the semiconductor material 112 on affecting the current path between the anode region 108 and the cathode region 110.

[0025] The upper portion of each region 108, 110, 112 may be separated from each other by a set of trench isolations (TIs) 114, each of which may be located above the doped well 104 and the substrate 102. The TIs 114 may be formed by removing an initial portion of the doped well 104 and / or the substrate 102 before forming the remainder of the structure 100, and then filling the removed semiconductor material with one or more insulating materials known in the art. An insulator 116 may also be formed over the TIs 114, for example as an interlayer dielectric and / or other insulating material layer to separate the substrate 102 from the overlying metal line layer. The TIs 114 and / or insulators 116, respectively, may include one or more dielectric materials, such as oxide and / or nitride insulators, and / or other insulating materials, including those with low dielectric constants (i.e., any insulating material having a dielectric constant "k" less than about 3.9).

[0026] The insulator 116 of the structure 100 can have a set of contacts extending vertically therethrough, each of which can be formed of one or more conductive materials. The anode contact 120 can be coupled to the anode region 108, the guard ring contact 122 can be coupled to the semiconductor material 112, and the cathode contact 124 can be coupled to the cathode region 110. Each contact 120, 122, 124 can include any currently known or later developed conductive material, such as tungsten (W), etc., and / or other materials suitable for use in conductive contacts or vias of circuit structures. The contacts 120, 122, 124 may include a refractory metal liner (not shown) along their sidewalls, for example, as is known in the art to reduce electromigration degradation. One or more metal wiring layers (referred to in the art as "metal layers") can be located on or above the contacts 120, 122, 124 to connect the structure 100 to other structures and / or devices. Such connections are made in a manner that allows the structure 100 to be connected to the semiconductor material 112. Figure 1 100 as via an anode terminal to an anode contact 120, via a ring bias terminal to a guard ring contact 122, and via a cathode terminal to a cathode contact 124. The anode terminal and the cathode terminal indicate electrical coupling to a circuit for detecting current in the structure 100 induced by radiation R. A bias voltage may be coupled to the ring bias terminal and thereby to the guard ring contact 122. The bias voltage may be set to a predetermined voltage level (e.g., set by a manufacturer and / or operator of the structure 100) to electrically bias the guard ring 106 through the semiconductor material 112.

[0027] refer to Figure 2 , the anode region 108 may be a doped well 104 ( Figure 1) above the anode region 108 so that the guard ring 106 (including its semiconductor material 112) horizontally surrounds the anode region 108. Any desired number of guard ring contacts 122 for the guard ring 106 may be located at various locations on the semiconductor material 112 (e.g., Figure 2 Two are shown in the figure) to further control the electrical bias of the guard ring 106. Although the guard ring 106 is shown as having a generally circular shape by way of example, other shapes of semiconductor material (e.g., ellipses, triangles, quadrilaterals, polygons with any number of sides) horizontally surrounding the anode region 108 may also provide a "guard ring" shape. The cathode region 110 may similarly surround the semiconductor material 112 of the guard ring 106. Although the cathode region 110 is shown as having a shape similar to the guard ring 106, this is not required. In other embodiments, the cathode region 110 may not surround the guard ring 106, but may simply be located at the doped well 104 ( Figure 1 ) near the guard ring 106 within the TI 114. The TI 114 can be horizontally located between the guard ring 106 and the regions 108, 110, so that the regions 108, 110, 112 are structurally and electrically isolated from each other. Figure 1 Perspective drawing Figure 2 As shown in the view line 1-1, Figure 1 Multiple instances of the guard ring 106 , the semiconductor material 112 , the cathode region 110 , etc. in can each be part of a continuous material region.

[0028] Figure 3 A diagram of a portion of structure 100 during operation is shown to better illustrate the effect of bias voltage on the current flowing through the SPAD (i.e., the path from anode region 108 through doped well 104 to cathode region 110). Figure 3, darker shaded areas indicate stronger electric fields and lighter shaded areas indicate weaker electric fields. The electrical bias on the semiconductor material 112 of the guard ring 106 induces an electric field of opposite polarity to the electric field induced by the incident photons (indicated by the radiating lines R). Therefore, the electric field from the semiconductor material 112 reduces the electric field strength near the boundary between the anode region 108 and the TI 114, and similarly reduces the electric field strength at the boundary between the cathode region 110 and the TI 114. The electric field within the doped well 104 below the semiconductor material is stronger than the electric field next to the upper portion of the semiconductor material 112, thereby preserving a current path through the depletion region that is wide enough to provide an avalanche junction. Other circuits (not shown) coupled to the anode region 108 and the cathode region 110 can provide a complete circuit for transmitting electrical signals. Radiation entering anode region 108 may generate current from anode region 108 to cathode region 110 , and embodiments of the present disclosure reduce or eliminate the risk of edge breakdown in portions of doped well 104 near corners of anode region 108 , cathode region 110 , and / or TI 114 .

[0029] Figure 4 Another example of a structure 100 is shown, wherein a guard ring 106 includes a plurality of guard ring regions 106a, 106b, each guard ring region including a semiconductor material 112 located between an anode region 108 and a cathode region 110. Each guard ring region 106a, 106b can be similar in shape to other embodiments of the guard ring 106 discussed herein, except for having different sizes to be positioned at their respective locations. According to one example, one guard ring region 106a horizontally surrounds the anode region 108, and another guard ring region 106b horizontally surrounds the guard ring region 106a in addition to the anode region 108. Each guard ring region 106a, 106b can be coupled to a different bias voltage at an electrically coupled "ring bias 1" and "ring bias 2", such as at a plurality of electrically coupled "ring bias 3". Figure 4 Different bias amounts may allow an operator or manufacturer to further control the electric field strength between the anode region 108 and the cathode region 110 , thereby further affecting the current path through the doped well 104 .

[0030] Go to Figure 5 and Figure 6 The present disclosure also provides a method for forming a structure 100 ( Figure 1 ) method, wherein the SPAD guard ring 106 ( Figure 1 ) can be electrically biased. Figure 4An initial structure 128 is shown in which a first set of doping masks 130 (e.g., silicon dioxide and / or any other currently known or later developed insulator for preventing doping of underlying materials) is formed over the substrate 102 and the doped well 104 to cover portions of the substrate 102, the doped well 104, and / or the TI 114. In this example, the substrate 102 and the doped well 104 have been doped according to conventional processing techniques. The first set of doping masks 130 may include a first opening J1 shaped to dope and define an anode of the SPAD and a second opening J2 shaped to dope and define a semiconductor material of the guard ring. The first set of doping masks 130 may be configured to include openings J1, J2 because these openings are used to dope two regions of the same doping type. Figure 6 The use of another set of doping masks 130 is shown, which has a third opening J3 for doping and defining the cathode of the SPAD. Figure 5 and Figure 6 Two different sets of doping masks 130 are shown in FIG. 1 , but it should be understood that any number of doping masks 130 may be formed in any number of stages so that only certain sets (e.g., only one set) of openings J1, J2, and J3 may be used for simultaneous doping to better control the doping polarity and concentration in the doped well 104. Different materials may also be doped at different times. Figure 5 and Figure 6 to be implemented in the order shown.

[0031] refer to Figure 5-7, the doping mask 130 can be used to form an anode region 108, a cathode region 110, and a semiconductor material 114 in the doped well 104. Regardless of the number of doping masks 130 and openings J1, J2, J3 available at a given time, the portion of the doped well 104 within the openings J1, J2, J3 can be doped by introducing impurities (dopants) into the doped well 104. In the example of doping by implantation, an ion implanter can be used. In other examples, in-situ doping or other doping techniques can be used. In order to provide a SPAD with an avalanche junction, the anode region 108 can be extremely heavily doped (e.g., "p++ doping") compared to the light doping (e.g., "n-doping") in the doped well 104, while the cathode region 110 can be heavily doped with the opposite polarity (e.g., "n+ doping"). As discussed elsewhere herein, the extension depth of the anode region 108 in the doped well 104 can be shallower than the cathode region 110, so that the lower surface S1 of the cathode region 110 is below the lower surface S3 of the anode region 108. Similarly, the doping mask 130 having the second opening J2 can be used to form the semiconductor material 112 of the guard ring 106 located between the anode region 108 and the cathode region 110. The semiconductor material 112 may have the same doping type as the anode region 108, but with a lower doping concentration (e.g., where the anode region 108 has p++ doping, the semiconductor material 112 has "p+ doping"). The semiconductor material 112 having the same doping type as the anode region 108 can allow the electrical bias applied thereto to counteract any electric fields induced near the upper surfaces and / or corners of the anode region 108 and the cathode region 110, as discussed herein. The semiconductor material 112 may have a lower surface S2 vertically located between the lower surface S1 of the cathode region 110 and the lower surface S3 of the anode region 108, as discussed herein.

[0032] Figure 8 Further processing is shown according to an embodiment of the present disclosure to produce a structure 100 having an anode region 108, a cathode region 110, and a guard ring 106 therein. An insulator 116 (e.g., an ILD material or other electrical insulator discussed herein) may be formed as a single layer over the upper surfaces of the TI 114 and the anode region 108, the semiconductor material 112, and the cathode region 110. Thereafter, a set of openings (not shown) may be formed by targeting and removing areas of the insulator 116 material over the regions 108, 110, 112. These openings may be filled with a refractory metal liner and a conductive material to produce contacts 120, 122, 124 discussed elsewhere herein. Each contact 120, 122, 124 may then be connected to a corresponding terminal to enable current to flow from the anode region 108 to the cathode region 110 and to allow electrical biasing of the guard ring 106.

[0033] Fig. 9 and Fig.10 It shows how to implement the method of the present disclosure to form, for example, Figure 4 The plurality of guard ring regions 106a, 106b discussed. Fig. 9 As shown, the doping mask 130 may include a plurality of second openings J2 (only Fig. 9 The portion of the doped well 104 located below each opening J2 may receive the same type of doping to produce multiple guard ring regions 106a, 106b where needed (only Fig.10 ). In addition to having a third opening J3 formed to form the cathode region 110 (see Figure 6 ) other processes discussed herein may be implemented without any changes except for possible changes in the shape of the doping mask 130. When forming the guard ring contacts 122, each guard ring contact 122 may be coupled to a different bias voltage so that different guard ring regions 106a, 106b may be coupled to different bias voltages.

[0034] Embodiments of the present disclosure may provide several technical and commercial advantages, some of which are discussed herein by way of example. The electrical biasing of the guard ring 106 will reduce the electric field strength near the sidewalls and corners of the anode region 108 and the cathode region 110 of the SPAD, while the electric field strength will not be strong enough to prevent the formation of an avalanche junction within the doped well 104 between the anode region 108 and the cathode region 110. One advantage of inducing a counteracting electric field through the guard ring 106 is the ability to reduce or even prevent any premature edge breakdown from occurring during device operation. Furthermore, embodiments of the present disclosure provide for simpler integration of SPADs into integrated circuits with few manufacturing differences compared to conventional SPADs. The presence of an electrically biased SPAD may allow for more reliable light detection and longer product life.

[0035] The description of various embodiments of the present disclosure is given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art within the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found on the market, and / or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: A single photon avalanche diode photodetector SPAD, comprising an anode located in a doped well and a cathode located in the doped well; as well as A guard ring is located within the doped well and between the cathode and the anode, wherein the semiconductor material of the guard ring and the doped well have opposite doping types.

2. The structure according to claim 1, wherein: The guard ring includes a plurality of guard ring regions within the doped well and between the cathode and the anode, wherein two of the plurality of guard ring regions are coupled to different bias voltages.

3. The structure according to claim 1, wherein: The guard ring horizontally surrounds the anode.

4. The structure according to claim 3, wherein: The cathode horizontally surrounds the guard ring.

5. The structure according to claim 1, wherein: The guard ring includes a lower surface vertically located between a lower surface of the anode and a lower surface of the cathode.

6. The structure according to claim 1, wherein: The doped well is located in one of a bulk semiconductor substrate and a semiconductor layer of a semiconductor-on-insulator (SOI) substrate.

7. The structure according to claim 1, wherein: The semiconductor material of the guard ring and the anode have the same doping type, and wherein a dopant concentration in the anode is greater than a dopant concentration in the semiconductor material of the guard ring.

8. A structure comprising: a doped well located in the substrate; A single photon avalanche diode photodetector SPAD, which is located in the substrate, and the SPAD comprises: an anode located within the first portion of the doped well and having an anode contact thereto, and a cathode located within the second portion of the doped well and having a cathode contact thereto, wherein the cathode is horizontally distal from the anode within the doped well; and A guard ring includes a semiconductor material located within the doped well and between the cathode and the anode, wherein the semiconductor material and the doped well have opposite doping types.

9. The structure according to claim 8, wherein: The guard ring includes a plurality of guard ring regions within the doped well and between the cathode and the anode, wherein two of the plurality of guard ring regions are coupled to different bias voltages.

10. The structure according to claim 8, wherein: The guard ring horizontally surrounds the anode.

11. The structure according to claim 10, wherein: The cathode horizontally surrounds the guard ring.

12. The structure according to claim 8, wherein: The guard ring includes a lower surface vertically located between a lower surface of the anode and a lower surface of the cathode.

13. The structure according to claim 8, wherein: The doped well is located in one of a bulk semiconductor substrate and a semiconductor layer of a semiconductor-on-insulator (SOI) substrate.

14. The structure according to claim 8, wherein: The semiconductor material and the anode have the same doping type, and wherein a dopant concentration in the anode is greater than a dopant concentration in the semiconductor material.

15. A method comprising: forming a single photon avalanche diode photodetector SPAD including an anode located in a doped well and a cathode located in the doped well; as well as A guard ring is formed within the doped well and between the cathode and the anode, wherein the semiconductor material of the guard ring and the doped well have opposite doping types.

16. The method according to claim 15, wherein: Forming the guard ring includes forming a plurality of guard ring regions within the doped well and between the cathode and the anode, wherein two of the plurality of guard ring regions are coupled to different bias voltages.

17. The method according to claim 15, further comprising: A bias voltage is applied to the semiconductor material through the guard ring to reduce the electric field strength within the doped well.

18. The method according to claim 15, wherein: The guard ring is formed such that the semiconductor material horizontally surrounds the anode.

19. The method according to claim 15, wherein: Forming the guard ring includes forming a lower surface of the guard ring vertically between a lower surface of the anode and a lower surface of the cathode.

20. The method of claim 15, further comprising: The doped well is formed in one of a bulk semiconductor substrate and a semiconductor layer of a semiconductor-on-insulator (SOI) substrate.

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