Solar cells and photovoltaic modules

Abstract

This application provides a solar cell and a photovoltaic module, belonging to the field of semiconductor technology. The solar cell includes: a silicon substrate with a surface having conductive regions; a doped semiconductor layer located on the conductive regions of the silicon substrate, the doped semiconductor layer including electrode regions; a passivation antireflection layer located on the surface of the doped semiconductor layer away from the silicon substrate; and an electrode located on the passivation antireflection layer, the electrode partially contacting the passivation antireflection layer and the electrode regions; wherein the passivation antireflection layer located at the edge of the electrode regions has a first etched region, the first etched region having a plurality of first pores.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to solar cells and photovoltaic modules. Background Technology

[0002] With the advancement of solar cell technology, there is increasing attention being paid to the lifespan and reliability of solar cells. The lifespan and reliability of solar cells are influenced by many factors, among which a suitable electrode structure is a crucial factor affecting reliability.

[0003] However, current electrode design optimization mainly focuses on improving the contact and passivation effect between the electrode and the semiconductor, while there are relatively few technical solutions to improve battery reliability by optimizing the electrode structure. Summary of the Invention

[0004] In view of this, in order to at least partially solve at least one of the aforementioned technical problems, this application provides a solar cell.

[0005] According to an embodiment of this application, a solar cell is provided, comprising: a silicon substrate including a surface having a conductive region; a doped semiconductor layer located on the conductive region of the silicon substrate, the doped semiconductor layer including an electrode region; a passivation antireflection layer located on the surface of the doped semiconductor layer away from the silicon substrate; an electrode located on the passivation antireflection layer, the electrode being in contact with a portion of the passivation antireflection layer and the electrode region; wherein the passivation antireflection layer located at the edge of the electrode region has a first etched region, the first etched region having a plurality of first pores.

[0006] According to an embodiment of this application, the electrode region includes a pore-free transition region located on the side of the first corrosion region away from the edge of the electrode region.

[0007] According to embodiments of this application, at least a portion of the plurality of first holes are blind holes, and / or the distribution density of blind holes is greater than or equal to 50%.

[0008] According to an embodiment of this application, the electrode region includes a second corrosion region located at the middle position of the electrode region, and the second corrosion region has a plurality of second holes.

[0009] According to an embodiment of this application, the diameter of the second hole is larger than the diameter of the first hole.

[0010] According to an embodiment of this application, the conductive region includes an N-region and a P-region, which are located on the same surface or different surfaces of the solar cell, respectively; the doped semiconductor layer includes an N-type doped semiconductor layer and a P-type doped semiconductor layer, with the N-type doped semiconductor layer located on the N-region and the P-type doped semiconductor layer located on the P-region; the electrode region of the N-type doped semiconductor layer is designated as the first electrode region, and the electrode region of the P-type doped semiconductor layer is designated as the second electrode region, wherein the area ratio of the second hole located in the first electrode region on the first electrode region is smaller than the area ratio of the second hole located in the second electrode region on the second electrode region.

[0011] According to embodiments of this application, the area ratio of the second hole located in the first electrode region on the first electrode region is 0% to 60%, and the area ratio of the second hole located in the second electrode region on the second electrode region is 10% to 90%; and / or, the difference between the area ratio of the second hole located in the first electrode region on the first electrode region and the area ratio of the second hole located in the second electrode region on the second electrode region is 10% to 30%.

[0012] According to an embodiment of this application, the conductive region includes an N-region and a P-region, which are located on the same surface or different surfaces of the solar cell, respectively; the passivation antireflection layer includes a first passivation antireflection layer and a second passivation antireflection layer, the first passivation antireflection layer is located on the doped semiconductor layer of the N-region, and the second passivation antireflection layer is located on the doped semiconductor layer of the P-region; the first etched region is strip-shaped and extends along the extension direction of the electrode region; along the extension direction perpendicular to the electrode region, the width of the first etched region located in the first passivation antireflection layer is different from the width of the first etched region located in the second passivation antireflection layer.

[0013] According to an embodiment of this application, the width of the first corrosion region located in the first passivation antireflection layer is greater than the width of the first corrosion region located in the second passivation antireflection layer.

[0014] According to an embodiment of this application, the conductive region includes an N-region and a P-region, which are located on the same surface or different surfaces of the solar cell, respectively; the passivation antireflection layer includes a first passivation antireflection layer and a second passivation antireflection layer, the first passivation antireflection layer is located on the doped semiconductor layer of the N-region, and the second passivation antireflection layer is located on the doped semiconductor layer of the P-region; the distribution density of the first pores in the first etched region of the first passivation antireflection layer is greater than the distribution density of the first pores in the first etched region of the second passivation antireflection layer.

[0015] According to an embodiment of this application, the conductive region includes an N-region and a P-region, which are located on the same surface or different surfaces of the solar cell, respectively; the doped semiconductor layer includes an N-type doped semiconductor layer and a P-type doped semiconductor layer, with the N-type doped semiconductor layer located on the N-region and the P-type doped semiconductor layer located on the P-region; the electrode region of the N-type doped semiconductor layer is designated as the first electrode region, and the electrode region of the P-type doped semiconductor layer is designated as the second electrode region, with the width of the first electrode region being smaller than the width of the second electrode region.

[0016] According to an embodiment of this application, a photovoltaic module is provided, comprising: a battery string, the battery string including solar cells as described above; and a plurality of solder strips, the solder strips connecting at least two adjacent solar cells.

[0017] According to an embodiment of this application, by providing a first corrosion zone with multiple first pores on the passivation antireflection layer located at the edge of the electrode region, the contact area between the electrode and the passivation antireflection layer is increased, thereby improving the adhesion of the electrode to the passivation antireflection layer, thus improving the tensile strength of the electrode and improving the reliability of the battery. Attached Figure Description

[0018] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0019] Figure 1 This is a partial structural schematic diagram of a solar cell according to an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of the structure of a solar cell according to an embodiment of this application after the electrodes have been removed and acid-washed to expose the first corrosion zone and the transition zone;

[0021] Figure 3 This is a SEM image of the electrode area of ​​the solar cell according to an embodiment of this application after the electrodes have been removed and acid-washed;

[0022] Figure 4 This is a schematic diagram of the overall structure of the back contact battery according to an exemplary embodiment of this application;

[0023] Figure 5 This is a schematic diagram of the overall structure of a back-contact battery according to another exemplary embodiment of this application;

[0024] Figure 6 This is a schematic diagram of the overall structure of a bifacial battery according to an exemplary embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0026] In the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments of this application. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "comprising" as used herein indicates the presence of features, steps, or operations, but does not exclude the presence or addition of one or more other features.

[0028] When using expressions such as "at least one of A, B, and C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When using expressions such as "at least one of A, B, or C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0029] In this application, the relative position between two components (e.g., a membrane or region), as referred to by terms such as "above," "on," or "above," can mean that the two components are in direct contact or that they are not in direct contact. Similarly, the relative position between two components, as referred to by terms such as "below," "under," or "below," can mean that the two components are in direct contact or that they are not in direct contact. For example, when one component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when one component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, thus this vertical relationship depends on the orientation of the device.

[0030] A reasonable electrode structure has a direct impact on the lifespan and reliability of solar cells. However, in the related structures of solar cell electrodes, the main research focuses on improving the contact and passivation effect between the electrode and the semiconductor layer, while less research is done on how to optimize the related electrode structure to improve cell reliability.

[0031] In realizing the concept of this application, it was discovered that by selecting a suitable fabrication process to control the edge structure of the electrode, a porous structure can be formed on the passivation and antireflection layer located at the edge of the electrode region of the doped semiconductor layer. This can increase the contact area between the electrode edge and the passivation and antireflection layer, thereby improving the adhesion of the electrode and thus improving the reliability of the battery.

[0032] Specifically, according to one embodiment of this application, a solar cell is provided. Figure 1 This is a partial structural schematic diagram of the solar cell according to an embodiment of this application, as shown below. Figure 1 As shown, the solar cell provided in this application embodiment includes a silicon substrate 1, a doped semiconductor layer 2, a passivation antireflection layer 3, and an electrode 4, wherein: the silicon substrate 1 includes a surface having a conductive region 11; the doped semiconductor layer 2 is located on the conductive region 11 of the silicon substrate 1, and the doped semiconductor layer 2 includes an electrode region 21, as shown in the dashed box; the passivation antireflection layer 3 is located on the surface of the doped semiconductor layer 2 away from the silicon substrate 1; the electrode 4 is located on the passivation antireflection layer 3, and the electrode 4 is in contact with the portion of the passivation antireflection layer 3 and the electrode region 21.

[0033] According to embodiments of this application, the silicon substrate 1 can be an N-type silicon substrate or a P-type silicon substrate. Specifically, the silicon substrate 1 can be a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate. Cells based on monocrystalline silicon substrates have higher conversion efficiency compared to other types, such as polycrystalline silicon cells. An N-type silicon substrate is obtained by introducing donor impurities such as group VA elements like phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, or a P-type silicon substrate is obtained by introducing acceptor impurities such as group IIIA elements like boron (B), aluminum (Al), or gallium (Ga). Here, no specific type of silicon substrate 1 is imposed; in practical applications, those skilled in the art can select a suitable silicon substrate 1 as needed.

[0034] According to embodiments of this application, the surface of the silicon substrate 1 can be the front and / or back of the battery, without limitation. Generally, the front of the battery serves as the light-receiving surface and the back as the backlighting surface, or it can be light-receiving on both sides, in which case both the front and back serve as light-receiving surfaces. The surface of the silicon substrate 1 with conductive regions can be a polished surface, and can have discretely distributed tower-based structures, thereby being suitable for obtaining a relatively flat passivation antireflection layer 3 on the polished surface, which is beneficial for forming a first etched region 31 with multiple first pores 32.

[0035] The conductive region 11 on the surface of the silicon substrate 1 is suitable as a region for separating and / or transporting charge carriers. Further, the surface region of the silicon substrate 1 where a doped semiconductor layer is formed can be used as the conductive region. Optionally, depending on the type of conductivity, the conductive region 11 may include an N-region and / or a P-region. The N-region and P-region may be located on the same surface or different surfaces of the solar cell. Where they are on the same surface, the N-region and P-region may be partial regions of one surface of the silicon substrate 1. Where they are on different surfaces, the N-region and P-region may each be at least a partial region of one surface of the silicon substrate 1, i.e., they may be the entire surface of the silicon substrate 1 or a partial region of the surface of the silicon substrate 1.

[0036] According to embodiments of this application, the doped semiconductor layer 2 may include semiconductor materials such as single-crystal silicon, polycrystalline silicon, or microcrystalline silicon. The doping type may be N-type doping and / or P-type doping. For example, N-type doping can be achieved by introducing donor impurities, such as group VA elements like phosphorus (P), arsenic (As), or antimony (Sb), into the semiconductor material; or P-type doping can be achieved by introducing acceptor impurities, such as group IIIA elements like boron (B), aluminum (Al), or gallium (Ga), into the aforementioned semiconductor material. The electrode region 21 of the doped semiconductor layer 2 represents a region that can be used to form an electrode, allowing the electrode to contact the doped semiconductor layer 2 in that region. This is to take into account the precision of the electrode fabrication process; therefore, the electrode region 21 includes an area where the electrode position can be reasonably adjusted.

[0037] According to embodiments of this application, the passivation antireflection layer 3 can be a single-layer film formed of silicon dioxide, aluminum dioxide, silicon nitride, or silicon oxynitride, or a multilayer film composed of one or more of the aforementioned materials. It can simultaneously protect and passivate the underlying silicon substrate 1 or functional layers, such as the doped semiconductor layer 2, and reduce the reflection of light incident on the surface of the silicon substrate 1. It can be prepared using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD) to form a relatively dense passivation antireflection layer 3.

[0038] According to embodiments of this application, the electrode 4 can be made of silver, silver-clad copper, aluminum, or copper, etc. Preferred electrode types include silver electrodes, doped aluminum electrodes (doped with group IIIA elements), or silver-aluminum electrodes. The electrode 4 can be fabricated using a suitable electrode paste through printing, followed by drying, sintering, and photoinjection treatments. Printing methods can include screen printing or inkjet printing, with screen printing being a more cost-effective option. The electrode can include structures such as current collector lines, busbar lines, or pads.

[0039] According to an embodiment of this application, the passivation antireflection layer 3 located at the edge of the electrode region 21 has a first corrosion region 31, and the first corrosion region 31 has a plurality of first pores 32. This application selects a suitable fabrication process to fabricate the passivation antireflection layer and the electrode, so that after the electrode is sintered, a first corrosion region suitable for contact with the electrode can be formed on the passivation antireflection layer located at the edge of the electrode region. Based on the porous structure of the first corrosion region, the contact area between the electrode edge and the passivation antireflection layer can be increased, thereby improving the adhesion of the electrode and improving the reliability of the battery.

[0040] According to embodiments of this application, at least a portion of the plurality of first holes 32 are blind holes, suitable for accommodating the metal crystal or glass body formed after the electrode 4 is sintered, for improving the tensile strength of the electrode 4, wherein the metal crystal is an alloy containing the metal element of the electrode and silicon element, such as silver-silicon alloy. Further optionally, the distribution density of blind holes is 1~40 holes / μm. 2 For example, it could be 1 / μm 2 5 per μm 2 8 per μm 2 10 cells / μm 2 15 cells / μm 2 18 cells / μm 2 20 cells / μm 2 25 cells / μm 2 30 cells / μm 2 35 cells / μm 2 40 cells / μm 2 Etc. Insufficient blind vias will hinder the adhesion of electrode 4 to the passivation and antireflection layer 3. The "distribution density" in this application can refer to the number of characterization objects, such as blind vias, within a characterization area per unit area, such as the first corrosion zone.

[0041] This application does not impose any limitations on the measurement of the distribution density of blind holes. Those skilled in the art can perform the measurement using conventional methods in the field. For example, an image of the surface of the battery cell after electrode removal and acid washing can be acquired using a scanning electron microscope (SEM). On the SEM top view obtained by measurement, at least one area of ​​the same size, for example 1 μm, can be selected. 2 Within a given region, the number of blind holes observed in each region is counted. The number of blind holes per unit area within each region is then calculated, and the average value is taken as the blind hole distribution density. It is important to note that, to reduce the impact of image acquisition resolution and statistical errors, blind holes with a diameter less than 20 nm are excluded from the measurement range when measuring their diameter and distribution density.

[0042] According to an embodiment of this application, optionally, the diameter and distribution of the first hole 32 on the first etched region 31 are different for either the N-type doped semiconductor layer 2 or the P-type doped semiconductor layer.

[0043] For example, a passivation antireflection layer located on an N-type doped semiconductor layer is used as the first passivation antireflection layer, and a passivation antireflection layer located on a P-type doped semiconductor layer is used as the second passivation antireflection layer. The aperture of the first hole in the first passivation antireflection layer is 20~300 nm, for example, it can be 20 nm, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, etc. The aperture of the first hole in the second passivation antireflection layer is 40~400 nm, for example, it can be 40 nm, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, 330 nm, 350 nm, 380 nm, 400 nm, etc. nm, etc.

[0044] For example, the distribution density of the first pores in the first corrosion zone located in the first passivation antireflection layer is 10~40 pores / μm. 2 For example, it could be 10 per μm 2 15 cells / μm 2 20 cells / μm 2 25 cells / μm 2 30 cells / μm 2 35 cells / μm 2 40 cells / μm 2 The distribution density of the first pores in the first corrosion zone of the second passivation antireflection layer is 1~20 per μm. 2 For example, it could be 1 / μm 2 5 per μm 2 8 per μm 2 10 cells / μm 2 15 cells / μm 2 18 cells / μm 2 20 cells / μm 2 wait.

[0045] For example, the width of the first etched region located in the first passivation antireflection layer is 0.2~4μm, such as 0.2μm, 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.3μm, 2.5μm, 2.8μm, 3.0μm, 3.3μm, 3.5μm, 3.8μm, 4.0μm, etc., and the width of the first etched region located in the second passivation antireflection layer is 0.1~2μm, such as 0.1μm, 0.3μm, 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, etc.

[0046] Regarding the measurement of the aperture of the first hole, this application does not impose any restrictions. Those skilled in the art can determine it using conventional methods in the field. For example, an image of the surface of the battery cell after the electrodes have been removed and acid-washed can be acquired using a scanning electron microscope (SEM). On the top view of the SEM obtained by measurement, the aperture of the observed hole can be statistically analyzed. The maximum diagonal dimension of the first hole in a certain direction can be taken as the aperture, or the diameter of an equivalent circle with the same area as the first hole can be taken as the aperture, which is beneficial to simplify measurement and statistical analysis.

[0047] This application does not impose any restrictions on the measurement of the distribution density of the first pore. Those skilled in the art can determine it using conventional methods in the field. For example, at least one area of ​​the same size, such as 1 μm, can be taken from the above SEM top view. 2 The number of first holes observed in each region is counted, and the number of first holes per unit area in each region is calculated and averaged to obtain the distribution density of the first holes. It should be noted that, to reduce the impact of image acquisition resolution and statistical errors, first holes with a diameter less than 20 nm are not included in the measurement range when measuring the pore size and distribution density.

[0048] This application does not impose any restrictions on the measurement of the width of the first corrosion zone. Those skilled in the art can measure it using conventional methods in the field. For example, on the above SEM top view, a region within a certain length range, such as 10 μm, can be taken in the extension direction of the first corrosion zone, and the average width of the first corrosion zone within this length range can be calculated.

[0049] Thus, by configuring the passivation and antireflection layer on the N-type doped semiconductor layer as a porous structure with a fine and / or densely distributed pore pattern, and further combining it with a first etched region of considerable width, the reliability of the electrodes on the N-type doped semiconductor layer can be significantly improved. Alternatively, by configuring the passivation and antireflection layer on the P-type doped semiconductor layer as a porous structure with a coarse and / or sparsely distributed pore pattern, and further combining it with a first etched region of relatively small width, the reliability of the electrodes on the P-type doped semiconductor layer can be improved while reducing damage to the passivation and antireflection layer at the electrode edge, thereby reducing recombination losses. Especially for N-type silicon substrates with higher minority carrier lifetimes, the PN junction region involves the injection and recombination of minority carriers, and reducing junction recombination losses is even more beneficial for improving photoelectric conversion efficiency.

[0050] According to the embodiments of this application, Figure 2 This is a schematic diagram of the structure of a solar cell according to an embodiment of this application after the electrodes have been removed and acid-washed to expose the first corrosion zone and the transition zone, wherein the electrode region 21 is indicated by a dashed box. Figure 2 As shown, electrode region 21 includes a pore-free transition region 211, which is located on the side of the first etched region 31 away from the edge of electrode region 21. The transition region 211 can disperse the contact stress between the electrode 4 and the doped semiconductor layer 2 and the passivation antireflection layer 3, thereby improving the connection reliability of the electrode.

[0051] According to an embodiment of this application, the passivation and antireflection layer 3 at both edges of the electrode region 21 has a first corrosion region 31, and a transition region 211 is provided on the side of each of the two first corrosion regions 31 away from the edge of the electrode region 21. This can improve the contact stress balance of the electrode 4 and enhance the connection reliability of the electrode 4.

[0052] To better illustrate the morphology of the electrode region, this application sequentially acid-washes the solar cell with NHNO3-HF-HNO3 solution after removing the electrodes, exposing the doped semiconductor layer 2 and the passivation antireflection layer 3. Figure 3 This is a SEM image of the electrode region of a solar cell according to an embodiment of this application after electrode removal and acid etching, where the dashed line marks the boundary between part of the transition region 211 and the first etched region 31. Figure 2 and Figure 3 As shown, a transition region 211 is provided on the side of the first etched region 31 away from the edge of the electrode region 21. This transition region is a pore-free area, presumably formed due to factors such as the wetting angle of the electrode paste, the distribution of the glass frit, and sintering shrinkage during the solar cell fabrication process. It should be noted that the pore-free area here refers to an area where it is difficult to observe obvious pores, for example, an area where the pore size is all less than 20 nm.

[0053] According to an embodiment of this application, at least a portion of the transition region 211 may be covered or not covered with a passivation antireflection layer 3, and obviously the covered passivation antireflection layer 3 is pore-free or has barely observable pores.

[0054] For example, the width of the transition region 211 is 0% to 35% of the width of the electrode region, such as 0%, 5%, 10%, 15%, 20%, 25%, 30%, etc. If the width of the transition region 211 is too large, the contact space between the electrode 4 and the passivation antireflection layer 3 and the doped semiconductor layer 2 will be small, resulting in a decrease in the tensile strength of the electrode.

[0055] According to an embodiment of this application, for example... Figure 1 , Figure 2 , Figure 3 As shown, electrode region 21 may further include a second etched region 212, located in the middle of electrode region 21, and having multiple second pores 22. The second pores 22 are suitable for accommodating the metal crystal or glass formed after sintering of electrode 4, thereby improving the tensile strength of electrode 4. Simultaneously, by increasing the contact area between electrode 4 and the doped semiconductor layer 2, it helps improve the contact performance between electrode 4 and, consequently, the doped semiconductor layer 2.

[0056] According to an embodiment of this application, the aperture of the second hole 22 is larger than the aperture of the first hole 32. This could mean that the average aperture of the second holes 22 is greater than the average aperture of the first holes 32; or, a certain percentage (e.g., more than 50%, preferably more than 70%, more preferably more than 90%) of the second holes 22 have apertures larger than the maximum aperture of the first holes 32. Thus, a larger aperture of the second holes 22 is beneficial for increasing the contact area between the electrode 4 and the doped semiconductor layer 2, thereby improving the adhesion of the electrode, thus improving electrode connection reliability, and improving contact resistance, thus improving carrier collection capability and battery efficiency. Meanwhile, the relatively smaller aperture of the first holes 32 ensures both the adhesion of the electrode 4 to the passivation and antireflection layer 3 and the structural strength of the passivation and antireflection layer located at the edge of the electrode region, thereby improving the connection reliability of the electrode 4.

[0057] According to the embodiments of this application, the diameter and distribution of the second holes 22 on the second etched region 212 are different for the doped semiconductor layer 2 being an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0058] For example, using the electrode region of the N-type doped semiconductor layer as the first electrode region and the electrode region of the P-type doped semiconductor layer as the second electrode region, the area ratio of the second hole located in the first electrode region on the first electrode region is 0% to 60%, for example, it can be 0%, 10%, 20%, 30%, 40%, 50%, 60%, etc.; or, the area ratio of the second hole located in the second electrode region on the second electrode region is 10% to 90%, for example, it can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, etc. A suitable area ratio of the second hole can balance contact performance and passivation effect.

[0059] Regarding the measurement of the area ratio of the second hole, this application does not impose any restrictions. Those skilled in the art can determine it using conventional methods in the field. For example, at least one area of ​​the same size, such as 4 μm, can be taken from the SEM top view described above. 2 For each region, the area percentage of the second hole observed in each region is calculated. Then, the average area percentage of the second hole in at least one region is calculated, which is the area percentage of the second hole.

[0060] According to the embodiments of this application, the passivation antireflection layer 3 of this application may also include an ablation-affected region 33, located on the side of the first corrosion region 31 near the edge of the electrode region 21. It is mainly the region affected by the sintering and photoinjection process of the electrode 4, which manifests as changes in the surface morphology or microstructure of the material.

[0061] According to embodiments of this application, the contact structure located at the edge of the electrode region described above is applicable to different types of solar cells, such as bifacial cells or back-contact cells. Figure 4 This is a schematic diagram of the overall structure of the back contact battery according to an exemplary embodiment of this application; Figure 5 This is a schematic diagram of the overall structure of a back-contact battery according to another exemplary embodiment of this application; Figure 6 This is a schematic diagram of the overall structure of a bifacial battery according to an exemplary embodiment of this application. Figure 4 and Figure 5 As shown, the conductive region 11 includes an N-region 111 and a P-region 112, which are located on the same surface of the solar cell, thus forming a back-contact cell; or as... Figure 6 As shown, N region 111 and P region 112 are located on different surfaces of the solar cell, that is, two surfaces arranged opposite to each other, thus forming a bifacial cell.

[0062] In one embodiment, the contact structure located at the edge of the electrode region described above is applicable to one of the N-region 111 and the P-region 112, where the doped semiconductor layer 2 can be an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0063] For example, such as Figure 1 and Figure 4 As shown, taking an HPBC (Hybrid Passivated Back Contact) battery as an example, the silicon substrate 1 includes a first surface and a second surface opposite to each other. The conductive region 11 of the silicon substrate 1 includes alternately distributed N-regions 111 and P-regions 112. The tunneling oxide passivation contact structure can be located in the N-region, and the passivated emitter structure can be located in the P-region. In this case, there is no electrode structure on the second surface of the silicon substrate 1, which helps to reduce the shading of the front electrode and thus improve light utilization. The second surface of the silicon substrate 1 can be a textured structure (not shown in the figure).

[0064] Furthermore, the passivated emitter structure includes a doped conductive layer 202 located in the P-region 112 of the silicon substrate 1, and a third passivation antireflection layer 302 located on the doped conductive layer 202. Exemplarily, an aluminum-containing electrode can be fabricated after trenching the third passivation antireflection layer 302, and the silicon substrate in the P-region 112 can be P-type doped using the aluminum-containing electrode to obtain the doped conductive layer 202 on the P-region 112.

[0065] The N-type doped semiconductor layer 201 is located on the N-region 111, and its material can be polycrystalline silicon or microcrystalline silicon. At this time, the first passivation antireflection layer 301 located at the edge of the electrode region 21 of the N-type doped semiconductor layer 201 has a first etched region 31 for contacting the electrode 4. Further, the electrode region 21 also includes a transition region 211 located on the side of the first etched region 31 away from the edge of the electrode region and a second etched region 212 located in the middle of the electrode region 21. The specific structure and morphology of the first etched region 31, the transition region 211, and the second etched region 212 will not be described in detail.

[0066] At this time, the N-type doped semiconductor layer 201 can be prepared by low-temperature chemical vapor deposition (LPCVD), and the thickness can be 100~600nm, for example, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, etc.

[0067] Optionally, the solar cell may further include an interface passivation layer 5 located between the N-type doped semiconductor layer 201 and the silicon substrate 1. This passivation layer selectively passes through majority carriers to achieve a field passivation effect, thereby improving carrier separation and collection. The interface passivation layer 5 may be made of materials such as aluminum oxide, silicon oxide, or titanium oxide, and can form a tunneling oxide passivation contact structure with the N-type doped semiconductor layer 201. The aforementioned material of the interface passivation layer 5 also serves to prevent the electrode 4 from corroding the silicon substrate 1 inward. In this case, the interface passivation layer 5 can be prepared by low-temperature chemical vapor deposition (LPCVD), and its thickness can be 0.5~10 nm, for example, 0.5 nm, 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc.

[0068] In another embodiment, the contact structure located at the edge of the electrode region described above can also be applied to both the N region 111 and the P region 112.

[0069] For example, taking a back-contact battery as an example, such as Figure 1 and Figure 5 As shown, taking a TBC (TopCon-Back Contact) battery as an example, the silicon substrate 1 includes a first surface and a second surface opposite to each other, and N-regions and P-regions can be alternately distributed on the first surface. The doped semiconductor layer 2 may include an N-type doped semiconductor layer 201 and a P-type doped semiconductor layer 203, with the N-type doped semiconductor layer 201 located on the N-region 111 and the P-type doped semiconductor layer 203 located on the P-region 112.

[0070] For example Figure 5 As shown, the TBC battery may further include a first interface passivation layer 501 and a second interface passivation layer 502. Tunneling oxide passivation contact structures are formed between the first interface passivation layer 501 and the N-type doped semiconductor layer 201, and between the second interface passivation layer 502 and the P-type doped semiconductor layer 203, respectively. One of the two tunneling oxide passivation contact structures is a PN junction, and the other is a high-low junction. The two can be further isolated by an isolation region (i.e., an isolation region). The isolation region can be, for example, an isolation trench located between the N region and the P region.

[0071] In the embodiments of this application, the passivation antireflection layer 3 may include a first passivation antireflection layer 301 and a second passivation antireflection layer 303. The first passivation antireflection layer 301 is located on the N-type doped semiconductor layer 201, and the second passivation antireflection layer 303 is located on the P-type doped semiconductor layer 203. In this case, the electrode region of the N-type doped semiconductor layer 201 is considered the first electrode region, and the electrode region of the P-type doped semiconductor layer 203 is considered the second electrode region. The first passivation antireflection layer 301 located at the edge of the first electrode region and the second passivation antireflection layer 303 located at the edge of the second electrode region each have a first etched region 31. Further, the first electrode region and the second electrode region may also include a transition region 211 and a second etched region 212, respectively. The structures of the first etched region 31, the transition region 211, and the second etched region 212 are the same as described above and will not be repeated here.

[0072] In embodiments of this application, the aperture of the first hole 32 located in the first passivation antireflection layer 301 is smaller than the aperture of the first hole 32 located in the second passivation antireflection layer 303. This can be because the average aperture of the first holes in the first passivation antireflection layer 301 is smaller than the average aperture of the first holes in the second passivation antireflection layer 303; or, a certain percentage (e.g., more than 50%, preferably more than 70%, more preferably more than 90%) of the first holes 32 located in the first passivation antireflection layer 301 are smaller than the minimum aperture of the first holes 32 located in the second passivation antireflection layer 303. Exemplarily, the difference between the two can be further selected as 20~100 nm, for example, 20 nm, 30 nm, 45 nm, 50 nm, 75 nm, 80 nm, 95 nm, 100 nm, etc.

[0073] In the embodiments of this application, the distribution density of the first pores on the first corrosion region of the first passivation antireflection layer 301 is greater than the distribution density of the first pores on the first corrosion region of the second passivation antireflection layer 303. Exemplarily, the difference between the two can be further selected as 9 to 20 pores / μm. 2 For example, it could be 9 / μm 2 12 cells / μm 2 14 cells / μm 2 16 cells / μm 2 18 cells / μm 2 20 cells / μm 2 wait.

[0074] Thus, by adjusting the pore size and distribution density of the first pores in the first etched region on the first passivation antireflection layer 301 and the second passivation antireflection layer 303 within the aforementioned range, even with a slight reduction in the width of the first etched region on the P-region, it is beneficial to simultaneously improve the tensile strength of the N-region and P-region electrodes. Furthermore, reducing the width of the first etched region on the P-region helps to reduce recombination losses, thereby further improving the photoelectric conversion efficiency of the battery.

[0075] In embodiments of this application, the silicon substrate 1 includes opposing first and second surfaces, N-regions and P-regions may be alternately distributed on the first surface, and the N-region surface is lower than the P-region surface. Figure 5 (Not shown in the image), thus the upper surface of the N-region electrode is lower than the upper surface of the P-region electrode. Therefore, during the welding process between the cell and the solder ribbon, the tensile force borne by the N-region electrode along the thickness direction of the solar cell is greater than that borne by the P-region electrode in that direction. Thus, by adjusting the pore size and distribution density of the first pores in the first corrosion area of ​​the first passivation antireflection layer 301 and the second passivation antireflection layer 303 within the aforementioned range, i.e., the distribution of small and / or dense first pores in the N-region, the distribution of the first pores in the N-region provides greater adhesion between the electrode and the solar cell than the distribution of the first pores in the P-region, which helps to balance the tensile forces between the P-region and N-region electrodes.

[0076] In the embodiments of this application, the first corrosion region 31 is strip-shaped and extends along the extension direction of the electrode region; along the extension direction perpendicular to the electrode region, the width of the first corrosion region located in the first passivation antireflection layer 301 is different from the width of the first corrosion region located in the second passivation antireflection layer 303.

[0077] In order to reduce the recombination loss in the P-region, the width of the first etched region located in the first passivation antireflection layer 301 can be greater than the width of the first etched region located in the second passivation antireflection layer 303. For example, the difference between the two can be selected as 0.1~2μm, such as 0.1μm, 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1.0μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2.0μm, etc.

[0078] To eliminate the contact difference caused by the lower doping concentration of the P-type doped semiconductor layer compared to the N-type doped semiconductor layer, the width of the first electrode region is smaller than the width of the second electrode region. This reduces the contact resistance between the P-type doped semiconductor layer and the electrode, improves the carrier collection balance between the N and P regions, and increases battery efficiency. For example, the width of the first electrode region can be 20-35 μm, such as 20 μm, 23 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, etc.; the width of the second electrode region can be 25-40 μm, such as 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, etc.; the difference between the two can further be selected as 5-15 μm, such as 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, etc.

[0079] In embodiments of this application, the area ratio of the second hole located in the first electrode region on the first electrode region is smaller than that of the second hole located in the second electrode region on the second electrode region. For example, the difference can be 10% to 30%. By controlling the area ratio of the second hole located in the second electrode region to be larger, when the P-type doped semiconductor layer 203 has a lower doping concentration and higher contact resistance than the N-type doped semiconductor layer 201, it is beneficial to further improve the contact performance between the P-type doped semiconductor layer 203 and the P-region electrode, thereby facilitating a balance in carrier transport between the N-region and P-region.

[0080] Of course, this application is not limited to the aforementioned TBC battery; the solar cell can also be a TOPCon battery, such as... Figure 1 and Figure 6 As shown, a TOPCon cell with a tunneling oxide passivation contact structure on one side is illustrated. The main difference between it and a TBC cell is that the N region 111 is located on the first surface of the silicon substrate 1, the P region 112 is located on the second surface of the silicon substrate 1, the tunneling oxide passivation contact structure is located in the N region 111, and the passivated emitter structure is located in the P region 112.

[0081] The tunneling oxide passivation contact structure includes an N-type doped semiconductor layer 201 located in the N-region 111, which can be made of polycrystalline silicon or microcrystalline silicon; and a first passivation antireflection layer 301 located on the N-type doped semiconductor layer 201. The passivated emitter structure includes a P-type doped semiconductor layer 203 located in the P-region 112, and a second passivation antireflection layer 303 located on the P-type doped semiconductor layer 203. The P-type doped semiconductor layer 203 can be obtained in the P-region 112 by boron diffusion doping.

[0082] Of course, it's not limited to this; it can also include, for example... Figure 6The passivated emitter structure in P region 112 shown is replaced with another tunneling oxide passivation contact structure, specifically including a P-type doped semiconductor layer 203 on P region 112, which can be made of polycrystalline silicon or microcrystalline silicon, etc., and another interface passivation layer on P-type doped semiconductor layer 203. The corresponding solar cell is a TOPCon cell with tunneling oxide passivation contact structure on both sides.

[0083] At this time, the electrode region of the N-type doped semiconductor layer 201 is also taken as the first electrode region, and the electrode region of the P-type doped semiconductor layer 203 is taken as the second electrode region. The first passivation antireflection layer 301 located at the edge of the first electrode region and the second passivation antireflection layer 303 located at the edge of the second electrode region each have a first etched region 31. In the embodiments of this application, the first electrode region and the second electrode region may respectively include a transition region 211 and a second etched region 212. The structures of the first etched region 31, the transition region 211 and the second etched region 212 are the same as described above, and will not be repeated here.

[0084] In embodiments of this application, a photovoltaic module is provided, including a cell string comprising the aforementioned solar cells; and a plurality of solder ribbons, wherein the solder ribbons connect at least two adjacent solar cells. By forming a first etched region suitable for contact with the electrode on the passivation antireflection layer at the edge of the electrode region in the solar cell, the porous structure of the first etched region can increase the contact area between the electrode edge and the passivation antireflection layer, thereby improving the adhesion of the electrode. During the connection process between the solar cell and the solder ribbons, the solder ribbons contact the electrode, and the electrode has good adhesion, meaning that the electrode has good tensile strength after connection with the solder ribbons, thus improving the reliability of the connection between the solder ribbons and the solar cell.

[0085] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, characterized by, The solar cell comprises: a silicon substrate comprising a surface with a conductive region; a doped semiconductor layer on the conductive region of the silicon substrate, the doped semiconductor layer comprising an electrode region; a passivation anti-reflection layer on the surface of the doped semiconductor layer away from the silicon substrate; an electrode on the passivation anti-reflection layer, the electrode being in contact with part of the passivation anti-reflection layer and the electrode region; wherein the passivation anti-reflection layer at the edge of the electrode region has a first etching region, the first etching region having a plurality of first holes distributed in the extension direction of the electrode and the width direction of the electrode, the electrode region comprising a second etching region at the middle of the electrode region, the second etching region having a plurality of second holes distributed in the extension direction of the electrode and the width direction of the electrode; the doped semiconductor layer comprises an N-type doped semiconductor layer, the first holes of the passivation anti-reflection layer on the N-type doped semiconductor layer having a pore size of 20-300 nm; and / or the doped semiconductor layer comprises a P-type doped semiconductor layer, the first holes of the passivation anti-reflection layer on the P-type doped semiconductor layer having a pore size of 40-400 nm.

2. The solar cell according to claim 1, characterized in that, The electrode region comprises a transition region without holes, the transition region being on one side of the first etching region away from the edge of the electrode region.

3. The solar cell according to claim 1, characterized in that, At least part of the plurality of first holes are blind holes, and / or the distribution density of the blind holes is 1-40 / μm 2 .

4. The solar cell of claim 1, wherein The second holes have a larger pore size than the first holes.

5. The solar cell of claim 1, wherein The conductive region comprises an N region and a P region, which are respectively on the same surface or different surfaces of the solar cell; The doped semiconductor layer comprises an N-type doped semiconductor layer and a P-type doped semiconductor layer, the N-type doped semiconductor layer being on the N region and the P-type doped semiconductor layer being on the P region; the electrode region of the N-type doped semiconductor layer is a first electrode region, and the electrode region of the P-type doped semiconductor layer is a second electrode region, the area ratio of the second holes in the first electrode region on the first electrode region being less than the area ratio of the second holes in the second electrode region on the second electrode region.

6. The solar cell of claim 5, wherein: the area ratio of the second holes in the first electrode region on the first electrode region is 0-60%, and the area ratio of the second holes in the second electrode region on the second electrode region is 10%-90%; and / or the difference between the area ratio of the second holes in the first electrode region on the first electrode region and the area ratio of the second holes in the second electrode region on the second electrode region is 10%-30%. The conductive region comprises an N region and a P region, which are respectively on the same surface or different surfaces of the solar cell; 7. The solar cell of claim 1, wherein The passivation anti-reflection layer comprises a first passivation anti-reflection layer and a second passivation anti-reflection layer, the first passivation anti-reflection layer being on the doped semiconductor layer of the N region and the second passivation anti-reflection layer being on the doped semiconductor layer of the P region; and the first etching region is in the form of a strip extending along the extension direction of the electrode region. ​ The width of the first etching region of the first passivation anti-reflection layer is different from the width of the first etching region of the second passivation anti-reflection layer along the direction perpendicular to the extension direction of the electrode region.

8. The solar cell of claim 7, wherein, The width of the first etching region of the first passivation anti-reflection layer is greater than the width of the first etching region of the second passivation anti-reflection layer.

9. The solar cell of claim 1, wherein, The conductive region includes an N region and a P region, which are located on the same surface or different surfaces of the solar cell, respectively. The passivation anti-reflection layer includes a first passivation anti-reflection layer and a second passivation anti-reflection layer, the first passivation anti-reflection layer is located on the doped semiconductor layer of the N region, and the second passivation anti-reflection layer is located on the doped semiconductor layer of the P region. The distribution density of the first holes in the first etching region of the first passivation anti-reflection layer is greater than the distribution density of the first holes in the first etching region of the second passivation anti-reflection layer.

10. The solar cell of claim 1, wherein, The conductive region includes an N region and a P region, which are located on the same surface or different surfaces of the solar cell, respectively. The doped semiconductor layer includes an N-type doped semiconductor layer and a P-type doped semiconductor layer, the N-type doped semiconductor layer is located on the N region, and the P-type doped semiconductor layer is located on the P region. The electrode region of the N-type doped semiconductor layer is a first electrode region, and the electrode region of the P-type doped semiconductor layer is a second electrode region, the width of the first electrode region is less than the width of the second electrode region.

11. A photovoltaic module, characterized by It includes: A cell string, the cell string includes the solar cell according to any one of claims 1 to 10; A plurality of solder strips, the solder strips are connected to at least two adjacent solar cells.

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