Flip light emitting diode chip and preparation method thereof

Abstract

The invention provides a flip light-emitting diode chip and a preparation method thereof, and the method comprises the steps: providing a substrate for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer on the substrate; preparing a first semiconductor layer; preparing a Bragg reflection layer and a Bragg reflection layer through hole; preparing a current blocking layer through hole; preparing a metal reflecting layer; preparing a first insulating layer and a first insulating layer through hole; preparing a connecting electrode; preparing a second insulating layer and a second insulating layer through hole; and preparing a bonding pad layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a flip-chip light emitting diode chip and a preparation method thereof. Background Art

[0002] In recent years, the light-emitting diode chip technology has developed rapidly under the competition of major manufacturers and has been widely used in various fields such as general lighting, special lighting, direct display screens, backlight display screens, and car lights.

[0003] In the prior art, existing flip-chip LED chips have also begun to be used in car lamp applications. Car lamp applications require chips to have extremely strong thrust to ensure long-term use and shock resistance. However, existing flip-chip LED chips are used in the field of general lighting and have relatively low thrust requirements. How to improve the thrust of existing flip-chip LED chips so that they can be used in car lamp chips is an issue that needs to be explored. Summary of the invention

[0004] Based on this, the purpose of the present invention is to provide a flip-chip light emitting diode chip and a preparation method thereof, which can effectively solve the deficiencies in the above-mentioned prior art.

[0005] A flip-chip light emitting diode chip, comprising: A substrate and an N-type semiconductor layer, an active light-emitting layer, a P-type semiconductor layer, a first semiconductor layer, a Bragg reflection layer, a Bragg reflection layer through hole, a current blocking layer through hole, a metal reflection layer, a first insulating layer, a first insulating layer through hole, a connecting electrode, a second insulating layer, a second insulating layer through hole and a pad layer sequentially prepared on the substrate; The pad layer includes an N-type pad layer and a P-type pad layer, and the N-type pad and the P-type pad each include a stack consisting of a layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal arranged in sequence, wherein the thickness of each group of AuSn alloy metal in the stack is the same and the Au metal in the stack decreases by 5%-15% layer by layer from bottom to top.

[0006] Furthermore, the sum of the thickness of the AuSn alloy metal in the stack is between 3um and 5um.

[0007] Furthermore, the mass ratio of the AuSn alloy metal in the stack is between 75:25 and 80:20.

[0008] Furthermore, the thickness of the Au metal in the group of the stacked layers closest to the Ni metal is 60%-100% of the thickness of the AuSn alloy metal.

[0009] Furthermore, the higher the mass ratio of the AuSn alloy metal is, the lower the ratio of the Au metal thickness closest to the Ni metal in the stack to the AuSn alloy metal thickness is, and the smaller the reduction of the Au metal in the stack from bottom to top is.

[0010] Furthermore, the more layers the stack has, the smaller the reduction of the Au metal in the stack from bottom to top.

[0011] On the other hand, the present invention also provides a method for preparing a flip-chip light-emitting diode chip, the method comprising the following steps: S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; S2, preparing a first semiconductor layer on the P-type semiconductor layer; S3, preparing a Bragg reflection layer and a Bragg reflection layer through hole on the first semiconductor layer; S4, preparing a current blocking layer through hole on the Bragg reflection layer and the Bragg reflection layer through hole; S5, preparing a metal reflection layer on the Bragg reflection layer, the Bragg reflection layer through hole, the current blocking layer through hole, and the location where the current blocking layer through hole is exposed; S6, preparing a first insulating layer and a first insulating layer through hole on the metal reflective layer and at a place not covered by the metal reflective layer; S7, preparing connecting electrodes on the first insulating layer and the through holes of the first insulating layer; S8, preparing a second insulating layer and a second insulating layer through hole on the connecting electrode and at a place not covered by the connecting electrode; S9, preparing a pad layer on the second insulating layer and the through hole of the second insulating layer; Among them, the pad layer includes an N-type pad layer and a P-type pad layer, and the N-type pad and the P-type pad both include a stack consisting of a layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal arranged in sequence, in which the thickness of each group of AuSn alloy metal is the same and the Au metal in the stack is reduced by 5%-15% layer by layer from bottom to top.

[0012] Furthermore, the first semiconductor layer includes an N-type conductive step, a current spreading layer and a current blocking layer which are sequentially arranged from bottom to top.

[0013] Furthermore, the specific process for preparing the first semiconductor layer includes: A photoresist is coated on the surface of the P-type semiconductor layer, and then a part of the photoresist is removed by exposure and development process to expose a part of the P-type semiconductor layer, and then an inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer below the part of the P-type semiconductor layer to form the N-type conductive step, and then the photoresist is removed; indium tin oxide is deposited on the surface of the P-type semiconductor layer and the N-type conductive step by magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide, and then a part of the photoresist is removed by exposure and development to expose a part of the indium tin oxide, and then an indium tin oxide etching solution is used to remove the exposed indium tin oxide, and then the photoresist is removed to form the current spreading layer; SiO2 is deposited on the surface of the P-type semiconductor layer, the N-type conductive step and the current spreading layer by PECVD process as the current blocking layer.

[0014] Furthermore, the specific process of preparing the pad layer includes: A layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal stacks are sequentially deposited on the second insulating layer and the through holes of the second insulating layer using an electron beam evaporation process, and then the metal on the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form a pad layer, which includes an N-type pad layer and a P-type pad layer.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: both the N-type pad and the P-type pad include a layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal stacks arranged in sequence, and the thickness of each group of AuSn alloy metal in the stack is the same, and the Au metal in the stack is reduced by 5%-15% layer by layer from bottom to top. Such an arrangement enables the flip-chip light-emitting diode chip to obtain a uniform eutectic structure composed of Au metal and Sn metal after high-temperature reflow, which can greatly improve the thrust of the flip-chip light-emitting diode chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a flow chart of a method for preparing a flip-chip light-emitting diode chip in Example 1 of the present invention; Figure 2 is a cross-sectional schematic diagram of a flip-chip light-emitting diode chip in Embodiment 1 of the present invention; Figure 3 It is the thrust value test table in the present invention; Description of main component symbols:

[0017] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0018] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0019] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0021] Example 1 See also Figure 1 to Figure 2 The method for preparing a flip-chip light-emitting diode chip in an embodiment of the present invention comprises: S1, providing a substrate 10 required for growth, and sequentially depositing an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10; The substrate 10 may be a GaN substrate, an Al2O3 substrate or a Si substrate.

[0022] S2, preparing a first semiconductor layer on the P-type semiconductor layer 113; Furthermore, the first semiconductor layer includes an N-type conductive step 114 , a current spreading layer 12 , and a current blocking layer 13 which are sequentially arranged from bottom to top.

[0023] Furthermore, the specific process for preparing the first semiconductor layer includes: A photoresist is coated on the surface of the P-type semiconductor layer 113, and then a part of the photoresist is removed by exposure and development processes to expose a part of the P-type semiconductor layer. Then, the exposed P-type semiconductor layer and the active light-emitting layer below the part of the P-type semiconductor layer are removed by inductively coupled plasma etching process to form the N-type conductive step 114, and then the photoresist is removed; indium tin oxide is deposited on the surface of the P-type semiconductor layer 113 and the N-type conductive step 114 by magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide, and then a part of the photoresist is removed by exposure and development to expose a part of the indium tin oxide, and then the exposed indium tin oxide is removed by indium tin oxide etching solution, and then the photoresist is removed to form the current spreading layer 12; SiO2 is deposited on the surface of the P-type semiconductor layer 113, the N-type conductive step 114 and the current spreading layer 12 by PECVD process as the current blocking layer 13.

[0024] S3, preparing a Bragg reflection layer 14 and a Bragg reflection layer through hole on the first semiconductor layer; Furthermore, the specific process of preparing the Bragg reflection layer 14 and the Bragg reflection layer through hole includes: 2-10 groups of TiO2 and SiO2 stacks are deposited on the surface of the current blocking layer 13 by electron beam evaporation process as the Bragg reflection layer 14, then photoresist is coated on the surface of the Bragg reflection layer 14, and then the photoresist on part of the Bragg reflection layer is removed by exposure and development, and then the exposed Bragg reflection layer is removed by inductively coupled plasma etching process to form the Bragg reflection layer through hole, exposing the current blocking layer under the part of the Bragg reflection layer through hole, and then the photoresist is removed, and the Bragg reflection layer through hole includes a P-type Bragg reflection layer through hole 141 and an N-type Bragg reflection layer through hole 142.

[0025] S4, preparing a current blocking layer through hole on the Bragg reflection layer 14 and the Bragg reflection layer through hole; Furthermore, the specific process for preparing the current blocking layer through hole is: Photoresist is coated on the surface of the Bragg reflection layer 14 and the Bragg reflection layer through hole, and then the photoresist in part of the Bragg reflection layer through hole is removed by exposure and development to expose the current blocking layer under the Bragg reflection layer through hole, and then the exposed current blocking layer is removed by BOE etching solution to form a current blocking layer through hole, and then the photoresist is removed, and the current blocking layer through hole includes a P-type current blocking layer through hole 131 and an N-type current blocking layer through hole 132.

[0026] S5, preparing a metal reflection layer 15 on the Bragg reflection layer 14, the Bragg reflection layer through hole, the current blocking layer through hole, and the exposed area of ​​the current blocking layer through hole; Furthermore, the specific process for preparing the metal reflective layer 15 is as follows: Photoresist is coated on the Bragg reflection layer 14, the Bragg reflection layer through hole, the current blocking layer through hole and the exposed portion of the current blocking layer through hole, and then part of the photoresist is removed by exposure and development, and then Ag metal, Ni metal, Ti metal, Pt metal and Ti metal are sequentially evaporated by electron beam evaporation process as the metal reflection layer 15, and then the metal located on the photoresist is removed by blue film stripping process, and then the photoresist is removed.

[0027] S6, preparing a first insulating layer 16 and a first insulating layer through hole on the metal reflective layer 15 and at a place not covered by the metal reflective layer 15; Furthermore, the specific process of preparing the first insulating layer 16 and the first insulating layer through hole is: An AL203 film is prepared on the metal reflective layer 15 and the area not covered by the metal reflective layer 15 by atomic layer deposition technology, and then a SiO2 film is prepared on the AL203 film by PECVD process, and the AL2O3 film and the SiO2 film together constitute the first insulating layer 16, and then a positive photoresist is coated on the surface of the first insulating layer 16, and then exposed and developed to form photoresist openings, exposing the first insulating layer under the photoresist openings, and then BOE etching solution is used to etch away the exposed first insulating layer to form first insulating layer through holes, and the first insulating layer through holes include P-type first insulating layer through holes 161 and N-type first insulating layer through holes 162.

[0028] S7, preparing connecting electrodes on the first insulating layer 16 and the through holes of the first insulating layer; Furthermore, the specific process for preparing the connecting electrode is: Negative photoresist is coated on the first insulating layer and the through holes of the first insulating layer, and then exposed and developed to remove part of the photoresist. Then, Cr metal, Al metal, Ti metal, Pt metal, Ti metal, Ni metal and Ti metal are sequentially evaporated using an electron beam evaporation process as the connecting electrodes, and the connecting electrodes include a P-type connecting electrode 171 and an N-type connecting electrode 172.

[0029] S8, preparing a second insulating layer 18 and a second insulating layer through hole on the connecting electrode and at a place not covered by the connecting electrode; Furthermore, the specific process for preparing the second insulating layer 18 and the through hole of the second insulating layer is: SiO2 is deposited as the second insulating layer 18 on the connecting electrode and the area not covered by the connecting electrode using a PECVD process, and then a negative photoresist is coated on the surface of the second insulating layer 18, and then a portion of the photoresist is removed by exposure and development to expose a portion of the second insulating layer, and then the exposed second insulating layer is removed by an inductively coupled plasma etching process to form a second insulating layer through hole, wherein the second insulating layer through hole includes a P-type second insulating layer through hole 181 and an N-type second insulating layer through hole 182.

[0030] S9, using an electron beam evaporation process to sequentially deposit a layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal stacks on the second insulating layer 18 and the second insulating layer through hole, and then using a Lift-Off process to remove the metal on the photoresist, and then remove the photoresist to form a pad layer, wherein the pad layer includes an N-type pad layer 192 and a P-type pad layer 191; Wherein, the thickness of each group of AuSn alloy metals in the stack is the same, the sum of the thickness of the AuSn alloy metals in the stack is between 3um and 5um, and the mass ratio of the AuSn alloy metals in the stack is between 75:25 and 80:20; The thickness of the Au metal closest to the Ni metal in the stack is 60%-100% of the thickness of the AuSn alloy metal, and the Au metal in the stack decreases by 5%-15% layer by layer from bottom to top; The higher the mass ratio of the AuSn alloy metal, the lower the ratio of the Au metal thickness closest to the Ni metal in the stack to the AuSn alloy metal thickness, and the smaller the reduction of the Au metal in the stack from bottom to top. The more layers the stack has, the smaller the reduction of the Au metal in the stack from bottom to top.

[0031] Specifically, in this embodiment, the number of stacked layers is 3, the thickness of the Ti metal in the stack is 0.1um, the thickness of the Ni metal in the stack is 0.2um, the thickness of the AuSn alloy metal in the stack is 1um, the mass ratio of the AuSn alloy metal in the stack is 75:15, and the thickness of the Au metal in the stack from bottom to top is 1um, 0.85um and 0.6um.

[0032] It can be understood that by using the electron beam evaporation process to sequentially evaporate a layer of Ti metal, a layer of Ni metal, and a stack consisting of 3 groups of Au metal and AuSn alloy metal on the second insulating layer 18 and the through hole of the second insulating layer, and the thickness of each group of AuSn alloy metal in the stack is the same, and the Au metal in the stack is reduced by 5%-15% layer by layer from bottom to top, such an arrangement enables the flip-chip light-emitting diode chip to obtain a uniform eutectic structure composed of Au metal and Sn metal after high-temperature reflow, which can greatly improve the thrust of the flip-chip light-emitting diode chip.

[0033] See also Figure 2 , which is a cross-sectional schematic diagram of a flip-chip light-emitting diode chip prepared by the method for preparing a flip-chip light-emitting diode chip in Example 1 of the present invention.

[0034] Example 2 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: Specifically, in this embodiment, the number of stacked layers is 5, the thickness of the AuSn alloy metal in the stacked layers is 0.6 um, and the thickness of the Au metal in the stacked layers is 0.6 um, 0.55 um, 0.51 um, 0.47 um and 0.43 um from bottom to top.

[0035] Example 3 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: The thickness of the AuSn alloy metal in the stack is 1 um, the mass ratio of the AuSn alloy metal in the stack is 75:15, and the thickness of the Au metal in the stack is 1 um, 0.85 um and 0.6 um from bottom to top.

[0036] Specifically, in the present embodiment, the mass ratio of the AuSn alloy metal in the stack is 80:20, and the thickness of the Au metal in the stack is 0.6 um, 0.5 um and 0.4 um from bottom to top.

[0037] Example 4 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: Specifically, in this embodiment, the number of stacked layers is 5, the thickness of the AuSn alloy metal in the stacked layers is 0.6um, the mass ratio of the AuSn alloy metal in the stacked layers is 80:20, and the thickness of the Au metal in the stacked layers is 0.36um, 0.33um, 0.3um, 0.27um and 0.24um from bottom to top.

[0038] Comparative Example 1 A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that: Specifically in this comparative example, the specific process for preparing the pad layer is: A layer of Ti metal, a layer of Ni metal and a layer of AuSn alloy metal are sequentially evaporated on the second insulating layer and the through hole of the second insulating layer using an electron beam evaporation process, and then the metal on the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form a pad layer, which includes an N-type pad layer and a P-type pad layer.

[0039] Specifically, in this comparative example, the thickness of the Ti metal is 0.1 um, the thickness of the Ni metal is 0.2 um, the thickness of the AuSn alloy metal is 4 um, and the mass ratio of the AuSn alloy metal in the stack is 80:20.

[0040] See also Figure 3 Based on the flip-chip light-emitting diode chips prepared in the above-mentioned embodiments 1, 2 and 3 and the flip-chip light-emitting diode chip in comparative example 1, the flip-chip light-emitting diode chips prepared in embodiments 1, 2 and 3 and the flip-chip light-emitting diode chip in comparative example 1 were subjected to thrust value tests, and the corresponding test results are shown in the following table:

[0041] In summary, in the flip-chip light-emitting diode chip and the preparation method thereof in the above-mentioned embodiments of the present invention, both the N-type pad and the P-type pad include a layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal stacks arranged in sequence, and the thickness of each group of AuSn alloy metal in the stack is the same, and the Au metal in the stack is reduced by 5%-15% layer by layer from bottom to top. Such an arrangement enables the flip-chip light-emitting diode chip to obtain a uniform eutectic structure composed of Au metal and Sn metal after high-temperature reflow, which can greatly improve the thrust of the flip-chip light-emitting diode chip.

[0042] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0043] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A flip-chip light emitting diode chip, characterized in that: include: A substrate and an N-type semiconductor layer, an active light-emitting layer, a P-type semiconductor layer, a first semiconductor layer, a Bragg reflection layer, a Bragg reflection layer through hole, a current blocking layer through hole, a metal reflection layer, a first insulating layer, a first insulating layer through hole, a connecting electrode, a second insulating layer, a second insulating layer through hole and a pad layer sequentially prepared on the substrate; The pad layer includes an N-type pad layer and a P-type pad layer, and the N-type pad and the P-type pad each include a stack consisting of a layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal arranged in sequence, wherein the thickness of each group of AuSn alloy metal in the stack is the same and the Au metal in the stack decreases by 5%-15% layer by layer from bottom to top.

2. The flip-chip light emitting diode chip according to claim 1, characterized in that: The sum of the thickness of the AuSn alloy metal in the stack is between 3um and 5um.

3. The flip-chip light emitting diode chip according to claim 1, characterized in that: The mass ratio of the AuSn alloy metal in the stack is between 75:25 and 80:

20.

4. The flip-chip light emitting diode chip according to claim 3, characterized in that: The thickness of the Au metal in the group closest to the Ni metal in the stack is 60%-100% of the thickness of the AuSn alloy metal.

5. The flip-chip light emitting diode chip according to claim 4, characterized in that: The higher the mass ratio of the AuSn alloy metal is, the lower the ratio of the Au metal thickness closest to the Ni metal in the stack to the AuSn alloy metal thickness is, and the smaller the reduction of the Au metal in the stack from bottom to top is.

6. The flip-chip light emitting diode chip according to claim 1, characterized in that: The more layers the stack has, the smaller the reduction of the Au metal in the stack from bottom to top.

7. A method for preparing a flip-chip light-emitting diode chip, characterized in that: The preparation method comprises: S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; S2, preparing a first semiconductor layer on the P-type semiconductor layer; S3, preparing a Bragg reflection layer and a Bragg reflection layer through hole on the first semiconductor layer; S4, preparing a current blocking layer through hole on the Bragg reflection layer and the Bragg reflection layer through hole; S5, preparing a metal reflection layer on the Bragg reflection layer, the Bragg reflection layer through hole, the current blocking layer through hole, and the location where the current blocking layer through hole is exposed; S6, preparing a first insulating layer and a first insulating layer through hole on the metal reflective layer and at a place not covered by the metal reflective layer; S7, preparing connecting electrodes on the first insulating layer and the through holes of the first insulating layer; S8, preparing a second insulating layer and a second insulating layer through hole on the connecting electrode and at a place not covered by the connecting electrode; S9, preparing a pad layer on the second insulating layer and the through hole of the second insulating layer; Among them, the pad layer includes an N-type pad layer and a P-type pad layer, and the N-type pad and the P-type pad both include a stack consisting of a layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal arranged in sequence, in which the thickness of each group of AuSn alloy metal is the same and the Au metal in the stack is reduced by 5%-15% layer by layer from bottom to top.

8. The method for preparing a flip-chip light emitting diode chip according to claim 7, characterized in that: The first semiconductor layer includes an N-type conductive step, a current spreading layer and a current blocking layer which are sequentially arranged from bottom to top.

9. The method for preparing a flip-chip light emitting diode chip according to claim 8, characterized in that: The specific process of preparing the first semiconductor layer includes: A photoresist is coated on the surface of the P-type semiconductor layer, and then a part of the photoresist is removed by exposure and development process to expose a part of the P-type semiconductor layer, and then an inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer below the part of the P-type semiconductor layer to form the N-type conductive step, and then the photoresist is removed; indium tin oxide is deposited on the surface of the P-type semiconductor layer and the N-type conductive step by magnetron sputtering process, and then a photoresist is coated on the surface of the indium tin oxide, and then a part of the photoresist is removed by exposure and development to expose a part of the indium tin oxide, and then an indium tin oxide etching solution is used to remove the exposed indium tin oxide, and then the photoresist is removed to form the current spreading layer; SiO2 is deposited on the surface of the P-type semiconductor layer, the N-type conductive step and the current spreading layer by PECVD process as the current blocking layer.

10. The method for preparing a flip-chip light emitting diode chip according to claim 7, characterized in that: The specific process of preparing the pad layer includes: A layer of Ti metal, a layer of Ni metal, and 3-5 groups of Au metal and AuSn alloy metal stacks are sequentially deposited on the second insulating layer and the through holes of the second insulating layer using an electron beam evaporation process, and then the metal on the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form a pad layer, which includes an N-type pad layer and a P-type pad layer.

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