Polycrystalline integrated device and manufacturing method thereof, display panel

Abstract

The present application relates to a kind of polycrystalline integrated device and its manufacturing method, display panel.The method comprises: providing a support substrate;Form a temporary layer on the support substrate;On the temporary layer, metal wiring process is carried out to obtain a conductive wiring layer;At least three different colors of light emitting chip is transferred to the conductive wiring layer respectively, and is bonded with the conductive wiring layer respectively;Fill a light barrier between adjacent light emitting chip;And dissociate the temporary layer to expose the conductive wiring layer.The polycrystalline integrated device prepared by the method is compared with prior art, the thickness is obviously reduced, so as to avoid the problem of inverted crystal in the process of testing and die bonding.In addition, in product application end, thinner polycrystalline integrated device means that thinner and higher PPI display device can be produced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a polycrystalline integrated device, a manufacturing method thereof, and a display panel. BACKGROUND

[0002] Compared with other display technologies (LCD, PDP, OLED, etc.), Micro / Mini LED technology has the advantages of high brightness, high contrast, wide color gamut, large viewing angle, low power consumption, long service life, and ultra-thin flexible display, and is considered to be the ultimate technology for future display.

[0003] MIP (Micro LED In Package, package architecture based on micro-scale light-emitting diodes) is a combination of Micro-LED chips and high-precision carrier boards to achieve fan-out packaging, which can reduce the difficulty of testing and the difficulty of downstream mounting. MIP devices can achieve full testing, sorting, and mixed Bin of RGB Micro pixels, and can achieve high display consistency of the panel.

[0004] However, to make the MIP device smaller, the substrate and the packaging layer need to be made thinner, but it is difficult to make a BT (Bismaleimide Triazine, bismaleimide triazine) substrate very thin. The MIP device with an excessively thick substrate will have a reverse crystal problem during subsequent testing and die bonding processes. After the glass substrate and the sapphire substrate are made thin, the substrate is prone to breakage during subsequent processes. SUMMARY

[0005] In view of the deficiencies of the prior art described above, the purpose of the present application is to provide a polycrystalline integrated device, a manufacturing method thereof, and a display panel, which aims to solve the problem of excessively large size of the existing MIP device.

[0006] A manufacturing method of a polycrystalline integrated device, comprising:

[0007] providing a support substrate;

[0008] forming a temporary layer on the support substrate;

[0009] performing a metal wiring process on the temporary layer to obtain a conductive wiring layer;

[0010] transferring at least three light-emitting chips of different colors to the conductive wiring layer, respectively, and bonding the light-emitting chips to the conductive wiring layer, respectively;

[0011] filling a light-blocking layer between adjacent light-emitting chips; and

[0012] dissociating the temporary layer to expose the conductive wiring layer.

[0013] The polycrystalline integrated device prepared by the method is prepared by first preparing a temporary layer on a support substrate, then preparing a conductive wiring layer on the temporary layer, then transferring a plurality of light-emitting chips of different colors to the conductive wiring layer for bonding, and then filling a light-blocking layer between adjacent light-emitting chips, so that the plurality of light-emitting chips are integrated together. Finally, the temporary layer is dissociated, which means that the support substrate bonded with the temporary layer is also removed, and the polycrystalline integrated device prepared accordingly has a thickness less than that of the existing scheme, so that the thickness of the polycrystalline integrated device of the present application is obviously reduced, thereby avoiding the problems of easy breakage of the traditional substrate and the problem of inverted crystal in the testing and die bonding process of the traditional polycrystalline integrated device. In addition, at the product application end, the thinner polycrystalline integrated device means that a thinner and higher PPI display device can be produced.

[0014] In one embodiment, the conductive wiring layer comprises a first wiring and at least three second wirings; the first wiring is electrically connected with the first electrode of each light-emitting chip, and one second wiring is connected with the second electrode of one light-emitting chip.

[0015] In one embodiment, the conductive wiring layer further comprises a first pad and at least three second pads; the first pad is connected with the first wiring, and one second pad is connected with one second wiring.

[0016] In one embodiment, after the step of filling a light-blocking layer between adjacent light-emitting chips, the method further comprises:

[0017] forming a packaging layer on the surface of each light-emitting chip and the light-blocking layer.

[0018] In one embodiment, the method further comprises:

[0019] patterning the light-blocking layer to expose the side surface of the light-emitting chip; wherein the packaging layer is also filled in the side surface of the light-emitting chip.

[0020] In one embodiment, the metal wiring process comprises any one of the following ways:

[0021] way one: forming a metal layer on the temporary layer;

[0022] performing a patterning process on the metal layer to form the conductive wiring layer;

[0023] way two: forming a sacrificial layer on the temporary layer;

[0024] performing a patterning process on the sacrificial layer to partially expose the temporary layer; wherein the pattern of the exposed temporary layer is the same as the pattern of the conductive wiring layer;

[0025] evaporating a metal layer on the exposed surface of the temporary layer to form the conductive wiring layer;

[0026] removing the sacrificial layer.

[0027] In one embodiment, the metal layer comprises a single layer metal structure or a multi-layer metal stack structure.

[0028] In one embodiment, the material of the metal layer comprises any one of copper, aluminum, titanium, chromium, platinum, gold.

[0029] In one embodiment, further comprising:

[0030] removing the dissociated material remained on the surface of the conductive wiring layer.

[0031] In one embodiment, the temporary layer comprises any one of gallium nitride, benzocyclobutene, polyimide, graphite, boron nitride, poly-p-phenylene benzobisoxazole and organic material.

[0032] Based on the same inventive concept, the present application further provides a polycrystalline integrated device, which is prepared by the method for preparing a polycrystalline integrated device as described above.

[0033] Compared with the conventional scheme, the polycrystalline integrated device has no supporting substrate and is thinner, and can avoid the problems of easy breakage of the conventional substrate and inverted crystal in the testing and die bonding process of the conventional polycrystalline integrated device. In addition, at the product application end, the thinner polycrystalline integrated device means that a thinner and higher PPI display device can be produced.

[0034] Based on the same inventive concept, the present application further provides a display panel, which comprises a driving substrate and a polycrystalline integrated device as described above; wherein the driving substrate is electrically connected with the polycrystalline integrated device.

[0035] The display panel has a thinner thickness and a higher PPI due to the use of the polycrystalline integrated device as described above. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A flowchart of the method for preparing a polycrystalline integrated device in one embodiment;

[0037] Figure 2 A flowchart of the method for preparing a polycrystalline integrated device in another embodiment;

[0038] Figure 3 A flowchart of the method for preparing a polycrystalline integrated device in another embodiment; Figure 1 A flowchart of the sub-steps of step S300 in the method for preparing a polycrystalline integrated device;

[0039] Figure 4 For Figure 1 The sub-step flow chart of step S300 in the embodiment;

[0040] Figures 5 to 10b For Figure 1 The structural change diagram corresponding to the method step in the embodiment;

[0041] Figure 11 For Figure 1 The structural change diagram corresponding to the implementation scheme of step S300 in the embodiment;

[0042] Figure 12 For Figure 1 The structural change diagram corresponding to another implementation scheme of step S300 in the embodiment.

[0043] Explanation of reference signs:

[0044] ST - support substrate; 110 - temporary layer; 120 - conductive wiring layer; P1 - first pad; P2 - second pad; S1 - first wiring; S2 - second wiring; R - red light chip; G - green light chip; B - blue light chip; 130 - light barrier layer; 140 - encapsulation layer; MT - metal layer; PR1 - first photoresist; PR2 - second photoresist; 150 - sacrificial layer. DETAILED DESCRIPTION

[0045] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application.

[0047] It will be understood that the spatially relative terms "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device is inverted or flipped over, a lower surface or element can become an upper surface or element, and vice versa. Accordingly, the exemplary term "below" or "under" can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0048] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "comprises" and / or "comprising", and / or the like, when used in this specification, can indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0049] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0050] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation was made. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0051] Micro / Mini LED technology has high brightness, high contrast, wide color gamut, large viewing angle, low power consumption, long life, ultra-thin flexible display and other advantages compared with other existing display technologies (LCD, PDP, OLED, etc.), and is considered as the ultimate technology of future display.

[0052] MIP (Micro LED In Package, package architecture based on micro light emitting diode) is to combine Micro-LED chips and high-precision carrier boards to realize fan-out packaging, which can reduce the difficulty of testing and the difficulty of downstream mounting. MIP devices can achieve full testing, sorting and mixing of RGB Micro pixels, and can make the display consistency of the panel high.

[0053] However, if the MIP device is to be made smaller in size, the substrate and the packaging layer need to be made thinner, but it is difficult to make the BT substrate very thin. The MIP device that is too thick will have a reverse crystal problem in the subsequent testing and die bonding process. The glass substrate and the sapphire substrate are prone to breakage in the subsequent process after being made thin.

[0054] Therefore, the present application provides a solution to solve the above technical problems, and the detailed content will be described in the subsequent embodiments.

[0055] For the method of manufacturing a polycrystalline integrated device provided by the present application, refer to Figure 1 The flowchart of the method of manufacturing a polycrystalline integrated device provided by the present application. The method can include steps S100-S600.

[0056] Step S100, providing a support substrate;

[0057] Step S200, forming a temporary layer on the support substrate;

[0058] Step S300, performing a metal wiring process on the temporary layer to obtain a conductive wiring layer;

[0059] Step S400, transferring at least three light emitting chips of different colors to the conductive wiring layer respectively, and bonding with the conductive wiring layer respectively;

[0060] Step S500, filling a light blocking layer between adjacent light emitting chips; and

[0061] Step S600, dissociating the temporary layer to expose the conductive wiring layer.

[0062] The polycrystalline integrated device prepared by the method is integrated by first preparing a temporary layer on the support substrate, then preparing a conductive wiring layer on the temporary layer, then transferring a plurality of light-emitting chips of different colors to the conductive wiring layer for bonding, and then filling a light-blocking layer between adjacent light-emitting chips. Finally, the temporary layer is dissociated, which means that the support substrate bonded with the temporary layer is also removed. Compared with the existing scheme, the polycrystalline integrated device prepared accordingly has a thickness less than the thickness of the support substrate and the temporary layer, so that the thickness of the polycrystalline integrated device of the present application is significantly reduced, thereby avoiding the problems of easy breakage of the traditional substrate and the problem of inverted crystal in the testing and die bonding process of the traditional polycrystalline integrated device. In addition, at the product application end, the thinner polycrystalline integrated device means that a thinner and higher PPI display device can be produced.

[0063] Specifically, reference can be made to Figure 5 The support substrate ST can be a transparent substrate, and the material of the transparent substrate includes inorganic materials or III-V semiconductor materials. The inorganic materials include silicon carbide (SiC), germanium (Ge), sapphire (Sapphire), lithium aluminate (LiAlO2), zinc oxide (ZnO), glass or quartz. The III-V semiconductor materials include indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), aluminum nitride (AlN) materials. The temporary layer 110 can be any one of gallium nitride, benzocyclobutene, polyimide, graphite, boron nitride, poly-p-phenylene benzobisoxazole and organic materials. Since the temporary layer 110 can be a plurality of different materials, the process of forming the temporary layer 110 on the support substrate ST is also different. For example, when the temporary layer 110 is gallium nitride, it can be grown on the support substrate ST by deposition. For another example, when the temporary layer 110 is benzocyclobutene, it can be formed on the support substrate ST by spin coating. In addition, the thickness of the temporary layer 110 can be selected between tens of nanometers and one hundred nanometers, which is not limited by the present application. For example, the thickness of the temporary layer 110 in the present embodiment can be 10 nanometers, or 20 nanometers, or 30 nanometers, or 40 nanometers, or 50 nanometers, or 60 nanometers, or 70 nanometers, or 80 nanometers, or 90 nanometers, or 100 nanometers. In other embodiments, the thickness of the temporary layer 110 can also be 15 nanometers, or 25 nanometers, or 35 nanometers, or 45 nanometers, or 55 nanometers, or 65 nanometers, or 75 nanometers, or 85 nanometers, or 95 nanometers.

[0064] Reference can be made to Figure 6a After the preparation of the temporary layer 110 is completed, a metal wiring process can be performed on the temporary layer 110 to obtain a conductive wiring layer 120. The conductive wiring layer 120 serves as a carrier for electrical connection of the device and provides a guarantee for normal operation of the subsequent device.

[0065] Specifically, reference can be made toFigure 3 and 11 , Figure 3 is a metal wiring process embodiment provided by the present application, Figure 11 is a metal wiring process embodiment provided by the present application, Figure 3 is a structural variation diagram corresponding to Figure 3 As shown in the figure, the metal wiring process can include steps: S302a-S304a.

[0066] Step S302a, forming a metal layer on the temporary layer.

[0067] Step S304a, performing a patterning process on the metal layer to form the conductive wiring layer.

[0068] Referring to Figure 11 , a metal layer MT is formed on the temporary layer 110, and the forming process of the metal layer MT includes but is not limited to evaporation and sputtering, and in addition, the thickness of the formed metal layer MT can also be selected and adjusted according to actual needs, which is not limited by the present application. After the metal layer MT is formed, a patterning process can be performed on the metal layer MT, which is specifically to spin a layer of first photoresist PR1 on the metal layer MT, and then by means of exposure, development, etching and other processes, the photoresist pattern is pre-prepared on the first photoresist PR1, and after the desired photoresist pattern is obtained, the exposed part of the metal layer MT is etched by the block of the remaining photoresist material in the photoresist pattern, thereby completing the patterning of the metal layer MT and obtaining the conductive wiring layer 120. The etching of the metal layer MT can be selected according to the specific material of the metal layer MT, and the selected etching method includes dry etching or wet etching.

[0069] The material of the metal layer MT in the specific embodiment is selected from at least one of chromium, aluminum, titanium, platinum, gold, and copper. At the same time, the metal layer MT can include a single-layer metal structure or a multi-layer metal stack structure. For example, when the metal layer MT is a single-layer metal structure, it can only be chromium, and its thickness should be at least able to guarantee the performance requirements of the device. When the metal layer MT is a multi-layer metal stack structure, it can be any stack combination of aluminum, titanium, platinum, gold, and copper or an alloy containing these materials. In further consideration of the push-pull performance and tin-under-string prevention capability of the electrode, copper can also be considered as part of the multi-layer metal stack structure, for example, replacing the aluminum layer in the traditional multi-layer metal stack structure with a copper-aluminum alloy.

[0070] In other embodiments, referring to Figure 4 and 12 , Figure 4 is another metal wiring process embodiment provided by the present application, Figure 12 is a structural variation diagram corresponding to Figure 4 As shown in the figure, the metal wiring process can include steps: S302a-S304a. Figure 4As shown, the metal wiring process can include steps: S302b-S308b.

[0071] At step S302b, a sacrificial layer is formed on the temporary layer.

[0072] At step S304b, a patterning process is performed on the sacrificial layer to expose part of the temporary layer; wherein the pattern of the exposed temporary layer is the same as the pattern of the conductive wiring layer.

[0073] At step S306b, a metal layer is evaporated on the surface of the exposed temporary layer to form the conductive wiring layer.

[0074] At step S308b, the sacrificial layer is removed.

[0075] Reference can be made to Figure 12 A sacrificial layer 150 is formed on the temporary layer 110, which can include materials such as silicon dioxide, silicon nitride, aluminum oxide, etc. Then, the same patterning process as described above is performed on the sacrificial layer 150. The patterning process can refer to the description in the previous embodiment, which will not be repeated here. It is emphasized that the pattern obtained after the patterning process of the sacrificial layer 150 is complementary to the pattern obtained after the patterning process of the first photoresist PR1, that is, the pattern of the second photoresist PR2 used to shield the sacrificial layer 150 is complementary to the pattern of the first photoresist PR1. Then, a metal layer MT can be evaporated between the patterns of the sacrificial layer 150. Then, the sacrificial layer 150 is removed, and the conductive wiring layer 120 described above is obtained.

[0076] Reference can be made to Figure 7a After the conductive wiring layer 120 is made, at least three different colors of light emitting chips can be transferred to the conductive wiring layer 120 for bonding by a mass transfer process. In the present embodiment, the light emitting chips can be mini LEDs or micro LEDs. The three different colors include red, green, and blue light emitting chips; in other embodiments, they can also include red, red, green, and blue light emitting chips; in other embodiments, they can also include red, green, green, and blue light emitting chips; in other embodiments, they can also include red, green, blue, and blue light emitting chips; in other embodiments, they can also include red, green, blue, and white light emitting chips. The present application uses red light chips R, green light chips G, and blue light chips B, and each of the red light chips R, green light chips G, and blue light chips B includes two electrodes on the same side of the chip.

[0077] In one embodiment, as Figure 6b and 7bAs shown, the conductive wiring layer 120 may include a first wiring S1 and at least three second wirings S2; the first wiring S1 is electrically connected to the first electrode of each of the light-emitting chips, and each second wiring S2 is correspondingly connected to the second electrode of a light-emitting chip. That is, in this application, one electrode of each of the three color chips (red chip R, green chip G, and blue chip B) transferred to the conductive wiring layer 120 is connected to the first wiring S1, forming a common electrode, for example, a common N-electrode, while the remaining electrode (P electrode) is connected to a second wiring S2, thus forming an electrical integration of the red chip R, green chip G, and blue chip B. This method can improve the PPI. Bonding methods include, but are not limited to, laser bonding and gold-to-gold bonding.

[0078] Furthermore, to facilitate electrical connection of the aforementioned integrated devices with external circuits, please refer to [further details omitted]. Figure 6b and Figure 7b The conductive wiring layer 120 of this application may further include a first pad P1 and at least three second pads P2; the first pad P1 is connected to the first wiring S1, and each second pad P2 is correspondingly connected to a second wiring S2. Leading out the electrodes of each light-emitting chip through the first pad P1 and the second pads P2 can reduce the difficulty of subsequent bonding. It is understood that the case containing four light-emitting chips can be described with reference to the principles of the foregoing embodiments, and this application does not further limit it in this regard.

[0079] After the transfer and bonding of the red light chip R, green light chip G, and blue light chip B are completed, a light-blocking layer 130 can be filled between adjacent light-emitting chips. This light-blocking layer 130 is primarily a black light-absorbing dielectric insulating layer, including but not limited to BM black adhesive. Further details can be found in... Figure 8a and Figure 8b Furthermore, the light-blocking layer 130 can be patterned to expose the side of the light-emitting chip.

[0080] In one embodiment, it may be helpful to refer to Figure 2 After the step of filling a light-blocking layer between adjacent light-emitting chips, step S5002 may also be included.

[0081] Step S5002: An encapsulation layer is formed on the surface of each of the light-emitting chips and on the light-blocking layer.

[0082] For reference Figure 9 After the aforementioned patterning of the light-blocking layer 130, the gaps between adjacent light-emitting chips can be filled by the encapsulation layer 140. In this specific embodiment, the encapsulation layer 140 can be made of a high-transparency adhesive, such as epoxy resin, PI adhesive, or silicone, using a spin coating process, molding process, or vacuum lamination process, or by depositing SiO2 using a PECVD process.x SiN x SiN, SiO2, Al2O3, etc. or Al2O3 deposited by ALD process.

[0083] For further information, reference can be made to Figure 10a and Figure 10b After the fabrication of the encapsulation layer 140, the temporary layer 110 can be removed to expose the conductive wiring layer 120. As an example, the temporary layer 110 can include, but is not limited to, any one of gallium nitride, benzocyclobutene, polyimide, graphite, boron nitride, poly-para-phenylene-benzobisoxazole and organic materials. These materials can be removed by laser or solution or mechanical removal, etc. As an example, when the temporary layer 110 is gallium nitride, the gallium nitride can be decomposed by laser ablation to form nitrogen and gallium. The use of gallium nitride as the temporary layer 110 is more compatible with the existing epitaxial process, and the process is relatively simple. For the specific removal of other materials, the present application will not be further described, and the prior art can be referred to for understanding.

[0084] In one embodiment, in order to clean the surface of the conductive wiring layer 120 after removal, reference can be made to Figure 2 The method can further include step S700.

[0085] Step S700, removing the residual removal material on the surface of the conductive wiring layer.

[0086] As an example, the residual removal material on the surface of the conductive wiring layer can be removed by dry or wet method. The dry or wet method includes, but is not limited to, plasma etching and organic solvent dissolution. It should be pointed out that the removal method of the residual removal material is mainly related to the material selection of the temporary layer 110.

[0087] Based on the same inventive concept, the present application also provides a polycrystalline integrated device, which is prepared by the method for preparing a polycrystalline integrated device as described above.

[0088] Compared with the conventional scheme, the polycrystalline integrated device described above has less support substrate and is thinner, which can avoid the problem of easy breakage of the conventional substrate and the problem of inverted crystal in the process of testing and die bonding of the conventional polycrystalline integrated device. In addition, at the product application end, the thinner polycrystalline integrated device means that a thinner and higher PPI display device can be produced.

[0089] Specifically, the polycrystalline integrated device of the present application mainly integrates a plurality of light emitting chips of different colors, and the final structure can be, for example, Figure 10a and Figure 10bThe polycrystalline integrated device is thinner than the conventional scheme, and can avoid the problems of the conventional substrate being easy to break and the polycrystalline integrated device being inverted during the testing and die bonding processes. In addition, the thinner polycrystalline integrated device means that a thinner and higher PPI display device can be produced.

[0090] Based on the same inventive concept, the application further provides a display panel, comprising a driving circuit and a polycrystalline integrated device electrically connected to the driving circuit.

[0091] The light emitting device in the display panel described above adopts the polycrystalline integrated device described above, which is thinner than the conventional scheme and can avoid the problems of the conventional substrate being easy to break and the polycrystalline integrated device being inverted during the testing and die bonding processes. In addition, the thinner polycrystalline integrated device means that the display panel produced is thinner and has a higher PPI.

[0092] Specifically, the driving circuit of the application can be an active matrix circuit (AM) or a passive matrix circuit (PM) according to the driving mode. The display panel can be a Mini LED display panel, a Micro LED display panel, or a backlight module applied to a passive light emitting display device, which can be a liquid crystal display device.

[0093] It should be understood that the application of the application is not limited to the above examples, and those of ordinary skill in the art can make improvements or changes according to the above description, and all such improvements and changes shall fall within the protection scope of the claims of the application.

Claims

1. A method of fabricating a polycrystalline integrated device, comprising: The method comprises: providing a support substrate; forming a temporary layer on the support substrate; performing a metal wiring process on the temporary layer to obtain a conductive wiring layer; transferring at least three light-emitting chips of different colors to the conductive wiring layer respectively and bonding them to the conductive wiring layer respectively; filling a light-blocking layer between adjacent light-emitting chips; and dissociating the temporary layer to expose the conductive wiring layer.

2. The method of claim 1, wherein the step of forming the polycrystalline integrated device further comprises the step of: The conductive wiring layer comprises a first wiring and at least three second wirings; the first wiring is electrically connected to the first electrode of each light-emitting chip, and a second wiring is connected to the second electrode of a light-emitting chip. ​ 3. The method of claim 2, wherein the step of forming the polycrystalline integrated device further comprises the step of: The conductive wiring layer further comprises a first pad and at least three second pads; the first pad is connected to the first wiring, and a second pad is connected to a second wiring. ​ 4. The method for fabricating a polycrystalline integrated device as described in claim 1, characterized in that, After the step of filling a light-blocking layer between adjacent light-emitting chips, the method further comprises: forming a packaging layer on the surface of each light-emitting chip and the light-blocking layer.

5. The method of claim 4, wherein the step of forming the polycrystalline integrated device further comprises the step of: The method further comprises: ​ patterning the light-blocking layer to expose the side surface of the light-emitting chip; wherein the packaging layer also fills the side surface of the light-emitting chip.

6. The method of claim 1, wherein the step of forming the polycrystalline integrated device further comprises the step of: The metal wiring process comprises any of the following methods: ​ Method 1: forming a metal layer on the temporary layer; performing a patterning process on the metal layer to form the conductive wiring layer; Method 2: forming a sacrificial layer on the temporary layer; performing a patterning process on the sacrificial layer to partially expose the temporary layer; wherein the pattern of the exposed temporary layer is the same as that of the conductive wiring layer; evaporating a metal layer on the surface of the exposed temporary layer to form the conductive wiring layer; removing the sacrificial layer.

7. The method of fabricating a poly crystalline integrated device of claim 6, wherein, The metal layer comprises a single-layer metal structure or a multi-layer metal stack structure.

8. The method of fabricating a poly crystalline integrated device of claim 7, wherein, The material of the metal layer comprises any of copper, aluminum, titanium, chromium, platinum, and gold.

9. The method of claim 1, wherein the step of forming the polycrystalline integrated device further comprises the step of: The method further comprises: ​ removing the dissociation material remaining on the surface of the conductive wiring layer.

10. The method of claim 1, wherein The temporary layer comprises any of gallium nitride, benzocyclobutene, polyimide, graphite, boron nitride, poly-p-phenylene benzobisoxazole, and organic material.

11. A polycrystalline integrated device, characterized by The polycrystalline integrated device is made by the method of any of claims 1-10.

12. A display panel, characterized by, The display panel comprises a driving substrate and the polycrystalline integrated device of claim 11; wherein the driving substrate is electrically connected to the polycrystalline integrated device.

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