Display panel and manufacturing method thereof

Abstract

A display panel and a method of manufacturing the same are disclosed. The method includes forming a pixel circuit layer on a substrate, the pixel circuit layer including a sub-pixel circuit of each of a plurality of sub-pixels; forming a first electrode of a light emitting element on the pixel circuit layer, the first electrode of the light emitting element being electrically connected to the sub-pixel circuit; forming a pixel defining layer on the first electrode of the light emitting element; and forming a light emitting structure of a light emitting element on the pixel defining layer. In addition, the method includes forming a hole at a boundary region between the plurality of sub-pixels. The aperture may be formed using a wire of the aperture generator. Further, the method may include forming a second electrode of the light emitting element on the light emitting structure.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0113996 filed in the Korean Intellectual Property Office on August 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more embodiments described herein relate to a display panel and a method of manufacturing the same. Background Art

[0003] As information technology develops, the importance of display devices has increased. Examples of display devices include liquid crystal display devices, organic light emitting display devices, and inorganic light emitting display devices.

[0004] In a super-resolution display, the distance between sub-pixels is narrow. As a result, leakage current (or lateral leakage phenomenon) occurs between adjacent sub-pixels through the co-arranged light-emitting structure. Therefore, the sub-pixels do not emit light with the desired brightness, which adversely affects the display quality. Summary of the invention

[0005] Embodiments provide a display panel and a method of manufacturing the same that can reduce the influence of leakage current migrating between pixels or sub-pixels, which may deteriorate the quality of an image displayed by the display panel.

[0006] According to one aspect of the present disclosure, a method for manufacturing a display panel is provided, the method comprising the following steps: forming a pixel circuit layer on a substrate, the pixel circuit layer comprising a sub-pixel circuit for each of a plurality of sub-pixels; forming a first electrode of a light-emitting element on the pixel circuit layer, wherein the first electrode of the light-emitting element is electrically connected to the sub-pixel circuit; forming a pixel defining layer on the first electrode of the light-emitting element; forming a light-emitting structure of the light-emitting element on the pixel defining layer; forming a hole in a boundary region between adjacent sub-pixels among the plurality of sub-pixels, wherein the hole is formed using a wire of a hole generator; and forming a second electrode of the light-emitting element on the light-emitting structure.

[0007] The step of forming the hole may include: applying a high potential voltage to a first end of the conductive line; and applying a low potential voltage to a second end of the conductive line.

[0008] A plurality of sub-pixels may be arranged side by side in the display panel in a first direction and in a second direction intersecting the first direction. The step of forming the hole may include: forming a first hole between the plurality of sub-pixels arranged side by side in the first direction; and forming a second hole between the plurality of sub-pixels arranged side by side in the second direction.

[0009] The light emitting structure may include a first light emitting region, a charge generation layer stacked on the first light emitting region in a third direction, and a second light emitting region stacked on the charge generation layer in the third direction. In the step of forming the hole, the light emitting structure may be removed by a wire to a predetermined depth.

[0010] In the step of forming the hole, the second light emitting region and the charge generation layer may be sequentially removed.

[0011] In the step of forming the hole, at least a portion of the first light emitting region may also be removed.

[0012] In the step of forming the hole, the pixel defining layer may be exposed.

[0013] In the step of forming the hole, a width of the hole may be formed to be smaller than a width of a top surface of the pixel defining layer.

[0014] In the step of forming the hole, at least a portion of the first light emitting region may be exposed.

[0015] In the step of forming the hole, a width of the hole may be formed to be greater than a width of a top surface of the pixel defining layer.

[0016] The hole and the first electrode of the light emitting element may be positioned while overlapping each other in the third direction.

[0017] The conductive line may comprise silver and have a width of 200 nm.

[0018] In the step of forming the hole, either the substrate and the hole generator may be rotated 90 degrees.

[0019] According to another aspect of the present disclosure, a display panel is provided, the display panel comprising: a substrate on which a plurality of sub-pixels are disposed; a pixel circuit layer disposed on the substrate, the pixel circuit layer comprising a sub-pixel circuit for each of the plurality of sub-pixels; and a light-emitting element layer disposed on the pixel circuit layer, the light-emitting element layer comprising a plurality of light-emitting elements each comprising a first electrode, a light-emitting structure, and a second electrode, the light-emitting element layer having a hole formed by removing at least a portion of the light-emitting structure in a boundary region between the plurality of sub-pixels. The hole can be formed using a wire of a hole generator.

[0020] The plurality of sub-pixels may be arranged side by side in a first direction and in a second direction intersecting the first direction. The hole may be positioned between the plurality of sub-pixels arranged side by side in the first direction and between the plurality of sub-pixels arranged side by side in the second direction.

[0021] The light emitting structure may include: a first light emitting unit including a first light emitting layer; a charge generating layer stacked on the first light emitting unit in a third direction; and a second light emitting unit including a second light emitting layer, the second light emitting unit stacked on the charge generating layer in the third direction. The hole may be positioned in a region where the second light emitting unit and the charge generating layer are removed.

[0022] The hole may be positioned in the region where the first light emitting unit is also removed.

[0023] The hole and the first electrode of the light emitting element may overlap each other in the third direction.

[0024] According to one or more embodiments, a display panel includes: a first sub-pixel including a first electrode; a second sub-pixel including a second electrode adjacent to the first electrode; and a light-emitting structure disposed on the first electrode and the second electrode, wherein the light-emitting structure includes a hole disposed at a position between the first sub-pixel and the second sub-pixel, the hole extending to a depth of a charge generation layer between a stacked arrangement of different light-emitting regions of at least one of the first sub-pixel and the second sub-pixel being removed.

[0025] The display panel may further include a pixel defining layer commonly included in the first sub-pixel and the second sub-pixel. The depth of the hole may be less than the distance between the top surface of the first electrode and the top surface of the light emitting structure. The hole may overlap the pixel defining layer. The hole may have a width smaller than a width between the first electrode and the second electrode.

[0026] The hole may have a width greater than a width between the first electrode and the second electrode. The hole may overlap corresponding portions of the first electrode and the second electrode. The depth of the hole may be equal to the distance between the top surface of the pixel defining layer and the top surface of the light emitting structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals refer to the same elements throughout.

[0029] Figure 1 is a system block diagram of a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown Figure 1 A block diagram of an embodiment of any of the sub-pixels shown in .

[0031] Figure 3 It is shown Figure 1 A plan view of an embodiment of a display panel is shown in FIG.

[0032] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 3 An exploded perspective view of a portion of a display panel is shown in FIG.

[0033] Figure 5 It is shown Figure 4 A plan view of an embodiment of any of the pixels shown in FIG.

[0034] Figure 6 It is shown along Figure 5 A cross-sectional view of a light emitting structure including a hole according to an embodiment of the present disclosure, taken along line II′ of a pixel shown in FIG.

[0035] Figure 7 It is shown along Figure 5 A cross-sectional view of a light emitting structure including a hole according to an embodiment of the present disclosure, taken along line II′ of a pixel shown in FIG.

[0036] Figure 8 It is shown along Figure 5 A cross-sectional view of a light emitting structure including a hole according to an embodiment of the present disclosure, taken along line II′ of a pixel shown in FIG.

[0037] Fig. 9 is a cross-sectional view showing an embodiment of a light emitting structure according to an embodiment of the present disclosure.

[0038] Fig.10 It is shown Fig. 9 0014] The light emitting structure shown in FIG. 1 is a cross-sectional view of an embodiment in which the light emitting structure includes a hole.

[0039] Fig.11 It is shown Fig. 9 The light emitting structure shown in FIG. 1 includes a cross-sectional view of another embodiment of a hole.

[0040] Fig.12 is a cross-sectional view showing another embodiment of a light emitting structure according to an embodiment of the present disclosure.

[0041] Fig.13 It is shown Fig.12 0014] The light emitting structure shown in FIG. 1 is a cross-sectional view of an embodiment in which the light emitting structure includes a hole.

[0042] Fig.14 It is shown Fig.12 The light emitting structure shown in FIG. 1 includes a cross-sectional view of another embodiment of a hole.

[0043] Fig.15 is a plan view illustrating a display panel in which holes are generated in one direction by a hole generator according to an embodiment of the present disclosure.

[0044] Fig.16 is a plan view illustrating a display panel in which holes are generated in another direction by a hole generator according to an embodiment of the present disclosure.

[0045] Fig.17 is a plan view showing a display panel in which a hole is formed according to an embodiment.

[0046] Fig.18 is a system diagram of a hole generator according to an embodiment of the present disclosure.

[0047] Fig.19 is a diagram showing an embodiment of a display system according to an embodiment of the present disclosure.

[0048] Fig. 20 It is shown Fig.19 A perspective view of an application example of the display system shown in FIG.

[0049] Fig.21 is a diagram showing an embodiment of a head mounted display device worn by a user. DETAILED DESCRIPTION

[0050] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the exemplary embodiments described in this specification.

[0051] Parts not related to the description will be omitted to clearly describe the present disclosure, and the same or similar constituent elements will be represented by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used to identify the same or similar elements in different drawings.

[0052] In addition, for better understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clarity of description, the thickness of several parts and regions is exaggerated.

[0053] In the description, the expression "same", "equal" may mean "substantially the same", "substantially equal". That is, it may mean equality to the extent that a person skilled in the art can understand equality. Other expressions may be expressions in which "substantially" is omitted.

[0054] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0055] For ease of description, spatially relative terms such as "below", "above", etc. may be used here to describe the relationship of one element to another element as shown in the figure. It will be understood that, in addition to the orientations described here and depicted in the figures, the spatially relative terms and the configurations shown are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as "below" or "beneath" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the exemplary term "above" can cover both above and below orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used here are interpreted accordingly.

[0056] It will be understood that, unless otherwise defined, all terms (including technical terms and scientific terms) used in the specification have the same meanings as those understood by those skilled in the art. In addition, unless clearly specifically defined, terms defined by commonly used dictionaries should not be defined ideally or too formally.

[0057] It will also be understood that when the term "comprise" and / or its variations are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0058] Throughout the specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or directly coupled to the other element, or indirectly connected or indirectly coupled to the other element, and one or more intermediate elements are placed therebetween. The technical terms used here are only used to illustrate the purpose of a specific embodiment, and are not intended to limit the embodiment. It will be understood that when a component "includes" an element, unless there is another description to the contrary, it should be understood that the component does not exclude another element, but can also include another element. It will be understood that, for the purpose of this disclosure, "at least one (kind / person) of X, Y and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more items in X, Y and Z (for example, XYZ, XYY, YZ, ZZ). Similarly, for the purpose of this disclosure, "at least one (kind / person) selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more items in X, Y and Z (for example, XYZ, XYY, YZ, ZZ).

[0059] In addition, the disclosed embodiments are described herein with reference to schematic diagrams of idealized embodiments (and intermediate structures) of the present disclosure, such that variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, the disclosed embodiments should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the accompanying drawings are schematic in nature, and their shapes do not represent the actual shape of a region of the device and do not limit the scope of the disclosure.

[0060] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0061] Figure 1 is a system block diagram of a display device 100 according to an embodiment of the present disclosure.

[0062] Reference Figure 1 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110 , a gate driving circuit 120 , a data driver 130 , a voltage generator 140 , a controller 150 , and a temperature sensor 160 .

[0063] The display panel 110 may include a plurality of pixels PXL each including a plurality of sub-pixels SP. First to m-th gate lines GL1 to GLm (m is an integer of 2 or more) connected to the plurality of sub-pixels SP may be provided in the display panel 110. First to n-th data lines DL1 to DLn (n is an integer of 2 or more) connected to the plurality of sub-pixels SP may be provided in the display panel 110.

[0064] The plurality of subpixels SP may be connected (eg, electrically connected) to the gate driving circuit 120 through first to m-th gate lines GL1 to GLm. The plurality of subpixels SP may be connected (eg, electrically connected) to the data driver 130 through first to n-th data lines DL1 to DLn.

[0065] Each of the plurality of sub-pixels SP may include at least one light emitting element configured to generate light. Each of the plurality of sub-pixels SP may generate light of a predetermined color (e.g., a specific color or a specific wavelength band) such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels SP among the plurality of sub-pixels SP may constitute one pixel PXL. For example, Figure 1 As shown in FIG. 4 , three sub-pixels SP may constitute one pixel PXL.

[0066] The gate driving circuit 120 may be connected (e.g., electrically connected) to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP arranged entirely in a first direction DR1) through first to m-th gate lines GL1 to GLm. The first direction DR1 may be, for example, a direction crossing the display panel 110 from one side (e.g., the left side) to the other side (e.g., the right side) of the display panel 110. The first direction DR1 may be, for example, a row direction.

[0067] The gate driving circuit 120 may output a gate signal (e.g., a gate signal having an on level or an off level) to the first gate line GL1 to the mth gate line GLm in response to the gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, and / or other signals.

[0068] In an embodiment, the first emission control line EL1 to the m-th emission control line ELm (connected to the plurality of sub-pixels SP) may also be provided in the display panel 110. The first emission control line EL1 to the m-th emission control line ELm may be provided in the display panel 110 and extend in the row direction. The plurality of sub-pixels SP may be connected (e.g., electrically connected) to the first emission control line EL1 to the m-th emission control line ELm. In the above embodiment, the gate drive circuit 120 may include an emission control driver configured to control the first emission control line EL1 to the m-th emission control line ELm. In an embodiment, the emission control driver may be provided separately from the gate drive circuit 120. The emission control driver may operate under the control of the controller 150.

[0069] The gate drive circuit 120 may be disposed at one side of the display panel 110. However, the embodiments of the present disclosure are not limited thereto. For example, the gate drive circuit 120 may be divided into two or more drive circuits that are physically and / or logically divided, and these drive circuits may be disposed at one side of the display panel 110 and at the other side of the display panel 110 (e.g., the other side of the display panel 110 that faces the one side of the display panel 110). Thus, in some embodiments, the gate drive circuit 120 may be disposed in the display panel 110 or at the periphery of the display panel 110 in various forms.

[0070] The data driver 130 may be connected (e.g., electrically connected) to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP arranged entirely in the second direction DR2) through the first to n-th data lines DL1 to DLn. The second direction DR2 may be, for example, a direction crossing the display panel 110 from one side (e.g., the lower side) of the display panel 110 to the other side (e.g., the upper side) of the display panel 110. The second direction DR2 may be, for example, a column direction.

[0071] The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include one or more of a source start pulse, a source shift clock, a source output enable signal, and other signals.

[0072] The data driver 130 may apply a grayscale voltage corresponding to the image data DATA to the first to nth data lines DL1 to DLn by using a voltage (e.g., a gamma voltage Vgamma) from the voltage generator 140. When a gate signal (e.g., a gate signal having an on level) is applied to each of the first to mth gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the data lines DL1 to DLn. Each of the plurality of sub-pixels SP may receive a data signal applied at a corresponding timing in response to the gate signal (e.g., a gate signal having an on level). Each of the plurality of sub-pixels SP may generate light corresponding to the received data signal. Thus, an image may be displayed in the display panel 110.

[0073] In an embodiment, each of the gate driving circuit 120 and the data driver 130 may include a complementary metal oxide semiconductor (CMOS) circuit element.

[0074] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from an external source of the display device 100. The voltage generator 140 may adjust (e.g., reduce) the level of the received input voltage and regulate the voltage having the adjusted level. The voltage generator 140 may be configured to generate a plurality of voltages.

[0075] The voltage generator 140 may generate, for example, a first power supply voltage VDD, a second power supply voltage VSS, a gamma voltage Vgamma, etc. The generated first power supply voltage VDD and the second power supply voltage VSS may be applied (e.g., applied together) to a plurality of sub-pixels SP. The first power supply voltage VDD may have a relatively high voltage level. The second power supply voltage VSS may have a voltage level lower than that of the first power supply voltage VDD. The generated gamma voltage Vgamma may be provided to the data driver 130. In other embodiments, the first power supply voltage VDD and / or the second power supply voltage VSS may be provided by an external device (e.g., a power management integrated circuit (PMIC)) of the display device 100.

[0076] In some embodiments, the voltage generator 140 may also generate another voltage. For example, the voltage generator 140 may generate an initialization voltage to be applied (e.g., commonly applied) to the plurality of sub-pixels SP. For example, in a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the plurality of sub-pixels SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate the reference voltage.

[0077] The controller 150 may be configured to control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the display of the image data IMG from an external source. The controller 150 may provide a gate control signal GCS, a data control signal DCS, a voltage control signal VCS, etc. in response to the received control signal CTRL.

[0078] The controller 150 may convert input image data IMG suitable for the display device 100 or the display panel 110 so that the image data DATA may be output. In an embodiment, the controller 150 may align the input image data IMG in a row unit to be suitable for the sub-pixel SP, thereby outputting the image data DATA.

[0079] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In one embodiment, the data driver 130, the voltage generator 140, and the controller 150 may be components functionally divided in one (divided in the same) driver integrated circuit DIC. In one embodiment, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be installed in the driver integrated circuit DIC, and the other of the data driver 130, the voltage generator 140, and the controller 150 may be arranged to be installed in an integrated circuit different from the driver integrated circuit DIC.

[0080] The temperature sensor 160 may be configured to sense a temperature (e.g., a temperature at the periphery of the temperature sensor 160) and generate temperature data TEP indicating the sensed temperature. In some embodiments, the temperature sensor 160 may be disposed in the display panel 110. In some embodiments, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC. In some embodiments, the display device 100 may include two or more temperature sensors 160.

[0081] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust at least one of a data signal input to the display panel 110, a first power supply voltage VDD, and a second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0082] Figure 2 It is shown Figure 1 A block diagram of an embodiment of any one of the sub-pixels SP shown in FIG. Figure 2 As an example, the sub-pixel SPij is Figure 1 Among the plurality of sub-pixels SP shown in , the sub-pixels are arranged in the i-th row (i is an integer of 1 or more and m or less) and the j-th column (j is an integer of 1 or more and n or less).

[0083] Reference Figure 2 The sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD. The light emitting element LD may be connected (eg, electrically connected) between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN may be Figure 1 The node to which the first power supply voltage VDD is applied as shown in FIG. The second power supply voltage node VSSN may be Figure 1A node to which the second power supply voltage VSS shown in is applied.

[0084] The light emitting element LD may include a first electrode AE, a light emitting structure EMS, and a second electrode CE. The first electrode AE ​​may be any one of an anode electrode and a cathode electrode of the light emitting element LD. The second electrode CE may be the other of the anode electrode and the cathode electrode of the light emitting element LD. Hereinafter, for the convenience of description, a case where the first electrode AE ​​of the light emitting element LD is an anode electrode and the second electrode CE of the light emitting element LD is a cathode electrode is described as an example.

[0085] The first electrode AE ​​of the light emitting element LD may be connected (e.g., electrically connected) to the first power supply voltage node VDDN through the sub-pixel circuit SPC. The second electrode CE of the light emitting element LD may be connected (e.g., electrically connected) to the second power supply voltage node VSSN. For example, the first electrode AE ​​of the light emitting element LD may be connected (e.g., electrically connected) to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0086] The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm shown in FIG. The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1 The i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm shown in FIG. The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1 The j-th data line DLj among the first to n-th data lines DL1 to DLn shown in FIG. The sub-pixel circuit SPC may be configured to control the emission timing and / or emission brightness of the light emitting element LD according to (or in response to) signals received through these signal lines.

[0087] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The sub-pixel circuit SPC may also operate in response to an emission control signal received through the i-th emission control line ELi.

[0088] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage of the data signal (or a voltage corresponding to the data signal) in response to a gate signal (e.g., a gate signal having a conduction level) received through the i-th gate line GLi. The sub-pixel circuit SPC may adjust the timing of the current flowing through the light-emitting element LD in response to an emission control signal (e.g., an emission control signal having a conduction level) applied through the i-th emission control line ELi. The magnitude of the current flowing through the light-emitting element LD may vary according to the voltage stored in the sub-pixel circuit SPC. The light-emitting element LD may generate light having a brightness corresponding to the data signal.

[0089] Figure 3 It is shown Figure 1 1 is a plan view of an embodiment of a display panel 110 shown in FIG.

[0090] Figure 3 The embodiment of the display panel DP shown in FIG. 1 can be applied to Figure 1 The display panel 110 shown in FIG.

[0091] Reference Figure 3 , the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed at the periphery of the display area DA (e.g., may be disposed in an edge area of ​​the display area DA), and may correspond to, for example, a frame area.

[0092] The display panel DP may include a substrate SUB, a plurality of sub-pixels SP disposed (or formed) on the substrate SUB, and a plurality of signal pads (or referred to as “pads”) PD disposed (or formed) on the substrate SUB.

[0093] When the display panel DP according to an embodiment of the present disclosure is used as a display screen for a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP can be positioned very close to the user's eyes. In the above embodiments, the sub-pixels SP can be integrated at a relatively high density. In order to increase the integration of the sub-pixels SP, the substrate SUB according to an embodiment of the present disclosure can be set to a silicon substrate. The sub-pixels SP can be formed on a substrate SUB that is a silicon substrate. A display device 100 (for example, see Figure 1 ) can be designated as an OLED-on-silicon (OLEDoS) display device.

[0094] A plurality of sub-pixels SP may be disposed in the display area DA on the substrate SUB. Figure 3, the sub-pixels SP may be arranged in a matrix along the first direction DR1 and the second direction DR2 intersecting the first direction DR1. However, the embodiments of the present disclosure are not limited thereto. For example, the plurality of sub-pixels SP according to the embodiments of the present disclosure may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the plurality of sub-pixels SP may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction. Two or more sub-pixels SP among the plurality of sub-pixels SP may constitute one pixel PXL.

[0095] Components for controlling the sub-pixels SP may be disposed in the non-display area NDA on the substrate SUB. Figure 1 Lines such as the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn shown in FIG. 5 may be disposed to extend to at least a portion of the non-display area NDA.

[0096] Figure 1 At least one of the gate driving circuit 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 shown in FIG. 1 may be disposed (eg, integrated) in the non-display area NDA of the display panel DP.

[0097] In an embodiment, Figure 1 The gate driving circuit 120 shown in FIG. 1 may be formed and disposed in the non-display area NDA of the display panel DP. In another embodiment, the gate driving circuit 120 may be implemented as a separate integrated circuit separated from the display panel DP to be installed in the non-display area NDA.

[0098] In an embodiment, Figure 1 The temperature sensor 160 shown in FIG. 1 may be disposed in the non-display area NDA to sense the temperature of the display panel DP. The temperature sensor 160 may be disposed at a predetermined position, for example, at a vertex or in a region corresponding to the vertex. In one embodiment, two or more temperature sensors 160 may be disposed in the display panel DP.

[0099] The signal pad PD may be disposed in the non-display area NDA on the substrate SUB. The signal pad PD may be electrically connected to the sub-pixel SP through a line. For example, the signal pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0100] The signal pad PD can connect the display panel DP to other components of the display device 100 (eg, Figure 1 ) docking. In an embodiment, the signal pad PD can be used from Figure 1The driver integrated circuit DIC shown in FIG. 1 provides voltages and signals to be used for the operation of components included in the display panel DP. For example, the first data line DL1 to the nth data line DLn (see FIG. 1 ) Figure 1 ) can be connected to the driver integrated circuit DIC through the signal pad PD. For example, the first power supply voltage VDD and the second power supply voltage VSS (see FIG. 5 ) can be received from the driver integrated circuit DIC through the signal pad PD. Figure 1 ). In an embodiment where the gate driving circuit 120 is installed in the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driving circuit 120 through the signal pad PD.

[0101] In an embodiment, the circuit board may be electrically connected to the signal pad PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC (see Figure 1 ) can be mounted on a circuit board to be electrically connected to a signal pad PD.

[0102] In an embodiment, the display area DA may have one of various shapes. For example, the display area DA may have a closed loop shape including linear edges and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, and an ellipse.

[0103] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may at least partially have a circular display surface. In an embodiment, the display panel DP may be bendable, foldable or rollable. The display panel DP and / or the substrate SUB may include a rigid or flexible material.

[0104] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 3 8 is an exploded perspective view of a portion of the display panel DP shown in FIG.

[0105] exist Figure 4 In the embodiment, for the sake of clarity and brief description, the display panel DP is schematically shown. Figure 3 A portion of the display panel DP corresponding to the first pixel PXL1 and the second pixel PXL2 among the pixels PXL shown in FIG. A portion of the display panel DP corresponding to other pixels PXL may also be constructed in the same manner.

[0106] Reference Figure 3 and Figure 4 , the first pixel PXL1 and the second pixel PXL2 may be adjacent to each other when arranged along the second direction DR2. Each of the first pixel PXL1 and the second pixel PXL2 may include a plurality of sub-pixels SP. Figure 4, each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged in the first direction DR1. However, the embodiments of the present disclosure are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels SP or two sub-pixels SP.

[0107] exist Figure 4 , it is shown that when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2 (e.g., perpendicular to the first direction DR1 and the second direction DR2), the first to third sub-pixels SP1 to SP3 may have a quadrilateral shape and have the same size. However, the embodiment is not limited thereto. The first to third sub-pixels SP1 to SP3 may be modified to have various shapes.

[0108] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a thin film encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0109] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0110] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least some of circuit elements, lines, etc. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0111] The circuit element may include a sub-pixel circuit SPC (see FIG. Figure 2). The sub-pixel circuit SPC may include at least two transistors and at least one capacitor. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapped with the semiconductor portion (e.g., the channel region). In an embodiment, when the substrate SUB is set to a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is set to a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. The capacitor may include electrodes spaced apart from each other (e.g., facing each other), and a dielectric is disposed between the electrodes. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, the capacitor may include electrodes spaced apart from each other in a third direction DR3, and a dielectric insulating layer is disposed between the electrodes.

[0112] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first to third sub-pixels SP1 to SP3, for example, gate lines, emission control lines, data lines, etc. The lines may also include signals connected to Figure 2 The line may also include a line connected to the first power supply voltage node VDDN shown in FIG. Figure 2 The line of the second supply voltage node VSSN is shown in .

[0113] The light emitting element layer LDL may include a first electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a second electrode CE. The first electrode AE ​​may be disposed on the pixel circuit layer PCL, and may be, for example, an anode electrode. The first electrode AE ​​may be connected to a circuit element of the pixel circuit layer PCL (e.g., in contact with a circuit element of the pixel circuit layer PCL). The first electrode AE ​​may include an opaque conductive material capable of reflecting light. However, embodiments of the present disclosure are not limited thereto.

[0114] The pixel defining layer PDL may be disposed on the first electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each of the first electrodes AE. The opening OP of the pixel defining layer PDL may be an emission region of each of the first to third sub-pixels SP1 to SP3.

[0115] In an embodiment, the pixel defining layer PDL may include an inorganic material. In the above embodiment, the pixel defining layer PDL may include an inorganic layer (eg, a plurality of stacked inorganic layers). For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and / or silicon nitride (SiN x). In other embodiments, the pixel defining layer PDL may include an organic layer including an organic material. However, the material constituting the pixel defining layer PDL according to an embodiment of the present disclosure is not limited to the materials described above.

[0116] The light emitting structure EMS may be disposed on the first electrode AE ​​exposed through the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include at least one functional layer. The light emitting structure EMS may include, for example, a plurality of functional layers, such as a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0117] In an embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL. In an embodiment, the light emitting structure EMS may be entirely disposed on top of the pixel defining layer PDL. For example, the light emitting structure EMS may extend throughout the first to third sub-pixels SP1 to SP3. In the above embodiments, at least some of the functional layers in the light emitting structure EMS may be cut or bent at the boundaries between the first to third sub-pixels SP1 to SP3. However, the embodiments of the present disclosure are not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first to third sub-pixels SP1 to SP3 may be separated from each other, and each of the portions may be disposed in the opening OP of the pixel defining layer PDL.

[0118] The second electrode CE may be disposed on the light emitting structure EMS and may be, for example, a cathode electrode. The second electrode CE may extend throughout the first to third subpixels SP1 to SP3 (or overlap the first to third subpixels SP1 to SP3). The second electrode CE may be disposed to be commonly connected to the common electrodes of the first to third subpixels SP1 to SP3.

[0119] The second electrode CE may have light transmittance. For example, the second electrode CE may be a thin metal layer having a thickness to the extent that the light emitted from the light emitting structure EMS can be transmitted therethrough. The second electrode CE may be formed of a metal material to have a relatively thin thickness, or may be formed of a conductive material having light transmittance (e.g., transparency). In an embodiment, the second electrode CE may include at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. However, the material constituting the second electrode CE according to an embodiment of the present disclosure is not limited to the materials described above. In one embodiment, the second electrode CE may be used as a semi-reflective semi-transmissive mirror (half mirror) that allows light emitted from the light emitting structure EMS to be partially transmitted therethrough and allows light emitted from the light emitting structure EMS to be partially reflected therefrom.

[0120] It can be understood that any first electrode AE ​​among the first electrodes AE, the portion of the light emitting structure EMS (overlapping with the first electrode AE) and the portion of the second electrode CE (overlapping with the first electrode AE) constitute a light emitting element LD (for example, see Figure 2 ). Each of the light emitting elements LD of the first to third sub-pixels SP1 to SP3 may include one first electrode AE, a portion of the light emitting structure EMS overlapping the one first electrode AE, and a portion of the second electrode CE overlapping the one first electrode AE. In each of the first to third sub-pixels SP1 to SP3, holes injected from the first electrode AE ​​and electrons injected from the second electrode CE may be transferred to the light emitting structure EMS to form excitons, and light may be generated when the excitons change from an excited state to a ground state. The brightness of the light may be determined according to the amount of current flowing through the light emitting structure EMS. The wavelength band of the generated light may be determined according to the configuration of the light emitting structure EMS.

[0121] The thin film encapsulation layer TFE may be disposed above the second electrode CE. The thin film encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The thin film encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In an embodiment, the thin film encapsulation layer TFE may include a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ) etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the thin film encapsulation layer TFE are not limited to the materials described above.

[0122] In order to improve the encapsulation efficiency of the thin film encapsulation layer TFE, the thin film encapsulation layer TFE may further include aluminum oxide (AlO x ). The thin film including aluminum oxide can be positioned on the top surface of the thin film encapsulation layer TFE (facing the optical function layer OFL) and / or the bottom surface of the thin film encapsulation layer TFE facing the light emitting element layer LDL. The thin film including aluminum oxide can be formed, for example, by an atomic layer deposition (ALD) process. However, the embodiments of the present disclosure are not limited thereto. The thin film encapsulation layer TFE may also include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0123] The optical function layer OFL may be disposed on the thin film encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA. In an embodiment, the optical function layer OFL may be attached to the thin film encapsulation layer TFE through an adhesive layer. For example, the optical function layer OFL may be manufactured separately so that it is attached to the thin film encapsulation layer TFE through an adhesive layer. The adhesive layer may also perform the function of protecting the lower layer including the thin film encapsulation layer TFE.

[0124] The color filter layer CFL may be disposed between the thin film encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter light emitted from the light emitting structure EMS to selectively output light having a wavelength band corresponding to each sub-pixel SP.

[0125] The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the color filters CF may allow light having a wavelength band corresponding to the corresponding sub-pixel SP to pass therethrough. For example, the color filter CF corresponding to the first sub-pixel SP1 may allow light of a first (e.g., red) color to pass therethrough, the color filter CF corresponding to the second sub-pixel SP2 may allow light of a second (e.g., green) color to pass therethrough, and the color filter CF corresponding to the third sub-pixel SP3 may allow light of a third (e.g., blue) color to pass therethrough. At least some of the color filters CF may be omitted according to the light emitted from the light emitting structure EMS in each sub-pixel SP. In some embodiments, the color filter layer CFL may be omitted. In an embodiment, the color filters CF may overlap each other (e.g., partially overlap) in a boundary region between the first to third sub-pixels SP1 to SP3. In other embodiments, the color filters CF may be spaced apart from each other in a boundary region between the first to third sub-pixels SP1 to SP3, and a black matrix may be provided between the color filters CF.

[0126] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may output light emitted from the light emitting structure EMS along an intended path, thereby improving light emission efficiency. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acryl-based material. However, the material of the lens LS is not limited thereto.

[0127] In an embodiment, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be offset in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, the opening OP of the pixel defining layer PDL may be completely overlapped with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the area of ​​the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be offset from the center of the opening OP of the pixel defining layer PDL in the plane direction. For example, in the area of ​​the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may be partially overlapped with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, light emitted from the light emitting structure EMS can be effectively output in the normal direction of the display surface. At the outside of the display area DA, light emitted from the light emitting structure EMS can be effectively output in a direction inclined at a predetermined angle relative to the normal direction.

[0128] The outer coating OC may be disposed on the lens array LA. The outer coating OC may cover the optical function layer OFL, the thin film encapsulation layer TFE, the light emitting structure EMS and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting the layers thereunder from foreign matter such as dust, debris and moisture. For example, the outer coating OC may include an inorganic insulating layer. For example, the outer coating OC may include an epoxy resin, but the embodiment is not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0129] The cover window CW may be disposed on the outer coating OC. The cover window CW may be configured to protect the layers thereunder. The cover window CW may have a refractive index different from (e.g., higher than) the refractive index of the outer coating OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect components disposed on its bottom. In other embodiments, the cover window CW may be omitted.

[0130] Figure 5 It is shown Figure 4 A plan view of an embodiment of any of the pixels shown in FIG. Figure 5 In order to make the description clear and brief, the schematic diagram is shown. Figure 4The first pixel PXL1 among the first pixel PXL1 and the second pixel PXL2 shown in FIG. The other pixels may be configured identically to the first pixel PXL1. The first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0131] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA at the periphery of the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA at the periphery of the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA at the periphery of the third emission area EMA3.

[0132] The first emission area EMA1 may be where the light from the light emitting structure EMS (eg, see Figure 4 ) may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Figure 4 As described, each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0133] In order to improve the resolution, efforts are being made to reduce the size of the pixel PXL. As the size of the first pixel PXL1 becomes smaller, the distance between the first sub-pixel SP1 to the third sub-pixel SP3 becomes smaller. Therefore, the leakage current flows into the adjacent sub-pixel SP. Therefore, the display quality is deteriorated due to the leakage current. In addition, the leakage current passes through the light emitting structure EMS (for example, see Figure 4 ) flows into the adjacent sub-pixel SP. In order to reduce (or prevent) the leakage current from flowing into the adjacent sub-pixel SP, at least a portion of the light emitting structure EMS may be removed through the hole.

[0134] Figure 6 It is shown along Figure 5 A cross-sectional view of the light emitting structure EMS including the hole CUH according to an embodiment of the present disclosure, taken along line II' of the pixel shown in FIG. Figure 6 In the cross-sectional view shown in FIG. , for ease of description, the Figure 4 The second electrode CE and the layers positioned on the second electrode CE are shown in FIG.

[0135] Reference Figure 6, showing the following: a pixel circuit layer PCL, a first electrode AE, a pixel defining layer PDL and a light emitting structure EMS stacked on a substrate SUB. The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon-germanium.

[0136] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor of the first sub-pixel SP1, a transistor of the second sub-pixel SP2, and a transistor of the third sub-pixel SP3.

[0137] Each of the first to third sub-pixels SP1 to SP3 may include a first electrode AE. Figure 6 , showing the first electrode AE1 of the first sub-pixel SP1, the first electrode AE2 of the second sub-pixel SP2, and the first electrode AE3 of the third sub-pixel SP3. When viewed in the third direction DR3, the first electrodes AE1 to AE3 may have the same Figure 5 The shapes of the first emission areas EMA1 to EMA3 shown in FIG. 1 are similar to those of the first emission areas EMA1 to EMA3 shown in FIG. In an embodiment, the first electrodes AE1 to AE3 may include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the first electrodes AE1 to AE3 is not limited thereto. For example, the first electrodes AE1 to AE3 may include titanium nitride.

[0138] The pixel defining layer PDL may be disposed on portions of the first electrodes AE1 to AE3 and the pixel circuit layer PCL (eg, a planarization layer of the pixel circuit layer PCL). The pixel defining layer PDL may include an opening OP (eg, see also FIG. 2 ) exposing portions of corresponding electrodes among the first electrodes AE1 to AE3. Figure 4 The opening OP of the pixel defining layer PDL may define the emission areas of the first to third sub-pixels SP1 to SP3. The pixel defining layer PDL may define the first to third emission areas EMA1 to EMA3, and at the same time, Figure 5 In the non-emitting area NEA shown in .

[0139] In an embodiment, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x). For example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked sequentially, and each of the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon oxynitride. However, the embodiments of the present disclosure are not limited thereto. The first to third inorganic insulating layers may have a stepped cross-section in a region adjacent to the opening OP.

[0140] The light emitting structure EMS may be disposed in the opening OP formed by the pixel defining layer PDL (see, for example, Figure 4 ) on the exposed first electrode AE. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be integrally disposed throughout the first to third sub-pixels SP1 to SP3. The light emitting structure EMS may be formed by a process such as vacuum deposition or inkjet printing.

[0141] According to one or more embodiments described herein, Figure 6 As shown in , at least a portion of the light emitting structure EMS may be removed in a region between adjacent sub-pixels SP positioned in the sub-pixel SP. The hole CUH may correspond to a region in which at least a portion of the light emitting structure EMS is removed. As will be described in more detail, the hole CUH may prevent leakage current from migrating between adjacent sub-pixels SP. Figure 6 , the first hole 710 is shown as an embodiment of the hole CUH. Figure 6 , the first hole 710 according to the embodiment of the present disclosure may be formed by removing at least a portion of the light emitting structure EMS.

[0142] For example, the first hole 710 may be positioned in a boundary region between adjacent sub-pixels SP. Figure 6 The first hole 710 may be positioned in a boundary region between the first sub-pixel SP1 and the second sub-pixel SP2. Another first hole 710 may be positioned in a boundary region between the second sub-pixel SP2 and the third sub-pixel SP3 to prevent leakage current from migrating between the sub-pixels SP.

[0143] like Figure 6 As further shown in FIG. 7 , a first hole 710 may be positioned between the first electrode AE1 of the first subpixel SP1 and the first electrode AE2 of the second subpixel SP2. Another first hole 710 may be positioned between the first electrode AE2 of the second subpixel SP2 and the first electrode AE3 of the third subpixel SP3.

[0144] The width of the first hole 710 (for example, the width in the first direction DR1 or the second direction DR2) may be a first width WT1. The depth of the first hole 710 (for example, the depth in the third direction DR3) may be a first depth DEP1. The width and depth of the first hole 710 may be described relative to the pixel defining layer PDL. For example, the width of the top surface of the pixel defining layer PDL may be a reference width WTr. The distance from the top surface of the light emitting structure EMS to the top surface of the pixel defining layer PDL may be a reference depth DEPr. According to one embodiment, the width of the first hole 710 (or the first width WT1) may be smaller than the reference width WTTr, and the depth of the first hole 710 (or the first depth DEP1) may be smaller than the reference depth DEPr.

[0145] Figure 7 It is shown along Figure 5 2 is a cross-sectional view of a light emitting structure EMS including a hole CUH according to another embodiment of the present disclosure, taken along line II′ of a pixel shown in FIG.

[0146] Reference Figure 7 , the second hole 810 is shown as another embodiment of the hole CUH. Figure 7 , the second hole 810 according to the embodiment of the present disclosure may be formed by removing at least a portion of the light emitting structure EMS. Similar to the first hole 710 in the previous embodiment, the second hole 810 may be positioned in a boundary region between adjacent sub-pixels SP. Figure 7 , the second hole 810 may be positioned at a boundary area between the first sub-pixel SP1 and the second sub-pixel SP2. Another second hole 810 may be positioned at a boundary area between the second sub-pixel SP2 and the third sub-pixel SP3. The second hole 810 may be positioned between the first electrode AE1 of the first sub-pixel SP1 and the first electrode AE2 of the second sub-pixel SP2. Another second hole 810 may be positioned between the first electrode AE2 of the second sub-pixel SP2 and the first electrode AE3 of the third sub-pixel SP3. As described in detail, the second hole 810 may prevent leakage current from migrating between adjacent sub-pixels SP.

[0147] The width of the second hole 810 (e.g., the width in the first direction DR1 or the second direction DR2) may be a first width WT1. The depth of the second hole 810 (e.g., the depth in the third direction DR3) may be a second depth DEP2. The width and depth of the second hole 810 may be described relative to the pixel defining layer PDL. The width of the top surface of the pixel defining layer PDL may be a reference width WTr. The distance from the top surface of the light emitting structure EMS to the top surface of the pixel defining layer PDL may be a reference depth DEPr. The width of the second hole 810 (or the first width WT1) may be less than the reference width WTr. According to the present embodiment, the depth of the second hole 810 (or the second depth DEP2) may be equal to (or substantially equal to) the reference depth DEPr. As shown, at least a portion of the pixel defining layer PDL (e.g., the top surface of the pixel defining layer PDL) may be exposed through the second hole 810.

[0148] Figure 8 It is shown along Figure 5 2 is a cross-sectional view of a light emitting structure EMS including a hole CUH according to another embodiment of the present disclosure, taken along line II′ of a pixel shown in FIG.

[0149] Reference Figure 8 , the third hole 910 is shown as another embodiment of the hole CUH. Figure 8 , the third hole 910 according to the embodiment of the present disclosure may be formed by removing at least a portion of the light emitting structure EMS. The third hole 910 may be positioned at a boundary region between adjacent sub-pixels SP. Figure 8 , the third hole 910 may be positioned at a boundary region between the first sub-pixel SP1 and the second sub-pixel SP2. Another third hole 910 may be positioned between the second sub-pixel SP2 and the third sub-pixel SP3. When positioned at these positions, the third hole 910 may prevent the migration of leakage current between adjacent sub-pixels SP.

[0150] The third hole 910 may overlap at least a portion of the first electrode AE1 of the first sub-pixel SP1 (e.g., overlap in the third direction DR3). In one embodiment, the third hole 910 may also overlap at least a portion of the first electrode AE2 of the second sub-pixel SP2 (e.g., overlap in the third direction DR3). Another third hole 910 may overlap at least a portion of the first electrode AE3 of the third sub-pixel SP3 (e.g., overlap in the third direction DR3). The degree to which the third hole 910 overlaps adjacent first electrodes AE among the first electrodes AE may be the same or different.

[0151] The width of the third hole 910 (e.g., the width in the first direction DR1 or the second direction DR2) may be the second width WT2. The depth of the third hole 910 (e.g., the depth in the third direction DR3) may be the first depth DEP1. The width and depth of the third hole 910 may be described relative to the pixel defining layer PDL. The width of the top surface of the pixel defining layer PDL may be a reference width WTr. The distance from the top surface of the light emitting structure EMS to the top surface of the pixel defining layer PDL may be a reference depth DEPr. The width (or second width WT2) of the third hole 910 may be greater than the reference width WTTr, and the depth (or first depth DEP1) of the third hole 910 may be less than the reference depth DEPr.

[0152] The third hole 910 may define a non-emission area NEA (see Figure 5 ). The third hole 910 may overlap at least some of the first electrodes AE1 to AE3 (eg, overlap in the third direction DR3).

[0153] Reference Figures 6 to 8 The described hole CUH can be formed, for example, using a wire (e.g., a nanowire). The wire can extend in the first direction DR1 or the second direction DR2. For example, the hole CUH can be formed by allowing the wire to generate heat. For example, the heat generated from the wire can be transferred to the light emitting structure EMS by allowing the wire to contact the area on the light emitting structure EMS where the hole CUH will be formed. When a voltage is applied to the wire, heat can be generated. At least a portion of the light emitting structure EMS can be removed by the heat generated from the wire. The wire can be moved in one direction (e.g., a third direction DR3) to remove at least a corresponding portion of the light emitting structure EMS (e.g., removing the light emitting structure EMS to a predetermined depth as previously described).

[0154] According to the manufacturing method for forming the hole CUH using the wire, the hole CUH can be formed regardless of any material that is positioned while overlapping with the region in which the hole CUH is formed (for example, positioned while overlapping in the third direction DR3). For example, according to the above-mentioned manufacturing method of the hole CUH, even when a material that can reflect light (for example, the first electrode AE ​​of the light emitting element, etc.) is positioned while overlapping with the region in which the hole CUH is formed, the hole CUH can be easily formed.

[0155] On the other hand, when removing at least a portion of the light emitting structure EMS using a laser, the laser is reflected in an area where a material (e.g., metal, etc.) capable of reflecting light is positioned below an area on which the laser is irradiated. In this case, it may be difficult to properly remove the material of the light emitting structure EMS to form the hole CUH. For example, when a display device (e.g., an OLEDoS display device) is manufactured to have pixels integrated at a high density or resolution, such technical difficulties may occur.

[0156] Fig. 9 is a cross-sectional view showing an embodiment of a light emitting structure EMS according to an embodiment of the present disclosure.

[0157] Reference Fig. 9 The light emitting structure EMS may have a series structure in which a first light emitting unit (or region) EU1 and a second light emitting unit (or region) EU2 are stacked. Figure 5 The light emitting element LD of each of the first to third sub-pixels SP1 to SP3 shown in FIG. Figure 2 ) are constructed essentially identically.

[0158] Each of the first light emitting unit EU1 and the second light emitting unit EU2 may include a light emitting layer configured to generate light according to an applied current. The first light emitting unit EU1 may include a first light emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light emitting unit EU2 may include a second light emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0159] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer. In some embodiments, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may further include a hole buffer layer, an electron blocking layer, etc. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration or different configurations.

[0160] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer. In some embodiments, each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may also include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration or different configurations.

[0161] The connection layer may be provided between the first light emitting unit EU1 and the second light emitting unit EU2 in the form of a charge generation layer CGL. The connection layer may electrically connect the first light emitting unit EU1 and the second light emitting unit EU2 to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-type dopant layer and an n-type dopant layer. For example, the p-type dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9. For example, the n-type dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or any combination thereof. However, embodiments of the present disclosure are not limited thereto.

[0162] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors (or wavelength bands). The light emitted from the first light-emitting layer EML1 and the second light-emitting layer EML2, respectively, may be mixed together to be regarded as white light. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may generate yellow light. In an embodiment, the second light-emitting layer EML2 may include a structure in which a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light are stacked. In an embodiment, red light and green light may be mixed together to provide yellow light. An intermediate layer (or functional layer) configured to perform a function of transporting holes and / or a function of blocking the transport of electrons may be further disposed between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0163] In other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color (or wavelength band).

[0164] In the embodiment, the light emitting structure EMS may be formed through a process such as vacuum deposition or inkjet printing, but the embodiment is not limited thereto.

[0165] Fig.10 It is shown Fig. 9 The light emitting structure EMS shown in FIG. 1 includes a cross-sectional view of an embodiment of a hole CUH. The hole CUH may be formed by removing the charge generation layer CGL and one or more layers positioned on the charge generation layer CGL. Fig.10 The hole CUH may be formed by removing (eg, sequentially removing) corresponding portions of the second electron transport unit ETU2, the second light emitting layer EML2, the second hole transport unit HTU2, and the charge generation layer CGL. The depth of the hole CUH may be a first depth DEP1. Fig.10 The holes shown in CUH can be connected with Figure 6 The first hole 710 shown in Figure 8 Corresponding to the third hole 910 shown in FIG.

[0166] In the absence of the hole CUH, leakage current may be generated between adjacent sub-pixels SP due to charges generated in the charge generation layer CGL. According to the embodiments described herein, since the charge generation layer CGL is removed at the boundary region between the sub-pixels SP, the phenomenon in which leakage current is generated may be reduced (or prevented), thereby preventing degradation of an image displayed by the display device.

[0167] Fig.11 It is shown Fig. 9 FIG. 1 is a cross-sectional view of another embodiment in which the light emitting structure EMS shown in FIG. includes a hole CUH. The hole CUH may be formed by removing the charge generation layer CGL, one or more layers positioned on the charge generation layer CGL, and at least one layer positioned below the charge generation layer CGL. Fig.11 In one embodiment, the hole CUH may be formed by removing (e.g., sequentially removing) the second electron transport unit ETU2, the second light emitting layer EML2, the second hole transport unit HTU2, the charge generation layer CGL, the first electron transport unit ETU1, the first light emitting layer EML1, and the first hole transport unit HTU1. The depth of the hole CUH may be the second depth DEP2. Fig.11 The holes shown in CUH can be connected with Figure 7 Corresponding to the second hole 810 shown in .

[0168] In the absence of the hole CUH, leakage current may be generated between adjacent sub-pixels SP due to charges generated in the charge generation layer CGL. According to one or more embodiments, the charge generation layer CGL is removed at the boundary region between the sub-pixels SP, so that the phenomenon in which leakage current is generated can be reduced (or prevented), thereby preventing degradation of an image generated by the display device.

[0169] Fig.12 is a cross-sectional view showing another embodiment of the light emitting structure EMS' according to an embodiment of the present disclosure.

[0170] Reference Fig.12, the light emitting structure EMS' may have a series structure in which the first light emitting unit EU1' to the third light emitting unit EU3' are stacked. Each of the first light emitting unit EU1' to the third light emitting unit EU3' may include a light emitting layer configured to generate light according to an applied current. The first light emitting unit EU1' may include a first light emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light emitting unit EU2' may include a second light emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light emitting unit EU3' may include a third light emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light emitting layer EML3 ′ may be disposed between the third electron transport unit ETU3 ′ and the third hole transport unit HTU3 ′.

[0171] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer. In some embodiments, each of the first to third hole transport units HTU1' to HTU3' may further include a hole buffer layer, an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same configuration or may have different configurations.

[0172] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer. In some embodiments, each of the first to third electron transport units ETU1' to ETU3' may further include an electron buffer layer, a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' may have the same configuration or different configurations.

[0173] The first charge generation layer CGL1' may be disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' may be disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0174] In an embodiment, the first light-emitting layer EML1' to the third light-emitting layer EML3' may generate light of different colors (or wavelengths). The light emitted from the first light-emitting layer EML1' to the third light-emitting layer EML3' may be mixed together to form white light. For example, the first light-emitting layer EML1' may generate light of a first wavelength band (e.g., blue), the second light-emitting layer EML2' may generate light of a second wavelength band (e.g., green), and the third light-emitting layer EML3' may generate light of a third wavelength band (e.g., red). In other embodiments, at least two of the first light-emitting layer EML1' to the third light-emitting layer EML3' may generate light of the same color (or wavelength band).

[0175] Fig.13 It is shown Fig.12 The light emitting structure EMS' shown in FIG. 1 includes a cross-sectional view of an embodiment of a hole CUH. The hole CUH may be formed by removing the first charge generation layer CGL1' and one or more layers positioned on the first charge generation layer CGL1'. For example, Fig.13 As shown in , the hole CUH can be formed by removing (e.g., sequentially removing) the third electron transport unit ETU3', the third light-emitting layer EML3', the third hole transport unit HTU3', the second charge generation layer CGL2', the second electron transport unit ETU2', the second light-emitting layer EML2', the second hole transport unit HTU2' and the first charge generation layer CGL1'.

[0176] The depth of the hole CUH may be a first depth DEP1. Fig.13 The holes shown in CUH can be connected with Figure 6 The first hole 710 shown in Figure 8 Corresponding to the third hole 910 shown in FIG.

[0177] In the absence of the hole CUH, leakage current may be generated between adjacent sub-pixels SP due to charges generated in the first charge generation layer CGL1' and / or the second charge generation layer CGL2'. According to the present embodiment, the first charge generation layer CGL1' and the second charge generation layer CGL2' are removed at the boundary region between the sub-pixels SP, so that the phenomenon in which leakage current is generated therein can be reduced (or prevented), thereby preventing degradation of an image generated by the display device.

[0178] Fig.14 It is shown Fig.12 The light emitting structure EMS' shown in FIG. 1 includes a cross-sectional view of another embodiment of a hole CUH. The hole CUH may be formed by removing the first charge generation layer CGL1', one or more layers positioned on the first charge generation layer CGL1', and at least one layer positioned under the first charge generation layer CGL1'. Fig.14The hole CUH may be formed by removing (e.g., sequentially removing) the third electron transport unit ETU3', the third light emitting layer EML3', the third hole transport unit HTU3', the second charge generation layer CGL2', the second electron transport unit ETU2', the second light emitting layer EML2', the second hole transport unit HTU2', the first charge generation layer CGL1', the first electron transport unit ETU1', the first light emitting layer EML1', and the first hole transport unit HTU1'. The depth of the hole CUH may be the second depth DEP2. Fig.14 The holes shown in CUH can be connected with Figure 7 corresponds to the second hole 810 shown in .

[0179] In the absence of the hole CUH, leakage current may be generated between adjacent sub-pixels SP due to charges generated in the first charge generation layer CGL1' and / or the second charge generation layer CGL2'. According to one or more embodiments, the first charge generation layer CGL1' and the second charge generation layer CGL2' are removed at the boundary region between the sub-pixels SP, so that the phenomenon in which leakage current is generated therein can be reduced (or prevented), thereby preventing degradation of an image displayed by the display device.

[0180] Fig.15 is a plan view showing a display panel MDP in which holes are generated in one direction by a hole generator 1600 according to an embodiment of the present disclosure. More specifically, Fig.15 The display panel MDP may be a display panel in which the light emitting structure EMS (eg, Figure 4 ) is formed on a substrate SUB. The hole generator 1600 may be configured to form a hole in the display panel MDP.

[0181] Reference Fig.15 , the hole generator 1600 may include a first unit 1610, a second unit 1620, and a wire 1630. The first unit 1610 and the second unit 1620 may be positioned to be spaced apart from each other, and the display panel MDP is placed between the first unit 1610 and the second unit 1620. The wire 1630 has a first end connected to the first unit 1610 and a second end connected to the second unit 1620. The wire 1630 may include a conductive material (e.g., metal).

[0182] The first unit 1610 and the second unit 1620 may supply a voltage of a predetermined level. For example, one of the first unit 1610 and the second unit 1620 (e.g., the first unit 1610) may supply a high potential voltage, and the other of the first unit 1610 and the second unit 1620 (e.g., the second unit 1620) may supply a low potential voltage.

[0183] A high potential voltage may be applied to one end of the wire 1630, and a low potential voltage may be applied to the other end of the wire 1630. A voltage may be applied to the wire 1630, and heat may be generated in the wire 1630 by the resistance of the wire 1630. A hole may be formed in the display panel MDP by the heat generated in the wire 1630. The wire 1630 may include silver (Ag), but may be made of a different conductive material in another embodiment. The wire 1630 may have a predetermined width. For example, the wire 1630 may have a width of about 200 nm (nanometers), but embodiments of the present disclosure are not limited thereto.

[0184] Reference Fig.15 , the conductive line 1630 may extend in the first direction DR1. The first unit 1610 and the second unit 1620 may move in the second direction DR2 (or a direction horizontal to the second direction DR2). In one embodiment, the display panel MDP may move in the second direction DR2 (or a direction horizontal to the second direction DR2). Therefore, as previously described, holes may be sequentially formed in the display panel MDP to reduce the generation of leakage current between adjacent sub-pixels SP.

[0185] Reference Fig.15 , showing a method in which a hole CUH (e.g., see Figures 6 to 8 ) is formed to extend in the first direction DR1 entirely on the substrate SUB. However, the embodiments of the present disclosure are not limited thereto, and for example, the hole CUH may be partially (or locally) formed in a partial region on the substrate SUB.

[0186] Fig.16 is a plan view showing a display panel MDP in which holes are generated in another direction by the hole generator 1600 according to an embodiment of the present disclosure.

[0187] Reference Fig.16 , the conductive line 1630 may extend in the second direction DR2. The first unit 1610 and the second unit 1620 may move in the first direction DR1 (or a direction horizontal to the first direction DR1). In one embodiment, the display panel MDP may move in the first direction DR1 (or a direction horizontal to the first direction DR1). Therefore, as previously described, holes may be sequentially formed in the display panel MDP to reduce the generation of leakage current between adjacent sub-pixels SP.

[0188] and Fig.15In contrast, the hole generator 1600 is shown to be rotated 90 degrees clockwise in a state in which the substrate SUB is fixed. However, the embodiments of the present disclosure are not limited thereto. For example, at least one of the substrate SUB and the hole generator 1600 may be rotated 90 degrees. For example, each of the substrate SUB and the hole generator 1600 may be rotated by a predetermined angle, thereby forming Fig.16 The arrangement shown in .

[0189] Reference Fig.16 , showing a method in which a hole CUH (e.g., see Figures 6 to 8 ) is formed to extend entirely along the second direction DR2 on the substrate SUB. However, the embodiments of the present disclosure are not limited thereto, and the hole CUH may be partially (or locally) formed in a partial region on the substrate SUB.

[0190] Fig.17 is a plan view showing a display panel MDP in which holes CUH are formed. Each hole CUH may be formed between sub-pixels SP. Fig.17 In the embodiment, some of the holes CUH may be formed between the sub-pixels SP adjacent to each other in the first direction DR1. Other holes of the holes CUH may be formed between the sub-pixels SP adjacent to each other in the second direction DR2.

[0191] Reference Fig.17 , showing that the hole CUH is not formed at the outside of the display area DA. However, the embodiments of the present disclosure are not limited thereto, and the hole CUH may also be formed at the outside of the display area DA.

[0192] Reference Fig.17 , a plurality of sub-pixels SP in the display panel MDP may be arranged side by side in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. Some of the holes CUH may be positioned between the plurality of sub-pixels SP arranged side by side along the first direction DR1. Other holes of the holes CUH may be positioned between the plurality of sub-pixels SP arranged side by side along the second direction DR2.

[0193] Fig.18 is a system diagram of a hole generator 1600 according to an embodiment of the present disclosure.

[0194] Reference Fig.18, the hole generator 1600 according to an embodiment of the present disclosure may include a first unit 1610, a second unit 1620, a wire 1630, and a voltage source 1910. The voltage source 1910 may be connected to the first unit 1610 and the second unit 1620. The voltage source 1910 may provide a high potential voltage to one of the first unit 1610 and the second unit 1620 (e.g., the first unit 1610), and may provide a low potential voltage to the other of the first unit 1610 and the second unit 1620 (e.g., the second unit 1620). Therefore, a potential difference (e.g., a predetermined voltage difference Vs) may be formed between the first unit 1610 and the second unit 1620.

[0195] The wire 1630 may have a resistance (eg, a predetermined resistance R). Heat may be generated in the wire 1630 based on a potential difference Vs between the ends of the wire 1630. The hole CUH may be formed in the display panel MDP (eg, FIG. 1 ) by the heat generated in the wire 1630. Fig.17 )middle.

[0196] Fig.19 is a diagram showing an embodiment of a display system 2000 according to an embodiment of the present disclosure.

[0197] Reference Fig.19 , the display system 2000 may include a processor 2010 and one or more display devices 2020 and 2030. The processor 2010 may perform various tasks and various calculations. In an embodiment, the processor 2010 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 2010 may be connected to other components of the display system 2000 through a bus system to control the components of the display system 2000.

[0198] exist Fig.19 , it is shown that the display system 2000 includes a first display device 2020 and a second display device 2030. The processor 2010 may be connected to the first display device 2020 through a first channel CH1, and connected to the second display device 2030 through a second channel CH2.

[0199] Through the first channel CH1, the processor 2010 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 2020. The first display device 2020 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 The display device 100 described above is identically constructed. The first image data IMG1 and the first control signal CTRL1 may be respectively used as Figure 1The image data IMG and the control signal CTRL shown in are provided.

[0200] Through the second channel CH2, the processor 2010 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 2030. The second display device 2030 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The display device 100 described above is constructed identically. The second image data IMG2 and the second control signal CTRL2 may be respectively used as Figure 1 The image data IMG and the control signal CTRL shown in are provided.

[0201] The display system 2000 may include a computing system for providing an image display function. Examples include a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra mobile computer (UMPC). In addition, the display system 2000 may include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0202] Fig. 20 It is shown Fig.19 2 is a perspective view of an application example of display system 2000 shown in FIG.

[0203] Reference Fig. 20 , Fig.19 The display system 2000 shown in FIG. 2 may be applied to a head-mounted display device 2100. The head-mounted display device 2100 may be a wearable electronic device that may be worn on a user's head.

[0204] The head-mounted display device 2100 may include a head-mounted band 2110 and a display device housing 2120. The head-mounted band 2110 may be connected to the display device housing 2120. The head-mounted band 2110 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2100 to the user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper part of the user's head. However, the embodiment is not limited thereto. For example, the head-mounted band 2110 may be implemented in the form of a glasses frame, a helmet, etc.

[0205] The display device receiving housing 2120 can receive Fig.19 The first display device 2020 and the second display device 2030 shown in FIG. The display device receiving housing 2120 can also receive Fig.19 Processor 2010 shown in .

[0206] Fig.21 21 is a diagram showing a head mounted display device 2100 worn by a user.

[0207] Reference Fig.21 , the first display device 2020 (see Fig.19 ) of the first display panel DP1 and the second display device 2030 (see Fig.19 ) may be provided in the head mounted display device 2100. The head mounted display device 2100 may further include one or more lenses. For example, the head mounted display device 2100 may include a left eye lens LLNS and a right eye lens RLNS.

[0208] In the display device accommodating housing 2120, a right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user. In the display device accommodating housing 2120, a left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user.

[0209] The image output from the first display panel DP1 may be viewed by the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract the light emitted from the first display panel DP1 so as to face the right eye of the user. The right eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the right eye of the user.

[0210] The image output from the second display panel DP2 can be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS can refract the light emitted from the second display panel DP2 so that it faces the user's left eye. The left eye lens LLNS can perform an optical function for adjusting the viewing distance between the second display panel DP2 and the user's left eye.

[0211] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In the above embodiment, each of the first display panel DP1 and the second display panel DP2 may output an image corresponding to a sub-region of the multi-channel lens, and the output images may be viewed by a user while passing through the corresponding sub-regions, respectively.

[0212] In the display panel and the manufacturing method thereof according to the present disclosure, the influence of leakage current between adjacent pixels or adjacent sub-pixels of a pixel can be reduced or prevented.

[0213] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be interpreted only in a general and descriptive sense and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A method for manufacturing a display panel, the method comprising the following steps: forming a pixel circuit layer on a substrate, the pixel circuit layer including a sub-pixel circuit for each of a plurality of sub-pixels; forming a first electrode of a light-emitting element on the pixel circuit layer, wherein the first electrode of the light-emitting element is electrically connected to the sub-pixel circuit; forming a pixel defining layer on the first electrode of the light emitting element; forming a light emitting structure of the light emitting element on the pixel defining layer; forming a hole at a boundary region between adjacent sub-pixels among the plurality of sub-pixels, wherein the hole is formed using a conductive line of a hole generator; and A second electrode of the light emitting element is formed on the light emitting structure.

2. The method according to claim 1, wherein: The steps of forming the hole include: applying a high potential voltage to the first end of the wire; and A low potential voltage is applied to the second end of the wire.

3. The method according to claim 1, wherein: The plurality of sub-pixels are arranged side by side in the display panel in a first direction and in a second direction intersecting the first direction, and Wherein, the step of forming the hole comprises: forming a first hole between the plurality of sub-pixels arranged side by side along the first direction; and A second hole is formed between the plurality of sub-pixels arranged side by side along the second direction.

4. The method according to claim 1, wherein: The light emitting structure includes a first light emitting region, a charge generation layer stacked on the first light emitting region in a third direction, and a second light emitting region stacked on the charge generation layer in the third direction, and In the step of forming the hole, the light emitting structure is removed by the conductive wire to a predetermined depth. The step of forming the hole includes sequentially removing the second light emitting region and the charge generating layer.

5. The method according to claim 1, wherein: The step of forming the hole includes rotating one of the substrate and the hole generator by 90 degrees.

6. A display panel, comprising: A first sub-pixel including a first electrode; a second sub-pixel, comprising a second electrode adjacent to the first electrode; as well as A light-emitting structure is arranged on the first electrode and the second electrode, wherein the light-emitting structure includes a hole arranged at a position between the first sub-pixel and the second sub-pixel, and the hole extends to the depth of the charge generation layer between the stacked arrangement of different light-emitting regions of at least one of the first sub-pixel and the second sub-pixel is removed.

7. The display panel according to claim 6, further comprising: a pixel defining layer, commonly included in the first sub-pixel and the second sub-pixel, Wherein, the hole overlaps with the pixel defining layer.

8. The display panel according to claim 6, wherein: The depth of the hole is smaller than a distance between a top surface of the first electrode and a top surface of the light emitting structure.

9. The display panel according to claim 6, wherein: The hole has a width smaller than a width between the first electrode and the second electrode.

10. The display panel according to claim 6, wherein: The hole has a width greater than a width between the first electrode and the second electrode.

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