Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a substrate including a display area and a driving circuit area; a first insulating layer on the substrate; a second insulating layer on the first insulating layer; a first transistor in the display area and including a first semiconductor pattern layer formed as a semiconductor layer on the second insulating layer, a first gate electrode on the first semiconductor pattern layer, and a first lower electrode overlapping the first semiconductor pattern layer; and a second transistor in the driving circuit region and including a second semiconductor pattern layer formed as a semiconductor layer, a second gate electrode on the second semiconductor pattern layer, and a second lower electrode overlapping the second semiconductor pattern layer, in which the first lower electrode is between the substrate and the first insulating layer, and the second lower electrode is between the substrate and the second insulating layer. And the second lower electrode is between the first insulating layer and the second insulating layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0113680 filed in the Korean Intellectual Property Office on August 29, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0003] As multimedia technology develops, the importance of display devices has steadily increased. Therefore, various types of display devices, such as liquid crystal display devices or light emitting display devices, have been developed. Summary of the invention

[0004] The embodiment provides a display device capable of optimizing operation characteristics of a first transistor provided in a display region and a second transistor provided in a driving circuit region and a method of manufacturing the display device.

[0005] However, aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0006] According to the disclosed aspects, a display device is provided, which includes: a substrate including a display area and a driving circuit area; a first insulating layer arranged on the substrate; a second insulating layer arranged on the first insulating layer; a first transistor arranged in the display area and including a first semiconductor pattern layer formed as a semiconductor layer on the second insulating layer, a first gate electrode arranged on the first semiconductor pattern layer, and a first lower electrode stacked with the first semiconductor pattern layer; and a second transistor arranged in the driving circuit area and including a second semiconductor pattern layer formed as a semiconductor layer, a second gate electrode arranged on the second semiconductor pattern layer, and a second lower electrode stacked with the second semiconductor pattern layer, wherein the first lower electrode is formed as a first conductive layer arranged between the substrate and the first insulating layer, and the second lower electrode is formed as a second conductive layer arranged between the first insulating layer and the second insulating layer.

[0007] In an embodiment, the first semiconductor pattern layer and the first lower electrode may be spaced apart from each other, and the first insulating layer and the second insulating layer are disposed between the first semiconductor pattern layer and the first lower electrode, and the second semiconductor pattern layer and the second lower electrode may be spaced apart from each other, and the second insulating layer is disposed between the second semiconductor pattern layer and the second lower electrode.

[0008] In an embodiment, the first semiconductor pattern layer and the first lower electrode may be spaced apart from each other by a first distance, and the second semiconductor pattern layer and the second lower electrode may be spaced apart from each other by a second distance, the second distance being smaller than the first distance.

[0009] In an embodiment, the first semiconductor pattern layer and the second semiconductor pattern layer may include an oxide semiconductor.

[0010] In an embodiment, the display device may further include: a first gate insulation pattern layer disposed between the first semiconductor pattern layer and the first gate electrode, and covering a portion of the first semiconductor pattern layer.

[0011] In an embodiment, the first gate insulation pattern layer may have a shape and size corresponding to those of the first gate electrode, and may expose other portions of the first semiconductor pattern layer.

[0012] In an embodiment, the display device may further include: a second gate insulating pattern layer disposed between the second semiconductor pattern layer and the second gate electrode, and covering a portion of the second semiconductor pattern layer.

[0013] In an embodiment, the second gate insulation pattern layer may have a shape and size corresponding to those of the second gate electrode, and may expose other portions of the second semiconductor pattern layer.

[0014] In an embodiment, the display device may further include: an interlayer insulating layer covering the first gate electrode and the second gate electrode. The first transistor may further include a first source electrode and a first drain electrode disposed on the interlayer insulating layer and connected to different portions of the first semiconductor pattern layer, and the second transistor may further include a second source electrode and a second drain electrode disposed on the interlayer insulating layer and connected to different portions of the second semiconductor pattern layer.

[0015] In an embodiment, the first lower electrode may be connected to the first source electrode.

[0016] In an embodiment, the second lower electrode may be connected to the second gate electrode.

[0017] In an embodiment, the display device may further include: a pixel disposed in the display area and including a first transistor.

[0018] In an embodiment, the pixel may further include a third transistor including a third semiconductor pattern layer formed as a semiconductor layer, a third gate electrode disposed on the third semiconductor pattern layer, and a third lower electrode formed as a second conductive layer and overlapping the third semiconductor pattern layer.

[0019] In an embodiment, the display device may further include: a driving circuit disposed in the driving circuit region and including a second transistor.

[0020] In an embodiment, the driving circuit may output a gate signal that controls the operation of pixels disposed in the display area.

[0021] According to the disclosed aspects, a method for manufacturing a display device is provided, the method comprising: providing a substrate including a display area and a driving circuit area; forming a first lower electrode on the substrate in the display area; forming a first insulating layer covering the first lower electrode on the substrate; forming a second lower electrode on the first insulating layer in the driving circuit area; forming a second insulating layer covering the second lower electrode on the first insulating layer; forming a first semiconductor pattern layer overlapping the first lower electrode and a second semiconductor pattern layer overlapping the second lower electrode on the second insulating layer; forming a third insulating layer covering the first semiconductor pattern layer and the second semiconductor pattern layer on the second insulating layer; and forming a first gate electrode overlapping the first semiconductor pattern layer and a second gate electrode overlapping the second semiconductor pattern layer on the third insulating layer.

[0022] In an embodiment, in the step of forming the first semiconductor pattern layer and the second semiconductor pattern layer, the first semiconductor pattern layer and the second semiconductor pattern layer may be simultaneously formed of the same oxide semiconductor.

[0023] In an embodiment, the method may further include: forming a first gate insulation pattern layer on a portion of the first semiconductor pattern layer overlapping the first gate electrode by etching the third insulation layer; and forming a second gate insulation pattern layer on a portion of the second semiconductor pattern layer overlapping the second gate electrode.

[0024] In an embodiment, the method may further include: forming an interlayer insulating layer covering the first gate electrode and the second gate electrode on the second insulating layer.

[0025] In an embodiment, the method may further include: forming at least one of a first drain electrode, a first source electrode, a second drain electrode, and a second source electrode on the interlayer insulating layer. The first drain electrode and the first source electrode may be connected to the first semiconductor pattern layer, and the second drain electrode and the second source electrode may be connected to the second semiconductor pattern layer.

[0026] According to the display device and the method for manufacturing the display device of the embodiment, the first transistor arranged in the display area and the second transistor arranged in the driving circuit area can be formed in different structures according to the operating characteristics required by each transistor. For example, the first transistor of the pixel can have a double-gate structure including a first conductive layer arranged under the first semiconductor pattern layer of the first transistor and formed as a substrate and a first insulating layer. The second transistor of the driving circuit can have a double-gate structure including a second conductive layer arranged under the second semiconductor pattern layer of the second transistor and formed as a second conductive layer on the first insulating layer.

[0027] According to an embodiment, the size of the capacitance formed between the semiconductor pattern layer and the lower electrode of each transistor can be distinguished and / or optimized according to the characteristics required by each transistor. For example, the capacitance formed in the first transistor of each pixel is reduced or minimized, so that the brightness of the pixel can be prevented from changing and the image quality can be improved. In addition, the capacitance formed in the second transistor is increased to increase the on-current of the second transistor, so that the output characteristics of the driving circuit can be improved and the pixel can be stably driven.

[0028] However, the effects according to the embodiment are not limited to the above-mentioned effects, and various other effects are included therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the disclosure will become more apparent by describing the disclosed embodiments in detail with reference to the accompanying drawings, in which: Figure 1 is a schematic plan view showing a display device according to an embodiment; Figure 2 It is shown Figure 1 A schematic plan view of a display panel; Figure 3 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment; Figure 4 is a schematic diagram showing a driving circuit of a first driver according to an embodiment; Figure 5 is a schematic diagram showing an equivalent circuit of a stage of a driving circuit according to an embodiment; Figure 6 is a schematic cross-sectional view showing a display panel according to an embodiment; Figure 7 is a schematic cross-sectional view showing a display panel according to an embodiment; and Figures 8 to 18 is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0030] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is clear that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive or limit disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0031] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the invention. Therefore, without departing from the scope of the invention, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged.

[0032] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Thus, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0033] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bonded to" another element or layer, it may be directly on the other element or layer, directly connected to or directly bonded to the other element or layer, or there may be an intervening element or intervening layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intervening element or intervening layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intervening element. In addition, the axis of the first direction D1, the axis of the second direction D2, and the axis of the third direction D3 are not limited to three axes of a rectangular coordinate system such as an X-axis, a Y-axis, and a Z-axis, and may be interpreted in a broader sense. For example, the axis of the first direction D1, the axis of the second direction D2, and the axis of the third direction D3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0034] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be referred to as the second element.

[0035] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "lower," "above," "upper," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "below" or "below" other elements or features will subsequently be oriented as "above" the other elements or features. Thus, the term "below" may cover both above and below orientations. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0036] The terms used herein are for the purpose of describing a particular embodiment and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "the (intended)" are also intended to include plural forms. In addition, when the terms "include" and / or "comprise" are used in this specification, the stated features, integral bodies, steps, operations, elements, components and / or groups thereof are specified to exist, but one or more other features, integral bodies, steps, operations, elements, components and / or groups thereof are not excluded from existence or addition. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and are thus used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0037] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes caused by, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specifically illustrated regions, but rather include shape deviations caused by, for example, manufacturing. In this manner, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, no limitation is necessarily intended.

[0038] According to the practice in the art, some embodiments are described and shown in the accompanying drawings in the form of functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc., which can be formed using semiconductor-based manufacturing technology or other manufacturing technology. In the case where the blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed here, and can be optionally driven by firmware and / or software. It is also expected that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and related circuits) for performing other functions. In addition, without departing from the scope of the invention, each block, unit and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0039] Figure 1 is a schematic plan view showing a display device 100 according to an embodiment. Figure 2 It is shown Figure 1 Schematic plan view of the display panel 110.

[0040] Reference Figure 1 and Figure 2 , the display device 100 may be a device for displaying a moving image or a still image. The display device 100 may be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs). These are examples, and the display device 100 may be applied to various other types of electronic devices.

[0041] In an embodiment, the display device 100 may be a light-emitting display device (such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or an ultra-small light-emitting display using an ultra-small light-emitting diode such as a micro light-emitting diode or a nano light-emitting diode (micro-LED or nano-LED)), but the embodiment is not limited thereto. For example, the display device 100 may be a display device of other types other than the light-emitting display device. Hereinafter, an embodiment in which the display device 100 is an organic light-emitting display device will be described.

[0042] The display device 100 may include a display panel 110 including pixels PX, and a first driver 120 and a second driver 130 that supply a driving signal to the pixels PX. The display device 100 may also include additional components. For example, the display device 100 may also include a power supply unit that supplies a power voltage to the pixels PX, the first driver 120 and the second driver 130, and a timing controller that controls the operation of the first driver 120 and the second driver 130.

[0043] The display panel 110 may include a display area DA and a non-display area NDA (also referred to as a "frame area"). The display area DA may be an area including pixels PX for displaying an image. The non-display area NDA may be an area other than the display area DA, and an image may not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA may be positioned around the display area DA and may surround the display area DA.

[0044] exist Figure 1 and Figure 2 In the embodiment, the first direction D1, the second direction D2 and the third direction D3 are defined. In an embodiment, the first direction D1 and the second direction D2 may be perpendicular to each other, the first direction D1 and the third direction D3 may be perpendicular to each other, and the second direction D2 and the third direction D3 may be perpendicular to each other. For example, the first direction D1 may be the horizontal direction of the display panel 110 (e.g., the row direction or the X-axis direction), and the second direction D2 may be the vertical direction of the display panel 110 (e.g., the column direction or the Y-axis direction). The third direction D3 may be the thickness direction of the display panel 110 (e.g., the height direction or the Z-axis direction).

[0045] In an embodiment, the display panel 110 may have a rectangular shape in a plan view. For example, the display panel 110 may include two first sides extending in a first direction D1 and two second sides extending in a second direction D2 crossing the first direction D1. Figure 1 and Figure 2The display panel 110 is shown in which the first side in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction or the lengths of the first side and the second side may be substantially the same as each other.

[0046] In an embodiment, the display panel 110 may include an angled corner (or a curved corner) at a portion where the first side and the second side meet, but the embodiment is not limited thereto. For example, the display panel 110 may include a rounded corner at a portion where the first side and the second side meet.

[0047] The planar shape of the display panel 110 is not limited to the rectangular shape shown, and it can be applied in various shapes. For example, the display panel 110 can have a square shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes in a plan view.

[0048] In an embodiment, the display panel 110 may be substantially flat on a plane defined by the first direction D1 and the second direction D2, and may have a uniform thickness in the third direction D3. In another embodiment, the display panel 110 may be provided in a three-dimensional shape having a curved surface or the like.

[0049] The display panel 110 may be provided as a panel having a rigid property so as not to be substantially deformed, or may be provided as a panel having a flexible property that may be deformed to be at least partially folded, bent, or rolled. The display panel 110 may be provided to the display device 100 without being bent, or may be provided to the display device 100 while being partially bent.

[0050] The display panel 110 may include a substrate SUB and pixels PX disposed on the substrate SUB. The pixels PX may be disposed in a display area DA on the substrate SUB.

[0051] The substrate SUB, which is a base member for manufacturing or disposing the display panel 110, may form a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA positioned around the display area DA.

[0052] According to an embodiment, the display area DA may have various shapes. For example, the display area DA may have a quadrilateral shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes. In an embodiment, the display area DA may have a shape corresponding to the shape of the display panel 110, but the embodiment is not limited thereto.

[0053] The display area DA may include a pixel area in which pixels PX are arranged and / or disposed. For example, each pixel PX may be disposed in each pixel area located in the display area DA. In an embodiment, the display device 100 may be a light-emitting display device, and each pixel PX may include a light-emitting element located in each emission area and a pixel circuit connected to the light-emitting element. When describing an embodiment, the term "connection" may include electrical connection and / or physical connection.

[0054] Each pixel region may include an emission region where a light emitting element of a corresponding pixel is located and the pixel emits light and a pixel circuit region where circuit elements constituting a pixel circuit of the corresponding pixel are located. In an embodiment, the emission region and the pixel circuit region of each pixel PX may overlap each other, but the embodiment is not limited thereto.

[0055] The pixels PX may be arranged in the display area DA. For example, the pixels PX may be arranged in a stripe structure, a triangle structure, a pentile structure, or a ® Structures or other arrangements are arranged in the display area DA.

[0056] The non-display area NDA may include a driving circuit area positioned at least one side of the display area DA and a pad area PA where a pad (also referred to as a "pad") PD is positioned. At least one driver, pad PD and / or wiring may be provided in the non-display area NDA.

[0057] At least one driver or a portion of the driver for driving the pixel PX may be disposed in the driving circuit region. For example, circuit elements constituting the first driver 120 may be disposed in the driving circuit region on the substrate SUB. In an embodiment, the circuit elements of the first driver 120 may be formed in the display panel 110 together with the pixel PX.

[0058] The pad PD may be disposed in the pad area PA. At least one circuit board 140 may be disposed and / or bonded in the pad area PA. In an embodiment, the circuit board 140 connected to different pads PD may be disposed in the pad area PA. The pad PD may include a signal pad and a power pad for transmitting a driving signal and a power voltage required for driving the pixel PX and / or the first driver 120 to the display panel 110.

[0059] The first driver 120 and the second driver 130 may generate a driving signal for controlling the operation timing and brightness of the pixel PX, etc., and may supply the generated driving signal to the pixel PX. For example, the first driver 120 may be a gate driver including a scan driver, and may be connected to the pixel PX through a corresponding gate line. The first driver 120 may supply a gate signal (for example, including a gate line) to the pixel PX. Figure 3The second driver 130 may be a data driver including a source driving circuit and may be connected to the pixel PX through a corresponding data line. The second driver 130 may supply a corresponding data signal to the pixel PX.

[0060] In an embodiment, at least one of the first driver 120 and the second driver 130 or a portion of at least one of the first driver 120 and the second driver 130 may be embedded in the display panel 110. For example, the first driver 120 or a portion of the first driver 120 may be disposed or formed in the non-display area NDA of the display panel 110.

[0061] although Figure 1 It is shown that the first driver 120 is formed on one side (e.g., the opposite side) of the display area DA (e.g., the first driver 120 is formed in the non-display area NDA located on the left and right sides of the display area DA), but the embodiment is not limited thereto. For example, in another embodiment, the first driver 120 may be provided only on one side of the display area DA. In another embodiment, a portion of the first driver 120 (e.g., some of the circuit elements constituting the first driver 120) may be positioned in the non-display area NDA, and another portion of the first driver 120 (e.g., the rest of the circuit elements constituting the first driver 120) may be positioned in a non-emission area (e.g., an area between emission areas of the pixels PX) provided in the display area DA.

[0062] In an embodiment, other drivers or a portion of other drivers in the first driver 120 and the second driver 130 may be disposed or formed outside the display panel 110 to be electrically connected to the display panel 110. For example, the second driver 130 or a portion of the second driver 130 may be implemented by a plurality of integrated circuit chips and may be placed on a circuit board 140 electrically connected to the pixel PX of the display panel 110. In an embodiment, the second driver 130 and the timing controller may be integrated into a separate integrated circuit or may be integrated into an integrated chip. The second driver 130 may be implemented as at least one integrated circuit chip and may be mounted in the non-display area NDA of the display panel 110.

[0063] The circuit board 140 may be connected to the display panel 110 through a pad PD. In an embodiment, the circuit board 140 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF), but the embodiment is not limited thereto. In an embodiment, the circuit board 140 may be connected to the timing controller and / or the power supply unit through another circuit board or a connector, etc.

[0064] Figure 3 is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment. Figure 3 The pixel PX of FIG. 1 is an example, and the structure or type of the pixel PX may be changed in various ways according to the embodiment.

[0065] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 , the pixel PX may include a light emitting element ED and a pixel circuit PC connected to the light emitting element ED. The light emitting element ED may be a light source of the pixel PX, and it may be, for example, an organic light emitting diode, but the embodiment is not limited thereto. The pixel circuit PC may control the emission time point and brightness of the light emitting element ED.

[0066] The pixel circuit PC may include a pixel transistor Tpx (also referred to as a "first group transistor" or a "transistor of the display area DA") and at least one pixel capacitor Cpx. For example, the pixel circuit PC may include first to fifth pixel transistors T1 to T5 and first and second pixel capacitors C1 and C2. The structure of the pixel circuit PC or the types of circuit elements constituting the pixel circuit PC may be changed in various ways according to the embodiment. Although Figure 3 An embodiment in which the pixel transistors Tpx are all N-type transistors is shown, but the type of the pixel transistors Tpx is not limited thereto. For example, at least one pixel transistor Tpx may be formed of a P-type transistor.

[0067] The pixel circuit PC may supply the driving current Id to the light emitting element ED in response to the driving signals supplied from the first driver 120 and the second driver 130. For example, the pixel circuit PC may supply the driving current Id to the light emitting element ED in response to the corresponding gate signal GS supplied from the first driver 120 through the corresponding gate line GL and the data signal DATA supplied from the second driver 130 through the data line DL.

[0068] The first pixel transistor T1 may be a driving element of the pixel PX in which the size (or amount) of the source-drain current (e.g., the driving current Id) is determined according to the gate-source voltage. The second pixel transistor T2 to the fifth pixel transistor T5 may be a switching element that is turned on or off according to their own gate-source voltage (basically, their own gate voltage). According to the type (e.g., P-type or N-type) and / or operating conditions of each of the first pixel transistor T1 to the fifth pixel transistor T5, the first electrode of each of the first pixel transistor T1 to the fifth pixel transistor T5 may be a drain electrode (or drain region) or a source electrode (or source region), and the second electrode of each of the first pixel transistor T1 to the fifth pixel transistor T5 may be an electrode different from the first electrode. For example, in the case where the first electrode is a drain electrode, the second electrode may be a source electrode.

[0069] The pixel PX may be connected to a first gate line GWL transmitting a first gate signal GW (e.g., a scan signal), a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, an emission control line ECL transmitting an emission control signal EM, and a data line DL transmitting a data signal DATA. In addition, the pixel PX may be connected to a first pixel power line VDL transmitting a first pixel voltage ELVDD (also referred to as a "first pixel power voltage") and a second pixel power line VSL transmitting a second pixel voltage ELVSS (also referred to as a "second pixel power voltage"). In an embodiment, the pixel PX may also be connected to an initialization power line VIL transmitting an initialization voltage VINT (also referred to as a "third pixel power voltage") and a reference power line VRL transmitting a reference voltage VREF (also referred to as a "fourth pixel power voltage"). In an embodiment, the initialization power line VIL may include initialization power lines VIL (e.g., first initialization power line VIL1 and second initialization power line VIL2) for transmitting initialization voltages VINT having different magnitudes (e.g., first initialization voltage VINT1 and second initialization voltage VINT2).

[0070] In an embodiment, the first pixel transistor T1 to the fifth pixel transistor T5 may be positioned in corresponding pixel regions (eg, disposed at Figure 6The pixel area PXA of any one pixel PX in the display area DA may be an oxide transistor (also referred to as an "oxide semiconductor transistor") including an oxide semiconductor (e.g., an oxide semiconductor material). For example, the semiconductor pattern layer (also referred to as an "active pattern layer" or "active layer") of each of the first pixel transistor T1 to the fifth pixel transistor T5 may be formed of an oxide semiconductor. However, the embodiment is not limited thereto. For example, at least one pixel transistor Tpx may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0071] The oxide semiconductor may have high carrier mobility (e.g., high electron mobility in the case of an N-type transistor) and low leakage current, so the voltage drop may not be large when the driving time of the oxide transistor is long. For example, since the change in brightness and / or color of an image caused by the voltage drop is not significant even when driven at a low frequency, the pixel PX including the oxide transistor may be driven at a low frequency. In the case of the display device 100 in which the first pixel transistor T1 to the fifth pixel transistor T5 include an oxide semiconductor, the leakage current of the pixel PX may be reduced or prevented, and the power consumption may be reduced.

[0072] The oxide semiconductor is sensitive to light, so that the amount of current, etc. may vary due to external light. In an embodiment, a lower electrode (also referred to as a "gate electrode" or a "bottom electrode") may be disposed under a semiconductor pattern layer constituting at least one pixel transistor Tpx (e.g., at least one of the first pixel transistor T1 to the fifth pixel transistor T5). For example, the lower electrode may be disposed under a semiconductor pattern layer of a pixel transistor Tpx including an oxide semiconductor. The lower electrode may be disposed to face the gate electrode, and the semiconductor pattern layer of the corresponding pixel transistor Tpx is disposed between the lower electrode and the gate electrode.

[0073] In describing the following embodiments, the lower electrode provided to at least one pixel transistor Tpx is referred to as a "first lower electrode BG1". By providing the first lower electrode BG1 to the pixel transistor Tpx, a change in the amount of current of the pixel transistor Tpx caused by light can be prevented, reduced or minimized, and the operating characteristics of the pixel transistor Tpx can be stabilized. The pixel transistor Tpx including the first lower electrode BG1 may have operating characteristics corresponding to a capacitance (e.g., a parasitic capacitance) formed between the first lower electrode BG1 and the semiconductor pattern layer.

[0074] The first pixel transistor T1 may include a gate electrode connected to the first node N1 (or gate node), a first electrode (e.g., a drain electrode or drain region) connected to the second node N2, and a second electrode (e.g., a source electrode or source region) connected to the third node N3. In an embodiment, the first pixel transistor T1 may further include a first lower electrode BG1. For example, the first pixel transistor T1 may further include a first lower electrode BG1 (also referred to as a "first bottom electrode", "first bottom gate electrode" or "first back gate electrode") connected to the third node N3. In the case where the first lower electrode BG1 of the first pixel transistor T1 is connected to the third node N3 similarly to the second electrode of the first pixel transistor T1, the operating characteristics of the first pixel transistor T1 may be improved. The first electrode of the first pixel transistor T1 may be connected to the first pixel power line VDL via the fifth pixel transistor T5, and the second electrode of the first pixel transistor T1 may be connected to the light emitting element ED. The first pixel transistor T1 may be used as a driving element of the pixel PX, and may control the size (e.g., the amount of current) of the driving current Id flowing to the light emitting element ED in response to the data signal DATA transmitted according to the switching operation of the second pixel transistor T2.

[0075] In an embodiment, at least one of the second pixel transistor T2 to the fifth pixel transistor T5 may also include a lower electrode (e.g., each first lower electrode BG1). At least one transistor may have an operating characteristic corresponding to a capacitance formed between the lower electrode and the semiconductor pattern layer. In an embodiment, the lower electrode of at least one transistor may be connected to an electrode of the transistor (e.g., a gate electrode).

[0076] The second pixel transistor T2 may include a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The second pixel transistor T2 may be turned on by a first gate signal GW (e.g., a gate-on voltage of the first gate signal GW) transmitted to the first gate line GWL to connect the data line DL and the first node N1. Therefore, the data signal DATA transmitted through the data line DL may be transmitted to the first node N1.

[0077] The third pixel transistor T3 may include a gate electrode connected to the third gate line GRL, a first electrode connected to the reference power line VRL, and a second electrode connected to the first node N1. The third pixel transistor T3 may be turned on by a third gate signal GR transmitted through the third gate line GRL, and may transmit a reference voltage VREF transmitted to the reference power line VRL to the first node N1.

[0078] The fourth pixel transistor T4 may include a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3, and a second electrode connected to the initialization power line VIL. The fourth pixel transistor T4 may be turned on by the second gate signal GI transmitted via the second gate line GIL, and may transmit the initialization voltage VINT transmitted to the initialization power line VIL to the third node N3.

[0079] The fifth pixel transistor T5 may include a gate electrode connected to the emission control line ECL, a first electrode connected to the first pixel power line VDL, and a second electrode connected to the second node (or the first electrode of the first pixel transistor T1). The fifth pixel transistor T5 may be turned on by the emission control signal EM (e.g., the gate-on voltage of the emission control signal EM) transmitted to the emission control line ECL to control the emission time point of the pixel PX.

[0080] The first pixel capacitor C1 may be connected between the first node N1 and the third node N3. For example, the first pixel capacitor C1 may be connected between the second electrode and the gate electrode of the first pixel transistor T1. The first pixel capacitor C1 may be a storage capacitor of the pixel PX and may store a threshold voltage of the first pixel transistor T1 and a voltage corresponding to the data signal DATA (e.g., a data voltage).

[0081] The second pixel capacitor C2 may be connected between the first pixel power line VDL and the third node N3. In an embodiment, the capacitance of the second pixel capacitor C2 may be smaller than the capacitance of the first pixel capacitor C1.

[0082] The light emitting element ED may be connected between the third node N3 and the second pixel power line VSL. For example, the light emitting element ED may include a first electrode (e.g., an anode electrode or a pixel electrode), a second electrode (e.g., a cathode electrode or a counter electrode) facing the first electrode, and a light emitting layer disposed between the first electrode and the second electrode. The first electrode of the light emitting element ED may be connected to the third node N3. The second electrode of the light emitting element ED may be connected to the second pixel power line VSL. In an embodiment, the second electrode of the light emitting element ED may be a common electrode shared by the pixels PX. During a time period in which a driving current Id is supplied from the pixel circuit PC, the light emitting element ED may emit light having a brightness corresponding to the driving current Id.

[0083] Figure 4 is a schematic diagram showing a driving circuit 121 of the first driver 120 according to an embodiment. Figure 4A type of driving circuit 121 included in (or constituting) the first driver 120 is shown as an example for illustrating the configuration of the first driver 120. In an embodiment, the driving circuit 121 may be a scanning driving circuit (or scanning driver) that outputs a first gate signal GW of a pixel PX, but the embodiment is not limited thereto. For example, Figure 4 The driving circuit 121 is shown as an example, and the type, structure, number and / or input / output signals of the first driver 120 or the driving circuit 121 constituting the first driver 120 may be changed in various ways according to the embodiment.

[0084] In the following description, the term "previous stage (or the previous stage)" may refer to a stage that generates a first gate signal GW whose phase is faster than the first gate signal GW output at a specific stage as a reference. In addition, the term "next stage (or the next stage)" may refer to a stage that generates a first gate signal GW whose phase is later than the first gate signal GW output at a specific stage as a reference.

[0085] Apart from Figures 1 to 3 In addition, refer to Figure 4 , the driving circuit 121 may include a stage ST.

[0086] Each of the stages ST may receive a plurality of driving power voltages and a plurality of external signals. The stage ST may output a corresponding first gate signal GW based on a plurality of driving power voltages (or a plurality of driving voltages) and a plurality of external signals input thereto. In an embodiment, the driving power voltage may include a first driving voltage VON (also referred to as a "control voltage") as a high potential voltage, a second driving voltage VSS1 (also referred to as a "first driving power voltage" or a "first low potential driving voltage") as a first low potential voltage, and at least one of a third driving voltage VSS2 (also referred to as a "second driving power voltage" or a "second low potential driving voltage") as a second low potential voltage. For example, the plurality of external signals may include at least one of a scan start signal STV, a carry signal input from a previous stage, a reset signal input from a subsequent stage, and a scan clock signal (e.g., a first scan clock signal SCLK and a second scan clock signal SCLKB), but the embodiment is not limited thereto. In an embodiment, the third driving voltage VSS2 may have a potential lower than that of the second driving voltage VSS1.

[0087] The first gate signal GW output from each stage ST (eg, Figure 4The first gate signal GW1 outputted from the first stage ST1 may be supplied to the next stage (e.g., the second stage ST2) as a carry signal. In response to the carry signal (e.g., the first carry signal) inputted from the previous stage, each stage ST may output the first gate signal GW to the gate line GWL connected thereto. Among the stages ST, the first stage ST1 may receive the scan start signal STV from the outside as a carry signal.

[0088] The first gate signal GW output from each stage ST may be supplied to the previous stage as a reset signal (eg, a second carry signal). Each stage ST may transition the potential of the output node from a high potential voltage to a second low potential voltage (eg, a third driving voltage VSS2) in response to the reset signal input from the next stage.

[0089] The stage ST may output the first gate signal GW in response to the scan start signal STV. For example, the stage ST may sequentially output the first gate signal GW to the first gate line GWL in response to the scan start signal STV. For example, the nth (n is a natural number greater than 0) stage (eg, Figure 5 The nth level STn) can be Figure 5 The nth first gate signal GWn (eg, Figure 4 GW1, GW2, GW3, GW4, ...) are output to Figure 5 The nth first gate line GWLn (eg, Figure 4 A scan start signal STV for controlling an output timing of a first gate signal GW1 (eg, a first scan signal) may be supplied to the first stage ST1.

[0090] Each of the stages ST may include a first input terminal IN1 , a second input terminal IN2 , a third input terminal IN3 , a scan clock input terminal CK, a first power input terminal V1 , a second power input terminal V2 , a carry output terminal CR, and an output terminal OUT.

[0091] Each of the stages ST may receive the first scan clock signal SCLK or the second scan clock signal SCLKB through the scan clock input terminal CK. For example, when the even-numbered stages ST2, ST4, ... receive the second scan clock signal SCLKB, the odd-numbered stages ST1, ST3, ... may receive the first scan clock signal SCLK.

[0092] The first scan clock signal SCLK may be a square wave signal (or a pulse signal) that repeats a logic high level and a logic low level. The logic high level may correspond to a gate-on voltage, and the logic low level may correspond to a gate-off voltage. For example, the logic high level may be a gate high voltage having a voltage value in the range of about 10V to about 30V, and the logic low level may be a gate low voltage having a voltage value in the range of about -16V to about -3V.

[0093] The second scan clock signal SCLKB may be a square wave signal (or a pulse signal) that repeats a logic high level and a logic low level. In an embodiment, the second scan clock signal SCLKB may be set to a signal having the same period as the first scan clock signal SCLK but having an opposite phase. However, this is an example, and the waveform relationship between the first scan clock signal SCLK and the second scan clock signal SCLKB is not limited thereto. For example, a portion of the logic high level period of the first scan clock signal SCLK and a portion of the logic high level period of the second scan clock signal SCLKB may overlap.

[0094] For example, the number of scan clock signals supplied to one stage is not limited to the above example. For example, two or more scan clock signals may be applied to each of the stages ST.

[0095] The first input terminal IN1 may receive a scan start signal STV or a carry signal of a previous stage. For example, the scan start signal STV may be applied to the first input terminal IN1 of the first stage ST1, and the carry signal of the previous stage may be applied to the first input terminal IN1 of each of the stages ST2, ST3, ST4, ... except the first stage ST1.

[0096] The second input terminal IN2 may receive a carry signal of a subsequent stage. For example, the carry signal of the subsequent stage may be one of the carry signals supplied after a certain time has passed from the output of the carry signal of the current stage.

[0097] The third input terminal IN3 may receive a first drive voltage VON. In an embodiment, the first drive voltage VON may be a high potential voltage to be supplied to a source electrode of at least one transistor included in each of the stages ST. For example, the first drive voltage VON may be a constant voltage close to a logic high level (e.g., a gate-on voltage) of the first scan clock signal SCLK. For example, the first drive voltage VON may have a voltage value in the range of about 10V to about 30V.

[0098] In an embodiment, the first driving voltage VON and the scan clock signal SCLK or SCLKB may be identical to each other. For example, each of the stages ST may receive the same clock signal through the scan clock input terminal CK and the third input terminal IN3.

[0099] The carry output terminal CR may output a carry signal. The carry signal may be provided to a first input terminal IN1 of a subsequent stage.

[0100] The output terminal OUT may output the first gate signal GW generated at each stage ST. The first gate signal GW may be supplied to the pixel PX through the first gate line GWL corresponding to the pixel PX.

[0101] The first power input terminal V1 may be supplied with a second drive voltage VSS1, and the second power input terminal V2 may be supplied with a third drive voltage VSS2. The second drive voltage VSS1 and the third drive voltage VSS2 may be set as gate-off voltages. In an embodiment, the second drive voltage VSS1 and the third drive voltage VSS2 may be the same as each other. In an embodiment, the voltage level of the third drive voltage VSS2 may be lower than the voltage level of the second drive voltage VSS1. For example, the second drive voltage VSS1 may be set in a range of about -14V to about -1V, and the third drive voltage VSS2 may be set in a range of about -16V to about -3V.

[0102] Figure 5 is a schematic diagram showing an equivalent circuit of the stage ST (or STn) of the driving circuit 121 according to the embodiment. Figure 5 An n-th stage STn included in (or constituting) the above-described driving circuit 121 is shown as an example for illustrating the configuration of the driving circuit 121 . Figure 5 The nth stage STn is an example, and a structure, input / output signals, and / or operation method of the nth stage STn may be variously changed according to embodiments.

[0103] although Figure 5 An embodiment is shown in which the driving transistors Tdr (also referred to as "second group transistors" or "transistors of the built-in driving circuit") constituting the nth stage STn are N-type transistors, but the type of the driving transistors Tdr is not limited thereto. For example, at least one driving transistor Tdr may be formed of a P-type transistor.

[0104] Apart from Figures 1 to 4 In addition, refer to Figure 5 The nth stage STn may include a first input unit 510, a second input unit 520, a first controller 530, an output unit 540, and a leakage controller 550. In an embodiment, the nth stage STn may further include a second controller 560 and a third controller 570.

[0105] In an embodiment, the driving transistor Tdr included in the nth stage STn may be positioned in a driving circuit area of ​​the display panel 110 (e.g., a driving circuit area in which the first driver 120 is disposed in the non-display area NDA of the display panel 110). In an embodiment, the driving transistor Tdr may be an oxide transistor including an oxide semiconductor (e.g., an oxide semiconductor material). For example, the semiconductor pattern layer of each of the driving transistors Tdr may be formed of an oxide semiconductor. In an embodiment, the driving transistor Tdr and the pixel transistor Tpx may be formed simultaneously using the same oxide semiconductor. For example, the semiconductor pattern layer of the driving transistor Tdr and the pixel transistor Tpx may include the same oxide semiconductor and may be disposed on the same layer on the substrate SUB. However, the embodiment is not limited thereto. For example, at least one driving transistor Tdr may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0106] Each of the driving transistors Tdr may or may not include a lower electrode overlapping the semiconductor pattern layer (for example, the lower electrode is disposed under the semiconductor pattern layer and faces the gate electrode, and the semiconductor pattern layer is disposed between the lower electrode and the gate electrode). In an embodiment, the driving transistor Tdr may include a corresponding lower electrode disposed under the semiconductor pattern layer. When describing the following embodiments, the lower electrode provided to each of the driving transistors Tdr is referred to as a "second lower electrode BG2". By providing the second lower electrode BG2 to each of the driving transistors Tdr, the operating characteristics of the driving transistor Tdr can be improved and / or stabilized. The driving transistor Tdr including the second lower electrode BG2 may have an operating characteristic corresponding to a capacitance (for example, a parasitic capacitance) formed between the second lower electrode BG2 and the semiconductor pattern layer.

[0107] In an embodiment, at least one driving transistor Tdr may include a second lower electrode BG2 (also referred to as a "second bottom electrode", "second bottom gate electrode" or "second back gate electrode") connected to a gate electrode of the transistor. For example, some driving transistors Tdr including the driving transistor Tdr of the output unit 540 that performs a pull-up operation or a pull-down operation or all driving transistors Tdr constituting the nth stage STn may be transistors of a dual-gate structure including corresponding second lower electrodes BG2 connected to corresponding gate electrodes. Figure 5 An n-th stage STn is shown in which all driving transistors Tdr are formed in a dual-gate structure.

[0108] By forming the driving transistor Tdr into a dual-gate structure, the operating characteristics of the driving transistor Tdr can be improved. For example, by forming the driving transistor Tdr into a dual-gate structure, the cut-off characteristics and switching speed of the driving transistor Tdr can be improved, an additional voltage tolerance range can be ensured, leakage current can be reduced, and voltage stability can be improved.

[0109] The first input unit 510 may control the voltage of the first node Nd1 in response to the scan start signal STV or the carry signal CRn-1 of the previous stage supplied to the first input terminal IN1. The voltage of the first node Nd1 may be a voltage for controlling the output of the nth first gate signal (hereinafter, referred to as "nth scan signal GWn") and the nth carry signal CRn. For example, the voltage of the first node Nd1 may be a voltage for controlling the pull-up of the nth carry signal CRn and the nth scan signal GWn.

[0110] In an embodiment, the first input unit 510 may include a second drive transistor (eg, a second-first drive transistor M2-1 and a second-second drive transistor M2-2) connected in series between the first input terminal IN1 and the first node Nd1. Gate electrodes of the second drive transistors M2-1 and M2-2 may be commonly connected to the first input terminal IN1.

[0111] The first input unit 510 may transmit the gate-on voltage (eg, logic high level) of the n-1th carry signal CRn-1 to the first node Nd1. For example, the first input unit 510 may precharge the voltage of the first node Nd1 by using the gate-on voltage of the n-1th carry signal CRn-1.

[0112] The common node between the second driving transistors M2-1 and M2-2 may correspond to the third node Nd3. For example, the common node between the second driving transistors M2-1 and M2-2 may be connected to the third node Nd3.

[0113] In the case where the voltage of the first node Nd1 is a high level of the gate-on voltage, in the case where the voltage of the common node between the second driving transistors M2-1 and M2-2 is lower than a selectable / selected reference value, a leakage current may be generated (or occur) from the first node Nd1 to the first input unit 510. For example, in the case where the threshold voltage is negatively shifted due to degradation of the second driving transistors M2-1 and M2-2, a leakage current may be generated (or occur) from the first node Nd1 to the first input unit 510.

[0114] In each oxide transistor, a threshold voltage may shift to a negative value (eg, negative shift) due to degradation, etc. For example, a leakage current of the oxide transistor in an off state increases, so that the nth stage STn may operate abnormally.

[0115] In a state where the first node Nd1 is charged with the gate-on voltage, a high voltage level of the gate-on voltage may be applied to a common node between the second drive transistors M2-1 and M2-2. For example, the n-1th carry signal CRn-1 may have a gate-off voltage, and the gate-off voltage of the n-1th carry signal CRn-1 may be supplied to the gate electrodes of the second drive transistors M2-1 and M2-2. Therefore, the gate-source voltage of the second-second drive transistor M2-2 may be maintained at a very low value (e.g., a negative value), and in the case where the second drive transistors M2-1 and M2-2 are degraded, current leakage from the first node Nd1 to the first input unit 510 may be prevented.

[0116] The second input unit 520 may control the voltage of the first node Nd1 in response to a reset signal of a subsequent stage (e.g., the n+1th carry signal CRn+1). In an embodiment, the second input unit 520 may provide the voltage of the third driving voltage VSS2 to the first node Nd1 in response to the n+1th carry signal CRn+1. For example, the second input unit 520 may discharge the voltage of the first node Nd1 having a specific high potential voltage.

[0117] The second input unit 520 may include a third drive transistor (eg, a third-first drive transistor M3-1 and a third-second drive transistor M3-2) connected in series between the first node Nd1 and the second power input terminal V2. Gate electrodes of the third drive transistors M3-1 and M3-2 may be commonly connected to the second input terminal IN2.

[0118] A common node between the third transistors M3-1 and M3-2 may correspond to the third node Nd3. For example, a common node between the third driving transistors M3-1 and M3-2 may be connected to the third node Nd3.

[0119] The first controller 530 may control the voltage of the output terminal OUT outputting the nth scan signal GWn in response to the n+1th carry signal CRn+1. In an embodiment, the first controller 530 may provide the voltage of the second driving voltage VSS1 to the output terminal OUT in response to the n+1th carry signal CRn+1.

[0120] In an embodiment, the first controller 530 may include a fourth drive transistor M4 connected between the output terminal OUT and the first power input terminal V1. The gate electrode of the fourth drive transistor M4 may be connected to the second input terminal IN2. The fourth drive transistor M4 may discharge the voltage of the output terminal OUT to the voltage of the second drive voltage VSS1.

[0121] The output unit 540 may be connected to the scan clock input terminal CK, the first power input terminal V1, and the second power input terminal V2. The output unit 540 may output the nth scan signal GWn corresponding to the scan clock signal SCLK and the nth carry signal CRn to the output terminal OUT and the carry output terminal CR, respectively, in response to the voltage of the first node Nd1 and the voltage of the second node Nd2. The voltage of the second node Nd2 may control the gate cut-off voltage (e.g., logic low level) state of the nth scan signal GWn and the nth carry signal CRn. For example, the voltage of the second node Nd2 may be a voltage for controlling the pull-down of the nth carry signal CRn and the nth scan signal GWn. In an embodiment, the output unit 540 may include the fifth drive transistor M5 to the eighth drive transistor M8 and the drive capacitor C.

[0122] The fifth drive transistor M5 may be connected between the scan clock input terminal CK and the output terminal OUT. The fifth drive transistor M5 may include a gate electrode connected to the first node Nd1. The fifth drive transistor M5 may supply a gate-on voltage to the output terminal OUT in response to the voltage of the first node Nd1. For example, the fifth drive transistor M5 may be used as a pull-up buffer.

[0123] The sixth drive transistor M6 may be connected between the output terminal OUT and the first power input terminal V1. The sixth drive transistor M6 may include a gate electrode connected to the second node Nd2. The sixth drive transistor M6 may supply a gate-off voltage to the output terminal OUT in response to the voltage of the second node Nd2. For example, the sixth drive transistor M6 may maintain the voltage of the output terminal OUT at a gate-off voltage level (e.g., a logic low level).

[0124] The seventh drive transistor M7 may be connected between the scan clock input terminal CK and the carry output terminal CR. The seventh drive transistor M7 may include a gate electrode connected to the first node Nd1. The seventh drive transistor M7 may supply a gate-on voltage to the carry output terminal CR in response to the voltage of the first node Nd1. For example, the seventh drive transistor M7 may be used as a pull-up buffer.

[0125] The eighth drive transistor M8 may be connected between the carry output terminal CR and the second power input terminal V2. The eighth drive transistor M8 may include a gate electrode connected to the second node Nd2. The eighth drive transistor M8 may supply a gate-off voltage to the carry output terminal CR in response to the voltage of the second node Nd2. For example, the eighth drive transistor M8 may maintain the voltage of the carry output terminal CR at a gate-off voltage level (e.g., a logic low level).

[0126] The driving capacitor C may be connected between the first node Nd1 and the output terminal OUT. The driving capacitor C may be used as a boost capacitor. For example, when the fifth driving transistor M5 is turned on, the driving capacitor C may increase (or improve) the voltage of the first node Nd1 in response to the increase in the voltage of the output terminal OUT. Therefore, the fifth driving transistor M5 may stably maintain the turned-on state for a period of time.

[0127] The second controller 560 may maintain the voltage of the first node Nd1 as a gate-off voltage in response to the voltage of the second node Nd2. In an embodiment, the second controller 560 may provide a voltage of the third driving voltage VSS2 (eg, a gate-off voltage) to the first node Nd1 in response to the voltage of the second node Nd2.

[0128] In an embodiment, the second controller 560 may include a ninth drive transistor (eg, a ninth-first drive transistor M9-1 and a ninth-second drive transistor M9-2) connected in series between the first node Nd1 and the second power input terminal V2. The gate electrodes of the ninth drive transistors M9-1 and M9-2 may be commonly connected to the second node Nd2.

[0129] A common node between the ninth driving transistors M9-1 and M9-2 may correspond to the third node Nd3. For example, a common node between the ninth driving transistors M9-1 and M9-2 may be electrically connected to the third node Nd3.

[0130] Despite Figure 5 , two second drive transistors M2-1 and M2-2, two third drive transistors M3-1 and M3-2, and two ninth drive transistors M9-1 and M9-2 are shown, but the number of drive transistors Tdr connected in series is not limited thereto. For example, in the case where three or more third drive transistors are connected in series, at least one common node between the third drive transistors may be electrically connected to the third node Nd3.

[0131] The third controller 570 may control the voltage of the second node Nd2 in response to the scan clock signal SCLK and the n-th carry signal CRn. In an embodiment, the third controller 570 may transmit the scan clock signal SCLK to the second node Nd2 in response to the scan clock signal SCLK, and supply the gate-off voltage to the second node Nd2 in response to the n-th carry signal CRn.

[0132] The voltage of the second node Nd2 may control the gate-off voltage (eg, logic low level) state of the nth scan signal GWn and the nth carry signal CRn. For example, the voltage of the second node Nd2 may be a voltage for controlling the pull-down of the nth carry signal CRn and the nth scan signal GWn.

[0133] The third controller 570 may include tenth to thirteenth driving transistors M10 to M13 .

[0134] The tenth driving transistor M10 may be connected between the scan clock input terminal CK and the second node Nd2. The gate electrode of the tenth driving transistor M10 may be connected to the common node of the twelfth driving transistor M12 and the thirteenth driving transistor M13. The tenth driving transistor M10 may supply the scan clock signal SCLK to the second node Nd2 in response to the scan clock signal SCLK.

[0135] The eleventh driving transistor M11 may be connected between the second node Nd2 and the second power input terminal V2.

[0136] The twelfth drive transistor M12 and the thirteenth drive transistor M13 may be connected in series between the scan clock input terminal CK and the first power input terminal V1. The gate electrode of the twelfth drive transistor M12 may be connected to the scan clock input terminal CK. The gate electrodes of the eleventh drive transistor M11 and the thirteenth drive transistor M13 may be commonly connected to the carry output terminal CR.

[0137] In the case of outputting the n-th carry signal CRn (for example, in the case of the n-th carry signal CRn having the gate-on voltage), the thirteenth driving transistor M13 may be turned on to turn off the tenth driving transistor M10, and the eleventh driving transistor M11 may be turned on to supply the voltage of the third driving voltage VSS2 to the second node Nd2. Therefore, in the case of outputting the n-th carry signal CRn, the second node Nd2 may have the gate-off voltage.

[0138] In an embodiment, the voltage level of the third driving voltage VSS2 may be lower than the voltage level of the second driving voltage VSS1. For example, the voltage of the third driving voltage VSS2 lower than the voltage of the second driving voltage VSS1 may be provided to the second node Nd2 by the operation of the eleventh driving transistor M11. This may be performed to prevent the unintended operation of the sixth driving transistor M6 and / or the eighth driving transistor M8 due to the ripple of the voltage of the second node Nd2 when the voltage of the second node Nd2 changes from the gate-on voltage to the gate-off voltage. Therefore, the electrode of the eleventh driving transistor M11 may be connected to the second power input terminal V2 having the third driving voltage VSS2 lower than the voltage of the second driving voltage VSS1.

[0139] The leakage controller 550 may supply the first driving voltage VON supplied to the third input terminal IN3 to the first input unit 510, the second input unit 520, and the second controller 560 in response to one of the nth scan signal GWn and the nth carry signal CRn. In an embodiment, the leakage controller 550 may include a first driving transistor M1 connected between the third input terminal IN3 and the third node Nd3. The first driving transistor M1 may include a gate electrode receiving the nth scan signal GWn.

[0140] The first driving transistor M1 may supply the first driving voltage VON to the common node of the driving transistors Tdr respectively connected in series with the first node Nd1 in response to the nth scanning signal GWn. Therefore, in the case where the first node Nd1 is charged (for example, in the case where the voltage of the first node Nd1 is boosted), the high potential first driving voltage VON may be applied to the electrode of the second driving transistor (for example, the second-second driving transistor M2-2), the electrode of the third driving transistor (for example, the third-first driving transistor M3-1), and the electrode of the ninth driving transistor (for example, the ninth-first driving transistor M9-1). For example, in the case where the first node Nd1 is charged, the third node Nd3 may be charged with a high potential voltage by the first driving voltage VON. Therefore, in the case where the voltage of the first node Nd1 is boosted, the gate-source voltage of each of the second-second drive transistor M2-2, the third-first drive transistor M3-1, and the ninth-first drive transistor M9-1 can have a negative value, and the gate-source voltage of each of the second-second drive transistor M2-2, the third-first drive transistor M3-1, and the ninth-first drive transistor M9-1 can be maintained at a value much lower than their threshold voltage. Therefore, leakage current occurring from the first node Nd1 through the second-second drive transistor M2-2, the third-first drive transistor M3-1, and the ninth-first drive transistor M9-1 can be prevented or minimized.

[0141] Figure 6 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 6 A portion of the display area DA and a portion of the non-display area NDA of the display panel 110 are shown.

[0142] exist Figure 6 , as examples of circuit elements that may be provided or placed in the panel circuit layer PCL of the display panel 110 , any one pixel transistor Tpx (also referred to as “first transistor TFT1 ”) and any one driving transistor Tdr (also referred to as “second transistor TFT2 ”) are shown.

[0143] In addition, despite Figure 6A light-emitting display panel including a light-emitting element ED (e.g., an organic light-emitting diode) is shown as an example of a display panel 110 to which the embodiment can be applied, but the embodiment is not limited thereto. For example, the display panel 110 may include a light-emitting element of other types and / or structures, or may be a display panel of other types and / or structures other than a light-emitting display panel.

[0144] Apart from Figures 1 to 5 In addition, refer to Figure 6 , the display panel 110 may include a substrate SUB (also referred to as a "base member" or a "base layer"), a panel circuit layer PCL, a light emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be disposed or arranged to overlap each other on the substrate SUB. For example, with respect to the display area DA, the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be sequentially disposed or formed on the substrate SUB along a third direction D3. However, the embodiment is not limited thereto, and the relative positions of the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be changed. For example, the panel circuit layer PCL and the light emitting element layer LEL may be integrated with each other, or the light emitting element layer LEL may be disposed above the panel circuit layer PCL.

[0145] In an embodiment, the display panel 110 may further include additional elements disposed above and / or below the encapsulation layer ENL. For example, the display panel 110 may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a passivation layer (e.g., a passivation film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and / or the passivation layer may be disposed above the encapsulation layer ENL, or may be disposed between the light emitting element layer LEL and the encapsulation layer ENL. In an embodiment, the sensor layer, the optical layer, and / or the passivation layer may be disposed on the display panel 110. For example, the sensor layer, the optical layer, and / or the passivation layer may be manufactured integrally with the display panel 110. In another embodiment, the sensor layer, the optical layer, and / or the passivation layer may be manufactured separately from the display panel 110 and attached to the display panel 110 via an adhesive layer or the like.

[0146] The substrate SUB as a base member for forming the display panel 110 may be a substrate (or film) having a rigid property or a flexible property. In an embodiment, the substrate SUB may be a substrate including an insulating material such as glass and having a rigid property, and may not be bent. In other embodiments, the substrate SUB may be a flexible substrate including polyimide or other insulating materials, and may be bendable, foldable, or rollable. For example, the substrate SUB may be curved or may be flat. The type and / or material of the substrate SUB may vary according to the embodiment.

[0147] The substrate SUB may include a display area DA and a non-display area NDA. In an embodiment, the display area DA may include a pixel area PXA corresponding to the pixel PX, and the non-display area NDA may include a driving circuit area DRA. For example, the pixel area PXA provided with the pixel PX may be defined in the display area DA, and the driving circuit area DRA provided with the first driver 120 may be defined in the non-display area NDA.

[0148] In an embodiment, a barrier layer BRL (or a buffer layer) may be disposed on the substrate SUB. For example, the display panel 110 may further include a barrier layer BRL disposed between the substrate SUB and the panel circuit layer PCL. In another embodiment, the display panel 110 may not include the barrier layer BRL, and, for example, the panel circuit layer PCL may be disposed on the substrate SUB (e.g., directly on the substrate SUB).

[0149] The barrier layer BRL may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). The barrier layer BRL may protect the pixel PX from moisture that penetrates through the substrate SUB susceptible to moisture penetration. The material of the barrier layer BRL may be variously changed according to the embodiment.

[0150] The panel circuit layer PCL may be disposed on one surface of the substrate SUB provided with the barrier layer BRL. The panel circuit layer PCL may include circuit elements including pixel transistors Tpx and driving transistors Tdr and wiring (e.g., signal lines and power lines). In an embodiment, the panel circuit layer PCL may further include an additional conductive pattern layer. For example, the panel circuit layer PCL may further include a connection electrode CNE or a bridge pattern layer, etc.

[0151] The panel circuit layer PCL may further include an insulating layer disposed on the substrate SUB. For example, the panel circuit layer PCL may include a first insulating layer INS1, a second insulating layer INS2, an interlayer insulating layer ILD, and a first passivation layer PSV1 sequentially disposed on the substrate SUB along a third direction D3. In an embodiment, the panel circuit layer PCL may further selectively include a connection electrode CNE and a second passivation layer PSV2 disposed on the first passivation layer PSV1. In an embodiment, at least one of the first passivation layer PSV1 and the second passivation layer PSV2 may have a multilayer structure including an inorganic layer and an organic layer. For example, the first passivation layer PSV1 may include a first inorganic layer IOL1 and a first organic layer ORL1 sequentially disposed on the interlayer insulating layer ILD, and the second passivation layer PSV2 may include a second inorganic layer IOL2 and a second organic layer ORL2 sequentially disposed on the first passivation layer PSV1.

[0152] In an embodiment, the panel circuit layer PCL may further include a gate insulating pattern layer. For example, the panel circuit layer PCL may further include a first gate insulating pattern layer GI1 disposed between the first semiconductor pattern layer ACT1 and the first gate electrode GE1 of each first transistor TFT1 and a second gate insulating pattern layer GI2 disposed between the second semiconductor pattern layer ACT2 and the second gate electrode GE2 of each second transistor TFT2.

[0153] exist Figure 6, a display panel 110 having a structure of a pattern layer in which a first gate insulating pattern layer GI1 and a second gate insulating pattern layer GI2 are etched into islands respectively positioned only partially on a portion of a first semiconductor pattern layer ACT1 and a portion of a second semiconductor pattern layer ACT2 is shown. For example, the first gate insulating pattern layer GI1 may cover only a portion of the first semiconductor pattern layer ACT1 to cover the first channel region CH1 and expose the first drain region DR1 and the first source region SR1. For example, the first gate electrode GE1 and the first gate insulating pattern layer GI1 may be etched using a mask (e.g., a single mask). Therefore, the first gate insulating pattern layer GI1 may have a shape and size corresponding to the shape and size of the first gate electrode GE1. For example, the first gate insulating pattern layer GI1 may be disposed on a portion of the first semiconductor pattern layer ACT1 (e.g., the first channel region CH1 under the first gate electrode GE1) and may expose other portions of the first semiconductor pattern layer ACT1 (e.g., the first drain region DR1 and the first source region SR1). For example, the second gate insulation pattern layer GI2 may cover only a portion of the second semiconductor pattern layer ACT2 to cover the second channel region CH2 and expose the second drain region DR2 and the second source region SR2. For example, a mask (e.g., a single mask) may be used to etch the second gate electrode GE2 and the second gate insulation pattern layer GI2. Therefore, the second gate insulation pattern layer GI2 may have a shape and size corresponding to the shape and size of the second gate electrode GE2. For example, the second gate insulation pattern layer GI2 may be disposed on a portion of the second semiconductor pattern layer ACT2 (e.g., the second channel region CH2 under the second gate electrode GE2) and may expose other portions of the second semiconductor pattern layer ACT2 (e.g., the second drain region DR2 and the second source region SR2).

[0154] However, the shapes of the first gate insulating pattern layer GI1 and the second gate insulating pattern layer GI2 are not limited to Figure 6 For example, at least one of the first gate insulation pattern layer GI1 and the second gate insulation pattern layer GI2 may be formed (eg, fully shaped) in the display area DA and / or the non-display area NDA.

[0155] In an embodiment, the first insulating layer INS1, the second insulating layer INS2, the first gate insulating pattern layer GI1, the second gate insulating pattern layer GI2, the interlayer insulating layer ILD, the first inorganic layer IOL1 and the second inorganic layer IOL2 may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide or other inorganic insulating materials). The first organic layer ORL1 and the second organic layer ORL2 may include at least one organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or other organic insulating materials). The surface (e.g., top surface) of the first organic layer ORL1 and the second organic layer ORL2 may be substantially flat. The type, material, shape and / or structure of the insulating layer and / or insulating pattern layer provided in the panel circuit layer PCL may be variously changed according to the embodiment.

[0156] The pixel transistor Tpx may be included in the pixel circuit PC of each pixel PX and may be positioned in the display area DA. For example, each pixel transistor Tpx may be disposed in a pixel area PXA in which a corresponding pixel PX is disposed or formed. Figure 6 , represents the pixel transistor Tpx, any one of the pixel transistors Tpx (e.g., the first pixel transistor T1 connected to the light emitting element ED of the corresponding pixel PX) is shown, and this will be referred to as "first transistor TFT1". In an embodiment, the first transistor TFT1 may refer to at least one pixel transistor Tpx including the first lower electrode BG1 formed as (e.g., provided as) the first conductive layer CDL1 among the pixel transistors Tpx.

[0157] The driving transistor Tdr may be included in the driving circuit 121 of the first driver 120. Each driving transistor Tdr may be disposed in a driving circuit region DRA in which a corresponding stage ST is disposed or formed. In an embodiment, the driving circuit region DRA may be located in the non-display area NDA. Figure 6 , represents the driving transistor Tdr, any one of the driving transistors Tdr (for example, any one of the fifth to eighth driving transistors M5 to M8 included in the output unit 540 of the nth stage STn) is shown, and this will be referred to as "second transistor TFT2". In an embodiment, the second transistor TFT2 may refer to at least one driving transistor Tdr including the second lower electrode BG2 formed as (for example, provided as) the second conductive layer CDL2 among the driving transistors Tdr.

[0158] In an embodiment, the display panel 110 may include transistors TFT having different structures with respect to the lower electrode. For example, the first transistor TFT1 and the second transistor TFT2 may have different structures with respect to the lower electrode.

[0159] In an embodiment, similar to Figure 6 The first transistor TFT1 comprises Figure 3 Some pixel transistors Tpx of the first pixel transistor T1 or all pixel transistors Tpx provided in the display area DA may include a first lower electrode BG1 formed as (eg, provided as) the first conductive layer CDL1. Figure 6 The second transistor TFT2 comprises Figure 5 Some of at least one of the fifth to eighth driving transistors M5 to M8 or all of the driving transistors Tdr disposed in the driving circuit area DRA may include a second lower electrode BG2 formed as (e.g., disposed as) a second conductive layer CDL2. The second conductive layer CDL2, which is a conductive layer disposed at a different layer from the first conductive layer CDL1 on the substrate SUB, may be disposed closer to the semiconductor layer SCL of the semiconductor pattern layer including the transistor TFT than the first conductive layer CDL1.

[0160] The first transistor TFT1 may include a first lower electrode BG1, a first semiconductor pattern layer ACT1 (also referred to as a "first active pattern layer"), and a first gate electrode GE1. In an embodiment, the first transistor TFT1 may further include a first drain electrode DE1 and a first source electrode SE1 connected to different portions of the first semiconductor pattern layer ACT1. In another embodiment, the first transistor TFT1 may not include a separate drain electrode and / or a separate source electrode, and the first drain region DR1 and / or the first source region SR1 of the first semiconductor pattern layer ACT1 may be connected to another circuit element, wiring, and / or conductive pattern layer to serve as a drain electrode and / or source electrode of the first transistor TFT1.

[0161] The first lower electrode BG1 may be formed as (eg, disposed as) a first conductive layer CDL1 on the substrate SUB. In an embodiment, the first conductive layer CDL1 may be disposed between the substrate SUB and the first insulating layer INS1. For example, the first conductive layer CDL1 may be disposed on the barrier layer BRL and may be covered by the first insulating layer INS1.

[0162] The first lower electrode BG1 may overlap the first semiconductor pattern layer ACT1. For example, the first lower electrode BG1 may be disposed under the first semiconductor pattern layer ACT1 to overlap at least the first channel region CH1. The first insulating layer INS1 and the second insulating layer INS2 may be disposed between the first lower electrode BG1 and the first semiconductor pattern layer ACT1. For example, the first lower electrode BG1 and the first semiconductor pattern layer ACT1 may be spaced apart from each other by a first distance d1, and the first insulating layer INS1 and the second insulating layer INS2 are disposed between the first lower electrode BG1 and the first semiconductor pattern layer ACT1. In an embodiment, the first distance d1 may correspond to the sum (e.g., about 3000Å) of the thickness of the first insulating layer INS1 (e.g., about 2000Å) and the thickness of the second insulating layer INS2 (e.g., about 1000Å). The first lower electrode BG1 may face the first gate electrode GE1. The first semiconductor pattern layer ACT1 may be disposed between the first lower electrode BG1 and the first gate electrode GE1.

[0163] The first lower electrode BG1 may or may not be connected to the electrode of the first transistor TFT1. For example, the first lower electrode BG1 may be connected to the electrode of the first transistor TFT1 and may be used as a first back gate electrode (or a first bottom gate electrode) for adjusting the characteristics of the first transistor TFT1. In an embodiment, the first lower electrode BG1 may be connected to the first source electrode SE1 (or the first source region SR1).

[0164] The first semiconductor pattern layer ACT1 may be formed as (eg, disposed as) a semiconductor layer SCL on the substrate SUB. In an embodiment, the semiconductor layer SCL may be disposed on the second insulating layer INS2. For example, the semiconductor layer SCL may be disposed between the second insulating layer INS2 and the interlayer insulating layer ILD.

[0165] The first semiconductor pattern layer ACT1 may include a first channel region CH1 and a first source region SR1 and a first drain region DR1, the first source region SR1 and the first drain region DR1 being spaced apart from each other and the first channel region CH1 being disposed between the first source region SR1 and the first drain region DR1. For example, the first source region SR1 and the first drain region DR1 may be positioned at multiple sides (e.g., opposite sides) of the first channel region CH1. The first channel region CH1 may be a region that maintains semiconductor characteristics without becoming conductive, and the first source region SR1 and the first drain region DR1 may be regions having conductivity.

[0166] The first semiconductor pattern layer ACT1 may overlap the first lower electrode BG1 and the first gate electrode GE1. For example, a portion of the first semiconductor pattern layer ACT1 including the first channel region CH1 may overlap the first lower electrode BG1 and the first gate electrode GE1.

[0167] The first gate electrode GE1 (or the top gate electrode) may be formed as (eg, disposed as) a third conductive layer CDL3 on the substrate SUB. In an embodiment, the third conductive layer CDL3 may be disposed between the semiconductor layer SCL including the first semiconductor pattern layer ACT1 and the insulating layer (or the third insulating layer INS3 (see FIG. 1 ) including the first gate insulating pattern layer GI1. Fig.14 and Fig.15 The third conductive layer CDL3 may be covered by the interlayer insulating layer ILD.

[0168] The first gate electrode GE1 may be disposed on the first semiconductor pattern layer ACT1 to overlap the first channel region CH1. The first gate electrode GE1 and the first semiconductor pattern layer ACT1 may be separated and / or spaced apart from each other with a first gate insulating pattern layer GI1 disposed therebetween.

[0169] The first gate insulating pattern layer GI1 may be disposed between the first gate electrode GE1 and the first semiconductor pattern layer ACT1. The first gate insulating pattern layer GI1 may cover a portion of the first semiconductor pattern layer ACT1 overlapping the first gate electrode GE1 (eg, the first channel region CH1).

[0170] The first drain electrode DE1 and the first source electrode SE1 may be formed as (eg, disposed as) a fourth conductive layer CDL4 on the substrate SUB. In an embodiment, the fourth conductive layer CDL4 may be disposed on the interlayer insulating layer ILD covering the third conductive layer CDL3 including the first gate electrode GE1. For example, the fourth conductive layer CDL4 may be disposed between the interlayer insulating layer ILD and the first passivation layer PSV1.

[0171] The first drain electrode DE1 may be connected to a portion of the first semiconductor pattern layer ACT1. For example, the first drain electrode DE1 may be connected to the first drain region DR1 through at least one contact hole passing through the interlayer insulating layer ILD.

[0172] The first source electrode SE1 may be connected to another portion of the first semiconductor pattern layer ACT1. For example, the first source electrode SE1 may be connected to the first source region SR1 through at least one contact hole passing through the interlayer insulating layer ILD. In an embodiment, the first source electrode SE1 may also be connected to the first lower electrode BG1. For example, the first source electrode SE1 may be connected to the first lower electrode BG1 through at least one contact hole passing through the first insulating layer INS1, the second insulating layer INS2, and the interlayer insulating layer ILD.

[0173] The second transistor TFT2 may include a second lower electrode BG2, a second semiconductor pattern layer ACT2 (also referred to as a "second active pattern layer"), and a second gate electrode GE2. In an embodiment, the second transistor TFT2 may also include a second drain electrode DE2 and a second source electrode SE2 connected to different portions of the second semiconductor pattern layer ACT2. In another embodiment, the second transistor TFT2 may not include a separate drain electrode and / or a separate source electrode, and the second drain region DR2 and / or the second source region SR2 of the second semiconductor pattern layer ACT2 may be connected to another circuit element, wiring, and / or conductive pattern layer to serve as a drain electrode and / or source electrode of the second transistor TFT2.

[0174] The second lower electrode BG2 may be formed as (eg, disposed as) a second conductive layer CDL2 on the substrate SUB. In an embodiment, the second conductive layer CDL2 may be disposed on the first insulating layer INS1 covering the first lower electrode BG1. For example, the second conductive layer CDL2 may be disposed between the first insulating layer INS1 and the second insulating layer INS2.

[0175] The second lower electrode BG2 may overlap with the second semiconductor pattern layer ACT2. For example, the second lower electrode BG2 may be disposed under the second semiconductor pattern layer ACT2 to overlap with at least the second channel region CH2. The second insulating layer INS2 may be disposed between the second lower electrode BG2 and the second semiconductor pattern layer ACT2. For example, the second lower electrode BG2 and the second semiconductor pattern layer ACT2 may be spaced apart from each other by a second distance d2, and the second insulating layer INS2 is disposed between the second lower electrode BG2 and the second semiconductor pattern layer ACT2. In an embodiment, the second distance d2 may correspond to the thickness of the second insulating layer INS2 (e.g., about 1000Å), and may be less than the first distance d1. The second lower electrode BG2 may face the second gate electrode GE2, and the second semiconductor pattern layer ACT2 is disposed between the second lower electrode BG2 and the second gate electrode GE2.

[0176] The second lower electrode BG2 may or may not be connected to the electrode of the second transistor TFT2. For example, the second lower electrode BG2 may be connected to the electrode of the second transistor TFT2 (eg, the second gate electrode GE2) and may be used as a back gate electrode (eg, the second back gate electrode) for adjusting the characteristics of the second transistor TFT2.

[0177] The second semiconductor pattern layer ACT2 may be formed as (eg, disposed as) a semiconductor layer SCL on a substrate SUB. In an embodiment, the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 may be disposed and / or arranged on the same layer (eg, the same semiconductor layer SCL) on the substrate SUB. For example, the second semiconductor pattern layer ACT2 may be disposed between the second insulating layer INS2 and the interlayer insulating layer ILD.

[0178] The second semiconductor pattern layer ACT2 may include a second channel region CH2 and a second source region SR2 and a second drain region DR2, the second source region SR2 and the second drain region DR2 being spaced apart from each other and the second channel region CH2 being disposed between the second source region SR2 and the second drain region DR2. For example, the second source region SR2 and the second drain region DR2 may be positioned at multiple sides (e.g., opposite sides) of the second channel region CH2. The second channel region CH2 may be a region that maintains semiconductor characteristics without becoming conductive, and the second source region SR2 and the second drain region DR2 may be a region having conductivity.

[0179] The second semiconductor pattern layer ACT2 may overlap the second lower electrode BG2 and the second gate electrode GE2. For example, a portion of the second semiconductor pattern layer ACT2 including the second channel region CH2 may overlap the second lower electrode BG2 and the second gate electrode GE2.

[0180] The second gate electrode GE2 may be formed as (e.g., disposed as) a third conductive layer CDL3 on the substrate SUB. In an embodiment, the first gate electrode GE1 and the second gate electrode GE2 may be disposed and / or arranged on the same layer (e.g., the same third conductive layer CDL3) on the substrate SUB. For example, the second gate electrode GE2 may be disposed on an insulating layer (or a third insulating layer INS3 (see Fig.14 and Fig.15 )) and the interlayer insulating layer ILD.

[0181] The second gate electrode GE2 may be disposed on the second semiconductor pattern layer ACT2 to overlap the second channel region CH2. The second gate electrode GE2 and the second semiconductor pattern layer ACT2 may be separated and / or spaced apart from each other with a second gate insulating pattern layer GI2 disposed therebetween.

[0182] The second gate insulating pattern layer GI2 may be disposed between the second gate electrode GE2 and the second semiconductor pattern layer ACT2. The second gate insulating pattern layer GI2 may cover a portion of the second semiconductor pattern layer ACT2 overlapping the second gate electrode GE2 (eg, the second channel region CH2).

[0183] The second drain electrode DE2 and the second source electrode SE2 may be formed as (e.g., disposed as) a fourth conductive layer CDL4 on the substrate SUB. In an embodiment, the second drain electrode DE2, the second source electrode SE2, the first drain electrode DE1, and the first source electrode SE1 may be disposed on the same layer on the substrate SUB. For example, the second drain electrode DE2 and the second source electrode SE2 may be disposed between the interlayer insulating layer ILD and the first passivation layer PSV1. For example, the second drain electrode DE2 and the second source electrode SE2 may be disposed on the interlayer insulating layer ILD covering the third conductive layer CDL3 including the first gate electrode GE1 and the second gate electrode GE2, and may be covered by the first passivation layer PSV1.

[0184] The second drain electrode DE2 may be connected to a portion of the second semiconductor pattern layer ACT2. For example, the second drain electrode DE2 may be connected to the second drain region DR2 through at least one contact hole passing through the interlayer insulating layer ILD.

[0185] The second source electrode SE2 may be connected to another portion of the second semiconductor pattern layer ACT2. For example, the second source electrode SE2 may be connected to the second source region SR2 through at least one contact hole passing through the interlayer insulating layer ILD.

[0186] The transistor TFT including the first transistor TFT1 of the pixel PX and the second transistor TFT2 of the driving circuit 121 may be covered by at least one passivation layer. For example, the transistor TFT may be covered by the first passivation layer PSV1 and the second passivation layer PSV2.

[0187] In an embodiment, at least one first transistor TFT1 provided in each pixel PX may be connected to the light emitting element ED of the corresponding pixel PX through a connection electrode CNE. The connection electrode CNE may be formed as (e.g., provided as) a fifth conductive layer CDL5 on the substrate SUB. In an embodiment, the fifth conductive layer CDL5 may be provided on the first passivation layer PSV1. For example, the fifth conductive layer CDL5 may be provided between the first passivation layer PSV1 and the second passivation layer PSV2.

[0188] The connection electrode CNE may be connected to an electrode of the first transistor TFT1. For example, the connection electrode CNE may be disposed on the first source electrode SE1 and may be connected to the first source electrode SE1 through at least one contact hole or via hole passing through the first passivation layer PSV1.

[0189] The corresponding electrodes, conductive pattern layers and / or wirings formed as (e.g., set as) the conductive layers of the panel circuit layer PCL may include at least one conductive material, and may all have a single-layer structure or a multi-layer structure. For example, the electrodes, conductive pattern layers and / or wirings formed as (e.g., set as) each of the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include molybdenum (Mo), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), copper (Cu), magnesium (Mg) and other metals, alloys thereof and other conductive materials, and may all have a single-layer structure or a multi-layer structure. In an embodiment, the electrodes, conductive pattern layers and / or wirings set in the same conductive layer may be formed of the same conductive material at the same time.

[0190] In an embodiment, the semiconductor pattern layer formed as (e.g., arranged as) the semiconductor layer SCL may include an oxide semiconductor. For example, each of the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), indium tin gallium zinc oxide (ITGZO) and other oxide semiconductors. The oxide semiconductor used to form the oxide transistor including the first transistor TFT1 and the second transistor TFT2 is not limited to the above materials and may be changed differently according to the embodiment. In addition, at least one of the first transistor TFT1 and the second transistor TFT2 may be formed of a semiconductor material other than an oxide semiconductor.

[0191] The light emitting element layer LEL may be disposed on the panel circuit layer PCL and may be positioned in the display area DA. For example, the light emitting element layer LEL may be disposed on the panel circuit layer PCL in the display area DA.

[0192] The light emitting element layer LEL may include a light emitting element ED of the pixel PX. For example, the light emitting element layer LEL may include a pixel defining layer PDL (also referred to as a "bank") that separates emission regions of the pixel PX and a light emitting element ED positioned in each emission region. In an embodiment, the light emitting element layer LEL may further include a spacer SPC disposed on a portion of the pixel defining layer PDL.

[0193] Each light emitting element ED may include at least one pixel transistor Tpx (eg, Figure 6 The first transistor TFT1 of the embodiment of the present invention comprises a first electrode ET1 (e.g., an anode electrode) and a light emitting layer EML and a second electrode ET2 (e.g., a cathode electrode) sequentially disposed on the first electrode ET1. In an embodiment, the light emitting element ED may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) disposed between the first electrode ET1 and the light emitting layer EML and a second intermediate layer (e.g., an electron layer including an electron transport layer) disposed between the light emitting layer EML and the second electrode ET2.

[0194] The first electrode ET1 of the light emitting element ED may be disposed on the panel circuit layer PCL. For example, the first electrode ET1 may be disposed on the second passivation layer PSV2 to correspond to (or overlap) each emission region. In an embodiment, the first electrode ET1 may be connected to the connection electrode CNE through at least one contact hole or via hole passing through the second passivation layer PSV2. In another example, the first electrode ET1 may be directly connected to at least one pixel transistor Tpx without the connection electrode CNE.

[0195] The first electrode ET1 may include a conductive material. In an embodiment, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and multilayer structures of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni) (e.g., ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO).

[0196] The light-emitting layer EML of the light-emitting element ED may include a polymer material or a low-molecular material. The light emitted from the light-emitting layer EML may be used to display an image. In an embodiment, a light-emitting layer EML may be provided for each pixel PX, and the light-emitting layer EML of each pixel PX may emit visible light having a color corresponding to the corresponding pixel PX. In another embodiment, the light-emitting layer EML may be a common layer shared by pixels PX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light desired to be emitted from each pixel PX may be arranged in the emission region of at least some of the pixels PX.

[0197] The second electrode ET2 of the light emitting element ED may include a conductive material. In an embodiment, the second electrode ET2 may be a common layer formed throughout the entire display area DA to cover the light emitting layer EML and the pixel defining layer PDL. In an embodiment, the second electrode ET2 may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO, IZO, ZnO, or ITZO) or may be formed of a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0198] The pixel defining layer PDL may have an opening corresponding to each emission region and may surround the emission region. For example, the pixel defining layer PDL may be formed to cover an edge portion of the first electrode ET1 of the light emitting element ED and may include an opening that exposes the remaining portion of the first electrode ET1. A region where the exposed first electrode ET1 and the light emitting layer EML overlap (or a region including the exposed first electrode ET1 and the light emitting layer EML) may be defined as an emission region of each pixel PX.

[0199] In an embodiment, the pixel defining layer PDL may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer PDL may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) resin or other organic insulating materials.

[0200] The spacer SPC may be disposed on a portion of the pixel defining layer PDL. The spacer SPC may include at least one organic insulating layer including an organic insulating material. The spacer SPC and the pixel defining layer PDL may include the same material, or may include different materials. In an embodiment, the pixel defining layer PDL and the spacer SPC may be sequentially formed by separate mask processes. In another embodiment, the pixel defining layer PDL and the spacer SPC may be formed simultaneously using a halftone mask. For example, the pixel defining layer PDL and the spacer SPC may be formed as a single insulating layer that is integral with each other.

[0201] The encapsulation layer ENL may be disposed on the light emitting element layer LEL. The encapsulation layer ENL may cover the light emitting element layer LEL in the display area DA, and may extend to the non-display area NDA to contact the panel circuit layer PCL. For example, the encapsulation layer ENL may be disposed in the display area DA to cover the light emitting element layer LEL, and an end of the encapsulation layer ENL may be positioned in a portion of the non-display area NDA adjacent to the display area DA. The encapsulation layer ENL may block oxygen or moisture from penetrating into the light emitting element layer LEL, and may reduce electrical and / or physical impacts on the panel circuit layer PCL and the light emitting element layer LEL.

[0202] In an embodiment, the encapsulation layer ENL may have a multilayer structure including a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially disposed on the light emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer ENL2 may be an organic encapsulation layer including an organic material. The structure and / or material of the encapsulation layer ENL may vary according to the embodiment.

[0203] As described above, the display panel 110 may include a first conductive layer CDL1 and a second conductive layer CDL2 disposed under the semiconductor layer SCL. For example, the first conductive layer CDL1 and the second conductive layer CDL2 disposed on the substrate SUB and / or formed in different layers may be positioned between the substrate SUB and the semiconductor layer SCL. The first insulating layer INS1 and the second insulating layer INS2 may be disposed between the first conductive layer CDL1 and the semiconductor layer SCL. The second conductive layer CDL2 disposed on the first insulating layer INS1 covering the first conductive layer CDL1 may be disposed closer to the semiconductor layer SCL than the first conductive layer CDL1. The second insulating layer INS2 may be disposed between the second conductive layer CDL2 and the semiconductor layer SCL.

[0204] According to an embodiment, the size (or amount) of the capacitance formed between the lower electrode of each transistor TFT and the semiconductor pattern layer may be differentiated and / or optimized according to the characteristics required by each transistor TFT. For example, by selectively disposing the lower electrode of each transistor TFT on the first conductive layer CDL1 or the second conductive layer CDL2 according to the characteristics required by each transistor TFT, the characteristics of each transistor TFT may be appropriately adjusted and / or optimized.

[0205] In an embodiment, at least one pixel transistor Tpx requiring more uniform characteristics may be formed by a first transistor TFT1 including a first lower electrode BG1 formed as (e.g., arranged as) a first conductive layer CDL1. In the first transistor TFT1, a distance (e.g., a first distance d1) between the first semiconductor pattern layer ACT1 and the first lower electrode BG1 and a thickness of an insulating layer (e.g., an insulating layer including at least a double layer of a first insulating layer INS1 and a second insulating layer INS2) between the first semiconductor pattern layer ACT1 and the first lower electrode BG1 may be relatively large. In an embodiment, the thickness of the first insulating layer INS1 and the second insulating layer INS2 may be appropriately adjusted or set in consideration of the characteristics required by the first transistor TFT1. Therefore, a capacitance (e.g., a parasitic capacitance) formed in the first transistor TFT1 may be reduced or minimized, thereby preventing, reducing, or minimizing a change in the characteristics of the first transistor TFT1. Therefore, image blurring due to brightness changes of the pixel PX can be prevented, reduced, or minimized, and the image quality of the display device 100 can be improved.

[0206] In an embodiment, at least one driving transistor Tdr that requires a higher on-current (e.g., drain-source current in an on-state) to stably drive the pixel PX may be formed by a second transistor TFT2 including a second lower electrode BG2 formed as (e.g., arranged as) a second conductive layer CDL2. In the second transistor TFT2, the distance (e.g., second distance d2) between the second semiconductor pattern layer ACT2 and the second lower electrode BG2 and the thickness of the insulating layer (e.g., second insulating layer INS2) between the second semiconductor pattern layer ACT2 and the second lower electrode BG2 may be relatively small. In an embodiment, the thickness of the second insulating layer INS2 may be appropriately adjusted or set in consideration of the characteristics required by the second transistor TFT2. Therefore, the capacitance (e.g., parasitic capacitance) formed in the second transistor TFT2 increases, which enables the on-current of the second transistor TFT2 to be appropriately and / or easily increased without changing the length or width of the second semiconductor pattern layer ACT2. Therefore, the output characteristics (e.g., switching characteristics and / or response speed) of the second transistor TFT2 may be improved while preventing or minimizing the change in the threshold voltage of the second transistor TFT2. In addition, since the output characteristics of the second transistor TFT2 are improved, the output characteristics of the driving circuit 121 may be improved, thereby stably driving the pixel PX.

[0207] For example, the display panel 110 according to the embodiment may include a relatively large number of conductive layers (including the first conductive layer CDL1 and the second conductive layer CDL2). Therefore, even in a high-resolution panel, sufficient design space for forming the pixel circuit PC and / or wiring can be ensured. For example, even in a high-resolution panel with a small area of ​​the pixel region PXA and the wiring region, the electrostatic capacitance of the pixel capacitor Cpx can be sufficiently ensured, and the wiring can be stably designed by appropriately arranging the corresponding electrodes and / or the corresponding wiring on a plurality of conductive layers.

[0208] Figure 7 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 7 A portion of the display area DA of the display panel 110 is shown.

[0209] exist Figure 7 , a first transistor TFT1 and a third transistor TFT3 disposed in each pixel area PXA and having different structures with respect to the lower electrode are shown as examples of circuit elements disposed or arranged on the panel circuit layer PCL of the display panel 110. For example, the pixel transistor Tpx of each pixel PX may include a first transistor TFT1 including a first lower electrode BG1 and a third transistor TFT3 including a third lower electrode BG3. Figure 7 The same reference numerals will be given to the embodiments of Figure 6 The components of the embodiments are similar or identical, and for the convenience of description, redundant description will be omitted.

[0210] Apart from Figures 1 to 6 In addition, refer to Figure 7 , the pixel PX may include a first transistor TFT1 and a third transistor TFT3 having different structures. For example, similar to the first transistor TFT1, some of the pixel transistors Tpx provided in each pixel PX may include a first lower electrode BG1 formed as (e.g., provided as) a first conductive layer CDL1, and similar to the third transistor TFT3, other some of the pixel transistors Tpx may include a third lower electrode BG3 formed as (e.g., provided as) a second conductive layer CDL2.

[0211] In an embodiment, each pixel transistor Tpx may be formed in the same structure as the first transistor TFT1 or in the same structure as the third transistor TFT3, taking into account the required operating characteristics or reliability of each pixel transistor Tpx. For example, similar to the first transistor TFT1, the pixel transistor Tpx (e.g., Figure 3The first pixel transistor T1) may be formed in a structure in which the capacitance may be reduced or minimized, and similarly to the third transistor TFT3, the pixel transistor Tpx (eg, Figure 3 At least one of the second to fifth pixel transistors T2 to T5 may be formed in a structure in which switching characteristics may be improved by increasing capacitance.

[0212] The third transistor TFT3 may include a third lower electrode BG3, a third semiconductor pattern layer ACT3 (also referred to as a "third active pattern layer"), and a third gate electrode GE3. In an embodiment, the third transistor TFT3 may also include a third drain electrode DE3 and a third source electrode SE3 connected to different portions of the third semiconductor pattern layer ACT3. In another embodiment, the third transistor TFT3 may not include a separate drain electrode and / or a separate source electrode, and the third drain region DR3 and / or the third source region SR3 of the third semiconductor pattern layer ACT3 may be connected to another circuit element, wiring, and / or conductive pattern layer to serve as a drain electrode and / or source electrode of the third transistor TFT3.

[0213] The third lower electrode BG3 may be formed as (e.g., disposed as) a second conductive layer CDL2 on the substrate SUB. The third lower electrode BG3 may overlap with the third semiconductor pattern layer ACT3. For example, the third lower electrode BG3 may be disposed under the third semiconductor pattern layer ACT3 to overlap with at least the third channel region CH3. The second insulating layer INS2 may be disposed between the third lower electrode BG3 and the third semiconductor pattern layer ACT3. For example, the third lower electrode BG3 and the third semiconductor pattern layer ACT3 may be spaced apart from each other by a distance corresponding to the thickness of the second insulating layer INS2 (e.g., about 1000Å), and the second insulating layer INS2 is disposed between the third lower electrode BG3 and the third semiconductor pattern layer ACT3. The third lower electrode BG3 may face the third gate electrode GE3, and the third semiconductor pattern layer ACT3 is disposed between the third lower electrode BG3 and the third gate electrode GE3.

[0214] The third lower electrode BG3 may or may not be connected to the electrode of the third transistor TFT3. For example, the third lower electrode BG3 may be connected to the electrode of the third transistor TFT3 (for example, the third gate electrode GE3) and may be used as a back gate electrode (for example, the third back gate electrode) for adjusting the characteristics of the third transistor TFT3.

[0215] The third semiconductor pattern layer ACT3 may be formed as (eg, disposed as) a semiconductor layer SCL on the substrate SUB. In embodiments, the first semiconductor pattern layer ACT1 and the third semiconductor pattern layer ACT3 may be disposed and / or arranged on the same semiconductor layer SCL on the substrate SUB.

[0216] The third semiconductor pattern layer ACT3 may include a third channel region CH3 and a third source region SR3 and a third drain region DR3, the third source region SR3 and the third drain region DR3 being spaced apart from each other and the third channel region CH3 being disposed between the third source region SR3 and the third drain region DR3. For example, the third source region SR3 and the third drain region DR3 may be positioned at multiple sides (e.g., opposite sides) of the third channel region CH3. The third channel region CH3 may be a region that maintains semiconductor characteristics without becoming conductive, and the third source region SR3 and the third drain region DR3 may be regions having conductivity.

[0217] The third semiconductor pattern layer ACT3 may overlap the third lower electrode BG3 and the third gate electrode GE3. For example, a portion of the third semiconductor pattern layer ACT3 including the third channel region CH3 may overlap the third lower electrode BG3 and the third gate electrode GE3.

[0218] The third gate electrode GE3 may be formed as (eg, disposed as) a third conductive layer CDL3 on the substrate SUB. For example, the third gate electrode GE3 and the first gate electrode GE1 may be disposed and / or arranged at the same layer on the substrate SUB.

[0219] The third gate electrode GE3 may be disposed on the third semiconductor pattern layer ACT3 to overlap the third channel region CH3. The third gate electrode GE3 and the third semiconductor pattern layer ACT3 may be separated / spaced apart from each other with a third gate insulating pattern layer GI3 disposed therebetween.

[0220] The third gate insulating pattern layer GI3 may be disposed between the third gate electrode GE3 and the third semiconductor pattern layer ACT3. The third gate insulating pattern layer GI3 may cover a portion of the third semiconductor pattern layer ACT3 overlapping the third gate electrode GE3 (eg, the third channel region CH3).

[0221] The third drain electrode DE3 and the third source electrode SE3 may be formed as (eg, disposed as) a fourth conductive layer CDL4 on the substrate SUB. In an embodiment, the third drain electrode DE3, the third source electrode SE3, the first drain electrode DE1, and the first source electrode SE1 may be disposed on the same layer on the substrate SUB.

[0222] The third drain electrode DE3 may be connected to a portion of the third semiconductor pattern layer ACT3. For example, the third drain electrode DE3 may be connected to the third drain region DR3 through at least one contact hole passing through the interlayer insulating layer ILD.

[0223] The third source electrode SE3 may be connected to another portion of the third semiconductor pattern layer ACT3. For example, the third source electrode SE3 may be connected to the third source region SR3 through at least one contact hole passing through the interlayer insulating layer ILD.

[0224] According to the above-described embodiments, the size (or amount) of the capacitance (e.g., parasitic capacitance) formed in the pixel transistor Tpx can be differentiated and / or optimized according to the required operating characteristics or reliability of each pixel transistor Tpx. For example, by selectively arranging the lower electrode of each pixel transistor Tpx on the first conductive layer CDL1 or the second conductive layer CDL2 according to the required characteristics of each pixel transistor Tpx, the characteristics of the pixel transistor Tpx can be appropriately adjusted and / or optimized.

[0225] In an embodiment, it is possible to Figure 7 The size (or amount) of the capacitance (e.g., parasitic capacitance) formed in the driving transistor Tdr can be distinguished and / or optimized in the same manner as in the embodiments of the present invention. For example, in the case where it is desired to reduce the size (or amount) of the capacitance (e.g., parasitic capacitance) formed in at least one driving transistor Tdr, the lower electrode provided in at least one driving transistor Tdr can be provided on the first conductive layer CDL1, and the lower electrodes provided in other driving transistors Tdr can be provided on the second conductive layer CDL2.

[0226] Figures 8 to 18 is a schematic cross-sectional view showing a method of manufacturing the display device 100 according to an embodiment. For example, Figures 8 to 18 According to the embodiment, the manufacturing Figure 6 The step of forming the panel circuit layer PCL is included in the step of manufacturing the display panel 110.

[0227] Apart from Figures 1 to 7 In addition, refer to Figure 8 , a substrate SUB including a display area DA and a non-display area NDA may be provided. In an embodiment, the display area DA defined on the substrate SUB may include a pixel area PXA, and the non-display area NDA may include a driving circuit area DRA.

[0228] In an embodiment, a barrier layer BRL may be formed on a substrate SUB. The barrier layer BRL may be formed in the display area DA and the non-display area NDA. The barrier layer BRL may be formed by an insulating film forming process (e.g., a deposition process) using at least one insulating material (e.g., an inorganic insulating material) above. The material and / or method for forming the barrier layer BRL may be variously changed according to the embodiment.

[0229] Apart from Figures 1 to 8 In addition, refer to Fig. 9, a first lower electrode BG1 may be formed on the substrate SUB (e.g., on the barrier layer BRL) in the display area DA. For example, at least one first lower electrode BG1 may be formed in each pixel area PXA. The first lower electrode BG1 may be formed by a conductive film forming process (e.g., a deposition process) and a conductive film patterning process (e.g., an etching process) using at least one conductive material above. The material and / or method for forming the first lower electrode BG1 may be variously changed according to the embodiment.

[0230] Apart from Figures 1 to 9 In addition, refer to Fig.10 , a first insulating layer INS1 covering the first lower electrode BG1 may be formed on the substrate SUB. The first insulating layer INS1 may be formed in the display area DA and the non-display area NDA (e.g., the driving circuit area DRA). The first insulating layer INS1 may be formed by an insulating film forming process using at least one insulating material (e.g., an inorganic insulating material) above. The material and / or method for forming the first insulating layer INS1 may be variously changed according to the embodiment.

[0231] Apart from Figures 1 to 10 In addition, refer to Fig.11 , a second lower electrode BG2 may be formed on the first insulating layer INS1 in the driving circuit region DRA. For example, at least one second lower electrode BG2 may be formed in each stage region of each stage ST where the driving circuit 121 is provided. The second lower electrode BG2 may be formed by a conductive film forming process and a conductive film patterning process using at least one conductive material above. The material and / or method for forming the second lower electrode BG2 may be variously changed according to the embodiment.

[0232] In an embodiment, the pixel PX includes Figure 7 In the case of the third transistor TFT3 shown in FIG. 1 , the second lower electrode BG2 may be formed in the driving circuit area DRA, and at the same time, the third lower electrode BG3 may be formed in each pixel area PXA.

[0233] Apart from Figures 1 to 11 In addition, refer to Fig.12 , a second insulating layer INS2 covering the second lower electrode BG2 may be formed on the first insulating layer INS1. The second insulating layer INS2 may be formed in the display area DA and the non-display area NDA (e.g., the driving circuit area DRA). The second insulating layer INS2 may be formed by an insulating film forming process using at least one insulating material (e.g., an inorganic insulating material) above. The material and / or method for forming the second insulating layer INS2 may be variously changed according to the embodiment.

[0234] Apart from Figures 1 to 12In addition, refer to Fig.13 , a first semiconductor pattern layer ACT1 and a second semiconductor pattern layer ACT2 may be formed on the second insulating layer INS2. For example, at least one first semiconductor pattern layer ACT1 may be formed in each pixel region PXA, and at least one second semiconductor pattern layer ACT2 may be formed in each stage region of the driving circuit region DRA. Each first semiconductor pattern layer ACT1 may be formed to overlap each first lower electrode BG1, and each second semiconductor pattern layer ACT2 may be formed to overlap each second lower electrode BG2.

[0235] In an embodiment, the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 may be formed simultaneously from the same oxide semiconductor. For example, the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 may be formed in the pixel region PXA and the driving circuit region DRA, respectively, by a semiconductor film formation process and a patterning process using at least one oxide semiconductor above.

[0236] Apart from Figures 1 to 13 In addition, refer to Fig.14 , a third insulating layer INS3 covering the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 may be formed on the second insulating layer INS2. The third insulating layer INS3 may be formed in the display area DA and the non-display area NDA (e.g., the driving circuit area DRA). The third insulating layer INS3 may be formed by an insulating film forming process using at least one insulating material (e.g., an inorganic insulating material) above. The material and / or method for forming the third insulating layer INS3 may be variously changed according to the embodiment.

[0237] Apart from Figures 1 to 14 In addition, refer to Fig.15 , a first gate electrode GE1 and a second gate electrode GE2 may be formed on the third insulating layer INS3. For example, the first gate electrode GE1 may be formed on the first semiconductor pattern layer ACT1 to overlap with a portion of each first semiconductor pattern layer ACT1 in each pixel region PXA. In addition, the second gate electrode GE2 may be formed on the second semiconductor pattern layer ACT2 to overlap with a portion of each second semiconductor pattern layer ACT2 in each stage region of the drive circuit region DRA.

[0238] In an embodiment, the first gate electrode GE1 and the second gate electrode GE2 may be formed by a conductive film forming process and a conductive film patterning process using at least one conductive material above. Materials and / or methods for forming the first gate electrode GE1 and the second gate electrode GE2 may be variously changed according to embodiments.

[0239] Apart from Figures 1 to 15In addition, refer to Fig.16 , the first gate insulation pattern layer GI1 and the second gate insulation pattern layer GI2 may be formed by etching the third insulation layer INS3. For example, the third insulation layer INS3 may be etched by using a mask for patterning the first gate electrode GE1 and the second gate electrode GE2 or by using the first gate electrode GE1 and the second gate electrode GE2 as a mask. Therefore, the first gate insulation pattern layer GI1 and the second gate insulation pattern layer GI2 may be formed under the first gate electrode GE1 and the second gate electrode GE2, respectively. For example, the first gate insulation pattern layer GI1 may be formed on a portion of the first semiconductor pattern layer ACT1 overlapping the first gate electrode GE1, and the second gate insulation pattern layer GI2 may be formed on a portion of the second semiconductor pattern layer ACT2 overlapping the second gate electrode GE2.

[0240] In the process of forming the first gate insulation pattern layer GI1 and the second gate insulation pattern layer GI2 by etching the third insulation layer INS3, the characteristics of the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 may be changed so that the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 partially have different characteristics. Therefore, each of the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 may be divided into a plurality of regions having different characteristics.

[0241] For example, mainly at a portion not overlapping the first gate electrode GE1, a bond of an oxide may be broken to release oxygen, and oxygen vacancies may occur in an oxide semiconductor constituting the first semiconductor pattern layer ACT1 due to etching gas, etc. Therefore, the first semiconductor pattern layer ACT1 may be divided into a plurality of regions (e.g., a first channel region CH1, a first drain region DR1, and a first source region SR1) having different characteristics. In an embodiment, oxygen vacancies may mainly occur at a portion of the first semiconductor pattern layer ACT1 not overlapping the first gate electrode GE1 (e.g., the first drain region DR1 and the first source region SR1), and may diffuse to a portion of a region overlapping the first gate electrode GE1.

[0242] For example, oxygen vacancies may occur in the oxide semiconductor forming the second semiconductor pattern layer ACT2 mainly at the portion not overlapping the second gate electrode GE2. Therefore, the second semiconductor pattern layer ACT2 may be divided into a plurality of regions (e.g., the second channel region CH2, the second drain region DR2, and the second source region SR2) having different characteristics. In an embodiment, oxygen vacancies may occur mainly at the portion of the second semiconductor pattern layer ACT2 not overlapping the second gate electrode GE2 (e.g., the second drain region DR2 and the second source region SR2), and may diffuse to a portion of the region overlapping the second gate electrode GE2.

[0243] In another embodiment, in the display area DA and / or the driving circuit area DRA, the third insulating layer INS3 may not be etched to correspond to the first gate electrode GE1 and / or the second gate electrode GE2 (or overlap the first gate electrode GE1 and / or the second gate electrode GE2), and may be formed to cover (e.g., completely cover) the first semiconductor pattern layer ACT1 and / or the second semiconductor pattern layer ACT2. In an embodiment, the first drain region DR1, the first source region SR1, the second drain region DR2, and / or the second source region SR2 may become conductive by a doping process using the first gate electrode GE1 and / or the second gate electrode GE2 as a mask. In another example, the doping process may not be performed. For example, during a subsequent process of forming the interlayer insulating layer ILD, hydrogen may flow into the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2, so that the first drain region DR1, the first source region SR1, the second drain region DR2, and / or the second source region SR2 may become conductive to have a relatively low conductivity.

[0244] Apart from Figures 1 to 16 In addition, refer to Fig.17 , an interlayer insulating layer ILD covering the first semiconductor pattern layer ACT1, the second semiconductor pattern layer ACT2, the first gate insulating pattern layer GI1, the second gate insulating pattern layer GI2, the first gate electrode GE1 and the second gate electrode GE2 may be formed on the second insulating layer INS2. For example, the interlayer insulating layer ILD may be formed in the display area DA and the non-display area NDA (e.g., the driving circuit area DRA). The interlayer insulating layer ILD may be formed by an insulating film forming process using at least one insulating material (e.g., an inorganic insulating material) above. The material and / or method for forming the interlayer insulating layer ILD may be changed differently according to the embodiment.

[0245] During the process of forming the interlayer insulating layer ILD, hydrogen may flow into the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2. In an embodiment, a heat treatment process (e.g., an annealing process) may be additionally performed on the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2 before or after forming the interlayer insulating layer ILD. Even in the heat treatment process, hydrogen may flow into the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2.

[0246] Since hydrogen flows into the first semiconductor pattern layer ACT1 and the second semiconductor pattern layer ACT2, a portion of the first semiconductor pattern layer ACT1 and a portion of the second semiconductor pattern layer ACT2 may become conductive (e.g., N-type conductive) mainly at a portion including a large number of oxygen vacancies. For example, the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2 may become conductive.

[0247] Apart from Figures 1 to 17 In addition, refer to Fig.18 , a first drain electrode DE1, a first source electrode SE1, a second drain electrode DE2, and a second source electrode SE2 may be formed on the interlayer insulating layer ILD. In an embodiment, in the case where at least one of the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2 replaces at least one of the first drain electrode DE1, the first source electrode SE1, the second drain electrode DE2, and the second source electrode SE2, at least one of the first drain electrode DE1, the first source electrode SE1, the second drain electrode DE2, and the second source electrode SE2 may not be formed.

[0248] The first drain electrode DE1 and the first source electrode SE1 may be formed to be connected to different portions of the first semiconductor pattern layer ACT1. For example, the first drain electrode DE1 may be formed to be connected to the first drain region DR1, and the first source electrode SE1 may be formed to be connected to the first source region SR1. The second drain electrode DE2 and the second source electrode SE2 may be formed to be connected to different portions of the second semiconductor pattern layer ACT2. For example, the second drain electrode DE2 may be formed to be connected to the second drain region DR2, and the second source electrode SE2 may be formed to be connected to the second source region SR2. For example, a contact hole may be formed in the interlayer insulating layer ILD.

[0249] Through the above process, transistors TFT including a first transistor TFT1 and a second transistor TFT2 may be formed in the display area DA and the drive circuit area DRA. Fig.18 Other transistors shown in Figure 7 In the case of a third transistor TFT3, the other transistors may be formed simultaneously with the first transistor TFT1 and / or the second transistor TFT2. For example, elements formed as (eg, arranged as) the same conductive layer or the same semiconductor layer SCL in the display panel 110 may be formed simultaneously.

[0250] After forming the transistor TFT, the formation of Figure 6 The first passivation layer PSV1 may cover the transistor TFT. In an embodiment, a process of forming a fifth conductive layer CDL5 including a connection electrode CNE of each pixel PX on the first passivation layer PSV1 and a process of forming a second passivation layer PSV2 covering the fifth conductive layer CDL5 may be additionally performed. Thus, the panel circuit layer PCL of the display panel 110 may be formed.

[0251] In an embodiment, in the case where the display panel 110 includes the light emitting element layer LEL and the encapsulation layer ENL disposed on the panel circuit layer PCL, the light emitting element layer LEL and the encapsulation layer ENL may be sequentially formed on the panel circuit layer PCL.

[0252] According to the display device 100 and the method of manufacturing the display device 100 of the above-described embodiment, the transistor TFT may be formed into different structures according to the operation characteristics and / or performance required of each transistor TFT of the display panel 110. For example, according to the operation characteristics and / or performance required of each transistor TFT, the lower electrode of each transistor TFT may be disposed in the first conductive layer CDL1 or the second conductive layer CDL2. Therefore, the characteristics of the transistor TFT (e.g., characteristics related to capacitance (or parasitic capacitance)) may be controlled or optimized.

[0253] For example, a transistor TFT that requires a relatively low capacitance for stable operation (e.g., a first transistor TFT1 included in the pixel transistor Tpx) may be formed to include a first lower electrode BG1 formed as (e.g., arranged as) a first conductive layer CDL1. On the other hand, a transistor TFT that requires a relatively high capacitance to ensure a high on-current (e.g., a second transistor TFT2 included in the driving transistor Tdr) may be formed to include a second lower electrode BG2 formed as (e.g., arranged as) a second conductive layer CDL2. According to the above-described embodiments, the performance of the pixel transistor Tpx and the driving transistor Tdr may be improved and / or optimized at the same time.

[0254] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles of the invention. Therefore, the embodiments of the disclosed invention are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: A substrate, including a display area and a driving circuit area; A first insulating layer, disposed on the substrate; a second insulating layer, disposed on the first insulating layer; a first transistor disposed in the display area and including a first semiconductor pattern layer formed as a semiconductor layer on the second insulating layer, a first gate electrode disposed on the first semiconductor pattern layer, and a first lower electrode overlapping the first semiconductor pattern layer; as well as a second transistor disposed in the driving circuit region and comprising a second semiconductor pattern layer formed as the semiconductor layer, a second gate electrode disposed on the second semiconductor pattern layer, and a second lower electrode overlapping the second semiconductor pattern layer, wherein the first lower electrode is formed as a first conductive layer disposed between the substrate and the first insulating layer, and The second lower electrode is formed as a second conductive layer disposed between the first insulating layer and the second insulating layer.

2. The display device according to claim 1, wherein: The first semiconductor pattern layer and the first lower electrode are spaced apart from each other, and the first insulating layer and the second insulating layer are disposed between the first semiconductor pattern layer and the first lower electrode, and The second semiconductor pattern layer and the second lower electrode are spaced apart from each other, and the second insulating layer is disposed between the second semiconductor pattern layer and the second lower electrode.

3. The display device according to claim 1, wherein: The first semiconductor pattern layer and the first lower electrode are spaced apart from each other by a first distance, and The second semiconductor pattern layer and the second lower electrode are spaced apart from each other by a second distance, and the second distance is smaller than the first distance.

4. The display device according to claim 1, wherein: The first semiconductor pattern layer and the second semiconductor pattern layer include an oxide semiconductor.

5. The display device according to claim 1, further comprising: The first gate insulating pattern layer is disposed between the first semiconductor pattern layer and the first gate electrode and covers a portion of the first semiconductor pattern layer.

6. The display device according to claim 5, wherein: The first gate insulating pattern layer has a shape and a size corresponding to those of the first gate electrode and exposes other portions of the first semiconductor pattern layer.

7. The display device according to claim 1, further comprising: The second gate insulating pattern layer is disposed between the second semiconductor pattern layer and the second gate electrode and covers a portion of the second semiconductor pattern layer.

8. The display device according to claim 7, wherein: The second gate insulating pattern layer has a shape and a size corresponding to those of the second gate electrode and exposes other portions of the second semiconductor pattern layer.

9. The display device according to claim 1, further comprising: an interlayer insulating layer covering the first gate electrode and the second gate electrode, The first transistor further includes a first source electrode and a first drain electrode, the first source electrode and the first drain electrode are disposed on the interlayer insulating layer and connected to different portions of the first semiconductor pattern layer, and The second transistor further includes a second source electrode and a second drain electrode disposed on the interlayer insulating layer and connected to different portions of the second semiconductor pattern layer.

10. The display device according to claim 9, wherein: The first lower electrode is connected to the first source electrode.

11. The display device according to claim 1, wherein: The second lower electrode is connected to the second gate electrode.

12. The display device according to claim 1, further comprising: A pixel is arranged in the display area and includes the first transistor.

13. The display device according to claim 12, wherein: The pixel further includes a third transistor including a third semiconductor pattern layer formed as the semiconductor layer, a third gate electrode disposed on the third semiconductor pattern layer, and a third lower electrode formed as the second conductive layer and overlapping the third semiconductor pattern layer.

14. The display device according to claim 1, further comprising: The driving circuit is disposed in the driving circuit region and includes the second transistor.

15. The display device according to claim 14, wherein: The driving circuit outputs a gate signal that controls the operation of pixels provided in the display area.

16. A method for manufacturing a display device, the method comprising: Provide a substrate including a display area and a driving circuit area; forming a first lower electrode on the substrate in the display area; forming a first insulating layer covering the first lower electrode on the substrate; forming a second lower electrode on the first insulating layer in the driving circuit region; forming a second insulating layer covering the second lower electrode on the first insulating layer; forming a first semiconductor pattern layer overlapping the first lower electrode and a second semiconductor pattern layer overlapping the second lower electrode on the second insulating layer; forming a third insulating layer on the second insulating layer covering the first semiconductor pattern layer and the second semiconductor pattern layer; as well as A first gate electrode overlapping the first semiconductor pattern layer and a second gate electrode overlapping the second semiconductor pattern layer are formed on the third insulating layer.

17. The method according to claim 16, wherein: In the step of forming the first semiconductor pattern layer and the second semiconductor pattern layer, the first semiconductor pattern layer and the second semiconductor pattern layer are simultaneously formed of the same oxide semiconductor.

18. The method according to claim 16, further comprising: forming a first gate insulating pattern layer on a portion of the first semiconductor pattern layer overlapping the first gate electrode by etching the third insulating layer; as well as A second gate insulating pattern layer is formed on a portion of the second semiconductor pattern layer overlapping the second gate electrode by etching the third insulating layer.

19. The method according to claim 16, further comprising: An interlayer insulating layer covering the first gate electrode and the second gate electrode is formed on the second insulating layer.

20. The method according to claim 19, further comprising: forming at least one of a first drain electrode, a first source electrode, a second drain electrode, and a second source electrode on the interlayer insulating layer, wherein the first drain electrode and the first source electrode are connected to the first semiconductor pattern layer, and The second drain electrode and the second source electrode are connected to the second semiconductor pattern layer.

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